A six-pack encapsulation method for 3D integrated chips

Abstract

This invention belongs to the field of integrated chip packaging technology, and relates to a six-sided encapsulation method for 3D integrated chips. The invention involves mounting several 3D integrated chips onto a first wafer substrate; performing five-sided molding encapsulation on the chips, thinning the encapsulation on the side of the molded wafer furthest from the first wafer substrate to expose the chips; etching microchannels and manifold structures on the back side of the exposed chips; bonding a second wafer substrate to the exposed chip side of the molded wafer; performing pressure encapsulation on the side of the molded wafer with external interconnect structures, and using ultrafast laser technology to partially remove the encapsulation on the external interconnect structures to expose them; bonding a sealing heat dissipation cover to the side of the chip with microchannels and manifold structures; and fabricating solder balls on the molded wafer to connect with the external interconnect structures. This simplifies the external interconnect structure of the integrated chips and improves packaging process efficiency and reliability.

Description

Technical Field

[0001] This invention belongs to the field of integrated chip packaging technology, and relates to a six-sided encapsulation method for 3D integrated chips. Background Technology

[0002] Breakthroughs in disruptive technologies such as unmanned technology, artificial intelligence, and big data have spurred an urgent demand for smaller, faster, and smarter high-end chips. High-density integration of multiple functions within a single system through 3D integrated chips, achieving a comprehensive improvement in system performance, has become a crucial development path for high-end chips. To minimize damage to 3D integrated chips during subsequent assembly and testing, caused by clamping and external environments, and considering their reliability in subsequent applications, encapsulation is often necessary. Currently, epoxy molding compound (EMC) is primarily used for wafer-level five- or six-sided encapsulation of 3D integrated chips. For chips with five-sided encapsulation, the side with pads and wiring layers is not encapsulated with epoxy molding compound, thus leaving the possibility of damage to that side in subsequent processes. For six-sided encapsulation, copper pillars, solder balls, and other lead-out structures are typically fabricated on the external pads of the sixth side, followed by two rounds of five-sided encapsulation, and then the encapsulated sixth side is thinned to expose the interconnect structures. Existing six-sided encapsulation technology requires the fabrication of relatively complex lead-out structures. Stress concentration can easily occur during the fabrication of interconnect structures and subsequent work, leading to problems such as cracking and open circuits. On the other hand, existing six-sided encapsulation technology does not consider the heat dissipation problem of high-performance computing chips. Heat dissipation often relies on traditional cold plates or external jet cooling solutions, which suffer from problems such as high peak temperatures and poor temperature uniformity. Summary of the Invention

[0003] The purpose of this invention is to provide a six-sided encapsulation method for 3D integrated chips, in order to solve the technical problems of five-sided encapsulation chips having one side with pads and wiring layers being easily damaged in subsequent processes, six-sided encapsulation technology requiring the fabrication of complex lead-out structures and interconnect structures being prone to cracking, and six-sided encapsulation having poor temperature uniformity for high-computing-power chips.

[0004] To achieve the above objectives, the present invention employs the following technical solution:

[0005] This invention provides a six-sided encapsulation method for a 3D integrated chip, the 3D integrated chip including an external interconnect structure and several chips, comprising the following steps:

[0006] S1, mounting one side of the plurality of 3D integrated chips having the external interconnection structure onto the first wafer substrate;

[0007] S2, perform five-sided molding on several of the 3D integrated chips to obtain a molded wafer, and thin the molding on the side of the molded wafer away from the first wafer substrate to expose the chip;

[0008] S3, etching microchannel and manifold channel structures on the exposed back side of the chip;

[0009] S4, remove the first wafer substrate from the molded wafer, and bond a second wafer substrate to the side of the chip exposed on the molded wafer;

[0010] S5, perform lamination and encapsulation on the side of the plastic-encapsulated wafer with the external interconnect structure, and use ultrafast laser technology to partially remove the encapsulation on the external interconnect structure to expose the external interconnect structure;

[0011] S6, Remove the second wafer substrate of the plastic-encapsulated wafer, and bond a sealing heat dissipation cover plate to the side of the chip having the microchannel and manifold channel structure;

[0012] S7, solder balls connected to the external interconnect structure are prepared on the plastic-encapsulated wafer, and the plastic-encapsulated wafer is cut using the 3D integrated chip as the basic unit.

[0013] Furthermore, the step of mounting one side of the plurality of 3D integrated chips having the external interconnect structure onto the first wafer substrate includes:

[0014] One side of the aforementioned 3D integrated chips having the external interconnection structure is mounted onto a first wafer substrate using adhesive.

[0015] The adhesive used is a hot-dip PVC film, a laser temporary bonding adhesive, or a hydrolyzed adhesive.

[0016] Furthermore, the step of performing five-sided molding on the plurality of 3D integrated chips to obtain a molded wafer, and thinning the molding on the side of the molded wafer away from the first wafer substrate to expose the chip, includes:

[0017] A plastic-encapsulated wafer is obtained by five-sided plastic encapsulation of several 3D integrated chips, and the plastic encapsulation material forms a plastic encapsulation shell that encapsulates the 3D integrated chips;

[0018] The plastic encapsulation shell on the side of the plastic-encapsulated wafer away from the first wafer substrate is mechanically thinned by first rough thinning and then fine grinding to expose the chip away from the first wafer substrate.

[0019] Furthermore, the step of performing five-sided molding encapsulation on a plurality of the 3D integrated chips to obtain a molded wafer includes:

[0020] Using liquid or powdered molding compound, the remaining five sides of several 3D integrated chips are molded and the interlayer gaps of the 3D integrated chips are filled to obtain a molded wafer;

[0021] The thickness of the plastic encapsulation covering the top surface of the 3D integrated chip is 200um~500um.

[0022] Furthermore, etching the microchannel and manifold channel structures on the exposed back side of the chip includes:

[0023] A multilayer mask is photolithographically fabricated on the back of the exposed chip. Specifically, the multilayer mask consists of a 50nm thick low-pressure chemical vapor deposition silicon dioxide layer as a protective film, a 100nm thick physical vapor deposition aluminum layer as a hard mask, and a 10μm thick photoresist layer as an etching mask.

[0024] After photolithography is used to prepare multilayer masks, chemical reagents are used to etch the aluminum layer in the etched area;

[0025] After the aluminum layer is etched, the embedded microchannel and manifold channel structure is fabricated using deep silicon etching technology;

[0026] After the microchannel and manifold channel structures were fabricated, the multilayer mask was removed using chemical cleaning and plasma cleaning processes.

[0027] Furthermore, the method for removing the first wafer substrate from the molded wafer includes:

[0028] The first wafer substrate of the molded wafer is removed by heating, laser irradiation, and water washing;

[0029] The method for removing the first wafer substrate from the molded wafer is the same as the method for removing the second wafer substrate from the molded wafer.

[0030] Furthermore, the step of laminating and encapsulating the side of the molded wafer with the external interconnect structure, and then partially removing the encapsulation on the external interconnect structure using ultrafast laser technology to expose the external interconnect structure, includes:

[0031] A positioning mark is prepared on one side of the molded wafer that has an external interconnect structure;

[0032] A lamination encapsulation is performed on the side of the molded wafer with the external interconnect structure, and the molding material forms an encapsulation film layer;

[0033] The encapsulation film layer is thinned to the target thickness to expose the positioning mark;

[0034] Ultrafast laser technology is used to remove the portion of the encapsulation layer corresponding to the external interconnect structure, exposing the external interconnect structure.

[0035] Furthermore, the step of preparing positioning marks on the side of the molded wafer having external interconnect structures includes:

[0036] On one side of the plastic-encapsulated wafer with an external interconnect structure, a positioning mark is prepared using a semi-additive wiring process, and the height of the positioning mark is greater than the target thickness.

[0037] The process involves laminating and encapsulating the side of the molded wafer with the external interconnect structure, wherein the molding material forms an encapsulation film layer, including:

[0038] Using molding compound, a sixth-side encapsulation is performed on the side of the molding wafer with external interconnection structure using vacuum hot pressing technology. The molding compound forms an encapsulation film layer, which is then baked and cured.

[0039] The step of thinning the encapsulation film layer to the target thickness to expose the positioning mark includes:

[0040] The encapsulation film layer is thinned to the target thickness using mechanical thinning or polishing techniques to expose the positioning mark;

[0041] The step of using ultrafast laser technology to remove the portion of the encapsulation layer corresponding to the external interconnect structure, exposing the external interconnect structure, includes:

[0042] The positioning mark is used for positioning. Based on the relative position between the positioning mark and the external interconnect structure, ultrafast laser technology is used to remove the portion of the encapsulation layer corresponding to the external interconnect structure, exposing the external interconnect structure.

[0043] Furthermore, the bonding of a sealing heat dissipation cover plate to the side of the chip having the microchannel and manifold channel structure includes:

[0044] On the side of the chip having the microchannel and manifold channel structure, a gold bonding layer, a tin bonding layer, and an indium bonding layer are prepared using a patterned thin film growth process, and a stripping method is used for pattern transfer to complete the bonding of the sealing heat dissipation cover.

[0045] Furthermore, the step of fabricating solder balls on the molded wafer that are connected to the external interconnect structure includes:

[0046] The residual organic material on the surface of the external interconnect structure is removed by plasma dry etching.

[0047] The metal oxides on the surface of the external interconnect structure are removed using a chemical etching method;

[0048] Nickel and gold were prepared on the surface of the external interconnect structure by chemical electroplating;

[0049] Solder balls that connect to the external interconnect structure are prepared on the surface of the molded wafer after lamination and encapsulation using either screen printing or laser ball placement methods.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] This invention mounts several 3D integrated chips onto a first wafer substrate, avoiding interference with the sides of the 3D integrated chips having external interconnect structures when molding the other five sides. The several 3D integrated chips are molded on five sides to prevent external mechanical damage and environmental corrosion, while maintaining compatibility with existing 2.5D / 3D / fan-out packaging processes. The side of the molded wafer furthest from the first wafer substrate is thinned to expose the chip, providing operational space for subsequent microchannel etching and reducing thermal resistance. Microchannel and manifold channel structures are etched on the back of the exposed chip to introduce high-heat-transfer-coefficient fluid near the chip junction region, forming an "embedded microfluidic cooling" architecture. This helps eliminate local hot spots, improves system-level temperature uniformity, significantly shortens the heat conduction path, significantly reduces peak temperature, and improves temperature uniformity. A second wafer substrate is bonded to the side of the exposed chip on the molded wafer, providing reverse support for the molded wafer, which helps reduce wafer warpage and improve packaging quality. A lamination encapsulation is performed on the side of the molded wafer with the external interconnect structure, avoiding the complexity of the traditional two-stage five-sided encapsulation process. Ultrafast laser technology is used to partially remove the encapsulation on the external interconnect structure, exposing it. The low thermal effect of ultrafast lasers reduces stress changes in the molded wafer, which helps reduce wafer warpage. A sealing heat sink is bonded to the side of the chip with the microchannel and manifold channel structure. The heat sink and the microchannel on the back of the chip form a closed cavity, preventing cooling fluid leakage and providing mechanical protection. This invention avoids the complex fabrication of copper pillars / solder balls and other lead-out structures in traditional six-sided encapsulation, reducing the risk of cracking due to stress concentration. The reliability of the interconnect structure is significantly improved, and it is compatible with 2.5D / 3D / fan-out packaging, which helps improve encapsulation efficiency. The design of the microchannel and manifold channel structure on the back of the chip significantly shortens the heat conduction path, which helps reduce peak temperature and improve temperature uniformity. This invention achieves full-encapsulation protection by adding a sixth-side lamination to the five-sided plastic encapsulation. Based on the five-sided plastic encapsulation, the top chip is further thinned to expose it, and the sixth side is encapsulated with a lamination and combined with laser removal and other methods. While achieving the sixth-side encapsulation, it avoids the preparation of lead-out structures such as copper pillars and solder balls. This not only simplifies the external interconnection structure of the integrated chip, but also helps to improve the packaging process efficiency and enhance application reliability. Attached Figure Description

[0052] Figure 1 This is a flowchart of a method according to an embodiment of the present invention;

[0053] Figure 2 This is a schematic diagram of a 3D integrated chip structure according to an embodiment of the present invention;

[0054] Figure 3 This is a schematic diagram of the structure of a 3D integrated chip mounted on a wafer substrate using adhesive, according to an embodiment of the present invention.

[0055] Figure 4 This is a schematic diagram of the structure of a 3D integrated chip after wafer-level five-sided molding and encapsulation according to an embodiment of the present invention;

[0056] Figure 5 This is a schematic diagram of the structure of the plastic-encapsulated wafer after thinning according to an embodiment of the present invention;

[0057] Figure 6 This is a schematic diagram of the structure after etching the microchannel and manifold channel structure on the back of the chip according to an embodiment of the present invention;

[0058] Figure 7 This is a schematic diagram of the structure of the first wafer substrate after debonding in an embodiment of the present invention;

[0059] Figure 8 This is a schematic diagram of the structure after the positioning mark is prepared according to an embodiment of the present invention;

[0060] Figure 9 This is a schematic diagram of the structure of the plastic-encapsulated wafer after lamination and encapsulation on the sixth side according to an embodiment of the present invention;

[0061] Figure 10 This is a schematic diagram of the structure after thinning the sixth breading layer according to an embodiment of the present invention;

[0062] Figure 11 This is a schematic diagram of the exposed external interconnect structure of the molded wafer according to an embodiment of the present invention;

[0063] Figure 12 This is a schematic diagram of the structure after bonding and sealing the heat dissipation cover plate to the molded wafer in an embodiment of the present invention;

[0064] Figure 13 This is a schematic diagram of the structure after solder balls are fabricated on the external interconnect structure according to an embodiment of the present invention;

[0065] Figure 14 This is a mechanical dicing effect diagram of a molded wafer according to an embodiment of the present invention;

[0066] Figure 15 This is a flowchart of a method according to another embodiment of the present invention;

[0067] Figure 16 This is a schematic diagram of the structure of the 3D integrated chip after encapsulation and soldered onto the interconnect substrate according to Embodiment 6 of the present invention;

[0068] Figure 17Figures are provided for an embodiment of the present invention, wherein Figure (a) is an electron microscope image of the microchannel etching result and Figure (b) is the depth test result.

[0069] Among them: 100, 3D integrated chip; 101, chip; 102, redistribution layer; 103, interconnect bumps; 104, fan-out substrate; 105, interconnect via structure; 106, external interconnect structure; 201, adhesive; 202, first wafer substrate; 203, second wafer substrate; 301, plastic encapsulation shell; 401, microchannel and manifold channel structure; 501, positioning mark; 601, encapsulation film layer; 701, heat sink cover; 801, solder ball; 901, interconnect carrier; 902, filler. Detailed Implementation

[0070] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0071] It should be noted that the terms "first," "second," etc., in the specification and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0072] It's important to note that 2.5D packaging is an advanced technology situated between traditional 2D planar packaging and 3D vertical stacking packaging. Its core principle is to achieve high-density interconnection of multiple chips through an interposer while maintaining a horizontal chip layout on the substrate. 3D integrated chip technology is a semiconductor technology that achieves higher integration by vertically stacking multiple chip layers. 3D packaging integrates multiple chips or wafers directly in the vertical direction (Z-axis) through chip stacking or package stacking.

[0073] The present invention will now be described in further detail with reference to the accompanying drawings:

[0074] Example 1:

[0075] See Figure 1 This embodiment discloses a six-sided encapsulation method for 3D integrated chips, see [link to documentation]. Figure 2 The 3D integrated chip 100 includes a plurality of chips 101 and an external interconnection structure 106, and includes the following steps:

[0076] S1, see S1 Figure 3 The 3D integrated chips 100 are mounted on a first wafer substrate 202 with one side having the external interconnect structure 106. The first wafer substrate 202 provides stable mechanical support, preventing the surface of the 3D integrated chip 100 with the external interconnect structure 106 from being affected when the other five sides are encapsulated. Specifically, S1 is as follows:

[0077] A plurality of the 3D integrated chips 100 are attached to a first wafer substrate 202 with one side having the external interconnection structure 106 using adhesive 201.

[0078] The adhesive 201 is made of hot glass film, laser temporary bonding adhesive or hydrolytic adhesive.

[0079] S2, see S2. Figure 4 The aforementioned 3D integrated chips 100 are subjected to five-sided molding to obtain a molded wafer, forming a physical protective layer to prevent external mechanical damage and environmental corrosion. Simultaneously, it is compatible with existing 2.5D / 3D / fan-out packaging processes, which helps reduce technology migration costs. See also Figure 5 The molding process involves thinning the side of the molded wafer away from the first wafer substrate 202 to expose the chip 101, providing operating space for subsequent microchannel etching and reducing thermal resistance. Specifically, S2 is as follows:

[0080] A plurality of the 3D integrated chips 100 are subjected to five-sided molding to obtain a molded wafer. The molding material forms a molding shell 301 encapsulating the 3D integrated chips 100, comprising:

[0081] Using liquid or powdered molding compound, the remaining five sides of several 3D integrated chips 100 are molded and the interlayer gaps of the 3D integrated chips 100 are filled to obtain a molded wafer. At this time, the thickness of the molding shell 301 covering the top surface of the 3D integrated chip 100 is 200um~500um.

[0082] The plastic casing 301 on the side of the plastic-encapsulated wafer away from the first wafer substrate 202 is mechanically thinned by first rough thinning and then fine grinding to expose the chip 101 away from the first wafer substrate 202.

[0083] S3, see S3. Figure 6Microchannels and manifold structures 401 are etched on the back of the exposed chip 101 to introduce high-heat-transfer-coefficient fluid near the chip junction region, forming an "embedded microfluidic cooling" architecture. This helps eliminate local hot spots and improve system-level temperature uniformity. It avoids the series thermal resistance problems caused by multi-layer thermal interface materials and thick metal cover plates in traditional solutions, significantly reducing the chip peak temperature. Simultaneously, it significantly shortens the heat conduction path, significantly reduces the peak temperature, and improves temperature uniformity, resulting in higher energy efficiency with the same pump power. S3 is detailed below:

[0084] A multilayer mask is photolithographically fabricated on the back side of the exposed chip 101. Specifically, the multilayer mask consists of a 50nm thick low-pressure chemical vapor deposition silicon dioxide layer as a protective film, a 100nm thick physical vapor deposition aluminum layer as a hard mask, and a 10μm thick photoresist layer as an etching mask.

[0085] After photolithography is used to prepare multilayer masks, the aluminum layer in the etched area is etched using chemical reagents.

[0086] After the aluminum layer is etched, the embedded microchannel and manifold channel structure 401 is prepared using deep silicon etching technology.

[0087] After the embedded microchannel and manifold channel structure 401 is fabricated, the multilayer mask is removed by chemical cleaning and plasma cleaning processes.

[0088] S4, see S4 Figure 7 The first wafer substrate 202 of the plastic-encapsulated wafer is removed, and a second wafer substrate 203 is bonded to one side of the exposed chip 101 of the plastic-encapsulated wafer. The second wafer substrate 203 provides reverse support for the plastic-encapsulated wafer, which helps to reduce the warpage of the plastic-encapsulated wafer and improve the packaging quality.

[0089] In this embodiment of the invention, the method for removing the first wafer substrate 202 from the molded wafer includes:

[0090] The first wafer substrate 202 of the molded wafer is removed by heating, laser irradiation and water washing;

[0091] S5, see S5. Figure 9 A lamination encapsulation process is performed on one side of the molded wafer with the external interconnect structure 106, avoiding the complexity of the traditional two-stage five-sided encapsulation process. Ultrafast laser technology is used to partially remove the encapsulation on the external interconnect structure 106, exposing the external interconnect structure 106. The low thermal effect of ultrafast lasers reduces stress changes on the molded wafer, which helps to reduce wafer warpage. S5 is specifically as follows:

[0092] S51, see S51. Figure 8A positioning mark 501 is prepared on one side of the molded wafer having the external interconnect structure 106, including:

[0093] On one side of the molded wafer with the external interconnect structure 106, a positioning mark 501 is prepared using a semi-additive wiring process, wherein the height of the positioning mark 501 is greater than the target thickness.

[0094] S52, see S52. Figure 9 A molding compound is applied to one side of the molded wafer having the external interconnect structure 106, and the molding compound forms an encapsulation film layer 601, comprising:

[0095] Using molding compound material, a sixth-side encapsulation is performed on one side of the molding wafer with the external interconnect structure 106 through vacuum hot pressing technology. The molding compound material forms an encapsulation film layer 601, which is then baked and cured.

[0096] S53, see also Figure 10 Thinning the encapsulation film layer 601 to the target thickness to expose the positioning mark 501 includes:

[0097] The encapsulation film layer 601 is thinned to the target thickness using mechanical thinning or polishing techniques, exposing the positioning mark 501.

[0098] S54, see also Figure 11 Ultrafast laser technology is used to remove the portion of the encapsulation layer 601 corresponding to the external interconnect structure 106, exposing the external interconnect structure 106, including:

[0099] Positioning is performed using the positioning mark 501. Based on the relative position between the positioning mark 501 and the external interconnection structure 106, ultrafast laser technology is used to remove the portion of the encapsulation film layer 601 corresponding to the external interconnection structure 106, exposing the external interconnection structure 106.

[0100] S6, see S6. Figure 12 The second wafer substrate 203 of the plastic-encapsulated wafer is removed, and a heat dissipation cover 701 is bonded to the side of the chip 101 having the microchannel and manifold channel structure 401. The heat dissipation cover 701 and the microchannel on the back of the chip form a closed cavity to prevent cooling fluid leakage and provide mechanical protection. Step S6 is as follows:

[0101] On one side of the chip 101 having the microchannel and manifold channel structure 401, a gold bonding layer, a tin bonding layer and an indium bonding layer are prepared using a patterned thin film growth process, and a stripping method is used to transfer the pattern to complete the bonding of the sealed heat dissipation cover 701.

[0102] The method for removing the first wafer substrate 202 of the molded wafer is the same as the method for removing the second wafer substrate 203 of the molded wafer.

[0103] S7, see S7. Figure 13 Solder balls 801 are fabricated on the molded wafer to connect with the external interconnect structure 106. The solder balls 801 establish an electrical connection between the chip and external circuits to meet system-level integration requirements, including:

[0104] The residual organic material on the surface of the external interconnect structure 106 is removed by plasma dry etching.

[0105] The metal oxides on the surface of the external interconnect structure 106 are removed by chemical etching.

[0106] Nickel and gold were prepared on the surface of the external interconnect structure 106 by chemical electroplating.

[0107] Solder balls 801, which are connected to the external interconnect structure 106, are prepared on the surface of the molded wafer after lamination and encapsulation using either screen printing or laser ball placement.

[0108] See Figure 14 The plastic-encapsulated wafer is cut using the 3D integrated chip 100 as the basic unit, and a single 3D integrated chip 100 module is obtained after cutting, which is convenient for subsequent assembly and application.

[0109] This invention avoids the complex fabrication of copper pillars / solder balls 801 in traditional six-sided encapsulation, reducing the risk of cracking due to stress concentration and significantly improving the reliability of the interconnect structure. It is compatible with 2.5D / 3D / fan-out packaging, which is beneficial for improving encapsulation efficiency. The design of the microchannel and manifold channel structure 401 on the back of the chip significantly shortens the heat conduction path, which helps reduce peak temperature and improve temperature uniformity. This invention achieves fully enclosed protection by adding a sixth-sided lamination to the five-sided plastic encapsulation. Based on the five-sided plastic encapsulation, the top chip is further thinned and exposed. The sixth side is encapsulated using lamination and laser removal methods. While achieving the sixth-sided encapsulation, it avoids the fabrication of copper pillars, solder balls 801, and other lead-out structures, simplifying the external interconnect structure 106 of the integrated chip and improving packaging process efficiency and application reliability.

[0110] Example 2:

[0111] See Figure 15This embodiment proposes a six-sided encapsulation method for 3D integrated chips. It employs top-surface EMC thinning and exposure, deep silicon etching of flow channels and manifolds, EMC lamination, laser EMC removal, and wafer-level bonding to achieve efficient and reliable six-sided encapsulation of the 3D integrated chip 100, while also addressing the heat dissipation requirements of high-performance chips. The encapsulated 3D integrated chip 100 can be soldered to adapter boards, packaging carriers, and other structures to form more complex and multifunctional integrated microsystems.

[0112] See Figure 2 An example is shown of a three-layer stacked 3D integrated chip 100, but the present invention is not limited to this. Figure 2 The three-layer structure is shown. The 3D integrated chip 100 includes multiple chips 101. Chips 101 can be 3D integrated by fabricating a redistribution layer 102 and interconnect bumps 103 on their surfaces and then using flip-chip bonding. One or more chips 101 can also be embedded in a fan-out substrate 104 and 3D integrated by fabricating a redistribution layer 102, interconnect bumps 103, and interconnect via structures 105, using flip-chip bonding. The fan-out substrate 104 can be made of silicon, glass, or organic materials, etc. The bottom layer of the 3D integrated chip 100 should have external interconnect structures 106.

[0113] See Figure 15 The present invention provides a six-sided encapsulation method for 3D integrated chips, as detailed below:

[0114] S10, Temporary mounting of 3D integrated chips 100. Multiple 3D integrated chips 100 are mounted onto a first wafer substrate 202 using adhesive 201 to form a 3D micro-module, such as... Figure 3 As shown. The adhesive 201 can be a thermally bonded glass film, laser temporary bonding adhesive, or hydrolyzed adhesive, etc., which can be used to remove the encapsulated 3D integrated chip 100 from the first wafer substrate 202 through methods such as heating, laser irradiation, and washing, without leaving any adhesive residue. The material of the first wafer substrate 202 includes, but is not limited to, silicon and glass.

[0115] S20, 3D integrated chip 100 wafer-level molding. Using wafer-level molding technology, the 3D micro-module is molded to obtain a molded wafer. The molding material forms a molding shell 301 that encapsulates the five sides of the 3D integrated chip 100, such as... Figure 4 As shown. Preferably, liquid or powdered molding compound can be used to fill the interlayer gaps of the 3D integrated chip 100. The thickness after molding should be 200um to 500um higher than the top surface of the 3D integrated chip 100 to reduce molding voids.

[0116] S30, Molded Wafer Thinning. The molded wafer is mechanically thinned to expose the top chip 101, such as... Figure 5As shown. Exposing chip 101 facilitates heat dissipation of the 3D integrated chip 100. Mechanical thinning can be performed by first coarse thinning and then fine grinding to reduce damage at the interface between chip 101 and the plastic casing 301.

[0117] S40, heat dissipation structure fabrication. Microchannels and manifold channel structures 401 with different morphologies and sizes are etched on the back side of the exposed chip 101, such as... Figure 6 As shown, a multilayer mask was used during the etching process. This multilayer mask consisted of a 50nm thick low-pressure chemical vapor deposition (LPCVD) silicon dioxide layer as a protective film, a 100nm thick physical vapor deposition (PVD) aluminum layer as a hard mask, and a 10μm thick photoresist layer as an etching mask. The purpose of using a multilayer mask was to protect the non-etched areas of the bonding surface from etching. After photolithography to prepare the multilayer mask, the aluminum layer in the etchable area was etched using chemical reagents. Subsequently, deep reactive ion etching (DRIE) technology was used to fabricate the embedded microchannel and manifold channel structure 401. Finally, chemical cleaning and plasma cleaning processes were used to remove the multilayer mask.

[0118] S50, wafer substrate debonding. The encapsulated 3D integrated chip 100 is removed from the first wafer substrate 202 by means of heating, laser irradiation, water washing, etc. Optionally, a second wafer substrate 203 is temporarily bonded to the side of the chip 101 that exposes the top chip, such as... Figure 7 As shown, this can effectively reduce the warpage of molded wafers, facilitating subsequent wiring processes.

[0119] S60, Fabrication of positioning mark 501. On the side having the external interconnection structure 106, positioning mark 501 is fabricated using a semi-additive wiring process, such as... Figure 8 As shown. The height of the positioning mark 501 should be higher than the target thickness of the sixth envelope, and 20~50μm higher. The positioning mark 501 is used for subsequent processing positioning to remove the encapsulation material on the external interconnect structure 106.

[0120] S70, Sixth-side lamination encapsulation of a molded wafer. Using a dry film adhesive molding compound, a sixth-side lamination encapsulation is performed on one side of the molded wafer containing the positioning mark 501 via vacuum hot lamination technology. The molding compound forms an encapsulation film layer 601, which is then baked and cured. Figure 9 As shown. The thickness of the encapsulation layer 601 after lamination should be 30-50 μm greater than the target thickness of the sixth encapsulation layer, and there should be no obvious pores.

[0121] S80, sixth-side thinning of the molded wafer. Mechanical thinning or polishing techniques are used to thin the encapsulation layer 601 to the target thickness of the sixth-side encapsulation, simultaneously exposing the positioning mark 501, such as... Figure 10 As shown.

[0122] S90, the external interconnect structure is exposed. Based on the relative position between the positioning mark 501 and the external interconnect structure 106, an ultrafast laser is used to remove the encapsulation layer 601 on the external interconnect structure 106, such as... Figure 11 As shown. Due to the differences in the materials and laser absorption rates between the metal on the surface of the external interconnect structure 106 and the encapsulation layer 601, the damage to the external interconnect structure 106 can be reduced while removing the encapsulation layer 601 by adjusting parameters such as laser power, wavelength, and pulse width. Simultaneously, the low thermal effect of ultrafast lasers can reduce stress changes in the molded wafer, thereby reducing wafer warpage.

[0123] S100, Surface treatment of the external interconnect structure 106. Residual organic materials on the surface of the external interconnect structure 106 are removed using plasma dry etching, and metal oxides are removed using chemical etching. Finally, nickel, gold, or other materials are chemically electroplated onto the surface of the external interconnect structure 106 to facilitate the subsequent fabrication of solder balls 801. Optionally, for the second wafer substrate 203 temporarily bonded in S5 on the side of the plastic-encapsulated wafer exposing the top chip 101, the encapsulated 3D integrated chip 100 wafer can be removed from the second wafer substrate 203 using methods such as heating, laser irradiation, and water washing.

[0124] S110, Bonded Sealing Heat Dissipation Cover 701. The gold, tin, and indium bonding layers required for wafer-level bonding are typically fabricated using patterned thin-film growth processes and transferred using a lift-off method. The gold bonding layer is prepared using dual-gun electron beam evaporation, typically with a thickness of 300-600 nm. The tin and indium bonding layers are prepared using thermal evaporation, typically with a thickness of 4-6 μm. The sealing heat dissipation cover 701 is typically bonded to the chip 101, which has microchannel and manifold channel structures 401, using different low-temperature eutectic bonding techniques such as gold-tin, tin-tin, and indium-indium. Figure 12 As shown. This method reduces stress concentration caused by bonding and achieves hermetic sealing by matching the thermal expansion coefficients between silicon-silicon / silicon-metal materials, significantly improving the thermal cycling reliability and leak-proof performance of the device.

[0125] S120, solder balls are placed on the sixth side of the molded wafer. Solder balls 801 are fabricated on the external interconnect structure 106 using methods such as screen printing and laser soldering. Figure 13As shown. Used for reflow soldering of the encapsulated 3D integrated chip 100 to structures such as the packaging substrate.

[0126] S130, Mechanical Dicing of Molded Wafers. This method uses mechanical dicing to cut and dice the six-sided molded wafer, ultimately obtaining a single six-sided 3D integrated chip 100. Figure 14 As shown.

[0127] For S12 and S13, the two processes can be interchanged as needed.

[0128] This invention is compatible with advanced packaging technologies such as 2.5D / 3D / fan-out. On one hand, based on wafer-level five-sided molding, the top chip is further thinned and exposed for EMC. The sixth side employs EMC lamination and laser EMC removal methods. While achieving sixth-side encapsulation, this avoids the fabrication of copper pillars, solder balls 801, and other lead-out structures. This simplifies the external interconnect structure 106 of the integrated chip and improves packaging process efficiency and application reliability. On the other hand, addressing the thermal management issues of high-power microsystems, a microchannel and manifold channel structure 401 is integrated into the silicon cover plate to introduce high-heat-transfer-coefficient fluid near the junction region of the chip 101, while completely eliminating the series thermal resistance caused by multilayer thermal interface materials and thick metal cover plates. Compared to traditional cold plate or external jet cooling solutions, this system-level embedded microfluidic system establishes the shortest heat conduction path, significantly reduces peak temperature, and improves temperature uniformity, achieving higher energy efficiency with the same pump power.

[0129] See Figure 16 The six-sided encapsulated 3D integrated chip 100 formed by this invention can be directly soldered onto an interconnect substrate 901. The interconnect substrate 901 includes, but is not limited to, adapter boards, organic substrates, ceramic substrates, and PCBs, and the gaps are filled with filler 902. The encapsulated 3D integrated chip 100 is electrically interconnected with an external electronic system through the interconnect substrate 901, thereby realizing a high-performance microsystem. The heat dissipation system on the surface of the 3D integrated chip 100 consists of coolant, microchannels, and a manifold channel structure 401. The coolant is introduced into multiple microchannels through the manifold and then flows through the entire surface of the microchannels. The high surface area of ​​the microchannels contacts the coolant, making heat dissipation faster and more effective. The manifold design ensures that the coolant is evenly distributed in each channel, avoiding uneven flow and local overheating, ensuring uniform temperature distribution, and reducing local hot spots. To minimize thermal resistance, multiphysics numerical simulation software is used to optimize the flow channel size in the heat source area. Embedded microchannels are fabricated using deep silicon etching technology, such as... Figure 17 As shown, (a) is an electron microscope image of the microchannel etching result, and (b) is the depth test result.

[0130] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.

Claims

1. A six-sided encapsulation method for a 3D integrated chip, the 3D integrated chip (100) comprising an external interconnect structure (106) and a plurality of chips (101), characterized in that, Includes the following steps: S1, a plurality of the 3D integrated chips (100) having one side of the external interconnection structure (106) are mounted on a first wafer substrate (202); S2, the 3D integrated chips (100) are encapsulated on five sides to obtain a plastic-encapsulated wafer. The plastic encapsulation on the side of the plastic-encapsulated wafer away from the first wafer substrate (202) is thinned to expose the chip (101). S3, etching microchannel and manifold channel structures (401) on the exposed back side of the chip (101), including: A multilayer mask is photolithographically prepared on the back side of the exposed chip (101). Specifically, the multilayer mask is prepared by using a 50nm thick low-pressure chemical vapor deposition silicon dioxide as a protective film, a 100nm thick physical vapor deposition aluminum layer as a hard mask, and a 10μm thick photoresist as an etching mask. After photolithography is used to prepare multilayer masks, chemical reagents are used to etch the aluminum layer in the etched area; After the aluminum layer is etched, the embedded microchannel and manifold channel structure is prepared using deep silicon etching technology (401). After the microchannel and manifold channel structure (401) is prepared, the multilayer mask is removed by chemical cleaning and plasma cleaning processes; S4, remove the first wafer substrate (202) of the plastic-encapsulated wafer, and bond the second wafer substrate (203) to one side of the exposed chip (101) of the plastic-encapsulated wafer. S5, performing a lamination encapsulation on one side of the molded wafer with the external interconnect structure (106), and partially removing the encapsulation on the external interconnect structure (106) using ultrafast laser technology to expose the external interconnect structure (106), including: A positioning mark (501) is prepared on one side of the molded wafer having an external interconnect structure (106). A molding encapsulation is performed on one side of the molded wafer that has an external interconnect structure (106), and the molding material forms an encapsulation film layer (601). The encapsulation film layer (601) is thinned to the target thickness to expose the positioning mark (501). Ultrafast laser technology is used to remove the portion of the encapsulation film layer (601) corresponding to the external interconnect structure (106), exposing the external interconnect structure (106). S6, remove the second wafer substrate (203) of the plastic-encapsulated wafer, and bond a sealing heat dissipation cover plate (701) to the side of the chip (101) having the microchannel and manifold channel structure (401). S7, solder balls (801) connected to the external interconnect structure (106) are prepared on the plastic-encapsulated wafer, and the plastic-encapsulated wafer is cut with the 3D integrated chip (100) as the basic unit.

2. The six-sided encapsulation method for 3D integrated chips according to claim 1, characterized in that, The step of mounting one side of the plurality of 3D integrated chips (100) having the external interconnect structure (106) onto the first wafer substrate (202) includes: One side of the plurality of 3D integrated chips (100) having the external interconnection structure (106) is attached to the first wafer substrate (202) by adhesive (201); The adhesive (201) is a hot-dip PVC film, a laser temporary bonding adhesive, or a hydrolyzed adhesive.

3. The six-sided encapsulation method for 3D integrated chips according to claim 1, characterized in that, The step of performing five-sided molding on a plurality of the 3D integrated chips (100) to obtain a molded wafer, and thinning the molding on the side of the molded wafer away from the first wafer substrate (202) to expose the chip (101), includes: A plastic-encapsulated wafer is obtained by five-sided plastic encapsulation of several 3D integrated chips (100), and the plastic encapsulation material forms a plastic encapsulation shell (301) that encapsulates the 3D integrated chips (100). The plastic casing (301) on the side of the plastic-encapsulated wafer away from the first wafer substrate (202) is mechanically thinned by first coarse thinning and then fine grinding to expose the chip (101) away from the first wafer substrate (202).

4. The six-sided encapsulation method for 3D integrated chips according to claim 3, characterized in that, The process of performing five-sided molding of a plurality of the 3D integrated chips (100) to obtain a molded wafer includes: Using liquid or powdered molding compound, the remaining five sides of several 3D integrated chips (100) are molded and the interlayer gaps of the 3D integrated chips (100) are filled to obtain a molded wafer; The thickness of the plastic encapsulation shell (301) covering the top surface of the 3D integrated chip (100) is 200um~500um.

5. A six-sided encapsulation method for 3D integrated chips according to claim 1, characterized in that, The method for removing the first wafer substrate (202) from the molded wafer includes: The first wafer substrate (202) of the molded wafer is removed by heating, laser irradiation and water washing. The method for removing the first wafer substrate (202) of the molded wafer is the same as the method for removing the second wafer substrate (203) of the molded wafer.

6. The six-sided encapsulation method for 3D integrated chips according to claim 1, characterized in that, The step of fabricating a positioning mark (501) on one side of the molded wafer having an external interconnect structure (106) includes: On one side of the molded wafer with an external interconnect structure (106), a positioning mark (501) is prepared using a semi-additive wiring process, wherein the height of the positioning mark (501) is greater than the target thickness; The process of laminating and encapsulating the molded wafer on one side having the external interconnect structure (106), wherein the molding material forms an encapsulation film layer (601), includes: Using molding compound, a sixth-side encapsulation is performed on the side of the molding wafer with the external interconnect structure (106) by vacuum hot pressing film technology. The molding compound forms an encapsulation film layer (601), and the encapsulation film layer (601) is baked and cured. The step of thinning the encapsulation film layer (601) to the target thickness to expose the positioning mark (501) includes: The encapsulation film layer (601) is thinned to the target thickness using mechanical thinning or polishing techniques, exposing the positioning mark (501). The step of using ultrafast laser technology to remove the portion of the encapsulation layer (601) corresponding to the external interconnect structure (106) to expose the external interconnect structure (106) includes: Positioning is performed using the positioning mark (501). Based on the relative position between the positioning mark (501) and the external interconnection structure (106), ultrafast laser technology is used to remove the portion of the encapsulation film layer (601) corresponding to the external interconnection structure (106), exposing the external interconnection structure (106).

7. The six-sided encapsulation method for 3D integrated chips according to claim 1, characterized in that, The bonding and sealing heat dissipation cover plate (701) on one side of the chip (101) having the microchannel and manifold channel structure (401) includes: On the side of the chip (101) having the microchannel and manifold channel structure (401), a gold bonding layer, a tin bonding layer and an indium bonding layer are prepared using a patterned thin film growth process, and a pattern transfer is performed using a stripping method to complete the bonding of the sealed heat dissipation cover plate (701).

8. A six-sided encapsulation method for 3D integrated chips according to claim 1, characterized in that, The fabrication of solder balls (801) on the molded wafer and connected to the external interconnect structure (106) includes: The residual organic material on the surface of the external interconnect structure (106) was removed by plasma dry etching; The metal oxides on the surface of the external interconnect structure (106) are removed by chemical etching. Nickel and gold were prepared on the surface of the external interconnect structure (106) by chemical electroplating; Solder balls (801) that are connected to the external interconnect structure (106) are prepared on the surface of the plastic-encapsulated wafer after lamination and encapsulation by means of screen printing or laser ball placement.

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