Pixel driving circuit, driving method thereof and display panel

Abstract

The invention discloses a pixel driving circuit, a driving method and a display panel, and the pixel driving circuit comprises a driving sub-circuit which is configured to determine a driving current flowing between a fifth node (N5) and a fourth node (N4) under the control of signals of a first node (N1) and the fifth node (N5); the first control sub-circuit is configured to write a signal of a first initial signal line (Vint1) or a fourth node (N4) into a first node (N1) and write a signal of a second initial signal line (Vint2) into a third node (N3) under the control of signals of a first reset signal line (Reset1), a control signal line (CK) and a first scanning signal line (Gate1), and store a voltage difference between the signals of the first node (N1) and the second node (N2); a light emission control sub-circuit configured to provide a signal of a first power supply line (VDD) to a fifth node (N5) and a signal of a fourth node (N4) to a third node (N3) under the control of a signal of a light emission signal line (EM); and a second control sub-circuit configured to form a path among the data signal line (Vdata), the second node (N2) and the first power supply line (VDD) under the control of signals of the control signal line (CK) and the second scanning signal line (Gate2).

Description

Pixel driving circuit, driving method thereof and display panel TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, display technology, in particular to a pixel driving circuit, a driving method thereof and a display panel. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a pixel driving circuit, comprising: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, and a light-emitting control sub-circuit.

[0006] The driving sub-circuit is electrically connected with a first node, a fourth node, and a fifth node respectively, and is configured to determine a driving current flowing between the fourth node and the fifth node under the control of signals of the first node and the fifth node.

[0007] The first control sub-circuit is electrically connected with a first reset signal line, a control signal line, a first scan signal line, a first initial signal line, a second initial signal line, the first node, a second node, a third node, and the fourth node respectively, and is configured to write a signal of the first initial signal line or the fourth node to the first node, write a signal of the second initial signal line to the third node, and store a voltage difference of signals of the first node and the second node under the control of signals of the first reset signal line, the control signal line, and the first scan signal line.

[0008] The light-emitting control sub-circuit is electrically connected with a first power supply line, a light-emitting signal line, the third node, the fourth node, and the fifth node respectively, and is configured to provide a signal of the first power supply line to the fifth node and a signal of the fourth node to the third node under the control of a signal of the light-emitting signal line.

[0009] The second control sub-circuit is electrically connected with the control signal line, the second scan signal line, the data signal line, the second node and the first power supply line, and is configured to form a path between the data signal line, the second node and the first power supply line under the control of signals of the control signal line and the second scan signal line.

[0010] In some possible implementation manners, the second control sub-circuit includes a fourth transistor and a fifth transistor.

[0011] The control electrode of the fourth transistor is electrically connected with the control signal line, the first electrode of the fourth transistor is electrically connected with the first power supply line, and the second electrode of the fourth transistor is electrically connected with the second node.

[0012] The control electrode of the fifth transistor is electrically connected with the second scan signal line, the first electrode of the fifth transistor is electrically connected with the data signal line, and the second electrode of the fifth transistor is electrically connected with the second node.

[0013] In some possible implementation manners, the first control sub-circuit includes a second transistor, a third transistor, an eighth transistor and a first capacitor.

[0014] The control electrode of the second transistor is electrically connected with the first scan signal line, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the fourth node.

[0015] The control electrode of the third transistor is electrically connected with the first reset signal line, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the first initial signal line.

[0016] The control electrode of the eighth transistor is electrically connected with the control signal line, the first electrode of the eighth transistor is electrically connected with the second initial signal line, and the second electrode of the eighth transistor is electrically connected with the third node.

[0017] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first node, and the second plate of the first capacitor is electrically connected with the second node.

[0018] In some possible implementation manners, the driving sub-circuit includes a first transistor.

[0019] The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fifth node, and the second electrode of the first transistor is electrically connected with the fourth node.

[0020] In some possible implementation manners, the light-emitting signal line includes a first light-emitting signal line and a second light-emitting signal line, and the light-emitting control sub-circuit includes a sixth transistor and a seventh transistor.

[0021] The control electrode of the sixth transistor is electrically connected with the first light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the first power supply line, and the second electrode of the sixth transistor is electrically connected with the fifth node;

[0022] The control electrode of the seventh transistor is electrically connected with the second light-emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the third node.

[0023] In some possible implementation manners, the light-emitting signal line comprises a second light-emitting signal line, and the light-emitting control sub-circuit comprises a sixth transistor, a seventh transistor and a second capacitor, the second capacitor comprising a first plate and a second plate.

[0024] The control electrode of the sixth transistor is electrically connected with the first plate of the second capacitor, the first electrode of the sixth transistor is electrically connected with the first power supply line, and the second electrode of the sixth transistor is electrically connected with the fifth node and the second plate of the second capacitor, respectively.

[0025] The control electrode of the seventh transistor is electrically connected with the second light-emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the third node.

[0026] In some possible implementation manners, the pixel driving circuit further comprises a third control sub-circuit.

[0027] The third control sub-circuit is electrically connected with a second reset signal line, a third scan signal line, a bias voltage signal line, a reference signal line, a second node and a fifth node, respectively, and is configured to provide a signal of the reference signal line to the second node and a signal of the bias voltage signal line to the fifth node under the control of signals of the second reset signal line and the third scan signal line.

[0028] In some possible implementation manners, the third control sub-circuit comprises a ninth transistor and a tenth transistor.

[0029] The control electrode of the ninth transistor is electrically connected with the second reset signal line, the first electrode of the ninth transistor is electrically connected with the reference signal line, and the second electrode of the ninth transistor is electrically connected with the second node.

[0030] The control electrode of the tenth transistor is electrically connected with the third scan signal line, the first electrode of the tenth transistor is electrically connected with the fifth node, and the second electrode of the tenth transistor is electrically connected with the bias voltage signal line.

[0031] In some possible implementation manners, the control signal line is a second reset signal line, the driving sub-circuit comprises a first transistor, the first control sub-circuit comprises a second transistor, a third transistor, an eighth transistor and a first capacitor, the second control sub-circuit comprises a fourth transistor and a fifth transistor, and the light-emitting control sub-circuit comprises a sixth transistor and a seventh transistor.

[0032] a control electrode of the first transistor is electrically connected with the first node, a first electrode of the first transistor is electrically connected with the fifth node, and a second electrode of the first transistor is electrically connected with the fourth node;

[0033] a control electrode of the second transistor is electrically connected with the first scan signal line, a first electrode of the second transistor is electrically connected with the first node, and a second electrode of the second transistor is electrically connected with the fourth node;

[0034] a control electrode of the third transistor is electrically connected with the first reset signal line, a first electrode of the third transistor is electrically connected with the first node, and a second electrode of the third transistor is electrically connected with the first initial signal line;

[0035] a control electrode of the fourth transistor is electrically connected with the second reset signal line, a first electrode of the fourth transistor is electrically connected with the first power supply line, and a second electrode of the fourth transistor is electrically connected with the second node;

[0036] a control electrode of the fifth transistor is electrically connected with the second scan signal line, a first electrode of the fifth transistor is electrically connected with the data signal line, and a second electrode of the fifth transistor is electrically connected with the second node;

[0037] a control electrode of the sixth transistor is electrically connected with the first emission signal line, a first electrode of the sixth transistor is electrically connected with the first power supply line, and a second electrode of the sixth transistor is electrically connected with the fifth node;

[0038] a control electrode of the seventh transistor is electrically connected with the second emission signal line, a first electrode of the seventh transistor is electrically connected with the fourth node, and a second electrode of the seventh transistor is electrically connected with the third node;

[0039] a control electrode of the eighth transistor is electrically connected with the second reset signal line, a first electrode of the eighth transistor is electrically connected with the second initial signal line, and a second electrode of the eighth transistor is electrically connected with the third node;

[0040] the first capacitor comprises a first plate and a second plate, a first plate of the first capacitor is electrically connected with the first node, and a second plate of the first capacitor is electrically connected with the second node.

[0041] In some possible implementation manners, the control signal line is a second reset signal line, the driving sub-circuit comprises a first transistor, the first control sub-circuit comprises a second transistor, a third transistor, an eighth transistor and a first capacitor, the second control sub-circuit comprises a fourth transistor and a fifth transistor, the emission control sub-circuit comprises a sixth transistor, a seventh transistor and a second capacitor, and the second capacitor comprises a first plate and a second plate;

[0042] a control electrode of the first transistor is electrically connected with the first node, a first electrode of the first transistor is electrically connected with the fifth node, and a second electrode of the first transistor is electrically connected with the fourth node;

[0043] a control electrode of the second transistor is electrically connected with the first scan signal line, a first electrode of the second transistor is electrically connected with the first node, and a second electrode of the second transistor is electrically connected with the fourth node;

[0044] a control electrode of the third transistor is electrically connected with the first reset signal line, a first electrode of the third transistor is electrically connected with the first node, and a second electrode of the third transistor is electrically connected with the first initial signal line;

[0045] a control electrode of the fourth transistor is electrically connected with the second reset signal line, a first electrode of the fourth transistor is electrically connected with the first power supply line, and a second electrode of the fourth transistor is electrically connected with the second node;

[0046] a control electrode of the fifth transistor is electrically connected with the second scan signal line, a first electrode of the fifth transistor is electrically connected with the data signal line, and a second electrode of the fifth transistor is electrically connected with the second node;

[0047] a control electrode of the sixth transistor is electrically connected with the first plate electrode of the second capacitor, a first electrode of the sixth transistor is electrically connected with the first power supply line, and a second electrode of the sixth transistor is electrically connected with the fifth node and the second plate electrode of the second capacitor respectively;

[0048] a control electrode of the seventh transistor is electrically connected with the second emitting signal line, a first electrode of the seventh transistor is electrically connected with the fourth node, and a second electrode of the seventh transistor is electrically connected with the third node;

[0049] a control electrode of the eighth transistor is electrically connected with the second reset signal line, a first electrode of the eighth transistor is electrically connected with the second initial signal line, and a second electrode of the eighth transistor is electrically connected with the third node;

[0050] the first capacitor comprises a first plate electrode and a second plate electrode, the first plate electrode of the first capacitor is electrically connected with the first node, and the second plate electrode of the first capacitor is electrically connected with the second node.

[0051] In some possible implementation manners, the control signal line is a first reset signal line, the driving sub-circuit comprises a first transistor, the first control sub-circuit comprises a second transistor, a third transistor, an eighth transistor and a first capacitor, the second control sub-circuit comprises a fourth transistor and a fifth transistor, and the emitting control sub-circuit comprises a sixth transistor and a seventh transistor;

[0052] a control electrode of the first transistor is electrically connected with the first node, a first electrode of the first transistor is electrically connected with the fifth node, and a second electrode of the first transistor is electrically connected with the fourth node;

[0053] a control electrode of the second transistor is electrically connected with the first scan signal line, a first electrode of the second transistor is electrically connected with the first node, and a second electrode of the second transistor is electrically connected with the fourth node;

[0054] The control electrode of the third transistor is electrically connected with the first reset signal line, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the first initial signal line;

[0055] The control electrode of the fourth transistor is electrically connected with the first reset signal line, the first electrode of the fourth transistor is electrically connected with the first power supply line, and the second electrode of the fourth transistor is electrically connected with the second node;

[0056] The control electrode of the fifth transistor is electrically connected with the second scan signal line, the first electrode of the fifth transistor is electrically connected with the data signal line, and the second electrode of the fifth transistor is electrically connected with the second node;

[0057] The control electrode of the sixth transistor is electrically connected with the first emitting signal line, the first electrode of the sixth transistor is electrically connected with the first power supply line, and the second electrode of the sixth transistor is electrically connected with the fifth node;

[0058] The control electrode of the seventh transistor is electrically connected with the second emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the third node;

[0059] The control electrode of the eighth transistor is electrically connected with the first reset signal line, the first electrode of the eighth transistor is electrically connected with the second initial signal line, and the second electrode of the eighth transistor is electrically connected with the third node;

[0060] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first node, and the second plate of the first capacitor is electrically connected with the second node.

[0061] In some possible implementation manners, the fourth transistor and the eighth transistor are of the same transistor type as the fifth transistor;

[0062] The first transistor, the fourth transistor to the eighth transistor are P-type transistors, and the second transistor and the third transistor are N-type transistors.

[0063] In some possible implementation manners, the control signal line is a second scan signal line, the driving sub-circuit includes a first transistor, the first control sub-circuit includes a second transistor, a third transistor, an eighth transistor and a first capacitor, the second control sub-circuit includes a fourth transistor and a fifth transistor, and the emitting control sub-circuit includes a sixth transistor and a seventh transistor;

[0064] The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fifth node, and the second electrode of the first transistor is electrically connected with the fourth node;

[0065] The control electrode of the second transistor is electrically connected with the first scan signal line, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the fourth node;

[0066] The control electrode of the third transistor is electrically connected with the first reset signal line, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the first initial signal line;

[0067] The control electrode of the fourth transistor is electrically connected with the second scan signal line, the first electrode of the fourth transistor is electrically connected with the first power supply line, and the second electrode of the fourth transistor is electrically connected with the second node;

[0068] The control electrode of the fifth transistor is electrically connected with the second scan signal line, the first electrode of the fifth transistor is electrically connected with the data signal line, and the second electrode of the fifth transistor is electrically connected with the second node;

[0069] The control electrode of the sixth transistor is electrically connected with the first emitting signal line, the first electrode of the sixth transistor is electrically connected with the first power supply line, and the second electrode of the sixth transistor is electrically connected with the fifth node;

[0070] The control electrode of the seventh transistor is electrically connected with the second emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the third node;

[0071] The control electrode of the eighth transistor is electrically connected with the second scan signal line, the first electrode of the eighth transistor is electrically connected with the second initial signal line, and the second electrode of the eighth transistor is electrically connected with the third node;

[0072] The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first node, and the second plate of the first capacitor is electrically connected with the second node.

[0073] In some possible implementation manners, the fourth transistor and the eighth transistor are opposite to the transistor type of the fifth transistor;

[0074] The first transistor, the fifth transistor to the seventh transistor are P-type transistors, and the second transistor to the fourth transistor and the eighth transistor are N-type transistors.

[0075] In some possible implementation manners, the pixel driving circuit further comprises a ninth transistor and a tenth transistor;

[0076] The control electrode of the ninth transistor is electrically connected with the second reset signal line, the first electrode of the ninth transistor is electrically connected with the reference signal line, and the second electrode of the ninth transistor is electrically connected with the second node;

[0077] The control electrode of the tenth transistor is electrically connected with the third scan signal line, the first electrode of the tenth transistor is electrically connected with the fifth node, and the second electrode of the tenth transistor is electrically connected with the bias signal line.

[0078] In a second aspect, the embodiments of the present disclosure provide a display panel, comprising the pixel driving circuit according to any one of the embodiments of the first aspect.

[0079] In a third aspect, the embodiments of the present disclosure provide a driving method of a pixel driving circuit, configured to drive the pixel driving circuit according to any one of the embodiments of the first aspect, and the method comprises:

[0080] The driving sub-circuit determines the driving current flowing between the fifth node and the fourth node under the control of the potential difference between the signals of the first node and the fifth node;

[0081] The first control sub-circuit writes the signal of the first initial signal line to the first node under the control of the signal of the first reset signal line, writes the signal of the second initial signal line to the third node under the control of the signal of the control signal line, and performs voltage compensation on the first node under the control of the signal of the first scan signal line;

[0082] The light-emitting control sub-circuit forms the driving current between the first power supply line and the third node under the control of the signal of the light-emitting signal line;

[0083] The second control sub-circuit forms a path between the data signal line and the first power supply line under the control of the signals of the control signal line and the second scan signal line.

[0084] Other aspects can become apparent from a review of the drawings and detailed description.

[0085] SUMMARY

[0086] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the embodiments of the present disclosure serve to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0087] FIG. 1 is a structural schematic diagram of a pixel driving circuit according to an example embodiment of the present disclosure;

[0088] FIG. 2 is an equivalent circuit diagram of a driving sub-circuit according to an example embodiment;

[0089] FIG. 3 is an equivalent circuit diagram of a first control sub-circuit according to an example embodiment;

[0090] FIG. 4 is an equivalent circuit diagram of a second control sub-circuit according to an example embodiment;

[0091] FIG. 5 is an equivalent circuit diagram of a light emitting control sub-circuit according to an example embodiment;

[0092] FIG. 6 is an equivalent circuit diagram of a light emitting control sub-circuit according to an example embodiment;

[0093] FIG. 7 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment;

[0094] FIG. 8 is an equivalent circuit diagram of a third control sub-circuit according to an example embodiment;

[0095] FIG. 9 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment;

[0096] FIG. 10 is a timing diagram of the pixel driving circuit according to FIG. 9;

[0097] FIG. 11A is an equivalent circuit diagram of a pixel driving circuit during a first operation;

[0098] FIG. 11B is an equivalent circuit diagram of a pixel driving circuit during a second operation;

[0099] FIG. 11C is an equivalent circuit diagram of a pixel driving circuit during a third operation;

[0100] FIG. 11D is an equivalent circuit diagram of a pixel driving circuit during a fourth operation;

[0101] FIG. 12 is a test path diagram of a pixel driving circuit according to an example embodiment;

[0102] FIG. 13 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment;

[0103] FIG. 14 is a timing diagram of the pixel driving circuit according to FIG. 13;

[0104] FIG. 15 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment;

[0105] FIG. 16 is a timing diagram of the pixel driving circuit according to FIG. 15;

[0106] FIG. 17 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment;

[0107] FIG. 18 is a timing diagram of the pixel driving circuit according to FIG. 17.

[0108] DETAILED DESCRIPTION

[0109] For the purpose of making the objects, technical solutions and advantages of the present disclosure clearer, the following will describe the embodiments of the present disclosure in detail with reference to the drawings. Note that the embodiments can be implemented in a variety of different forms. It should be understood by those skilled in the art that the embodiments and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0110] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0111] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of components, and are not intended to be limiting in terms of number.

[0112] In the present specification, for the purpose of convenience, words indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the purpose of facilitating the description of the present specification and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0113] In the present specification, unless explicitly specified and limited, the terms "mount", "connect", "connection" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0114] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode line, a drain region, or a drain electrode) and the source electrode (a source electrode line, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0115] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. In the case of using a transistor having opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0116] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0117] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0118] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be changed into "a conductive film". Similarly, "an insulating film" can be changed into "an insulating layer".

[0119] In this specification, "formation in the same layer" means that two (or more) structures are formed by patterning in the same process, and the materials thereof can be the same or different. For example, the materials of precursors used for forming the two (or more) structures in the same layer are the same, and the materials of the formed structures can be the same or different.

[0120] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximately triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, a rounded corner, a curved side, or the like.

[0121] In the present disclosure, "about" means not strictly limited boundaries, allowing values within the range of process and measurement errors.

[0122] The display panel of the OLED or QLED includes a substrate and a plurality of sub-pixels disposed on the substrate, at least one of the sub-pixels including a pixel driving circuit. When performing array testing, the pixel driving circuit cannot form a path between the data signal line and the first power supply line, affecting the test results.

[0123] FIG. 1 is a structural schematic diagram of a pixel driving circuit provided by an example embodiment of the present disclosure. As shown in FIG. 1, the pixel driving circuit can include a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, and a light-emitting control sub-circuit.

[0124] The driving sub-circuit is electrically connected with the first node N1, the fourth node N4, and the fifth node N5, respectively, and is configured to determine a driving current flowing between the fifth node N5 and the fourth node N4 under the control of signals of the first node N1 and the fifth node N5.

[0125] The first control sub-circuit is electrically connected with the first reset signal line Reset1, the control signal line CK, the first scan signal line Gate1, the first initial signal line Vint1, the second initial signal line Vint2, the first node N1, the second node N2, the third node N3, and the fourth node N4, respectively, and is configured to write the signal of the first initial signal line Vint1 or the fourth node N4 to the first node N1, write the signal of the second initial signal line Vint2 to the third node N3, and store the voltage difference of the signals of the first node N1 and the second node N2 under the control of the signals of the first reset signal line Reset1, the control signal line CK, and the first scan signal line Gate1.

[0126] The light-emitting control sub-circuit is electrically connected with the first power supply line VDD, the light-emitting signal line EM, the third node N3, the fourth node N4, and the fifth node N5, respectively, and is configured to provide the signal of the first power supply line VDD to the fifth node N5 and provide the signal of the fourth node N4 to the third node N3 under the control of the signal of the light-emitting signal line EM.

[0127] The second control sub-circuit is electrically connected with the control signal line CK, the second scan signal line Gate2, the data signal line Vdata, the second node N2, and the first power supply line VDD, respectively, and is configured to form a path between the data signal line Vdata, the second node N2, and the first power supply line VDD under the control of the signals of the control signal line CK and the second scan signal line Gate2.

[0128] In an example embodiment, the signal of the first power supply line VDD is continuously provided as a high-level signal.

[0129] The second control sub-circuit can form a path between the data signal line, the second node and the first power supply line. When the pixel driving circuit is performing array testing, a path can be formed between the data signal line and the first power supply line, and the driving sub-circuit and the like can be tested through the data signal line, thereby improving the effectiveness of testing.

[0130] FIG. 2 is an equivalent circuit diagram of a driving sub-circuit according to an example embodiment. As shown in FIG. 2, in an example embodiment, the driving sub-circuit can include a first transistor T1.

[0131] In an example embodiment, as shown in FIG. 2, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fifth node N5, and the second electrode of the first transistor T1 is electrically connected with the fourth node N4.

[0132] In an example embodiment, the first transistor T1 can be referred to as a driving transistor, and the driving current flowing between the fifth node N5 and the fourth node N4 (between the first power supply line VDD and the second power supply line VSS) is determined according to the potential difference between the gate electrode (also the first node N1) and the first electrode (also the fifth node N5) of the first transistor T1.

[0133] An example structure of the driving sub-circuit is shown in FIG. 2. It is easy for those skilled in the art to understand that the implementation of the driving sub-circuit is not limited thereto.

[0134] FIG. 3 is an equivalent circuit diagram of a first control sub-circuit according to an example embodiment. As shown in FIG. 3, in an example embodiment, the first control sub-circuit can include a second transistor T2, a third transistor T3, an eighth transistor T8 and a first capacitor C1.

[0135] In an example embodiment, as shown in FIG. 3, the control electrode of the second transistor T2 is electrically connected with the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected with the first node N1, and the second electrode of the second transistor T2 is electrically connected with the fourth node N4; the control electrode of the third transistor T3 is electrically connected with the first reset signal line Reset1, the first electrode of the third transistor T3 is electrically connected with the first node N1, and the second electrode of the third transistor T3 is electrically connected with the first initial signal line Vint1; the control electrode of the eighth transistor T8 is electrically connected with the control signal line CK, the first electrode of the eighth transistor T8 is electrically connected with the second initial signal line Vint2, and the second electrode of the eighth transistor T8 is electrically connected with the third node N3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the first node N1, and the second plate C12 of the first capacitor is electrically connected with the second node N2.

[0136] In an example embodiment, as shown in FIG. 3, the third node can also be connected with a light emitting device L, a first pole of the light emitting device L being electrically connected with the third node N3, and a second pole of the light emitting device L being electrically connected with the second power supply line VSS.

[0137] In an example embodiment, the light emitting device L can be an organic electroluminescence diode (OLED) or a quantum dot light emitting diode (QLED). The OLED can include a first pole (anode), an organic light emitting layer, and a second pole (cathode) stacked.

[0138] In an example embodiment, the signal of the second power supply line VSS is a low-level signal.

[0139] In an example embodiment, the second transistor T2 can be referred to as a compensation transistor, and when the first scanning signal line Gate1 inputs a valid level signal, the second transistor T2 writes the signal of the fourth node N4 to the first node N1.

[0140] In an example embodiment, the third transistor T3 can be referred to as a node reset transistor, and when the first reset signal line Reset1 inputs a valid level signal, the third transistor T3 writes the signal of the first initial signal line Vint1 to the first node N1 to initialize the charge amount of the first node N1.

[0141] In an example embodiment, the eighth transistor T8 can be referred to as an anode reset transistor, and when the control signal line CK provides a valid level signal, the eighth transistor T8 transmits the signal of the second initial signal line Vinit2 to the anode of the light emitting element L (also the third node N3) to initialize the charge amount of the anode of the light emitting element.

[0142] An example structure of the first control sub-circuit is shown in FIG. 3. It is easy for those skilled in the art to understand that the implementation of the first control sub-circuit is not limited to this.

[0143] FIG. 4 is an equivalent circuit diagram of a second control sub-circuit provided by an example embodiment. As shown in FIG. 4, in an example embodiment, the second control sub-circuit can include a fourth transistor T4 and a fifth transistor T5.

[0144] In an example embodiment, as shown in FIG. 4, the control pole of the fourth transistor T4 is electrically connected with the control signal line CK, the first pole of the fourth transistor T4 is electrically connected with the first power supply line VDD, and the second pole of the fourth transistor T4 is electrically connected with the second node N2; the control pole of the fifth transistor T5 is electrically connected with the second scanning signal line Gate2, the first pole of the fifth transistor T5 is electrically connected with the data signal line Vdata, and the second pole of the fifth transistor T5 is electrically connected with the second node N2.

[0145] In an example embodiment, the fifth transistor T5 can be referred to as a write transistor, which writes a signal of the data signal line Vdata to the second node when the second scan signal line Gate2 inputs a valid level signal.

[0146] An example structure of the second control sub-circuit is shown in FIG. 4. It is easily understood by those skilled in the art that the implementation of the second control sub-circuit is not limited to this.

[0147] An equivalent circuit diagram of the light emitting control sub-circuit provided by an example embodiment is shown in FIG. 5. As shown in FIG. 5, in an example embodiment, the light emitting signal line can include a first light emitting signal line EM1 and a second light emitting signal line EM2, and the light emitting control sub-circuit can include a sixth transistor T6 and a seventh transistor T7.

[0148] In an example embodiment, as shown in FIG. 5, the control electrode of the sixth transistor T6 is electrically connected with the first light emitting signal line EM1, the first electrode of the sixth transistor T6 is electrically connected with the first power supply line VDD, and the second electrode of the sixth transistor T6 is electrically connected with the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected with the second light emitting signal line EM2, the first electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected with the third node N3.

[0149] In an example embodiment, the sixth transistor T6 can be referred to as a first light emitting transistor, and the seventh transistor T7 can be referred to as a second light emitting transistor. When the first light emitting signal line EM1 and the second light emitting signal line EM2 input valid level signals, the sixth transistor T6 and the seventh transistor T7 make the light emitting device L emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0150] An example structure of the light emitting control sub-circuit is shown in FIG. 5. It is easily understood by those skilled in the art that the implementation of the light emitting control sub-circuit is not limited to this.

[0151] An equivalent circuit diagram of the light emitting control sub-circuit provided by an example embodiment is shown in FIG. 6. As shown in FIG. 6, in an example embodiment, the light emitting signal line can include a second light emitting control signal EM2, and the light emitting control sub-circuit can include a sixth transistor T6, a seventh transistor T7, and a second capacitor C2.

[0152] In an example embodiment, as shown in FIG. 6, the second capacitor C2 includes a first plate C21 and a second plate C22; the control electrode of the sixth transistor T6 is electrically connected with the first plate C21 of the second capacitor, the first electrode of the sixth transistor T6 is electrically connected with the first power supply line VDD, and the second electrode of the sixth transistor T6 is electrically connected with the fifth node N5 and the second plate C22 of the second capacitor respectively; the control electrode of the seventh transistor T7 is electrically connected with the second emission signal line EM2, the first electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected with the third node N3.

[0153] The control electrode of the sixth transistor T6 is electrically connected with the second capacitor, without the need to increase the first emission signal line, reducing the number of signal lines, and performing online testing on the second end of the sixth transistor T6 through the signal timing of the second emission signal line EM2 before the signal timing of the second emission signal line EM2, improving the display deterioration problem caused by the bias of the sixth transistor T6.

[0154] In an example embodiment, the sixth transistor T6 can be referred to as a first emission transistor, and the seventh transistor T7 can be referred to as a second emission transistor. When the second emission signal line EM2 inputs an effective level signal, the sixth transistor T6 and the seventh transistor T7 make the light emitting device L emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0155] An example structure of the light emission control sub-circuit is shown in FIG. 6. It is easy for those skilled in the art to understand that the implementation of the light emission control sub-circuit is not limited to this.

[0156] FIG. 7 is an equivalent circuit diagram of a pixel driving circuit provided by an example embodiment. As shown in FIG. 7, in an example embodiment, the pixel driving circuit can include a third control sub-circuit.

[0157] In an example embodiment, as shown in FIG. 7, the third control sub-circuit is electrically connected with the second reset signal line Reset2, the third scan signal line Gate3, the bias signal line Vbias, the reference signal line Vref, the second node N2 and the fifth node N5 respectively, and is configured to provide the signal of the reference signal line Vref to the second node N2 and provide the signal of the bias signal line Vbias to the fifth node N5 under the control of the signals of the second reset signal line Reset2 and the third scan signal line Gate3.

[0158] FIG. 8 is an equivalent circuit diagram of the third control sub-circuit provided by an example embodiment. As shown in FIG. 8, in an example embodiment, the third control sub-circuit can include a ninth transistor T9 and a tenth transistor T10.

[0159] In an example embodiment, as shown in FIG. 8, the control electrode of the ninth transistor T9 is electrically connected with the second reset signal line Reset2, the first electrode of the ninth transistor T9 is electrically connected with the reference signal line Vref, and the second electrode of the ninth transistor T9 is electrically connected with the second node N2; the control electrode of the tenth transistor T10 is electrically connected with the third scan signal line Gate3, the first electrode of the tenth transistor T10 is electrically connected with the fifth node, and the second electrode of the tenth transistor T10 is electrically connected with the bias signal line Vbias.

[0160] An example structure of the third control sub-circuit is shown in FIG. 8. It is easily understood by those skilled in the art that the implementation of the third control sub-circuit is not limited to this.

[0161] FIG. 9 is an equivalent circuit schematic diagram of a pixel driving circuit. As shown in FIG. 9, the control signal line can be the second reset signal line Reset2, the driving sub-circuit can include the first transistor T1, the first control sub-circuit can include the second transistor T2, the third transistor T3, the eighth transistor T8 and the first capacitor C1, the second control sub-circuit can include the fourth transistor T4 and the fifth transistor T5, and the light emitting control sub-circuit can include the sixth transistor T6 and the seventh transistor T7.

[0162] In an example embodiment, as shown in FIG. 9, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fifth node N5, and the second electrode of the first transistor T1 is electrically connected with the fourth node N4; the control electrode of the second transistor T2 is electrically connected with the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected with the first node N1, and the second electrode of the second transistor T2 is electrically connected with the fourth node N4; the control electrode of the third transistor T3 is electrically connected with the first reset signal line Reset1, the first electrode of the third transistor T3 is electrically connected with the first node N1, and the second electrode of the third transistor T3 is electrically connected with the first initial signal line Vint1; the control electrode of the fourth transistor T4 is electrically connected with the second reset signal line Reset2, the first electrode of the fourth transistor T4 is electrically connected with the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the second scan signal line Gate2, the first electrode of the fifth transistor T5 is electrically connected with the data signal line Vdata, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with the first emission signal line EM1, the first electrode of the sixth transistor T6 is electrically connected with the first power supply line VDD, and the second electrode of the sixth transistor T6 is electrically connected with the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected with the second emission signal line EM2, the first electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected with the third node N3; the control electrode of the eighth transistor T8 is electrically connected with the second reset signal line Reset2, the first electrode of the eighth transistor T8 is electrically connected with the second initial signal line Vint2, and the second electrode of the eighth transistor T8 is electrically connected with the third node N3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the first node N1, and the second plate C12 of the first capacitor is electrically connected with the second node N2.

[0163] In an example embodiment, the second reset signal line Reset2 connected with the fourth transistor T4 and the second reset signal line Reset2 connected with the eighth transistor T8 can be the same signal line or different signal lines with the same signal, and the present disclosure does not make any limitation in this regard.

[0164] In an example embodiment, the fourth transistor T4 and the eighth transistor T8 are of the same transistor type as the fifth transistor T5.

[0165] In an example embodiment, as shown in FIG. 9, the first transistor T1, the fourth transistor T4 to the eighth transistor T8 are P-type transistors, and the second transistor T2 and the third transistor T3 are N-type transistors.

[0166] FIG. 10 is a timing diagram of the pixel driving circuit provided in FIG. 9, FIG. 11A is an equivalent circuit diagram of a first working process of the pixel driving circuit, FIG. 11B is an equivalent circuit diagram of a second working process of the pixel driving circuit, FIG. 11C is an equivalent circuit diagram of a third working process of the pixel driving circuit, and FIG. 11D is an equivalent circuit diagram of a fourth working process of the pixel driving circuit. The working processes of the pixel driving circuit exemplified by FIG. 9 are described below, and the working processes of the pixel driving circuit can include:

[0167] The first stage S1 is referred to as an initialization stage. The signals of the first reset signal line Reset1, the second scan signal line Gate2, the first emission signal line EM1, and the second emission signal line EM2 are all high-level signals, and the signals of the second reset signal line Reset2 and the first scan signal line Gate1 are both low-level signals. The signal of the first reset signal line Reset1 is a high-level signal, the third transistor T3 is turned on, the third transistor T3 initializes the gate electrode (also the first node N1) of the first transistor T1, and the signal of the first initialization signal line Vinit1 is provided to the first node N1. The signal of the second reset signal line Reset2 is a low-level signal, the eighth transistor T8 is turned on, the initial voltage of the second initialization signal line Vinit2 is provided to the third node N3, and the eighth transistor T8 initializes the anode potential. The fourth transistor T4 is turned on, and the voltage of the first power supply line VDD is written to the second node N2 to stabilize the potential of the first node N1 and ensure that the gate electrode of the first transistor T1 is initialized. At this time, the voltage value of the signal of the first node N1 is equal to the voltage of the first initialization signal line Vint1, the voltage value of the signal of the second node N2 is equal to the voltage of the first power supply line VDD, and the voltage value of the signal of the third node N3 is equal to the voltage of the second initialization signal line Vint2. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0168] The third node N3 is electrically connected to the first electrode of the light emitting device L. When the eighth transistor T8 is turned on, the third node N3 provides the initial voltage of the second initialization signal line Vinit2 to the first electrode of the light emitting device L to initialize (reset) the first electrode of the light emitting device L, for example, to empty the pre-stored voltage in the first electrode, complete the initialization, and ensure that the light emitting device L does not emit light. In this stage, the light emitting device L does not emit light.

[0169] The second stage S2 is called a compensation stage, signals of the first scan signal line Gate1, the second scan signal line Gate2 and the second light-emitting signal line EM2 are all high level signals, and signals of the first reset signal line Reset1, the second reset signal line Reset2 and the first light-emitting signal line EM1 are all low level signals. The signal of the second reset signal line Reset2 is a low level signal, the fourth transistor T4 and the eighth transistor T8 are turned on, and potentials of the third node N3 and the second node N2 remain potentials of the last stage. The signal of the first scan signal line Gate1 is a high level signal, the second transistor T2 is turned on, the signal of the first light-emitting signal line EM1 is a low level signal, the sixth light-emitting transistor T6 is turned on, and the second transistor T2, the first transistor T1 and the sixth transistor T6 are turned on, so that the voltage output by the first power supply line VDD is provided to the first node N1 through the turned-on sixth transistor T6, the fifth node N5, the turned-on first transistor T1, the fourth node N4 and the turned-on second transistor T2, and the difference between the voltage VDD output by the first power supply line and the threshold voltage of the first transistor T1 is charged into the first capacitor C1, until the voltage of the first node N1 is Vd+Vth, Vd is the voltage output by the first power supply line VDD, and Vth is the threshold voltage of the first transistor T1. In this stage, the voltage of the first node N1 is Vd+Vth, the voltage of the second node N2 is the voltage Vd of the first power supply line VDD, and the voltage of the third node N3 is the voltage of the second initial signal line Vint2. The third transistor T3, the fifth transistor T5 and the seventh transistor T7 are turned off. In this stage, the light-emitting device L does not emit light.

[0170] The third stage S3 is called a writing stage, signals of the second reset signal line Reset2, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are all high level signals, and signals of the first reset signal line Reset1, the first scan signal line Gate1 and the second scan signal line Gate2 are all low level signals. The signal of the second scan signal line Gate2 is a low level signal, the fifth transistor T5 is turned on, and the data signal of the data signal line Vdata is written into the second node N2 through the turned-on fifth transistor T5, the voltage value of the signal of the second node N2 is Vdata, Vdata is the voltage value of the data signal, and the voltage value of the signal of the second node N2 jumps in this stage compared with the voltage value in the last stage. Therefore, under the action of the first capacitor C1, the voltage value of the signal of the first node N1 also jumps, at this time, the voltage value of the signal of the first node N1 is Vd+Vth+(Vdata-Vd). The second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. In this stage, the light-emitting device L does not emit light.

[0171] The fourth stage S4 is called a light emitting stage. The signal of the second reset signal line Reset2 is a high level signal. The signals of the first reset signal line Reset1, the first scan signal line Gate1, the second scan signal line Gate2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are all low level signals. The signal of the first light emitting signal line EM1 is a low level signal, the sixth transistor T6 is turned on, the signal of the second light emitting signal line EM2 is a low level signal, the seventh transistor T7 is turned on, and the voltage Vd output by the first power supply line VDD provides a driving voltage for the first electrode of the light emitting device L through the turned-on sixth transistor T6, the first transistor T1 and the seventh transistor T7, so as to drive the light emitting device L to emit light. The second transistor T2, the third transistor T3, the fourth transistor T4 and the eighth transistor T8 are turned off. In this stage, the light emitting device L emits light.

[0172] In the driving process of the pixel circuit, the driving current flowing through the first transistor T1 is determined by the voltage difference between the gate electrode (also the first node N1) and the first electrode. Since the voltage value of the signal of the first node N1 is Vd+Vth+(Vdata-Vd)=Vth+Vdata, the driving current of the first transistor T1 is I=K*(Vgs-Vth) 2 =K*[(Vth+Vdata-Vd)-Vth] 2 =K*(Vdata-Vd) 2 . Wherein I is the driving current flowing through the first transistor T1, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the first transistor T1.

[0173] FIG. 12 is a schematic diagram of a test path of a pixel driving circuit. As shown in FIG. 12, the gate electrode of the first transistor can be initialized through the turned-on third transistor T3, the anode end can be initialized through the eighth transistor T8, and the initialization path P0 can be formed through the turned-on at least one of the third transistor T3 and the eighth transistor T8.

[0174] In an example embodiment, the test path P1 can be formed through the turned-on third transistor T3, the second transistor T2, the first transistor T1, the sixth transistor T6, the fourth transistor T4 and the fifth transistor T5.

[0175] In an example embodiment, as shown in FIG. 12, the test path P2 can be formed through the turned-on eighth transistor T8, the seventh transistor T7, the first transistor T1, the sixth transistor T6, the fourth transistor T4 and the fifth transistor.

[0176] In the embodiment of the present disclosure, the second control sub-circuit can form a path between the data signal line, the second node and the first power supply line, that is, a path can be formed between the data signal line and the first power supply line. When the pixel driving circuit is tested, each transistor in the pixel driving circuit can be tested, so that the problem that some transistors in the pixel driving circuit cannot be detected due to missing test of the transistors is avoided, and the effectiveness of transistor test in the pixel driving circuit is improved.

[0177] FIG. 13 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 13, the control signal line can be a second reset signal line Reset2, the driving sub-circuit can include a first transistor T1, the first control sub-circuit can include a second transistor T2, a third transistor T3, an eighth transistor T8 and a first capacitor C1, the second control sub-circuit can include a fourth transistor T4 and a fifth transistor T5, and the light emitting control sub-circuit can include a sixth transistor T6, a seventh transistor T7 and a second capacitor C2. The second capacitor C2 includes a first plate C21 and a second plate C22.

[0178] In an example embodiment, as shown in FIG. 13, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fifth node N5, and the second electrode of the first transistor T1 is electrically connected with the fourth node N4; the control electrode of the second transistor T2 is electrically connected with the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected with the first node N1, and the second electrode of the second transistor T2 is electrically connected with the fourth node N4; the control electrode of the third transistor T3 is electrically connected with the first reset signal line Reset1, the first electrode of the third transistor T3 is electrically connected with the first node N1, and the second electrode of the third transistor T3 is electrically connected with the first initial signal line Vint1; the control electrode of the fourth transistor T4 is electrically connected with the second reset signal line Reset2, the first electrode of the fourth transistor T4 is electrically connected with the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the second scan signal line Gate2, the first electrode of the fifth transistor T5 is electrically connected with the data signal line Vdata, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with the first plate C21 of the second capacitor, the first electrode of the sixth transistor T6 is electrically connected with the first power supply line VDD, and the second electrode of the sixth transistor T6 is electrically connected with the fifth node N5 and the second plate C22 of the second capacitor; the control electrode of the seventh transistor T7 is electrically connected with the second emitting signal line EM2, the first electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected with the third node N3; the control electrode of the eighth transistor T8 is electrically connected with the second reset signal line Reset2, the first electrode of the eighth transistor T8 is electrically connected with the second initial signal line Vint2, and the second electrode of the eighth transistor T8 is electrically connected with the third node N3; the first capacitor C1 includes the first plate C11 and the second plate C12, the first plate C11 of the first capacitor is electrically connected with the first node N1, and the second plate C12 of the first capacitor is electrically connected with the second node N2.

[0179] In an example embodiment, the second reset signal line Reset2 connected with the fourth transistor T4 and the second reset signal line Reset2 connected with the eighth transistor T8 can be the same signal line or different signal lines with the same signal, and the present disclosure does not make any limitation in this regard.

[0180] In an example embodiment, the fourth transistor T4 and the eighth transistor T8 are of the same transistor type as the fifth transistor T5.

[0181] In an example embodiment, as shown in FIG. 13, the first transistor T1, the fourth transistor T4 to the eighth transistor T8 are P-type transistors, and the second transistor T2 and the third transistor T3 are N-type transistors.

[0182] FIG. 14 is a timing diagram of the pixel driving circuit provided in FIG. 13, and the working process of the pixel driving circuit exemplified by FIG. 13 is described below to illustrate the exemplary embodiments of the present disclosure. The working process of the pixel driving circuit can include:

[0183] The first stage S1 is referred to as the initial stage, the signals of the first reset signal line Reset1, the second scan signal line Gate2 and the second emission signal line EM2 are all high level signals, and the signals of the second reset signal line Reset2 and the first scan signal line Gate1 are all low level signals. The signal of the first reset signal line Reset1 is a high level signal, the third transistor T3 is turned on, the third transistor T3 initializes the gate electrode (also the first node N1) of the first transistor T1, and the signal of the first initial signal line Vinit1 is provided to the first node N1. The signal of the second reset signal line Reset2 is a low level signal, the eighth transistor T8 is turned on, the initial voltage of the second initial signal line Vinit2 is provided to the third node N3, and the eighth transistor T8 initializes the anode potential. The fourth transistor T4 is turned on, and the voltage of the first power supply line VDD is written to the second node N2 to stabilize the potential of the first node N1 and ensure the gate point initialization of the first transistor T1. At this time, the voltage value of the signal of the first node N1 is equal to the voltage of the first initial signal line Vint1, the voltage value of the signal of the second node N2 is equal to the voltage of the first power supply line VDD, and the voltage value of the signal of the third node N3 is equal to the voltage of the second initial signal line Vint2. Among them, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are disconnected.

[0184] The third node N3 is electrically connected to the first pole of the light emitting device L, and when the eighth transistor T8 is turned on, the third node N3 provides the initial voltage of the second initial signal line Vinit2 to the first pole of the light emitting device L to initialize (reset) the first pole of the light emitting device L, for example: empty the pre-stored voltage in its internal, complete initialization, and ensure that the light emitting device L does not emit light. In this stage, the light emitting device L does not emit light.

[0185] The second stage S2 is called a compensation stage, signals of the first scan signal line Gate1, the second scan signal line Gate2 and the second light-emitting signal line EM2 are all high level signals, and signals of the first reset signal line Reset1 and the second reset signal line Reset2 are all low level signals. The signal of the second reset signal line Reset2 is a low level signal, the fourth transistor T4 and the eighth transistor T8 are turned on, and potentials of the third node N3 and the second node N2 remain potentials of the last stage. The signal of the first scan signal line Gate1 is a high level signal, the second transistor T2 is turned on, the first transistor T1 is turned on, and a signal of the fourth node N4 is provided to the fifth node N5, the second capacitor C2 is initialized, original data voltage in the second capacitor C2 is cleared, and the sixth transistor T6 is turned on. The second transistor T2, the first transistor T1 and the sixth transistor T6 are turned on, so that voltage output by the first power supply line VDD is provided to the first node N1 through the turned-on sixth transistor T6, the fifth node N5, the turned-on first transistor T1, the fourth node N4 and the turned-on second transistor T2, and a difference between the voltage VDD output by the first power supply line and a threshold voltage of the first transistor T1 is charged into the first capacitor C1, until the voltage of the first node N1 is Vd+Vth, Vd is the voltage output by the first power supply line VDD, and Vth is the threshold voltage of the first transistor T1. In this stage, the voltage of the first node N1 is Vd+Vth, the voltage of the second node N2 is the voltage Vd of the first power supply line VDD, and the voltage of the third node N3 is the voltage of the second initial signal line Vint2. The third transistor T3, the fifth transistor T5 and the seventh transistor T7 are disconnected. In this stage, the light-emitting device L does not emit light.

[0186] The third stage S3 is called a writing stage, signals of the second reset signal line Reset2 and the second light-emitting signal line EM2 are all high level signals, and signals of the first reset signal line Reset1, the first scan signal line Gate1 and the second scan signal line Gate2 are all low level signals. The signal of the second scan signal line Gate2 is a low level signal, the fifth transistor T5 is turned on, and a data signal of the data signal line Vdata is written into the second node N2 through the turned-on fifth transistor T5, the voltage value of the signal of the second node N2 is Vdata, Vdata is the voltage value of the data signal, and the voltage value of the signal of the second node N2 in this stage jumps from the voltage value in the last stage. Therefore, under the action of the first capacitor C1, the voltage value of the signal of the first node N1 also jumps, at this time, the voltage value of the signal of the first node N1 is Vd+Vth+(Vdata-Vd). The second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are disconnected. In this stage, the light-emitting device L does not emit light.

[0187] The fourth stage S4 is called a light emitting stage, the signal of the second reset signal line Reset2 is a high level signal, the signals of the first reset signal line Reset1, the first scan signal line Gate1, the second scan signal line Gate2 and the second light emitting signal line EM2 are all low level signals. The signal of the second light emitting signal line EM2 is a low level signal, the seventh transistor T7 is turned on, the voltage Vd output by the first power supply line VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on sixth transistor T6, the first transistor T1 and the seventh transistor T7, and drives the light emitting device L to emit light. The second transistor T2, the third transistor T3, the fourth transistor T4 and the eighth transistor T8 are disconnected. In this stage, the light emitting device L emits light.

[0188] In the driving process of the pixel circuit, the driving current flowing through the first transistor T1 is determined by the voltage difference between the gate electrode (also the first node N1) and the first electrode. Since the voltage value of the signal of the first node N1 is Vd+Vth+(Vdata-Vd)=Vth+Vdata, the driving current of the first transistor T1 is: I=K*(Vgs-Vth) 2 =K*[(Vth+Vdata-Vd)-Vth] 2 =K*(Vdata-Vd) 2 . Wherein I is the driving current flowing through the first transistor T1, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the first transistor T1.

[0189] FIG. 15 is an equivalent circuit schematic diagram of a pixel driving circuit, as shown in FIG. 15, the control signal line can be the second scan signal line Gate2, the driving sub-circuit can include the first transistor T1, the first control sub-circuit can include the second transistor T2, the third transistor T3, the eighth transistor T8 and the first capacitor C1, the second control sub-circuit can include the fourth transistor T4 and the fifth transistor T5, and the light emitting control sub-circuit can include the sixth transistor T6 and the seventh transistor T7.

[0190] In an example embodiment, as shown in FIG. 15, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fifth node N5, and the second electrode of the first transistor T1 is electrically connected with the fourth node N4; the control electrode of the second transistor T2 is electrically connected with the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected with the first node N1, and the second electrode of the second transistor T2 is electrically connected with the fourth node N4; the control electrode of the third transistor T3 is electrically connected with the first reset signal line Reset1, the first electrode of the third transistor T3 is electrically connected with the first node N1, and the second electrode of the third transistor T3 is electrically connected with the first initial signal line Vint1; the control electrode of the fourth transistor T4 is electrically connected with the second scan signal line Gate2, the first electrode of the fourth transistor T4 is electrically connected with the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the second scan signal line Gate2, the first electrode of the fifth transistor T5 is electrically connected with the data signal line Vdata, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with the first emission signal line EM1, the first electrode of the sixth transistor T6 is electrically connected with the first power supply line VDD, and the second electrode of the sixth transistor T6 is electrically connected with the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected with the second emission signal line EM2, the first electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected with the third node N3; the control electrode of the eighth transistor T8 is electrically connected with the second scan signal line Gate2, the first electrode of the eighth transistor T8 is electrically connected with the second initial signal line Vint2, and the second electrode of the eighth transistor T8 is electrically connected with the third node N3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the first node N1, and the second plate C12 of the first capacitor is electrically connected with the second node N2.

[0191] In an example embodiment, the second scan signal line Gate2 connected with the fourth transistor T4 and the second scan signal line Gate2 connected with the eighth transistor T8 can be the same signal line or different signal lines with the same signal, and the present disclosure does not make any limitation in this regard.

[0192] In an example embodiment, the fourth transistor T4 and the eighth transistor T8 are of the opposite type of transistor to the fifth transistor T5.

[0193] In an example embodiment, as shown in FIG. 15, the first transistor T1, the fifth transistor T5 to the seventh transistor T7 are P-type transistors, and the second transistor T2 to the fourth transistor T4 and the eighth transistor T8 are N-type transistors.

[0194] FIG. 16 is a timing diagram of the pixel driving circuit provided in FIG. 15, and the working process of the pixel driving circuit exemplified by FIG. 15 is described below to illustrate the exemplary embodiments of the present disclosure, which can include:

[0195] The first stage S1 is called the initial stage, the signals of the first reset signal line Reset1, the second scan signal line Gate2, the first emission signal line EM1 and the second emission signal line EM2 are all high level signals, and the signal of the first scan signal line Gate1 is all low level signal. The signal of the first reset signal line Reset1 is a high level signal, the third transistor T3 is turned on, the third transistor T3 initializes the gate electrode (also the first node N1) of the first transistor T1, and the signal of the first initial signal line Vinit1 is provided to the first node N1. The signal of the second scan signal line Gate2 is a high level signal, the eighth transistor T8 is turned on, the initial voltage of the second initial signal line Vinit2 is provided to the third node N3, and the eighth transistor T8 initializes the anode potential. The fourth transistor T4 is turned on, the voltage of the first power supply line VDD is written to the second node N2 to stabilize the potential of the first node N1 and ensure the gate point of the first transistor T1 is initialized. At this time, the voltage value of the signal of the first node N1 is equal to the voltage of the first initial signal line Vint1, the voltage value of the signal of the second node N2 is equal to the voltage of the first power supply line VDD, and the voltage value of the signal of the third node N3 is equal to the voltage of the second initial signal line Vint2. Among them, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off.

[0196] The third node N3 is electrically connected to the first electrode of the light emitting device L, and when the eighth transistor T8 is turned on, the third node N3 provides the initial voltage of the second initial signal line Vinit2 to the first electrode of the light emitting device L to initialize (reset) the first electrode of the light emitting device L, for example: empty the pre-stored voltage in its internal, complete initialization, and ensure that the light emitting device L does not emit light. In this stage, the light emitting device L does not emit light.

[0197] The second stage S2 is called a compensation stage, signals of the first scan signal line Gate1, the second scan signal line Gate2 and the second light-emitting signal line EM2 are all high level signals, signals of the first reset signal line Reset1 and the first light-emitting signal line EM1 are all low level signals. The signal of the second scan signal line Gate2 is a high level signal, the fourth transistor T4 and the eighth transistor T8 are turned on, and potentials of the third node N3 and the second node N2 remain potentials of the last stage. The signal of the first scan signal line Gate1 is a high level signal, the second transistor T2 is turned on, the signal of the first light-emitting signal line EM1 is a low level signal, the sixth light-emitting transistor T6 is turned on, the second transistor T2, the first transistor T1 and the sixth transistor T6 are turned on, so that the voltage output by the first power supply line VDD is provided to the first node N1 through the turned-on sixth transistor T6, the fifth node N5, the turned-on first transistor T1, the fourth node N4 and the turned-on second transistor T2, and the difference between the voltage VDD output by the first power supply line and the threshold voltage of the first transistor T1 is charged into the first capacitor C1, until the voltage of the first node N1 is Vd+Vth, Vd is the voltage output by the first power supply line VDD, and Vth is the threshold voltage of the first transistor T1. In this stage, the voltage of the first node N1 is Vd+Vth, the voltage of the second node N2 is the voltage Vd of the first power supply line VDD, and the voltage of the third node N3 is the voltage of the second initial signal line Vint2. The third transistor T3, the fifth transistor T5 and the seventh transistor T7 are turned off. In this stage, the light-emitting device L does not emit light.

[0198] The third stage S3 is called a writing stage, signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are all high level signals, signals of the first reset signal line Reset1, the first scan signal line Gate1 and the second scan signal line Gate2 are all low level signals. The signal of the second scan signal line Gate2 is a low level signal, the fifth transistor T5 is turned on, and the data signal of the data signal line Vdata is written into the second node N2 through the turned-on fifth transistor T5, the voltage value of the signal of the second node N2 is Vdata, Vdata is the voltage value of the data signal, and the voltage value of the signal of the second node N2 in this stage jumps from the voltage value in the last stage. Therefore, under the action of the first capacitor C1, the voltage value of the signal of the first node N1 also jumps, at this time, the voltage value of the signal of the first node N1 is Vd+Vth+(Vdata-Vd). The second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. In this stage, the light-emitting device L does not emit light.

[0199] The fourth stage S4 is called a light emitting stage, and the signals of the first reset signal line Reset1, the first scan signal line Gate1, the second scan signal line Gate2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are all low signals. The signal of the first light emitting signal line EM1 is a low signal, the sixth transistor T6 is turned on, the signal of the second light emitting signal line EM2 is a low signal, the seventh transistor T7 is turned on, the voltage Vd output by the first power supply line VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on sixth transistor T6, the first transistor T1 and the seventh transistor T7, and drives the light emitting device L to emit light. The second transistor T2, the third transistor T3, the fourth transistor T4 and the eighth transistor T8 are turned off. In this stage, the light emitting device L emits light.

[0200] In the driving process of the pixel circuit, the driving current flowing through the first transistor T1 is determined by the voltage difference between the gate electrode (also the first node N1) and the first electrode. Since the voltage value of the signal of the first node N1 is Vd+Vth+(Vdata-Vd)=Vth+Vdata, the driving current of the first transistor T1 is: I=K*(Vgs-Vth) 2 =K*[(Vth+Vdata-Vd)-Vth] 2 =K*(Vdata-Vd) 2 . Wherein I is the driving current flowing through the first transistor T1, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the first transistor T1.

[0201] In an example embodiment, on the basis of the pixel driving circuit shown in FIG. 9, FIG. 13 and FIG. 15, the pixel driving circuit further comprises: a ninth transistor and a tenth transistor; the control electrode of the ninth transistor is electrically connected with the second reset signal line, the first electrode of the ninth transistor is electrically connected with the reference signal line, and the second electrode of the ninth transistor is electrically connected with the second node; the control electrode of the tenth transistor is electrically connected with the third scan signal line, the first electrode of the tenth transistor is electrically connected with the fifth node, and the second electrode of the tenth transistor is electrically connected with the bias signal line.

[0202] FIG. 17 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 17, the control signal line can be the first reset signal line Reset1, the driving sub-circuit can comprise the first transistor T1, the first control sub-circuit can comprise the second transistor T2, the third transistor T3, the eighth transistor T8 and the first capacitor C1, the second control sub-circuit can comprise the fourth transistor T4 and the fifth transistor T5, the light emitting control sub-circuit can comprise the sixth transistor T6 and the seventh transistor T7, and the pixel driving circuit can further comprise: a third control sub-circuit, which can comprise the ninth transistor T9 and the tenth transistor T10.

[0203] In an example embodiment, as shown in FIG. 17, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fifth node N5, and the second electrode of the first transistor T1 is electrically connected with the fourth node N4; the control electrode of the second transistor T2 is electrically connected with the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected with the first node N1, and the second electrode of the second transistor T2 is electrically connected with the fourth node N4; the control electrode of the third transistor T3 is electrically connected with the first reset signal line Reset1, the first electrode of the third transistor T3 is electrically connected with the first node N1, and the second electrode of the third transistor T3 is electrically connected with the first initial signal line Vint1; the control electrode of the fourth transistor T4 is electrically connected with the first reset signal line Reset1, the first electrode of the fourth transistor T4 is electrically connected with the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the second scan signal line Gate2, the first electrode of the fifth transistor T5 is electrically connected with the data signal line Vdata, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with the first emission signal line EM1, the first electrode of the sixth transistor T6 is electrically connected with the first power supply line VDD, and the second electrode of the sixth transistor T6 is electrically connected with the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected with the second emission signal line EM2, the first electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected with the third node N3; the control electrode of the eighth transistor T8 is electrically connected with the first reset signal line Reset1, the first electrode of the eighth transistor T8 is electrically connected with the second initial signal line Vint2, and the second electrode of the eighth transistor T8 is electrically connected with the third node N3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the first node N1, and the second plate C12 of the first capacitor is electrically connected with the second node N2; the control electrode of the ninth transistor T9 is electrically connected with the second reset signal line Reset2, the first electrode of the ninth transistor T9 is electrically connected with the reference signal line Vref, and the second electrode of the ninth transistor T9 is electrically connected with the second node N2; the control electrode of the tenth transistor T10 is electrically connected with the third scan signal line Gate3, the first electrode of the tenth transistor T10 is electrically connected with the fifth node N5, and the second electrode of the tenth transistor T10 is electrically connected with the bias signal line Vbias.

[0204] In an example embodiment, the first reset signal line Reset1 connected with the fourth transistor T4 and the first reset signal line Reset1 connected with the eighth transistor T8 can be the same signal line or different signal lines with the same signal, and the present disclosure does not make any limitation in this regard.

[0205] In an example embodiment, the fourth transistor T4 and the eighth transistor T8 are of the same type as the fifth transistor T5.

[0206] In an example embodiment, as shown in FIG. 17, the first transistor T1, the fourth transistor T4 to the eighth transistor T8 are P-type transistors, and the second transistor T2 and the third transistor T3 are N-type transistors.

[0207] FIG. 18 is a timing diagram of the pixel driving circuit provided in FIG. 17. The working process of the pixel driving circuit exemplified by FIG. 17 is described below to illustrate the example embodiment of the present disclosure. The working process of the pixel driving circuit can include:

[0208] The first stage S1 is referred to as an initial stage. The signals of the first reset signal line Reset1, the second reset signal line Reset2, the second scan signal line Gate2, the third scan signal line Gate3, the first emission signal line EM1 and the second emission signal line EM2 are all high-level signals, and the signal of the first scan signal line Gate1 is all low-level signal. The signal of the first reset signal line Reset1 is a high-level signal, the third transistor T3 is turned on, the third transistor T3 initializes the gate electrode (also the first node N1) of the first transistor T1, and the signal of the first initial signal line Vinit1 is provided to the first node N1. At this time, the voltage value of the signal of the first node N1 is equal to the voltage of the first initial signal line Vint1. Among them, the second transistor T2, the fourth transistor T4 to the tenth transistor T7 are disconnected. In this stage, the light emitting device L does not emit light.

[0209] In the second stage S2, signals of the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3 and the second emission signal line EM2 are high level signals, and signals of the first reset signal line Reset1, the second reset signal line Reset2 and the first emission signal line EM1 are low level signals. The signal of the first reset signal line Reset1 is a low level signal, the eighth transistor T8 is turned on, the initial voltage of the second initial signal line Vinit2 is provided to the third node N3, and the eighth transistor T8 initializes the anode potential. The fourth transistor T4 is turned on, and the voltage of the first power supply line VDD is written to the second node N2 to stabilize the potential of the first node N1. The voltage value of the signal of the second node N2 is equal to the voltage of the first power supply line VDD, and the voltage value of the signal of the third node N3 is equal to the voltage of the second initial signal line Vint2. The signal of the second reset signal line Reset2 is a low level signal, the ninth transistor T9 is turned on, and the signal of the reference signal line Vref is written to the second node N2; the tenth transistor T10 is turned on, and the signal of the bias signal line Vbias is written to the fifth node N5. The signal of the first scan signal line Gate1 is a high level signal, the second transistor T2 is turned on, the signal of the first emission signal line EM1 is a low level signal, the sixth light transistor T6 is turned on, the second transistor T2, the first transistor T1 and the sixth transistor T6 are turned on, so that the voltage output by the first power supply line VDD is provided to the first node N1 through the turned-on sixth transistor T6, the fifth node N5, the turned-on first transistor T1, the fourth node N4 and the turned-on second transistor T2, and the difference between the voltage VDD output by the first power supply line and the threshold voltage of the first transistor T1 is charged to the first capacitor C1, until the voltage of the first node N1 is Vd+Vth, Vd is the voltage output by the first power supply line VDD, and Vth is the threshold voltage of the first transistor T1. In this stage, the voltage of the first node N1 is Vd+Vth, the voltage of the second node N2 is the sum of the voltage Vd of the first power supply line VDD and the voltage of the reference signal line Vref, and the voltage of the third node N3 is the voltage of the second initial signal line Vint2. The third transistor T3, the fifth transistor T5 and the seventh transistor T7 are disconnected. In this stage, the light emitting device L does not emit light.

[0210] The third node N3 is electrically connected to the first electrode of the light emitting device L. When the eighth transistor T8 is turned on, the third node N3 provides the initial voltage of the second initial signal line Vinit2 to the first electrode of the light emitting device L to initialize (reset) the first electrode of the light emitting device L, for example, to empty the pre-stored voltage in the first electrode, complete the initialization and ensure that the light emitting device L does not emit light.

[0211] The third stage S3 is called a writing stage, signals of the second reset signal line Reset2, the third scan signal line Gate3, the first emitting signal line EM1 and the second emitting signal line EM2 are all high level signals, signals of the first reset signal line Reset1, the first scan signal line Gate1 and the second scan signal line Gate2 are all low level signals. The signal of the first reset signal line Reset1 is a low level signal, the fourth transistor T4 and the eighth transistor T8 are turned on, potentials of the third node N3 and the second node N2 remain potentials of the last stage. The signal of the second scan signal line Gate2 is a low level signal, the fifth transistor T5 is turned on, a data signal of the data signal line Vdata is written into the second node N2 through the turned-on fifth transistor T5, a voltage value of the signal of the second node N2 is Vdata, Vdata is a voltage value of the data signal, the voltage value of the signal of the second node N2 jumps in this stage compared with the voltage value of the last stage. Therefore, under the action of the first capacitor C1, the voltage value of the signal of the first node N1 also jumps, at this time, the voltage value of the signal of the first node N1 is Vd+Vth+(Vdata-Vd). The second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9 and the tenth transistor T10 are disconnected. In this stage, the light emitting device L does not emit light.

[0212] The fourth stage S4 is called a biasing stage, signals of the second reset signal line Reset2, the first emitting signal line EM1 and the second emitting signal line EM2 are all high level signals, signals of the first reset signal line Reset1, the first scan signal line Gate1, the second scan signal line Gate2 and the third scan signal line Gate3 are all low level signals. The signal of the first reset signal line Reset1 is a low level signal, the fourth transistor T4 and the eighth transistor T8 are turned on, potentials of the third node N3 and the second node N2 remain potentials of the last stage. The signal of the second scan signal line Gate2 is a low level signal, the fifth transistor T5 is turned on, the voltage value of the signal of the first node N1 remains Vd+Vth+(Vdata-Vd). The signal of the third scan signal line Gate3 is a low level signal, the tenth transistor T10 is turned on, a signal of the bias signal line Vbias is written into the fifth node N5. The second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are disconnected. In this stage, the light emitting device L does not emit light.

[0213] The fifth stage S5 is called a light emitting stage, the signals of the second reset signal line Reset2 and the third scan signal line Gate3 are high level signals, the signals of the first reset signal line Reset1, the first scan signal line Gate1, the second scan signal line Gate2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are low level signals. The signal of the first light emitting signal line EM1 is a low level signal, the sixth transistor T6 is turned on, the signal of the second light emitting signal line EM2 is a low level signal, the seventh transistor T7 is turned on, and the voltage Vd output by the first power supply line VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on sixth transistor T6, the first transistor T1 and the seventh transistor T7, and drives the light emitting device L to emit light. The signal of the first reset signal line Reset1 is a low level signal, the fourth transistor T4 and the eighth transistor T8 are turned on, the signal of the second scan signal line is a low level signal, and the fifth transistor T5 is turned on, so as to form a test path through the turned-on eighth transistor T8, the seventh transistor T7, the first transistor T1, the sixth transistor T6, the fourth transistor T4 and the fifth transistor. Among them, the second transistor T2, the third transistor T3, the ninth transistor T9 and the tenth transistor T10 are turned off. In this stage, the light emitting device L emits light.

[0214] In the driving process of the pixel circuit, the driving current flowing through the first transistor T1 is determined by the voltage difference between the gate electrode (also the first node N1) and the first electrode. Since the voltage value of the signal of the first node N1 is Vd+Vth+(Vdata-Vd)=Vth+Vdata, the driving current of the first transistor T1 is: I=K*(Vgs-Vth) 2 =K*[(Vth+Vdata-Vd)-Vth] 2 =K*(Vdata-Vd) 2 . Wherein I is the driving current flowing through the first transistor T1, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the first transistor T1.

[0215] The display panel provided by the embodiment of the present disclosure comprises: a pixel driving circuit. The pixel driving circuit is the pixel driving circuit provided by any one of the foregoing embodiments, and has similar implementation principles and implementation effects, which will not be described here.

[0216] The embodiment of the present disclosure also provides a driving method of a pixel driving circuit, which is configured to drive the pixel driving circuit. The driving method of the pixel driving circuit can comprise:

[0217] The driving sub-circuit determines the driving current flowing between the fifth node and the fourth node under the control of the potential difference between the signals of the first node and the fifth node; the first control sub-circuit writes the signal of the first initial signal line to the first node under the control of the signal of the first reset signal line, writes the signal of the second initial signal line to the third node under the control of the signal of the control signal line, and performs voltage compensation on the first node under the control of the signal of the first scan signal line; the light-emitting control sub-circuit forms the driving current between the first power supply line and the third node under the control of the signal of the light-emitting signal line; and the second control sub-circuit forms a path between the data signal line and the first power supply line under the control of the signals of the control signal line and the second scan signal line.

[0218] The pixel driving circuit is the pixel driving circuit provided by any one of the foregoing embodiments, and has similar implementation principles and implementation effects, which will not be described here again.

[0219] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0220] For the sake of clarity, the thickness and size of a layer or microstructure are exaggerated in the drawings used to describe embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0221] Although the embodiments disclosed in the present disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A pixel driving circuit, comprising: The driving sub-circuit, the first control sub-circuit, the second control sub-circuit and the light emitting control sub-circuit; The driving sub-circuit is electrically connected with the first node, the fourth node and the fifth node respectively, and is configured to determine a driving current flowing between the fifth node and the fourth node under the control of signals of the first node and the fifth node; The first control sub-circuit is electrically connected with the first reset signal line, the control signal line, the first scan signal line, the first initial signal line, the second initial signal line, the first node, the second node, the third node and the fourth node respectively, and is configured to write signals of the first initial signal line or the fourth node into the first node, write signals of the second initial signal line into the third node, and store a voltage difference of signals of the first node and the second node under the control of signals of the first reset signal line, the control signal line and the first scan signal line; The light emitting control sub-circuit is electrically connected with the first power supply line, the light emitting signal line, the third node, the fourth node and the fifth node respectively, and is configured to provide signals of the first power supply line to the fifth node and provide signals of the fourth node to the third node under the control of signals of the light emitting signal line; The second control sub-circuit is electrically connected with the control signal line, the second scan signal line, the data signal line, the second node and the first power supply line respectively, and is configured to form a path between the data signal line, the second node and the first power supply line under the control of signals of the control signal line and the second scan signal line.

2. The pixel driving circuit according to claim 1, wherein The second control sub-circuit comprises a fourth transistor and a fifth transistor; The control electrode of the fourth transistor is electrically connected with the control signal line, the first electrode of the fourth transistor is electrically connected with the first power supply line, and the second electrode of the fourth transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the second scan signal line, the first electrode of the fifth transistor is electrically connected with the data signal line, and the second electrode of the fifth transistor is electrically connected with the second node.

3. The pixel driving circuit of claim 1, wherein, The first control sub-circuit comprises a second transistor, a third transistor, an eighth transistor and a first capacitor; The control electrode of the second transistor is electrically connected with the first scan signal line, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the fourth node; The control electrode of the third transistor is electrically connected with the first reset signal line, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the first initial signal line; The control electrode of the eighth transistor is electrically connected with the control signal line, the first electrode of the eighth transistor is electrically connected with the second initial signal line, and the second electrode of the eighth transistor is electrically connected with the third node; The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first node, and the second plate of the first capacitor is electrically connected with the second node. The driving sub-circuit comprises a first transistor; 4. The pixel driving circuit of claim 1, wherein, The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fifth node, and the second electrode of the first transistor is electrically connected with the fourth node. The light emitting signal line comprises a first light emitting signal line and a second light emitting signal line, and the light emitting control sub-circuit comprises a sixth transistor and a seventh transistor; 5. The pixel driving circuit of claim 1, wherein, ​ A control electrode of the sixth transistor is electrically connected with the first light-emitting signal line, a first electrode of the sixth transistor is electrically connected with the first power supply line, and a second electrode of the sixth transistor is electrically connected with the fifth node; A control electrode of the seventh transistor is electrically connected with the second light-emitting signal line, a first electrode of the seventh transistor is electrically connected with the fourth node, and a second electrode of the seventh transistor is electrically connected with the third node.

6. The pixel driving circuit of claim 1, wherein, The light-emitting signal line comprises a second light-emitting signal line, and the light-emitting control sub-circuit comprises a sixth transistor, a seventh transistor and a second capacitor, the second capacitor comprising a first plate and a second plate; A control electrode of the sixth transistor is electrically connected with the first plate of the second capacitor, a first electrode of the sixth transistor is electrically connected with the first power supply line, and a second electrode of the sixth transistor is electrically connected with the fifth node and the second plate of the second capacitor respectively; A control electrode of the seventh transistor is electrically connected with the second light-emitting signal line, a first electrode of the seventh transistor is electrically connected with the fourth node, and a second electrode of the seventh transistor is electrically connected with the third node.

7. The pixel driving circuit of claim 1, wherein, The pixel driving circuit further comprises a third control sub-circuit; The third control sub-circuit is electrically connected with a second reset signal line, a third scan signal line, a bias voltage signal line, a reference signal line, a second node and a fifth node respectively, and is configured to provide a signal of the reference signal line to the second node and a signal of the bias voltage signal line to the fifth node under the control of signals of the second reset signal line and the third scan signal line.

8. The pixel driving circuit of claim 7, wherein, The third control sub-circuit comprises a ninth transistor and a tenth transistor; A control electrode of the ninth transistor is electrically connected with the second reset signal line, a first electrode of the ninth transistor is electrically connected with the reference signal line, and a second electrode of the ninth transistor is electrically connected with the second node; A control electrode of the tenth transistor is electrically connected with the third scan signal line, a first electrode of the tenth transistor is electrically connected with the fifth node, and a second electrode of the tenth transistor is electrically connected with the bias voltage signal line.

9. The pixel driving circuit of claim 1, wherein, The control signal line is a second reset signal line, the driving sub-circuit comprises a first transistor, the first control sub-circuit comprises a second transistor, a third transistor, an eighth transistor and a first capacitor, the second control sub-circuit comprises a fourth transistor and a fifth transistor, and the light-emitting control sub-circuit comprises a sixth transistor and a seventh transistor; A control electrode of the first transistor is electrically connected with the first node, a first electrode of the first transistor is electrically connected with the fifth node, and a second electrode of the first transistor is electrically connected with the fourth node; A control electrode of the second transistor is electrically connected with the first scan signal line, a first electrode of the second transistor is electrically connected with the first node, and a second electrode of the second transistor is electrically connected with the fourth node; A control electrode of the third transistor is electrically connected with the first reset signal line, a first electrode of the third transistor is electrically connected with the first node, and a second electrode of the third transistor is electrically connected with the first initial signal line; A control electrode of the fourth transistor is electrically connected with the second reset signal line, a first electrode of the fourth transistor is electrically connected with the first power supply line, and a second electrode of the fourth transistor is electrically connected with the second node; A control electrode of the fifth transistor is electrically connected with the second scan signal line, a first electrode of the fifth transistor is electrically connected with the data signal line, and a second electrode of the fifth transistor is electrically connected with the second node. The control electrode of the sixth transistor is electrically connected with the first light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the first power supply line, and the second electrode of the sixth transistor is electrically connected with the fifth node; The control electrode of the seventh transistor is electrically connected with the second light-emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the third node; The control electrode of the eighth transistor is electrically connected with the second reset signal line, the first electrode of the eighth transistor is electrically connected with the second initial signal line, and the second electrode of the eighth transistor is electrically connected with the third node; The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first node, and the second plate of the first capacitor is electrically connected with the second node.

10. The pixel driving circuit of claim 1, wherein, The control signal line is a second reset signal line, the driving sub-circuit comprises a first transistor, the first control sub-circuit comprises a second transistor, a third transistor, an eighth transistor and a first capacitor, the second control sub-circuit comprises a fourth transistor and a fifth transistor, the light-emitting control sub-circuit comprises a sixth transistor, a seventh transistor and a second capacitor, and the second capacitor comprises a first plate and a second plate; The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fifth node, and the second electrode of the first transistor is electrically connected with the fourth node; The control electrode of the second transistor is electrically connected with the first scan signal line, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the fourth node; The control electrode of the third transistor is electrically connected with the first reset signal line, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the first initial signal line; The control electrode of the fourth transistor is electrically connected with the second reset signal line, the first electrode of the fourth transistor is electrically connected with the first power supply line, and the second electrode of the fourth transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the second scan signal line, the first electrode of the fifth transistor is electrically connected with the data signal line, and the second electrode of the fifth transistor is electrically connected with the second node; The control electrode of the sixth transistor is electrically connected with the first plate of the second capacitor, the first electrode of the sixth transistor is electrically connected with the first power supply line, and the second electrode of the sixth transistor is electrically connected with the fifth node and the second plate of the second capacitor respectively; The control electrode of the seventh transistor is electrically connected with the second light-emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the third node; The control electrode of the eighth transistor is electrically connected with the second reset signal line, the first electrode of the eighth transistor is electrically connected with the second initial signal line, and the second electrode of the eighth transistor is electrically connected with the third node; The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first node, and the second plate of the first capacitor is electrically connected with the second node.

11. The pixel driving circuit of claim 1, wherein, The control signal line is a first reset signal line, the driving sub-circuit comprises a first transistor, the first control sub-circuit comprises a second transistor, a third transistor, an eighth transistor and a first capacitor, the second control sub-circuit comprises a fourth transistor and a fifth transistor, and the light-emitting control sub-circuit comprises a sixth transistor and a seventh transistor; The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fifth node, and the second electrode of the first transistor is electrically connected with the fourth node; The control electrode of the second transistor is electrically connected with the first scan signal line, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the fourth node; The control electrode of the third transistor is electrically connected with the first reset signal line, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the first initial signal line; The control electrode of the fourth transistor is electrically connected with the first reset signal line, the first electrode of the fourth transistor is electrically connected with the first power supply line, and the second electrode of the fourth transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the second scan signal line, the first electrode of the fifth transistor is electrically connected with the data signal line, and the second electrode of the fifth transistor is electrically connected with the second node; The control electrode of the sixth transistor is electrically connected with the first emitting signal line, the first electrode of the sixth transistor is electrically connected with the first power supply line, and the second electrode of the sixth transistor is electrically connected with the fifth node; The control electrode of the seventh transistor is electrically connected with the second emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the third node; The control electrode of the eighth transistor is electrically connected with the first reset signal line, the first electrode of the eighth transistor is electrically connected with the second initial signal line, and the second electrode of the eighth transistor is electrically connected with the third node; The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first node, and the second plate of the first capacitor is electrically connected with the second node.

12. The pixel driving circuit according to any one of claims 9 to 11, wherein, The fourth transistor and the eighth transistor are of the same type as the fifth transistor; The first transistor, the fourth transistor to the eighth transistor are P-type transistors, and the second transistor and the third transistor are N-type transistors.

13. The pixel driving circuit of claim 1, wherein, The control signal line is a second scan signal line, the driving sub-circuit comprises a first transistor, the first control sub-circuit comprises a second transistor, a third transistor, an eighth transistor and a first capacitor, the second control sub-circuit comprises a fourth transistor and a fifth transistor, and the emitting control sub-circuit comprises a sixth transistor and a seventh transistor; The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fifth node, and the second electrode of the first transistor is electrically connected with the fourth node; The control electrode of the second transistor is electrically connected with the first scan signal line, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the fourth node; The control electrode of the third transistor is electrically connected with the first reset signal line, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the first initial signal line; The control electrode of the fourth transistor is electrically connected with the second scan signal line, the first electrode of the fourth transistor is electrically connected with the first power supply line, and the second electrode of the fourth transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the second scan signal line, the first electrode of the fifth transistor is electrically connected with the data signal line, and the second electrode of the fifth transistor is electrically connected with the second node; A control electrode of the sixth transistor is electrically connected with the first light-emitting signal line, a first electrode of the sixth transistor is electrically connected with the first power supply line, and a second electrode of the sixth transistor is electrically connected with the fifth node; A control electrode of the seventh transistor is electrically connected with the second light-emitting signal line, a first electrode of the seventh transistor is electrically connected with the fourth node, and a second electrode of the seventh transistor is electrically connected with the third node; A control electrode of the eighth transistor is electrically connected with the second scanning signal line, a first electrode of the eighth transistor is electrically connected with the second initial signal line, and a second electrode of the eighth transistor is electrically connected with the third node; The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first node, and the second plate of the first capacitor is electrically connected with the second node.

14. The pixel driving circuit of claim 13, wherein, The fourth transistor and the eighth transistor are opposite to the transistor type of the fifth transistor; The first transistor, the fifth transistor to the seventh transistor are P-type transistors, and the second transistor to the fourth transistor and the eighth transistor are N-type transistors.

15. The pixel driving circuit of claim 9, 10, 11, or 13, wherein, The pixel driving circuit further includes a ninth transistor and a tenth transistor; A control electrode of the ninth transistor is electrically connected with the second reset signal line, a first electrode of the ninth transistor is electrically connected with the reference signal line, and a second electrode of the ninth transistor is electrically connected with the second node; A control electrode of the tenth transistor is electrically connected with the third scanning signal line, a first electrode of the tenth transistor is electrically connected with the fifth node, and a second electrode of the tenth transistor is electrically connected with the bias signal line.

16. A display panel comprising: The pixel driving circuit according to any one of claims 1 to 15.

17. A driving method of a pixel driving circuit configured to drive the pixel driving circuit according to any one of claims 1 to 15, the method comprising: determining, by the driving sub-circuit, a driving current flowing between the fifth node and the fourth node under control of a potential difference between signals of the first node and the fifth node; writing, by the first control sub-circuit, a signal of the first initial signal line to the first node under control of a signal of the first reset signal line, writing a signal of the second initial signal line to the third node under control of a signal of the control signal line, and performing voltage compensation to the first node under control of a signal of the first scanning signal line; forming, by the light-emitting control sub-circuit, the driving current between the first power supply line and the third node under control of a signal of the light-emitting signal line; forming, by the second control sub-circuit, a path between the data signal line and the first power supply line under control of signals of the control signal line and the second scanning signal line.

Images