Mainboard of electronic equipment and electronic equipment

Abstract

The invention provides a mainboard of an electronic device and the electronic device, which can be applied to the technical field of hardware, the mainboard of the electronic device is provided with a management controller and a first connector connected with the management controller, the first connector is used for being connected with a board card of the electronic device, and the first connector comprises a bus pin and a second pin, the bus connector is used for being connected with a bus pin of a board card so as to transmit a bus signal between the bus connector and the board card; the first in-place signal pin is used for being connected with an in-place signal pin of a first type of board card so as to receive an in-place signal of the first type of board card; the second in-place signal pin is used for being connected with an in-place signal pin of a second type of board card so as to receive an in-place signal of the second type of board card; and the management controller responds to the in-place signal received by the first in-place signal pin, determines the board card connected with the first connector as the board card of the first type, responds to the in-place signal received by the second in-place signal pin, and determines the board card connected with the first connector as the board card of the second type.

Description

Technical Field

[0001] This application relates to the field of hardware technology, and more specifically to a motherboard and an electronic device. Background Technology

[0002] In server design, functional devices such as hard drives and PCIe (Peripheral Component Interconnect Express) cards need to be interconnected with the motherboard via boards. Their control information relies on sideband signal lines that exist as independent physical links. Each channel needs to be connected to a specific type of board, which limits the flexibility of topology design and motherboard space layout. Summary of the Invention

[0003] According to a first aspect of this application, a motherboard for an electronic device is provided. The motherboard includes a management controller and a first connector connected to the management controller. The first connector is used to connect to a board of the electronic device. The first connector includes: a bus pin for connecting to a bus pin of the board to transmit a bus signal between the board and the board; a first presence signal pin for connecting to a presence signal pin of a first type board to receive a presence signal of the first type board; and a second presence signal pin for connecting to a presence signal pin of a second type board to receive a presence signal of the second type board. The management controller is configured to identify the board connected to the first connector as a first type board in response to receiving a presence signal on the first presence signal pin, and to identify the board connected to the first connector as a second type board in response to receiving a presence signal on the second presence signal pin.

[0004] A second aspect of this application provides an electronic device, including: the aforementioned motherboard; and a board connected to a first connector of the motherboard.

[0005] According to embodiments of this application, the presence signal of a first type of board can be obtained by setting a first presence signal pin, and the presence signal of a second type of board can be obtained by setting a second presence signal pin. The management controller can automatically identify the board connected to the first connector as a first type of board in response to the presence signal of the first type of board. The management controller can automatically identify the board connected to the first connector as a second type of board in response to the presence signal of the second type of board, and establish a communication path with the corresponding board type via a bus pin to transmit the corresponding bus signal. When the motherboard of the electronic device is connected to a board through the first connector, the motherboard can automatically identify the board type of the board connected to the first connector, realizing the reusability of a single connector. This removes restrictions on the types of boards that can be connected to the connectors on the motherboard, improves the flexibility of the motherboard's spatial layout, reduces maintenance difficulty, and enhances the reliability of the server. Attached Figure Description

[0006] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments of this application with reference to the accompanying drawings.

[0007] Figure 1 A schematic diagram of a motherboard of an electronic device according to an embodiment of this application is shown.

[0008] Figure 2A A schematic diagram of a motherboard of an electronic device according to another embodiment of this application is shown.

[0009] Figure 2B A schematic diagram of a first composite connector according to another embodiment of this application is shown.

[0010] Figure 2C A schematic diagram of a second composite connector according to another embodiment of this application is shown.

[0011] Figure 3A This diagram shows the topology of the adapter card on the previous generation motherboard.

[0012] Figure 3B This diagram shows a schematic of the backplane topology on the previous generation motherboard.

[0013] Figure 3C A schematic diagram of the I2C topology of a motherboard according to an embodiment of this application is shown.

[0014] Figure 4 A schematic diagram of a first type of hardware connection of the motherboard according to an embodiment of this application is shown.

[0015] Figure 5 A schematic diagram of a second type of hardware connection for the motherboard according to an embodiment of this application is shown.

[0016] Figure 6 A schematic diagram of the motherboard of an electronic device according to yet another embodiment of this application is shown.

[0017] Figure 7 A schematic diagram of a first connector according to another embodiment of this application is shown.

[0018] Figure 8A A schematic diagram of an electronic device according to an embodiment of this application is shown.

[0019] Figure 8B A schematic diagram of a board of a first type according to an embodiment of this application is shown.

[0020] Figure 8C A schematic diagram of a second type of board according to an embodiment of this application is shown.

[0021] Figure 9A This diagram illustrates the connector layout logic of the previous generation server.

[0022] Figure 9B This diagram illustrates the connector layout logic on the motherboard of a previous generation server.

[0023] Figure 10A A schematic diagram of a first connector layout logic for a server according to an embodiment of this application is shown.

[0024] Figure 10B A schematic diagram of a second connector layout logic for a server according to an embodiment of this application is shown.

[0025] Figure 10C A schematic diagram of the connector layout logic on the motherboard of a server according to an embodiment of this application is shown. Detailed Implementation

[0026] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0028] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0029] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0030] Sideband signal lines are dedicated auxiliary signal channels in digital systems, independent of the main data channel. They employ a physically separate wiring structure and are used to transmit low-bandwidth but critical sideband signals such as control commands, status information, management signals, or alarm information. By using dedicated lines independent of the main data channel, sideband signal lines prevent resource contention with the main data stream, ensuring high real-time performance and reliability for control commands such as resets and interrupts, and status alarms such as overheating and error occurrences. They can be responded to and processed immediately without waiting for the main data channel to become idle. Sideband signals are applied in scenarios such as processor system management, memory error reporting, and power timing control, forming a fundamental technical support for ensuring the stable and efficient collaborative operation of hardware systems.

[0031] The I2C bus employs a two-wire synchronous serial half-duplex communication protocol for low-speed control between board-level chips. The I2C bus physical layer includes two bidirectional open-drain lines: the Serial Data Line (SDA) and the Serial Clock Line (SCL). The SDA line transmits data, while the SCL line is driven by the current master device to synchronize communication timing. Slave devices on the I2C bus connect in parallel, are addressed by a unique address, and support multi-master arbitration and clock synchronization mechanisms. The I2C bus uses pull-up resistors to achieve a logic high level, offering advantages such as simple structure and economical pin count. It is used for control and configuration between peripherals such as sensors, EEPROMs (Electrically Erasable Programmable Read-Only Memory), and PMICs (Power Management Integrated Circuits) and the master controller.

[0032] In server design, functional components such as hard drives and PCIe cards are interconnected with the motherboard via back panels (BP), riser cards, and other boards and cables to expand storage, computing, and data exchange capabilities. The low-voltage DC power required by these components needs to be routed from the motherboard power supply to the load via circuit boards and cables. Therefore, DC power connectors conforming to current-carrying capacity and hot-swappable specifications must be installed at the mechanical interfaces of the motherboard and boards (including back panels and PCIe riser cards) to establish a low-loss, highly reliable power path.

[0033] In server design, online monitoring, fault alarms, and hot-swapping control of functional components such as hard drives and PCIe cards require the transmission of low-bandwidth critical information in a highly reliable manner. Therefore, it is necessary to design sideband signal lines that are physically isolated from the high-speed data channel. These sideband signal lines are arranged parallel to the data lines as chip pins and circuit board traces, and are physically independent of the high-speed channel, thus providing a dedicated, real-time, and highly reliable control path.

[0034] In the server design process, the register configuration, fault alarm, and hot-swapping management of functional devices such as hard drives and PCIe cards rely on an I2C path independent of the data channel. This path starts from the motherboard, extends to each board via a dedicated I2C signal line, and each board's interface must be equipped with a matching I2C signal connector to ensure the integrity and reliability of the control link.

[0035] The power lines and sideband signal lines of the board are separate. The board has dedicated low-voltage DC power connectors and power connection cables, as well as dedicated sideband signal connectors and sideband signal lines. Since the hard drive backplane and the adapter card cannot share the same I2C path, the routing of the connectors connecting the hard drive backplane and the adapter card on the motherboard needs to be separated during the server design process. The hard drive backplane is a high source of interference; the electrical noise generated by the hot-swapping operation of the hard drive backplane may interfere with the management bus of critical devices on the adapter card, such as the GPU (Graphics Processing Unit) and network card, leading to communication errors or bus lock-up. Both the hard drive backplane and the adapter card may contain I2C devices; if the addresses are the same, conflicts will occur, increasing the complexity of design and material management. Therefore, the I2C topology corresponding to the hard drive backplane and the adapter card needs to be separated on the motherboard. However, in actual design, since both the front and rear windows of the server have hard drive backplanes and adapter cards with different topologies, the physical connectors for the I2C path are inevitably increased.

[0036] As server architectures become increasingly complex, the number of components on motherboards and expansion cards grows, making the space on these boards increasingly cramped and precious. Limited physical space on expansion cards prevents the placement of more components; it increases the difficulty of cable management during server production and maintenance; and excessive connectors and cables increase system complexity, ultimately reducing reliability. Using separate connectors and cables on the motherboard to connect expansion cards and transmit power and sideband signals results in occupied motherboard space, complex wiring, and reduced reliability.

[0037] The embodiments of this application provide a motherboard and an electronic device, which aim to solve the problem of too many connectors and messy cables on the motherboard and board by merging the low-voltage DC power signal and the sideband signal on the physical connector and reconstructing the I2C bus topology.

[0038] Figure 1 A schematic diagram of a motherboard of an electronic device according to an embodiment of this application is shown.

[0039] like Figure 1 As shown, the motherboard 1 of the electronic device is provided with a management controller 3 and a first connector 4 connected to the management controller 3. The first connector 4 is used to connect to the board 2 of the electronic device.

[0040] The first connector includes a bus pin, a first presence signal pin, and a second presence signal pin. The bus pin is used to connect to a bus pin of a board to transmit bus signals with the board. The first presence signal pin is used to connect to a presence signal pin of a first-type board to receive a presence signal from the first-type board. The second presence signal pin is used to connect to a presence signal pin of a second-type board to receive a presence signal from the second-type board. The management controller is configured to identify the board connected to the first connector as a first-type board in response to receiving a presence signal from the first presence signal pin, and to identify the board connected to the first connector as a second-type board in response to receiving a presence signal from the second presence signal pin.

[0041] According to embodiments of this application, the presence signal of a first type of board can be obtained by setting a first presence signal pin, and the presence signal of a second type of board can be obtained by setting a second presence signal pin. The management controller can automatically identify the board connected to the first connector as a first type of board in response to the presence signal of the first type of board. The management controller can automatically identify the board connected to the first connector as a second type of board in response to the presence signal of the second type of board, and establish a communication path with the corresponding board type via a bus pin to transmit the corresponding bus signal. When the motherboard of the electronic device is connected to a board through the first connector, the motherboard can automatically identify the board type of the board connected to the first connector, realizing the reusability of a single connector. This removes restrictions on the types of boards that can be connected to the connectors on the motherboard, improves the flexibility of the motherboard's spatial layout, reduces maintenance difficulty, and enhances the reliability of the server.

[0042] According to embodiments of this application, the first type of board is a backplane, such as a hard drive backplane (BP). A hard drive backplane is a dedicated backplane in a server specifically designed to interface with hard drives; it can be understood as a signal and power adapter board between the hard drive and the motherboard. The second type of board is an adapter card. An adapter card is an interface adapter and physical extension component designed to expand PCIe devices. It can change the direction or position of the PCIe slot, adapt to the chassis structure, and support more expansion devices. The management controller is a Baseboard Management Controller (BMC) or a Central Processing Unit (CPU). The bus pins are Integrated Circuit Bus (I2C) pins.

[0043] According to an embodiment of this application, there are multiple first connectors, which are used to connect multiple boards respectively.

[0044] Figure 2A A schematic diagram of a motherboard of an electronic device according to another embodiment of this application is shown.

[0045] like Figure 2A As shown, the management controller 3 can be a BMC or a BIOS (Basic Input / Output System). The first type of board 21 can be an adapter card, and the second type of board 22 can be a backplane.

[0046] like Figure 2A As shown, the first connector includes bus pins, a first presence signal pin, and a second presence signal pin. Compared to a traditional bus connector, the first connector can be called a composite connector. There are two first connectors, namely the first composite connector MCONN_0 and the second composite connector MCONN_1. The first composite connector MCONN_0 and the second composite connector MCONN_1 are respectively connected to the board.

[0047] Figure 2B A schematic diagram of a first composite connector according to another embodiment of this application is shown.

[0048] Figure 2C A schematic diagram of a second composite connector according to another embodiment of this application is shown.

[0049] like Figure 2A and 2BAs shown, the first composite connector MCONN_0 is connected to the first type board 21 via a cable. When the board connected to the first composite connector MCONN_0 is the first type board 21, the first presence signal pin Riser_PRST# of the first composite connector MCONN_0 is connected to the first presence signal pin Riser_PRST# of the adapter card, and the bus pins of the first composite connector MCONN_0 are connected to the bus pins of the adapter card. The bus pins of the first composite connector MCONN_0 and the bus pins of the adapter card each include a bus data pin I2C_SDA and a bus clock pin I2C_CLK. The bus data pin I2C_SDA and the bus clock pin I2C_CLK of the first composite connector MCONN_0 are respectively connected to the bus data pin I2C_SDA and the bus clock pin I2C_CLK of the adapter card.

[0050] The first presence signal pin Riser_PRST# of the first composite connector MCONN_0 can receive the presence signal of the first type board 21. The second presence signal pin BP_PRST# of the first composite connector MCONN_0 does not receive the presence signal. In response to the first presence signal pin Riser_PRST# of the first composite connector MCONN_0 receiving the presence signal, the management controller 3 recognizes that the first type board 21 connected to the first composite connector MCONN_0 is a first type board, and connects to the bus pin of the adapter card through the bus pin of the first composite connector MCONN_0 to transmit bus signals with the first type board 21.

[0051] like Figure 2A and 2C As shown, the second composite connector MCONN_1 is connected to the second type board 22 via a cable. When the board connected to the second composite connector MCONN_1 is the second type board 22, the second presence signal pin BP_PRST# of the second composite connector MCONN_1 is connected to the second presence signal pin BP_PRST# of the backplane. The bus pins of the second composite connector MCONN_1 are connected to the bus pins of the backplane. Each of the bus pins of the second composite connector MCONN_1 and the bus pins of the backplane includes a bus data pin I2C_SDA and a bus clock pin I2C_CLK. The bus data pin I2C_SDA and the bus clock pin I2C_CLK of the second composite connector MCONN_1 are respectively connected to the bus data pin I2C_SDA and the bus clock pin I2C_CLK of the backplane.

[0052] The second presence signal pin BP_PRST# of the second composite connector MCONN_1 can receive the presence signal of the second type board 22. The first presence signal pin Riser_PRST# of the second composite connector MCONN_1 does not receive a presence signal. In response to the second presence signal pin BP_PRST# of the second composite connector MCONN_1 receiving a presence signal, the management controller 3 recognizes that the second type board 22 connected to the second composite connector MCONN_1 is a second type board, and connects to the bus pin of the second type board 22 through the bus pin of the second composite connector MCONN_1 to transmit bus signals with the second type board 22.

[0053] Embodiments of this application also provide an I2C topology circuit.

[0054] According to an embodiment of this application, the motherboard further includes a first expansion circuit, the upstream port of the first expansion circuit being connected to the bus interface of the management controller, and the multiple downstream ports of the first expansion circuit being respectively connected to the bus pins of multiple first connectors.

[0055] like Figure 2A and 2B As shown, the first downstream port of the first expansion circuit 51 is connected to the bus pin of the first composite connector MCONN_0 through the first port bus I2C_0. The first port bus I2C_0 includes a first port data line I2C_SDA_0 and a first port clock line I2C_CLK_0. The first port data line I2C_SDA_0 and the first port clock line I2C_CLK_0 are respectively connected to the bus data pin I2C_SDA and the bus clock pin I2C_CLK of the first composite connector MCONN_0, and then connected to the bus data pin I2C_SDA and the bus clock pin I2C_CLK of the adapter card.

[0056] like Figure 2A and 2C As shown, the second downstream port of the first expansion circuit 51 is connected to the bus pin of the second composite connector MCONN_1 through the second port bus I2C_1. The second port bus I2C_1 includes the second port data line I2C_SDA_1 and the second port clock line I2C_CLK_1. The second port data line I2C_SDA_1 and the second port clock line I2C_CLK_1 are respectively connected to the bus data pin I2C_SDA and the bus clock pin I2C_CLK of the second composite connector MCONN_1, and then connected to the bus data pin I2C_SDA and the bus clock pin I2C_CLK of the backplane.

[0057] Figure 3A This diagram shows the topology of the adapter card on the previous generation motherboard.

[0058] Figure 3B This diagram shows a schematic of the backplane topology on the previous generation motherboard.

[0059] Figure 3C A schematic diagram of the I2C topology of a motherboard according to an embodiment of this application is shown.

[0060] like Figure 3A As shown, the previous generation motherboard had two switching circuits and two Riser_I2C connectors. The two switching circuits were connected to the CPU0 processor, and each Riser_I2C connector connected to two adapter cards. Each device on the previous generation motherboard could be connected to a 3V 3_STBY power supply via a 4.7k resistor. Figure 3B As shown, the previous generation motherboard had two switching circuits and multiple I2C connectors, which could be connected to multiple backplanes respectively.

[0061] like Figure 3C As shown, the first expansion circuit 5 includes a bus controller 51 and multiple bus expanders. The upstream port of the bus controller 51 is connected to the bus interface of the management controller 3. The multiple downstream ports of the bus controller 51 are respectively connected to the multiple bus expanders. The upstream port of the bus expander is connected to the corresponding downstream port of the bus controller. The multiple downstream ports of the bus expander are respectively connected to the bus pins of the corresponding first connector 4.

[0062] like Figure 3C As shown, the bus expander includes a first bus expander 52 and a second bus expander 53. The downstream ports of the first bus expander 52 include a first set of downstream ports 54 and a second set of downstream ports 55. The first set of downstream ports 54 is used to connect to a first set of boards 24 via a first set of first connectors 44, and the second set of downstream ports 55 is used to connect to a second set of boards 25 via a second set of first connectors 45. The downstream ports of the second bus expander are connected to a third set of boards 26 via a third set of first connectors 46. The first set of boards 24 is located in a first area of ​​the electronic device. The second set of boards 25 is located in a second area of ​​the electronic device. The third set of boards 26 is located in a third area of ​​the electronic device.

[0063] According to embodiments of this application, the first group of boards 24, the second group of boards 25, and the third group of boards 26 each include at least one of a first type of board and a second type of board.

[0064] According to an embodiment of this application, the electronic device is a server. The first set of boards 24 is located on the front of the server, and the third set of boards 26 is located on the rear of the server. The second set of boards 25 is located in the area between the front and rear of the server, such as the center of the server or the middle backplane of the server. The center of the server means that it is located in the central area of ​​the server chassis, and boards can be inserted at both the front and rear of the center of the server. The middle backplane of the server means that it is located in the rear area of ​​the server chassis, and it is a single-sided cable outlet, that is, boards are inserted only on one side of the middle backplane of the server.

[0065] According to an embodiment of this application, the downstream port of the first bus extender 52 further includes an additional downstream port, which is connected to the built-in storage module of the motherboard 1. For example... Figure 3C As shown, the fifth downstream port S4 of the first bus expander 52 can be connected to the built-in storage module M_2 of the motherboard 1. The built-in storage module M_2 can be a solid-state drive that is directly plugged into the M.2 slot of the motherboard or adapter board. The M in M.2 represents the specification name jointly determined by the motherboard and the module, and the 2 in M.2 indicates the second generation size standard.

[0066] Previous generation servers used a topology based on function (adapter card / backplane), such as Figure 3A and Figure 3B As shown in Table 1, the card support requirements for the previous generation servers are as follows: The previous generation 2U server had 1 adapter card and 4 BPs in the front window, and 3, 4, or 6 adapter cards in the rear window. The previous generation 4U server had 4 BPs in the front window and 5 BPs in the rear window, with one BP mutually exclusive with another; in actual use, 4 BPs were used, and 4 BPs were configured in the middle.

[0067] Table 1

[0068]

[0069] The server in this embodiment can construct an I2C topology using a bus controller and two bus expanders, with each bus expander capable of expanding to eight I2C channels. Based on the first connector in this embodiment, each I2C channel can connect to both an adapter card and a backplane; therefore, the server in this embodiment can also be adapted to previous generation 4U servers.

[0070] like Figure 3CAs shown, the first four I2C channels (S0, S1, S2, S3) of the first bus expander 52 form the first group of downstream ports 54, which are connected to the first group of boards 24 located on the front window of the server via the first group of first connectors 44. The last three I2C channels (S5, S6, S7) of the first bus expander 52 form the second group of downstream ports 55, which are connected to the second group of boards 25 located in the center of the server via the second group of first connectors 45. The fifth I2C channel S4 of the first bus expander 52 can connect to the built-in M.2 device. The first four I2C channels (S0, S1, S2, S3) of the second bus expander 53 form the third group of downstream ports 56, which are connected to the third group of boards 26 located on the rear window of the server via the third group of first connectors 46.

[0071] The server in this application embodiment has a unified I2C topology planned according to physical location (front window / rear window / middle), which can simultaneously support 2U server and 4U server chassis and various hardware configurations such as front window, rear window, and middle window, and has good versatility and scalability.

[0072] According to embodiments of this application, a management controller is configured to, in response to receiving an presence signal on a first presence signal pin of the first connector, identify a board connected to the first connector as a first type of board and control a first expansion circuit to establish a first bus link between the management controller and the first type of board. In response to receiving an presence signal on a second presence signal pin of the first connector, the management controller identifies a board connected to the first connector as a second type of board and controls the first expansion circuit to establish a second bus link between the management controller and the second type of board.

[0073] like Figure 2A As shown, the management controller 3 receives an in-situ signal in response to the first in-situ signal pin Riser_PRST# of the first composite connector MCONN_0, recognizes that the first type board 21 connected to the first composite connector MCONN_0 is a first type board, and controls the first expansion circuit 5 to establish a first bus link between the management controller 3 and the first type board 21.

[0074] like Figure 2A As shown, the management controller 3 receives an in-situ signal in response to the second in-situ signal pin BP_PRST# of the second composite connector MCONN_1, recognizes that the second type board 22 connected to the second composite connector MCONN_1 is a second type board, and controls the first expansion circuit 5 to establish a second bus link between the management controller 3 and the second type board 22.

[0075] Bus controller 51 can be an I2C master device. An I2C master device is the primary control device in I2C bus communication, used to initiate and terminate data transmission, generate clock signals, and control bus access permissions. As the active party of the first bus link, bus controller 51 can address slave devices on the first type board 21 using a unique address and drive the serial clock line of the first bus link to synchronize data exchange with the first type board 21. As the active party of the second bus link, bus controller 51 can address slave devices on the second type board 22 using a unique address and drive the serial clock line of the second bus link to synchronize data exchange with the second type board 22. Bus controller 51 can also control the data transmission direction (read / write) of the first or second bus link, monitor the bus status of the first or second bus link (such as arbitration, slave device acknowledgment), and manage timing parameters (such as clock frequency, start / stop conditions). It can coordinate multi-device communication on the first or second bus link to ensure correct protocol execution.

[0076] The bus extender includes a first bus extender 52 and a second bus extender 53, which can be I2C switches. I2C switches can be used to expand I2C bus connectivity, switching the first bus link of an upstream port to one or more downstream ports, enabling time-division multiplexing communication between a single master device and multiple slave devices. The bus extender can control its internal switch state via the I2C protocol, resolving I2C bus address conflicts, excessive load capacitance, and electrical isolation issues, and supporting signal level matching across different voltage domains.

[0077] The motherboard of the electronic device in this application embodiment optimizes the I2C topology design, changing the division from function to physical location. This reduces the number of connection points and the physical error-proofing requirements of the production line. When connecting cables according to the I2C topology, the I2C signal can be automatically matched, reducing the human error rate and improving reliability.

[0078] Since the same cable can connect to both an adapter card and a backplane, the motherboard of the electronic device in this application embodiment can distinguish whether the card connected to the cable is an adapter card or a backplane through hardware design.

[0079] When all the server boards are connected to the motherboard via firmware, the management controller can establish corresponding bus links with the corresponding firmware-connected boards through multiple downstream channels of the first expansion circuit.

[0080] For example, when the adapter card is connected to the motherboard, the adapter card can ground the first presence signal pin Riser_PRST# of the first connector. The first presence signal pin Riser_PRST# is active low. The motherboard's management controller can receive the presence signal from the first presence signal pin Riser_PRST# through the downstream channel of the first expansion circuit connected to the corresponding firmware. The management controller establishes a first bus link with the adapter card through the downstream channel of the first expansion circuit connected to the corresponding firmware.

[0081] Firmware connectivity provides low-level driver functions to control the bus extender's switching to the target downstream channel. Upon system power-on or reset, the management controller sequentially scans each downstream channel of the bus extender according to a preset mapping table, discovers and initializes the I2C slave devices connected to the bus extender, and constructs the system device tree. If communication fails on a downstream channel of the bus extender, the firmware connection can retry multiple times. Multiple failures can mark the channel as abnormal and log them to prevent impact on normal communication of other downstream channels. Firmware connectivity also enables response to hot-plug interrupt events from boards, dynamically updating the status and channel availability of the corresponding devices in the device tree.

[0082] The motherboard of the electronic device in this application embodiment can prevent signal conflicts through intelligent firmware management.

[0083] When all server boards are physically connected to the motherboard, the management controller can establish corresponding bus links using in-situ signals. The following will describe two hardware connection methods, including multiplexers, to achieve automatic board type differentiation.

[0084] According to an embodiment of this application, the motherboard further includes multiple multiplexers. Multiple downstream ports of the first expansion circuit are respectively connected to multiple first connectors via multiple multiplexers. The control terminal of each multiplexer is connected to a management controller to receive selection signals from the management controller. The upstream ports of each multiplexer are respectively connected to corresponding downstream ports of the first expansion circuit via a first bus channel and a second bus channel. The downstream ports of each multiplexer are connected to corresponding first connectors. The first bus channel is used to transmit bus signals for a first type of board, and the second bus channel is used to transmit bus signals for a second type of board.

[0085] Figure 4 A schematic diagram of a first type of hardware connection of the motherboard according to an embodiment of this application is shown.

[0086] like Figure 4As shown, the motherboard also includes multiple multiplexers, such as a first multiplexer I2C_MUX_0 and a second multiplexer I2C_MUX_0. The management controller 3 on the motherboard can also be a BMC or a CPU. The bus controller can be an I2C bus controller I2C_M. The bus extender can be an I2C bus extender I2C_S. The first expansion circuit includes the I2C bus controller I2C_M and the I2C bus extender I2C_S. Multiple downstream ports of the I2C bus extender I2C_S of the first expansion circuit are connected to the first composite connector MCONN_0 and the second composite connector MCONN_1 respectively through the first multiplexer I2C_MUX_0 and the second multiplexer I2C_MUX_1.

[0087] When the board connected to the first composite connector MCONN_0 is a first type board 21, the control terminal of the first multiplexer I2C_MUX_0 is connected to the management controller 3, and receives the first selection signal SEL0 from the management controller 3. The upstream port of the first multiplexer I2C_MUX_0 is connected to the corresponding downstream port of the I2C bus extender I2C_S through the first bus channel I2C_Riser. The downstream port of the first multiplexer I2C_MUX_0 is connected to the first composite connector MCONN_0. The first bus channel I2C_Riser can transmit bus signals for the first type of board.

[0088] When the board connected to the second composite connector MCONN_1 is a second type board 22, the control terminal of the second multiplexer I2C_MUX_1 is connected to the management controller 3, and receives the second selection signal SEL1 from the management controller 3. The upstream port of the second multiplexer I2C_MUX_1 is connected to the corresponding downstream port of the I2C bus extender I2C_S through the second bus channel I2C_BP. The downstream port of the second multiplexer I2C_MUX_1 is connected to the second composite connector MCONN_1, and the second bus channel I2C_BP is used to transmit bus signals for the second type of board.

[0089] According to an embodiment of this application, the management controller is configured to provide a first selection signal to a multiplexer connected to the first connector in response to receiving an in-situ signal at a first in-situ signal pin of the first connector; and to provide a second selection signal to the multiplexer connected to the first connector in response to receiving an in-situ signal at a second in-situ signal pin of the first connector.

[0090] According to an embodiment of this application, the multiplexer is configured to connect the corresponding first connector to a first bus channel in response to receiving a first selection signal from the management controller; and to connect the corresponding first connector to a second bus channel in response to receiving a second selection signal from the management controller.

[0091] like Figure 2B , 2C and Figure 4 As shown, in response to receiving an in-situ signal on the first in-situ signal pin Riser_PRST# of the first composite connector MCONN_0, the management controller 3 recognizes that the first type board 21 connected to the first composite connector MCONN_0 is a first type board, and provides a first selection signal SEL0 to the first multiplexer I2C_MUX_0. In response to receiving the first selection signal SEL0 from the management controller 3, the first multiplexer I2C_MUX_0 connects the first composite connector MCONN_0 to the first bus channel I2C_Riser.

[0092] Upon receiving an presence signal on the second presence signal pin BP_PRST# of the second composite connector MCONN_1, the management controller 3 recognizes that the second type board 22 connected to the second composite connector MCONN_1 is a second type board, and provides a second selection signal SEL1 to the second multiplexer I2C_MUX_1. In response to receiving the second selection signal SEL1 from the management controller 3, the second multiplexer I2C_MUX_1 connects the second composite connector MCONN_1 to the second bus channel I2C_BP.

[0093] According to an embodiment of this application, the motherboard further includes multiple multiplexers. Multiple downstream ports of the bus controller are respectively connected to multiple bus expanders through multiple multiplexers. The control terminal of the multiplexer is connected to the management controller to receive selection signals from the management controller. The upstream ports of the multiplexers are respectively connected to the corresponding downstream ports of the bus controller through a first bus channel and a second bus channel. The downstream ports of the multiplexers are connected to the corresponding bus expanders. The first bus channel is used to transmit bus signals for a first type of board, and the second bus channel is used to transmit bus signals for a second type of board.

[0094] Figure 5 A schematic diagram of a second type of hardware connection for the motherboard according to an embodiment of this application is shown.

[0095] like Figure 5As shown, the motherboard also includes multiple multiplexers, such as a first multiplexer I2C_MUX_0 and a second multiplexer I2C_MUX_0. The management controller 3 on the motherboard can also be a BMC or a CPU. The bus controller can be an I2C bus controller I2C_M. The first bus extender can be a first I2C bus extender I2C_S_0. The second bus extender can be a second I2C bus extender I2C_S_1. The first expansion circuit includes the I2C bus controller I2C_M, the first I2C bus extender I2C_S_0, and the second I2C bus extender I2C_S_1. Multiple downstream ports of the I2C bus controller I2C_M of the first expansion circuit are connected to the first I2C bus extender I2C_S_0 and the second I2C bus extender I2C_S_1 respectively through the first multiplexer I2C_MUX_0 and the second multiplexer I2C_MUX_1.

[0096] The control terminal of the first multiplexer I2C_MUX_0 is connected to the management controller 3, and receives the first selection signal SEL0 from the management controller 3. The upstream port of the first multiplexer I2C_MUX_0 is connected to the corresponding downstream port of the I2C bus controller I2C_M through the first bus channel I2C_Riser. The downstream port of the first multiplexer I2C_MUX_0 is connected to the first I2C bus extender I2C_S_0. The first bus channel I2C_Riser can transmit bus signals for the first type of board.

[0097] The control terminal of the second multiplexer I2C_MUX_1 is connected to the management controller 3, and receives the second selection signal SEL1 from the management controller 3. The upstream port of the second multiplexer I2C_MUX_1 is connected to the corresponding downstream port of the I2C bus controller I2C_M through the second bus channel I2C_BP. The downstream port of the second multiplexer I2C_MUX_1 is connected to the second I2C bus extender I2C_S_1. The second bus channel I2C_BP is used to transmit bus signals for the second type of board.

[0098] According to an embodiment of this application, the management controller is configured to: for each of a plurality of bus extenders, in response to a first presence signal pin of a first connector to which the bus extender is connected receiving a presence signal, provide a first selection signal to a multiplexer connected to the bus extender; and in response to a second presence signal pin of a first connector to which the bus extender is connected receiving a presence signal, provide a second selection signal to a multiplexer connected to the bus extender.

[0099] According to an embodiment of this application, the multiplexer is configured to: in response to receiving a first selection signal from the management controller, connect the corresponding bus extender to a first bus channel; and in response to receiving a second selection signal from the management controller, connect the corresponding bus extender to a second bus channel.

[0100] like Figure 5 As shown, in response to receiving an presence signal on the first presence signal pin of the first connector 4 to which the first I2C bus extender I2C_S_0 is connected, the management controller 3 recognizes that the first type board 21 connected to the first I2C bus extender I2C_S_0 is a first type board, and provides a first selection signal SEL0 to the first multiplexer I2C_MUX_0 connected to the first I2C bus extender I2C_S_0. In response to receiving the first selection signal SEL0 from the management controller 3, the first multiplexer I2C_MUX_0 connects the first I2C bus extender I2C_S_0 to the first bus channel I2C_Riser.

[0101] In response to receiving an presence signal on the second presence signal pin of the first connector 4 to which the second I2C bus extender I2C_S_1 is connected, the management controller 3 recognizes that the second type board 22 connected to the second I2C bus extender I2C_S_1 is a second type board, and provides a second selection signal SEL1 to the second multiplexer I2C_MUX_1 connected to the second I2C bus extender I2C_S_1. In response to receiving the second selection signal SEL1 from the management controller 3, the second multiplexer I2C_MUX_1 connects the second I2C bus extender I2C_S_1 to the second bus channel I2C_BP.

[0102] For servers where all expansion cards and the motherboard are connected via hardware, as shown in... Figure 4 and Figure 5 The two hardware connection methods shown include multiplexers. The management controller can establish corresponding bus links through in-situ signals to achieve automatic hardware differentiation of board types without the need for firmware adaptation.

[0103] The motherboard of the electronic device in this application embodiment automatically distinguishes the board type through hardware, realizing multi-functionality of a single interface.

[0104] According to embodiments of this application, the motherboard further includes a second expansion circuit, through which the management controller is connected to the first and second in-situ signal pins of a plurality of first connectors. For example... Figure 2AAs shown, the management controller 3 is connected to the first and second presence signal pins of the first composite connector MCONN_0 via the second expansion circuit 6, and is also connected to the first and second presence signal pins of the second composite connector MCONN_1 via the second expansion circuit 6. The second expansion circuit 6 can be connected to the first and second presence signal pins of the first composite connector MCONN_0 via the first presence signal first trace Riser_PRST_0 and the second presence signal first trace BP_PRST_0, respectively. Similarly, the second expansion circuit 6 can be connected to the first and second presence signal pins of the second composite connector MCONN_1 via the first presence signal second trace Riser_PRST_1 and the second presence signal second trace BP_PRST_1, respectively.

[0105] According to embodiments of this application, the first connector further includes a power pin for connecting to a power pin on the board to provide a power signal to the board. Figure 2A , Figure 2B and Figure 2C As shown, the first composite connector MCONN_0 includes 2×5 power pins, representing 10 power pins. These 2×5 power pins of the first composite connector MCONN_0 are connected to the 2×5 power pins of the adapter card, providing power signals to the adapter card. The second composite connector MCONN_1 also includes 2×5 power pins, representing 10 power pins. These 2×5 power pins of the second composite connector MCONN_1 are connected to the 2×5 power pins of the BP (Browser Adapter), providing power signals to the BP. The power pins of both the first and second composite connectors MCONN_0 can also obtain power supply voltage through traces on the motherboard.

[0106] The motherboard of the electronic device in this application embodiment can reduce the number of connectors on the motherboard by merging the power connector and the sideband signal connector, thereby freeing up space for other functional devices on the motherboard. It can also reduce the number of cables between the motherboard and other boards in the server, reduce the difficulty of cable management during the generation and maintenance process, and make the server airflow smoother.

[0107] According to an embodiment of this application, the first presence signal pin, the second presence signal pin, and the bus pin of the first connector are connected to the management controller. The power supply pin of the first connector is connected to an external power module via a programmable protection circuit on the motherboard.

[0108] Figure 6 A schematic diagram of the motherboard of an electronic device according to yet another embodiment of this application is shown.

[0109] like Figure 6As shown, the 2×5 power pins of the first composite connector MCONN_0 can also be connected to the power module 8 outside the motherboard 1 via the programmable protection circuit 81 on the motherboard 1. The power module 8 outside the motherboard 1 can provide power supply voltage to the 2×5 power pins of the first composite connector MCONN_0 via the programmable protection circuit 81 on the motherboard 1.

[0110] According to an embodiment of this application, the first connector further includes an auxiliary power supply pin for connecting to the auxiliary power supply pin of the board to provide an auxiliary power supply signal to the board. The auxiliary power supply pin of the first connector is connected to a power management module on the motherboard, and the power management module on the motherboard is connected to a power module outside the motherboard. Figure 2A , Figure 2B and Figure 2C As shown, the first composite connector MCONN_0 includes an auxiliary power supply pin 3.3_AUX, which is connected to the auxiliary power supply pin 3.3_AUX of the adapter card, providing an auxiliary power supply signal to the adapter card. The second composite connector MCONN_1 also includes an auxiliary power supply pin 3.3_AUX, which is connected to the auxiliary power supply pin 3.3_AUX of the backplane, providing an auxiliary power supply signal to the backplane. The auxiliary power supply pins 3.3_AUX of both the first and second composite connectors MCONN_0 and MCONN_1 can also obtain auxiliary power supply voltage through traces on the motherboard. For example... Figure 2A , Figure 2B and Figure 2C As shown, the first composite connector MCONN_0 includes a multiplexed pin GND / GPIO, which is connected to the multiplexed pin GND / GPIO of the adapter card. The second composite connector MCONN_1 includes a multiplexed pin GND / GPIO, which is connected to the multiplexed pin GND / GPIO of the backplane. The multiplexed pin GND / GPIO can be used as a ground pin or a control pin. Therefore, the ground pins of the first composite connector MCONN_0 and the second composite connector MCONN_1 can be connected to the ground pins of the adapter card and the backplane, respectively, and the control pins of the first composite connector MCONN_0 and the second composite connector MCONN_1 can be connected to the control pins of the adapter card and the backplane, respectively.

[0111] like Figure 6As shown, the auxiliary power supply pin 3.3_AUX of the first composite connector MCONN_0 can be connected to the power module 8 outside the motherboard 1 through the power management module 82 on the motherboard 1. The power module 8 outside the motherboard 1 can provide auxiliary power supply voltage to the auxiliary power supply pin 3.3_AUX of the first composite connector MCONN_0 through the power management module 82 on the motherboard 1.

[0112] According to embodiments of this application, the first connector further includes a ground pin or a control pin. The ground pin is used to connect to the ground pin of the board, and the control pin is used to connect to the control pin of the board. The ground pin of the first connector is connected to the ground plane of the motherboard, and the control pin of the first connector is connected to the management controller on the motherboard. Figure 6 As shown, when the multiplexed pin GND / GPIO of the first composite connector MCONN_0 is used as a ground pin, the ground pin of the first composite connector MCONN_0 is connected to the ground plane 9 of the motherboard 1. When the multiplexed pin GND / GPIO of the first composite connector MCONN_0 is used as a control pin, the control pin of the first composite connector MCONN_0 is connected to the management controller 3 on the motherboard 1.

[0113] According to embodiments of this application, there are multiple first connectors, which are used to connect multiple boards respectively. The motherboard also includes a third expansion circuit, and the management controller is connected to the control pins of the multiple first connectors through the third expansion circuit. Figure 2A and Figure 6 As shown, the first composite connector MCONN_0 and the second composite connector MCONN_1 are connected to the adapter card and the backplane, respectively. The motherboard 1 is provided with a third expansion circuit 7, and the management controller 3 is connected to the control pins of the first composite connector MCONN_0 and the second composite connector MCONN_1 through the first control pin line GPIO_0 and the second control pin line GPIO_1 of the third expansion circuit 7, respectively.

[0114] Figure 7 A schematic diagram of a first connector according to another embodiment of this application is shown.

[0115] like Figure 7As shown, the first connector in this embodiment is a multi-functional composite connector with 16 pins, combining a power connector and a sideband signal connector. The first connector includes power pins and sideband signal pins. The top of the first connector has 10 power pins, which can be used to transmit low-voltage DC power such as +12V, +5V, and +3.3V, as well as a return ground line. The bottom 6 pins of the first connector are sideband signal pins. Referring to Table 2, the sideband signal pins are auxiliary power supply pin 3.3_AUX, bus data pin I2C_SDA, multiplexed pin GND / GPIO, bus clock pin I2C_CLK, first presence signal pin Riser_PRST#, and second presence signal pin BP_PRST#, totaling 16 pins.

[0116] Table 2

[0117]

[0118] As shown in Table 2, the first pin 0# is the auxiliary power supply pin 3.3_AUX. The auxiliary power supply pin 3.3_AUX provides 3V3 auxiliary power to the board in S5 state. In S5 state, the server motherboard maintains only a +5V standby voltage; the CPU, memory, and PCIe links are all powered down, and the system does not retain context. The second pin 1# and the fourth pin 3# are the bus data pin I2C_SDA and the bus clock pin I2C_CLK, respectively. The bus pin consisting of the bus data pin I2C_SDA and the bus clock pin I2C_CLK can connect to both the adapter card and the BP. The fifth pin 4# is the first presence signal pin Riser_PRST#. A low active state of the first presence signal pin Riser_PRST# indicates that the adapter card is present. The sixth pin 5# is the second presence signal pin BP_PRST#. A low active state of the second presence signal pin BP_PRST# indicates that the BP is present. The third pin 2# is the multiplexed pin GND / GPIO. The multiplexed pin GND / GPIO allows control of timing or configuration pins (Strap Pins) via GPIO (General Purpose Input / Output). After the management controller identifies the board type connected to the first connector, it can use the multiplexed pin GND / GPIO of the first connector as a control pin. The management controller can control timing through the control pin; for example, it can convert the 3V3_SDBY (3.3V Stand-by) voltage in standby mode to 3V3_CORE (3.3V Corepower) voltage usable by the load. The management controller can also control configuration pins through the control pins. For example, it can use configuration pin information to distinguish whether the hard drive backplane is directly connected to the CPU or connected to a Tri-mode Raid (Triple-Mode Redundant Array of Independent Disks) card.

[0119] Figure 8A A schematic diagram of an electronic device according to an embodiment of this application is shown.

[0120] like Figure 8A As shown, the electronic device includes a motherboard 1 and a board 2, with the board 2 connected to a first connector on the motherboard 1.

[0121] The board has a second connector, and the motherboard's first connector is connected to the board's second connector.

[0122] The second connector has 2×5 power supply pins, bus pins, and a presence signal pin. The 2×5 power supply pins of the second connector are connected to the 2×5 power supply pins of the first connector. The bus pins of the second connector are connected to the bus pins of the first connector. The presence signal pins of the second connector are connected to either the first presence signal pin or the second presence signal pin of the first connector. The bus pins of the second connector include bus data pins and bus clock pins.

[0123] When the board is of the first type, the presence signal pin of the second connector is connected to the first presence signal pin of the first connector. When the board is of the second type, the presence signal pin of the second connector is connected to the second presence signal pin of the first connector.

[0124] According to an embodiment of this application, the presence signal pin of the second connector is grounded in the board, so that when the second connector is connected to the first connector, a presence signal is generated at the first presence signal pin or the second presence signal pin of the first connector.

[0125] According to an embodiment of this application, the second connector also has an auxiliary power supply pin, which is used to provide an auxiliary power supply signal to the circuit module in the board, and the auxiliary power supply pin of the second connector is connected to the auxiliary power supply pin of the first connector.

[0126] The second connector also has a ground pin or a control pin. The ground pin of the second connector is connected to the ground pin of the first connector, and the control pin of the second connector is connected to the control pin of the first connector. The second connector also has a multiplexed pin, which is connected to a multiplexed pin of the first connector. When the multiplexed pin of the second connector is used as a ground pin, the ground pin of the second connector is connected to the ground pin of the first connector. When the multiplexed pin of the second connector is used as a control pin, the control pin of the second connector is connected to the control pin of the first connector.

[0127] The electronic device of this application embodiment can reduce the number of connectors on the board by merging the power connector and the sideband signal connector and setting a second connector on the board, thereby freeing up space for other functional devices on the board.

[0128] Figure 8B A schematic diagram of a board of a first type according to an embodiment of this application is shown.

[0129] like Figure 8B As shown, when the board is of the first type, the motherboard is connected to the first type board 21 via the first connector and the second connector 9. The first connector and the second connector 9 are connected by a cable.

[0130] The first type of board 21 may include a second connector 9, a PCIe (PCIe) expansion chip 221, an I2C expansion chip 222, a circuit module 223, and an I2C device 225. The I2C device 225 of the first type of board 21 represents an I2C slave device on the first type of board 21, such as a temperature sensor, an EEPROM, etc.

[0131] The 2×5 power pins of the second connector 9 are connected to the circuit module 223. The circuit module 223 can obtain a power supply voltage through the connection between the 2×5 power pins of the second connector 9 and the 2×5 power pins of the first connector. The circuit module 223 can convert the 12V power supply voltage. The circuit module 223 can step down the 12V power supply voltage through an electronic fuse (eFuse) and a multi-channel VR (Voltage Regulator) chip to generate 5V, 3.3V, etc. power supply rails to power other devices on the first type of board 21.

[0132] The auxiliary power supply pin 3.3_AUX of the second connector 9 connects to the PCIe expansion chip 221, the I2C expansion chip 222, and the I2C device 225. The PCIe expansion chip 221, the I2C expansion chip 222, and the I2C device 225 can obtain auxiliary power supply voltage through the connection between the auxiliary power supply pin 3.3_AUX of the second connector 9 and the auxiliary power supply pin 3.3_AUX of the first connector. The auxiliary power supply voltage is a standby voltage of 3.3V.

[0133] The bus pins of the second connector 9 are connected to the I2C expansion chip 222. The I2C expansion chip 222 can receive I2C control signals from the motherboard and send I2C status information of the first type board 21 to the motherboard through the connection between the bus pins of the second connector 9 and the bus pins of the first connector.

[0134] The multiplexed pin GND / GPIO of the second connector 9 can be connected to the PCIe expansion chip 221.

[0135] When the first type board 21 is connected to the first connector, the first presence signal pin Riser_PRST# of the first connector is grounded and is in a low active state. The motherboard's management controller can obtain the presence signal of the first presence signal pin Riser_PRST# of the first connector and confirm that the board connected to the first connector is a first type board.

[0136] Figure 8C A schematic diagram of a second type of board according to an embodiment of this application is shown.

[0137] likeFigure 8C As shown, when the board is of the second type, the motherboard is connected to the second type board 22 via the first connector and the second connector 9. The first connector and the second connector 9 are connected by a cable.

[0138] The second type of board 22 may include a second connector 9, an I2C expansion chip 222, a circuit module 223, a CPLD (Complex Programmable Logic Device) 224, and an I2C device 225. The I2C device 225 of the second type of board 22 represents an I2C slave device on the second type of board 22, such as a temperature sensor, an EEPROM, etc.

[0139] The 2×5 power pins of the second connector 9 are connected to the circuit module 223. The circuit module 223 can obtain a power supply voltage through the connection between the 2×5 power pins of the second connector 9 and the 2×5 power pins of the first connector. The circuit module 223 can convert the 12V power supply voltage. The circuit module 223 can step down the 12V power supply voltage through an electronic fuse (eFuse) and a multi-channel VR (Voltage Regulator) chip to generate 5V, 3.3V, etc. power supply rails to power other devices on the second type board 22.

[0140] The auxiliary power supply pin 3.3_AUX of the second connector 9 connects to the I2C expansion chip 222, CPLD 224, and I2C device 225. The I2C expansion chip 222, CPLD 224, and I2C device 225 can obtain auxiliary power supply voltage through the connection between the auxiliary power supply pin 3.3_AUX of the second connector 9 and the auxiliary power supply pin 3.3_AUX of the first connector. The auxiliary power supply voltage is a 3.3V standby voltage. When the hard drive type is E1.S or E3.S, or when it is necessary to read information such as the hard drive backplane temperature in S5 state, an auxiliary voltage line needs to be connected from the motherboard to provide a 3.3V auxiliary power supply voltage. E1.S and E3.S are two sub-series in the EDSFF (Enterprise & Datacenter SSD Form Factor) standard, where SSD stands for Solid State Drive.

[0141] The bus pins of the second connector 9 are connected to the I2C expansion chip 222. The I2C expansion chip 222 can receive I2C control signals from the motherboard and send I2C status information of the second type board 22 to the motherboard through the connection between the bus pins of the second connector 9 and the bus pins of the first connector.

[0142] The multiplexed pin GND / GPIO of the second connector 9 can be connected to the CPLD 224.

[0143] When the second present signal pin BP_PRST# of the second connector 9 is grounded, and the second type board 22 is connected to the first connector, the second present signal pin BP_PRST# of the first connector is grounded and is in a low active state. The motherboard's management controller can obtain the present signal of the second present signal pin BP_PRST# of the first connector and confirm that the board connected to the first connector is a second type board.

[0144] In one example, the second connector can have the same characteristics as the first connector. Figure 7 The same pin design is shown. The second connector may also include a first presence signal pin Riser_PRST# and a second presence signal pin BP_PRST#, which can be connected to the first presence signal pin Riser_PRST# and the second presence signal pin BP_PRST# of the second connector, respectively. For example, when the first type of board is connected to the first connector, the first presence signal pin Riser_PRST# of the second connector of the first type of board is grounded, and the second presence signal pin BP_PRST# of the second connector is left unconnected.

[0145] Figure 9A This diagram illustrates the connector layout logic of the previous generation server.

[0146] Figure 9B This diagram illustrates the connector layout logic on the motherboard of a previous generation server.

[0147] like Figure 9A and Figure 9B As shown, the filled blocks are power connectors, and the blank blocks are sideband signal connectors. Figure 9A As shown, the previous generation server had power connectors and sideband signal connectors on multiple adapter cards. The previous generation server also had power connectors and sideband signal connectors on multiple backplanes. The previous generation server's mainboard had multiple power connectors, which connected to the power connectors on the multiple adapter cards and the multiple backplanes. The previous generation server's mainboard also had multiple sideband signal connectors, which connected to the sideband signal connectors on the multiple adapter cards and the multiple backplanes. Referring to the configuration of the 4U server in Table 1, combined with... Figure 9BAs shown, the motherboard of the previous generation server required four power connectors and three sideband signal connectors to connect to the adapter card or backplane in the front window of the 4U server; three power connectors and two sideband signal connectors to connect to the adapter card or backplane in the center of the 4U server; and four power connectors and four sideband signal connectors to connect to the adapter card or backplane in the rear window of the 4U server. For the 4U server configuration in Table 1, the motherboard of the previous generation server required a total of 20 dedicated connectors.

[0148] Figure 10A A schematic diagram of a first connector layout logic for a server according to an embodiment of this application is shown.

[0149] Figure 10B A schematic diagram of a second connector layout logic for a server according to an embodiment of this application is shown.

[0150] Figure 10C A schematic diagram of the connector layout logic on the motherboard of a server according to an embodiment of this application is shown.

[0151] like Figure 10A As shown, the first connector in this embodiment includes power pins and sideband signal pins; therefore, a composite connector is used to represent the first connector in this embodiment. Multiple composite connectors are provided on the motherboard of the server in this embodiment. When a power connector including power pins and a sideband signal connector including sideband signal pins are respectively provided on an adapter card or backplane, multiple composite connectors on the motherboard can be connected to the power connectors and sideband signal connectors on multiple adapter cards or backplanes via Y-type cables.

[0152] The motherboard of the electronic device in this application embodiment can be compatible with some of the original I2C topology and power topology designs with separate adapter cards and backplanes. By optimizing the I2C topology design, it is compatible with the topology architecture of the previous generation of boards, increasing reusability and flexibility, and reducing design and material costs.

[0153] like Figure 10B As shown, when a composite connector is provided on an adapter card or backplane, the composite connector on the motherboard can be connected to multiple composite connectors on the adapter card or backplane via cables. The motherboard of the electronic device in this embodiment can be connected one-to-one via cables, providing better operability and maintainability.

[0154] Regarding the configuration of the 4U server in Table 1, combined with Figure 10CAs shown, the server motherboard in this embodiment requires a total of 11 dedicated composite connectors, i.e., 11 first connectors. The motherboard of the electronic device in this embodiment, through a merging scheme, reduces the number of connectors used to connect the adapter cards or backplanes in the front window of the 4U server to 4, the number of connectors used to connect the adapter cards or backplanes in the center of the 4U server to 3, and the number of connectors used to connect the adapter cards or backplanes in the rear window of the 4U server to 4. Overall, the number of connectors on the motherboard is reduced from 20 dedicated connectors in the previous generation of servers to 11.

[0155] The motherboard of the electronic device in this application embodiment, based on the technical concept of functional integration, topology optimization and logic reuse, can be used to solve the problems of numerous sensor management buses and complex wiring in other different types of servers under different front window, rear window and center configuration conditions, as well as the optimized design of heat dissipation control system.

[0156] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0157] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. A motherboard for an electronic device, characterized in that, The motherboard is provided with a management controller and a first connector connected to the management controller. The first connector is used to connect to the board of an electronic device, wherein the first connector includes: Bus pins are used to connect to the bus pins of the board to transmit bus signals between the board and the board. The first presence signal pin is used to connect to the presence signal pin of the first type of board to receive the presence signal of the first type of board; The second presence signal pin is used to connect to the presence signal pin of the second type of board to receive the presence signal of the second type of board; The management controller is configured to identify a board connected to the first connector as a first type of board in response to receiving an in-situ signal on a first in-situ signal pin, and to identify a board connected to the first connector as a second type of board in response to receiving an in-situ signal on a second in-situ signal pin.

2. The motherboard according to claim 1, characterized in that, There are multiple first connectors, which are used to connect multiple boards respectively.

3. The motherboard according to claim 1, characterized in that, The motherboard also includes a first expansion circuit, the upstream port of which is connected to the bus interface of the management controller, and multiple downstream ports of the first expansion circuit are respectively connected to the bus pins of multiple first connectors.

4. The motherboard according to claim 3, characterized in that, The first expansion circuit includes a bus controller and multiple bus expanders. The upstream port of the bus controller is connected to the bus interface of the management controller. The multiple downstream ports of the bus controller are respectively connected to the multiple bus expanders. The upstream port of the bus expander is connected to the corresponding downstream port of the bus controller. The multiple downstream ports of the bus expander are respectively connected to the bus pins of the corresponding first connector.

5. The motherboard according to claim 4, characterized in that, The bus expander includes a first bus expander and a second bus expander; The downstream ports of the first bus expander include a first set of downstream ports and a second set of downstream ports, wherein the first set of downstream ports is used to connect to a first set of boards through a first set of first connectors, and the second set of downstream ports is used to connect to a second set of boards through a second set of first connectors. The downstream port of the second bus expander connects to the third set of boards; The first set of boards is located in the first area of ​​the electronic device, and the second set of boards is located in the second area of ​​the electronic device. The third set of boards is located in the third area of ​​the electronic device.

6. The motherboard according to claim 5, characterized in that, The first group of boards, the second group of boards, and the third group of boards each include at least one of the first type of boards and the second type of boards.

7. The motherboard according to claim 5, characterized in that, The electronic device is a server, with the first set of boards located on the front of the server and the third set of boards located on the back of the server. The second set of boards is located in the area between the front and rear windows of the server.

8. The motherboard according to claim 5, characterized in that, The downstream ports of the first bus extender also include an additional downstream port, which connects to the motherboard's built-in storage module.

9. The motherboard according to claim 3, characterized in that, The management controller is configured as follows: In response to receiving an in-place signal on the first in-place signal pin of the first connector, the board connected to the first connector is identified as a first type of board, and the first expansion circuit is controlled to establish a first bus link between the management controller and the first type of board. In response to receiving an in-place signal on the second in-place signal pin of the first connector, the board connected to the first connector is identified as a second type of board, and the first expansion circuit is controlled to establish a second bus link between the management controller and the second type of board.

10. The motherboard according to claim 3, characterized in that, The motherboard further includes: multiple multiplexers, with multiple downstream ports of the first expansion circuit connected to multiple first connectors via multiple multiplexers, wherein the control terminal of the multiplexer is connected to the management controller to receive selection signals from the management controller, the upstream ports of the multiplexer are connected to the corresponding downstream ports of the first expansion circuit via a first bus channel and a second bus channel, and the downstream ports of the multiplexer are connected to the corresponding first connectors, wherein the first bus channel is used to transmit bus signals for the first type of board, and the second bus channel is used to transmit bus signals for the second type of board.

11. The motherboard according to claim 10, characterized in that, The management controller is configured to: for each of the plurality of first connectors, in response to receiving an in-place signal on a first in-place signal pin of the first connector, provide a first selection signal to a multiplexer connected to the first connector; In response to receiving an in-place signal on the second in-place signal pin of the first connector, a second selection signal is provided to the multiplexer connected to the first connector; The multiplexer is configured to connect the corresponding first connector to the first bus channel in response to receiving a first selection signal from the management controller; In response to receiving a second selection signal from the management controller, the corresponding first connector is connected to the second bus channel.

12. The motherboard according to claim 4, characterized in that, The motherboard further includes: multiple multiplexers, and multiple downstream ports of the bus controller are respectively connected to multiple bus expanders through multiple multiplexers. The control terminal of the multiplexer is connected to the management controller to receive selection signals from the management controller. The upstream ports of the multiplexers are respectively connected to the corresponding downstream ports of the bus controller through a first bus channel and a second bus channel. The downstream ports of the multiplexers are connected to the corresponding bus expanders. The first bus channel is used to transmit bus signals for the first type of board, and the second bus channel is used to transmit bus signals for the second type of board.

13. The motherboard according to claim 12, characterized in that, The management controller is configured to: for each of the plurality of bus extenders, in response to receiving an in-place signal on a first in-place signal pin of a first connector to which the bus extender is connected, provide a first selection signal to a multiplexer connected to the bus extender; In response to receiving an in-place signal on the second in-place signal pin of the first connector to which the bus extender is connected, a second selection signal is provided to the multiplexer connected to the bus extender; The multiplexer is configured to connect the corresponding bus extender to the first bus channel in response to receiving a first selection signal from the management controller; In response to receiving a second selection signal from the management controller, the corresponding bus extender is connected to the second bus channel.

14. The motherboard according to claim 2, characterized in that, The motherboard also includes a second expansion circuit, through which the management controller is connected to the first and second in-situ signal pins of multiple first connectors.

15. The motherboard according to claim 1, characterized in that, The first connector also includes a power pin for connecting to the power pin of the board to provide a power signal to the board.

16. The motherboard according to claim 15, characterized in that, The first in-place signal pin, the second in-place signal pin, and the bus pin of the first connector are connected to the management controller. The power pins of the first connector are connected to the power module outside the motherboard via a programmable protection circuit on the motherboard.

17. The motherboard according to claim 1, characterized in that, The first connector also includes an auxiliary power supply pin for connecting to the auxiliary power supply pin of the board to provide an auxiliary power supply signal to the board. The auxiliary power supply pin of the first connector is connected to the power management module on the motherboard, and the power management module on the motherboard is connected to the power module outside the motherboard. The first connector also includes a ground pin or a control pin. The ground pin is used to connect to the ground pin of the board, and the control pin is used to connect to the control pin of the board. The ground pin of the first connector is connected to the ground plane of the motherboard, and the control pin of the first connector is connected to the management controller on the motherboard.

18. The motherboard according to claim 17, characterized in that, The number of first connectors is multiple, used to connect multiple boards respectively. The motherboard also includes a third expansion circuit, and the management controller is connected to the control pins of the multiple first connectors through the third expansion circuit.

19. The motherboard according to any one of claims 1 to 18, characterized in that, The first type of board is a backplane, the second type of board is an adapter card, the management controller is a baseboard management controller or a central processing unit, and the bus pins are integrated circuit bus pins.

20. An electronic device, characterized in that, include: The motherboard as described in any one of claims 1 to 19; as well as The board connects to the first connector on the motherboard.

21. The electronic device according to claim 20, characterized in that, The board has a second connector, and the motherboard's first connector connects to the board's second connector. The second connector has a power supply pin, a bus pin, and an in-situ signal pin. The power supply pin of the second connector is connected to the power supply pin of the first connector, the bus pin of the second connector is connected to the bus pin of the first connector, and the in-situ signal pin of the second connector is connected to either the first in-situ signal pin or the second in-situ signal pin of the first connector.

22. The electronic device according to claim 21, characterized in that, The board is of type 1, and the presence signal pin of the second connector is connected to the first presence signal pin of the first connector; or The board is a second type of board, and the presence signal pin of the second connector is connected to the second presence signal pin of the first connector.

23. The electronic device according to claim 22, characterized in that, The presence signal pin of the second connector is grounded in the board, so that when the second connector is connected to the first connector, a presence signal is generated at the first presence signal pin or the second presence signal pin of the first connector.

24. The electronic device according to any one of claims 21 to 23, characterized in that, The second connector also has an auxiliary power supply pin for providing auxiliary power supply signals to the circuit modules inside the board. The auxiliary power supply pin of the second connector is connected to the auxiliary power supply pin of the first connector. The second connector also has a ground pin or a control pin, the ground pin of the second connector being connected to the ground pin of the first connector, and the control pin of the second connector being connected to the control pin of the first connector.

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