Power switch drive circuit and power converter
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- AUDAHETAO INTEGRATED CIRCUIT RES INST FUTIAN DISTRICT SHENZHEN
- Filing Date
- 2025-12-30
- Publication Date
- 2026-06-02
Smart Images
Figure CN121417658B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of switching power supply converter technology, and in particular to a power switch drive circuit and a power supply converter. Background Technology
[0002] Power switching drive technology is a technique for controlling the switching process of power semiconductor devices (such as gallium nitride field-effect transistors). It is widely used in high-frequency buck converters such as gallium nitride power supply systems and gallium nitride buck converters. Its core purpose is to reduce high-frequency current components by optimizing the switching waveform, thereby suppressing EMI (Electromagnetic Interference) and providing a stable, efficient, and low-noise power supply for servers and edge AI acceleration chips in AI (Artificial Intelligence) large-scale model data centers.
[0003] In current EMI suppression schemes for power switch drive technology, Miller plateau detection is typically used. This involves detecting the feedforward voltage and using a compensation mechanism to simulate the Miller plateau voltage. When the Miller plateau voltage arrives, the gate current is reduced to slow down the turn-on of the high-level power switch and reduce the rise rate of the VSW (Voltage Standing Wave) of the high-level power switch, thereby suppressing EMI in the circuit.
[0004] However, Miller platform detection technology is limited by picosecond-level signal delay and process angle variations, which can easily lead to detection errors and control lag, reducing the robustness and industrial applicability of the circuit. Summary of the Invention
[0005] The main objective of this application is to propose a power switch drive circuit and power converter that aims to achieve wide-area EMI suppression while ensuring high efficiency and high energy density, thereby improving the robustness and industrial applicability of the circuit.
[0006] In a first aspect, the present invention provides a power switch driving circuit, comprising: an electromagnetic interference (EMI) detection circuit, a first asynchronous sampling circuit, a second asynchronous sampling circuit, a comparator circuit, an off-chip control circuit, a first gate driving circuit, and a second gate driving circuit; wherein the first gate driving circuit is used to connect to the gate of a first power switch in a power converter, and the second gate driving circuit is used to connect to the gate of a second power switch in the power converter.
[0007] The input terminal of the EMI detection circuit is connected to a preset switching node between the first power switch and the second power switch to perform on-chip EMI detection on the switching voltage signal of the preset switching node to obtain an EMI detection signal. The output terminal of the EMI detection circuit is connected to the input terminal of the first asynchronous sampling circuit and the input terminal of the second asynchronous sampling circuit, so that the first asynchronous sampling circuit and the second asynchronous sampling circuit detect the EMI detection signal in different periods to obtain a first EMI performance detection parameter and a second EMI performance detection parameter.
[0008] The output terminals of the first asynchronous sampling circuit and the second asynchronous sampling circuit are also connected to the comparison circuit, so that the comparison circuit compares the first EMI performance detection parameter and the second EMI performance detection parameter to obtain a comparison result; the comparison circuit is also connected to the off-chip control circuit, which is connected to the first gate drive circuit, so that the off-chip control circuit adjusts the first gate drive signal according to the comparison result, and adjusts the EMI performance of the power converter through the first gate drive signal.
[0009] In an optional implementation, the EMI detection circuit includes: a speed-up detection circuit and a peak detection circuit;
[0010] The input terminal of the speed-up detection circuit is the input terminal of the EMI detection circuit, which is connected to the preset switch node to detect the speed-up of the switch voltage signal and obtain the speed-up detection signal. The output terminal of the speed-up detection circuit is connected to the input terminal of the peak detection circuit, so that the peak detection circuit performs peak detection on the speed-up detection signal to obtain the EMI detection signal. The output terminal of the peak detection circuit serves as the output terminal of the EMI detection circuit and is used to connect the first asynchronous sampling circuit and the second asynchronous sampling circuit.
[0011] In an optional embodiment, the speed-up detection circuit includes: a first P-type current mirror, a feedback circuit, a high-voltage NMOS transistor, a first capacitor, a second capacitor, a third capacitor, and a Zener diode.
[0012] Wherein, the power supply terminal of the first P-type current mirror is used to connect to the first preset power supply, the input terminal of the first P-type current mirror is connected to the drain of the high-voltage NMOS transistor, the gate of the high-voltage NMOS transistor is used to connect to the second preset power supply, the source of the high-voltage NMOS transistor is grounded through the first capacitor, the Zener diode is connected in parallel across the first capacitor, and the gate of the high-voltage NMOS transistor is also connected to the source through the second capacitor.
[0013] The input terminal of the first P-type current mirror is connected to one end of the third capacitor, and the other end of the third capacitor is the input terminal of the speed-up detection circuit, which is used to connect to the preset switch node; the output terminal of the first P-type current mirror is connected to the input terminal of the feedback circuit, and the output terminal of the feedback circuit is connected as the output terminal of the speed-up detection circuit.
[0014] In an optional embodiment, the feedback circuit includes: an N-type current mirror and a first NMOS transistor. The power supply terminal of the N-type current mirror is connected to the other end of the third capacitor. The input terminal of the N-type current mirror is connected to the source of the first NMOS transistor. The output terminal of the N-type current mirror and the output terminal of the first P-type current mirror are connected in series as the output terminal of the feedback circuit. The output terminal of the feedback circuit is also connected to the gate of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the first preset power supply.
[0015] In an optional implementation, the peak detection circuit includes: a transconductance amplifier, a second P-type current mirror, a fourth capacitor, and a second NMOS transistor;
[0016] The negative terminal of the transconductance amplifier is the input terminal of the peak detection circuit. The positive terminal of the transconductance amplifier is connected to the other end of the third capacitor. The output terminal of the transconductance amplifier is connected to the input terminal of the second P-type current mirror. The output terminal of the second P-type current mirror serves as the output terminal of the peak detection circuit. The output terminal of the second P-type current mirror is also connected to the other end of the third capacitor through the fourth capacitor. The drain of the second NMOS transistor is connected to the output terminal of the second P-type current mirror. The source of the second NMOS transistor is also connected to the other end of the third capacitor. The gate of the second NMOS transistor is also used to connect to a third preset power supply.
[0017] In an optional embodiment, the first gate drive circuit is a three-stage gate driver, which includes: a conventional charging gate driver, a pre-charge gate driver, a raised gate driver, a ramp raised gate driver, and a switching unit.
[0018] The conventional charging gate driver, the pre-charging gate driver, the raised gate driver, and the ramp raised gate driver are all connected to the gate of the first power switch.
[0019] The input terminal of the switching unit is connected to the off-chip control circuit, and the two output terminals of the switching unit are respectively connected to the raised gate driver and the ramp raised gate driver.
[0020] In an optional implementation, the power switch drive circuit includes: a plurality of first boost level shifters and a plurality of second boost level shifters;
[0021] The input terminals of the plurality of first boost level shifters are respectively connected to the plurality of first output terminals of the off-chip control circuit, and the output terminals of the plurality of first boost level shifters are respectively connected to the plurality of second output terminals of the off-chip control circuit; the output terminals of the plurality of first boost level shifters are respectively connected to the plurality of control pins of the conventional charging gate driver, and the output terminals of the plurality of second boost level shifters are respectively connected to the plurality of control pins of the pre-charge gate driver.
[0022] In an optional implementation, the comparison circuit includes: a hysteresis comparator and a comparator;
[0023] The output terminals of the first asynchronous sampling circuit and the second asynchronous sampling circuit are respectively connected to the two input terminals of the hysteresis comparator, so that the hysteresis comparator outputs a first comparison signal; the output terminals of the first asynchronous sampling circuit and the second asynchronous sampling circuit are respectively connected to the two input terminals of the comparator, so that the comparator outputs a second comparison signal.
[0024] The output of the hysteresis comparator and the output of the comparator are both connected to the two inputs of the off-chip control circuit.
[0025] In an optional embodiment, the power switch drive circuit further includes: two third boost level shifters, two pulse generators, and two buck level shifters; the input terminals of the two third boost level shifters are connected to the two third output terminals of the off-chip control circuit, the output terminals of the two third boost level shifters are connected to the first input terminals of the two pulse generators, and the second input terminals of the two pulse generators are respectively connected to a preset high-voltage drive signal and a preset low-voltage drive signal;
[0026] The output terminals of the two pulse generators are respectively connected to the control terminal of the first asynchronous sampling circuit and the control terminal of the second asynchronous sampling circuit;
[0027] The output of the hysteresis comparator and the output of the comparator are respectively connected to the inputs of the two buck level shifters, and the outputs of the two buck level shifters are respectively connected to the two inputs of the off-chip control circuit.
[0028] In a second aspect, the present invention provides a power converter, comprising: a first power switch, a second power switch, an output inductor, an output capacitor, and a power switch driving circuit as described in any of the foregoing embodiments;
[0029] The first gate driving circuit and the second gate driving circuit in the power switch driving circuit are respectively connected to the gate of the first power switch and the gate of the second power switch.
[0030] The drain of the first power switch is connected to a preset voltage input terminal to receive a preset input voltage. The source of the first power switch is connected to the drain of the second power switch, and the source of the second power switch is grounded. The source of the first power switch is a preset switch node, and the preset switch node is connected to a preset voltage output terminal through the output inductor. The preset voltage output terminal is also grounded through the output capacitor.
[0031] The beneficial effects of the embodiments of this application are:
[0032] The power switch driving circuit provided in this application includes: an electromagnetic interference (EMI) detection circuit, a first asynchronous sampling circuit, a second asynchronous sampling circuit, a comparator circuit, an off-chip control circuit, a first gate driving circuit, and a second gate driving circuit. The first gate driving circuit is used to connect to the gate of a first power switch in the power converter, and the second gate driving circuit is used to connect to the gate of a second power switch in the power converter. The input terminal of the EMI detection circuit is used to connect to a preset switching node between the first power switch and the second power switch to perform on-chip EMI detection on the switching voltage signal of the preset switching node to obtain an EMI detection signal. The output terminal of the EMI detection circuit is connected to the input terminal of the first asynchronous sampling circuit and the second asynchronous sampling circuit. The input terminal of the asynchronous sampling circuit allows the first and second asynchronous sampling circuits to detect the EMI detection signal at different periods, obtaining a first EMI performance detection parameter and a second EMI performance detection parameter. The output terminals of the first and second asynchronous sampling circuits are also connected to the comparison circuit, allowing the comparison circuit to compare the first and second EMI performance detection parameters and obtain a comparison result. The comparison circuit is also connected to the off-chip control circuit, which is connected to the first gate drive circuit. This allows the off-chip control circuit to adjust the first gate drive signal based on the comparison result, and adjust the EMI performance of the power converter through the first gate drive signal. This power switch drive circuit performs on-chip EMI detection on the switching voltage signal through the EMI detection circuit, and adjusts the gate drive circuit to achieve different circuit states through the off-chip control circuit. By collecting and comparing the EMI detection results under different circuit states, it realizes dynamic adjustment of the gate drive circuit through the off-chip control circuit, thereby dynamically finding the circuit state corresponding to the optimal circuit performance. This achieves wide-area EMI suppression while ensuring high efficiency and high energy density, improving the robustness and industrial applicability of the circuit. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0034] Figure 1 This is a schematic diagram of the structure of a power switch drive circuit provided in an embodiment of this application;
[0035] Figure 2 This is a schematic diagram of the structure of an EMI detection circuit provided in an embodiment of this application;
[0036] Figure 3 This is a schematic diagram of the structure of a power switch drive circuit provided in another embodiment of this application;
[0037] Figure 4 This is a schematic diagram of the structure of an off-chip control circuit provided in another embodiment of this application;
[0038] Figure 5 A schematic diagram of the structure of a power switch drive circuit provided in another embodiment of this application;
[0039] Figure 6 This is a schematic diagram of the structure of a power switch drive circuit provided in another embodiment of the present application;
[0040] Figure 7 This is a schematic diagram of the structure of a power switch drive circuit provided in another embodiment of the present application;
[0041] Figure 8 This is a schematic diagram of the structure of a power switch drive circuit provided in another embodiment of the present application;
[0042] Figure 9 A schematic diagram of the charging current waveform of a three-stage gate driver provided in an embodiment of this application;
[0043] Figure 10 This is a schematic diagram illustrating the relationship between the output voltage and the pre-charge current of an EMI detection circuit provided in an embodiment of this application, as well as the classification of different scenarios.
[0044] Figure 11 A schematic diagram illustrating the relationship between the charging current waveform of a three-stage gate driver and the Miller plateau, provided for embodiments of this application;
[0045] Figure 12 A schematic diagram illustrating the relationship between the charging current waveform of another three-stage gate driver and the Miller plateau, provided for an embodiment of this application;
[0046] Figure 13This is a schematic diagram showing the relationship between the charging current waveform of a three-stage gate driver and the Miller plateau, as provided in an embodiment of this application.
[0047] Figure label:
[0048] 001-EMI detection circuit; 0021-First asynchronous sampling circuit; 0022-Second asynchronous sampling circuit; 003-Comparison circuit; 004-Off-chip control circuit; 0051-First gate drive circuit; 0052-Second gate drive circuit; S1-First power switch; S2-Second power switch; VSW-Preset switching node; Lout-Output inductor; Cout-Output capacitor; 200-Speed-up detection circuit; 300-Peak detection circuit; HNM-High voltage NMOS transistor; VBST-First preset power supply; VDD5-Second preset power supply C1 - First capacitor; C2 - Second capacitor; C3 - Third capacitor; D1 - Zener diode; NM3 - First NMOS transistor; OTA - Transconductance amplifier; C4 - Fourth capacitor; NM4 - Second NMOS transistor; CLKHV' - Third preset power supply; 101 - Normal charging gate driver; 102 - Precharged gate driver; 103 - Rise gate driver; 104 - Ramp-raised gate driver; PMT - Switching unit; 0031 - Hysteresis comparator; 0032 - Comparator; 152 - Buck level shifter; 153 - Pulse generator. Detailed Implementation
[0049] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0050] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0051] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0052] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0053] In the description of this application, it should be noted that the terms "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0054] In the description of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0055] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0056] The power switch drive circuit provided in this application embodiment is mainly used in power converters, such as BUCK converters. The BUCK converter involved in this embodiment can be, for example, a gallium nitride BUCK converter, that is, a gallium nitride semiconductor device is used as the power switch in the BUCK converter.
[0057] Addressing the power supply requirements of BUCK converters in AI large-scale model data centers, as well as the demands for power management system stability, low noise, and low crosstalk, this application provides an example of an adaptive power converter capable of on-chip EMI detection and effectively reducing conducted EMI of the system while maintaining system efficiency and energy density through loop control and gate drivers.
[0058] To avoid the delays and process corners encountered in Miller platform detection technology, as well as the complex external equipment issues encountered in off-chip EMI detection technology, this invention does not employ traditional Miller platform detection technology or off-chip EMI detection circuits. Instead, it introduces a new EMI detection circuit into the power switch drive circuit. This EMI detection circuit is an on-chip EMI detection circuit. By performing on-chip EMI detection on the circuit and adjusting the drive current of the gate drive circuit corresponding to the high-level power switch to be in different current charging states, the EMI detection signals of different cycles obtained by the on-chip EMI detection circuit are compared. By comparing and adjusting the current state of the gate drive circuit corresponding to the high-level power switch several times, the current circuit can achieve optimal EMI performance, thereby realizing adaptive adjustment of the circuit's EMI performance.
[0059] Figure 1 Please refer to the schematic diagram of the power switch drive circuit provided in one embodiment of this application. Figure 1 The circuit within the dashed box, the power switch drive circuit, includes: an electromagnetic interference (EMI) detection circuit 001, a first asynchronous sampling circuit 0021, a second asynchronous sampling circuit 0022, a comparator circuit 003, an off-chip control circuit 004, a first gate drive circuit 0051, and a second gate drive circuit 0052. Specifically, the first gate drive circuit 0051 is connected to the gate of the first power switch S1 in the power converter, and the second gate drive circuit 0052 is connected to the gate of the second power switch S2 in the power converter.
[0060] The input terminal of the aforementioned EMI detection circuit 001 is connected to a preset switching node VSW between the first power switch S1 and the second power switch S2 to perform on-chip EMI detection on the switching voltage signal of the preset switching node VSW, thereby obtaining an EMI detection signal. The output terminal of the aforementioned EMI detection circuit is connected to the input terminals of the first asynchronous sampling circuit 0021 and the second asynchronous sampling circuit 0022, so that the first asynchronous sampling circuit 0021 and the second asynchronous sampling circuit 0022 detect the EMI detection signal in different periods, respectively, to obtain a first EMI performance detection parameter and a second EMI performance detection parameter.
[0061] The output terminals of the first asynchronous sampling circuit 0021 and the second asynchronous sampling circuit 0022 are also connected to the comparison circuit 003, so that the comparison circuit 003 compares the first EMI performance detection parameter and the second EMI performance detection parameter to obtain a comparison result. The comparison circuit 003 is also connected to the off-chip control circuit 004, which is connected to the first gate drive circuit 0051, so that the off-chip control circuit 004 adjusts the first gate drive signal according to the comparison result, and adjusts the EMI performance of the power converter through the first gate drive signal.
[0062] For example, the power converter described above may be a BUCK converter in a gallium nitride power management system, the first power switch may be a high-level power switch (also known as a high-level transistor) in the power converter, and the EMI detection circuit may be an off-chip EMI detection circuit, but these are not limited thereto.
[0063] The first asynchronous sampling circuit 0021 and the second asynchronous sampling circuit 0022 detect the EMI detection signal in different periods. For example, the circuit state of the first gate driving circuit 0051 can affect the overall circuit state of the power switch driving circuit. When the circuit state of the first gate driving circuit 0051 changes, the overall circuit state of the power switch driving circuit changes synchronously. The overall circuit state of each power switch driving circuit (or the circuit state of each first gate driving circuit 0051) can correspond to a period. Specifically, the period can start when the first power switch S1 starts to open under the current overall circuit state of the power switch driving circuit, and end when the first power switch S1 is fully open, but it is not limited to this.
[0064] The aforementioned EMI detection circuit 001 can, for example, output an EMI detection signal in the form of a stable voltage for the current cycle or the overall circuit state of the current power switch drive circuit. Therefore, the aforementioned first asynchronous sampling circuit 0021 and the aforementioned second asynchronous sampling circuit 0022 detect the aforementioned EMI detection signal in different cycles. For example, they can detect the voltage corresponding to the aforementioned EMI detection signal in different overall circuit states of the power switch drive circuit to obtain the aforementioned first EMI performance detection parameter and second EMI performance detection parameter.
[0065] After comparing the first EMI performance detection parameter and the second EMI performance detection parameter, the comparison result obtained by the comparison circuit 003 can be, for example, a comparison result of the superiority or inferiority of the EMI performance corresponding to the first EMI performance detection parameter and the second EMI performance detection parameter, and can be output to the external control circuit 004 in the form of 0 or 1, so that the external control circuit 004 can determine what circuit state the first gate drive circuit 0051 should maintain or adjust based on the comparison result, but is not limited thereto.
[0066] It is understood that the aforementioned off-chip control circuit 004 may include, for example, a microcontroller unit (MCU) or other components with computing and processing functions and instruction and data transmission and reception functions, and the components may store an adjustable control program.
[0067] The power switch drive circuit provided in this application performs on-chip EMI detection on the switching voltage signal through an on-chip EMI detection circuit, and adjusts the gate drive circuit through an external control circuit to achieve different circuit states. By collecting and comparing the EMI detection results under different circuit states, the circuit can dynamically adjust the gate drive circuit through an external control circuit, thereby dynamically finding the circuit state corresponding to the optimal circuit performance. This achieves wide-area EMI suppression while ensuring high efficiency and high energy density, thus improving the robustness and industrial applicability of the circuit.
[0068] Figure 2 This is a schematic diagram of the EMI detection circuit 001 provided in one embodiment of this application, as shown below. Figure 2 As shown, the EMI detection circuit 001 includes: a speed-up detection circuit 200 and a peak detection circuit 300.
[0069] The input terminal of the aforementioned speed-up detection circuit 200 is also the input terminal of the aforementioned EMI detection circuit 001, connected to the aforementioned preset switch node VSW, to detect the rise rate of the aforementioned switch voltage signal and obtain a rise rate detection signal. The output terminal of the aforementioned speed-up detection circuit 200 is connected to the input terminal of the aforementioned peak detection circuit 300, so that the aforementioned peak detection circuit 300 performs peak detection on the aforementioned rise rate detection signal to obtain the aforementioned EMI detection signal. The output terminal of the aforementioned peak detection circuit 300 serves as the output terminal of the aforementioned EMI detection circuit 001, used to connect the aforementioned first asynchronous sampling circuit 0021 and the aforementioned second asynchronous sampling circuit 0022.
[0070] Compared to the complex off-chip detection circuits in the prior art, the on-chip EMI detection circuit, which includes a speed-up detection circuit and a peak detection circuit, can evaluate the EMI performance of the current circuit at a significantly lower cost. Furthermore, the technical solution of this application evaluates the EMI performance of the current circuit through an on-chip EMI detection circuit, eliminating the need for the existing technology of tracking Miller plateaus. This avoids the situation where the charging current of the gate driver of the high-level transistor is still relatively large after the arrival of the high-level transistor Miller plateau due to delay issues, thus limiting the EMI optimization capability.
[0071] Alternatively, please continue to refer to Figure 2 In the above Figure 2 Based on the embodiments, the above-mentioned speed-up detection circuit 200 may include: a first P-type current mirror, a feedback circuit, a high-voltage NMOS transistor HNM, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a Zener diode D1.
[0072] The power supply terminal of the first P-type current mirror is connected to the first preset power supply VBST. The input terminal of the first P-type current mirror is connected to the drain of the high-voltage NMOS transistor HNM. The gate of the high-voltage NMOS transistor HNM is connected to the second preset power supply VDD5. The source of the high-voltage NMOS transistor HNM is grounded through the first capacitor C1. The Zener diode D1 is connected in parallel across the first capacitor C1. The gate of the high-voltage NMOS transistor HNM is also connected to the source through the second capacitor C2.
[0073] The input terminal of the first P-type current mirror is connected to one end of the third capacitor C3, and the other end of the third capacitor C3 is the input terminal of the speed-up detection circuit 200, used to connect to the preset switch node VSW. The output terminal of the first P-type current mirror is connected to the input terminal of the feedback circuit, and the output terminal of the feedback circuit is connected as the output terminal of the speed-up detection circuit 200.
[0074] For example, the aforementioned first P-type current mirror can refer to... Figure 2 The aforementioned feedback circuit, consisting of two PMOS transistors PM1 and PM2, can be, for example, referred to as... Figure 2 The circuit consists of three NMOS transistors, NM1, NM2, and NM3.
[0075] Furthermore, such as Figure 2As shown, based on the above embodiment, the feedback circuit may include: an N-type current mirror and a first NMOS transistor NM3. The power supply terminal of the N-type current mirror is connected to the other end of the third capacitor C3. The input terminal of the N-type current mirror is connected to the source of the first NMOS transistor NM3. The output terminals of the N-type current mirror and the first P-type current mirror are connected in series as the output terminal of the feedback circuit. The output terminal of the feedback circuit is also connected to the gate of the first NMOS transistor NM3, and the drain of the first NMOS transistor NM3 is connected to the first preset power supply VBST.
[0076] For example, the aforementioned N-type current mirror can refer to... Figure 2 The device consists of two NMOS transistors, NM1 and NM2.
[0077] Additionally, please continue to refer to Figure 2 Based on the aforementioned embodiments, the peak detection circuit 300 may include: a transconductance amplifier OTA, a second P-type current mirror, a fourth capacitor C4, and a second NMOS transistor NM4.
[0078] The negative terminal of the transconductance amplifier OTA is the input terminal of the peak detection circuit 300. The positive terminal of the transconductance amplifier is connected to the other end of the third capacitor C3. The output terminal of the transconductance amplifier OTA is connected to the input terminal of the second P-type current mirror. The output terminal of the second P-type current mirror serves as the output terminal of the peak detection circuit 300. The output terminal of the second P-type current mirror is also connected to the other end of the third capacitor C3 through the fourth capacitor C4. The drain of the second NMOS transistor is connected to the output terminal of the second P-type current mirror. The source of the second NMOS transistor NM4 is also connected to the other end of the third capacitor C3. The gate of the second NMOS transistor NM4 is also used to connect to a third preset power supply.
[0079] For example, the aforementioned second P-type current mirror can refer to... Figure 2 The device consists of two PMOS transistors, PM3 and PM4.
[0080] The aforementioned speed-up detection circuit 200 can, for example, be used to convert the VSW rise speed of the power switch drive circuit into a spike pulse, and the aforementioned peak detection circuit 300 can, for example, be used to process the voltage signal at the peak of the spike pulse into a stable, sampleable voltage signal. Specifically, the aforementioned speed-up detection circuit 200 can, for example, convert the rise time of the floating domain into a current signal through the aforementioned high-voltage NMOS transistor HNM and the first capacitor C1, then replicate it to the feedback circuit through the aforementioned first P-type current mirror, and convert the current signal into a stable, processable voltage signal. Figure 2Point A in the circuit can be, for example, the output point of the speed-up detection circuit 200. This point A can be connected to the negative terminal of the transconductance amplifier OTA in the peak detection circuit 300, i.e., the input terminal of the peak detection circuit 300. The circuit composed of the transconductance amplifier OTA and the second P-type current mirror can, for example, continuously charge the fourth capacitor C4 before the circuit voltage reaches its peak value, and shut off the charging circuit for the fourth capacitor C4 the instant the voltage begins to drop after reaching its peak value, thereby enabling... Figure 2 The VOUT point receives a stable, sampleable voltage. After sampling, the second NMOS transistor NM4 receives the reverse high-level transistor excitation signal ФH' and conducts the discharge path between the VOUT point and VSW, thereby resetting the VOUT point voltage and preparing for the next detection.
[0081] Figure 3 This is a schematic diagram of the power switch drive circuit provided in another embodiment of this application. Figure 4 This is a schematic diagram of the structure of an off-chip control circuit provided in another embodiment of this application. Figure 1 Based on the embodiments, such as Figure 3 and Figure 4 As shown, the first gate drive circuit 0051 is a three-stage gate driver, which includes: a conventional charging gate driver 101, a pre-charge gate driver 102, a raised gate driver 103, a ramp raised gate driver 104, and a switching unit PMT.
[0082] The conventional charging gate driver 101, the pre-charging gate driver 102, the raised gate driver 103, and the ramp-raised gate driver 104 are all connected to the gate of the first power switch S1. A three-stage gate driver is also called a three-segment gate driver.
[0083] The input terminal of the aforementioned switching unit PMT is connected to the aforementioned off-chip control circuit 004, and the two output terminals of the aforementioned switching unit PMT are respectively connected to the aforementioned raised gate driver 103 and the aforementioned ramp raised gate driver 104.
[0084] For example, within the same cycle, only one of the aforementioned raised gate driver 103 and ramp raised gate driver 104 may participate in charging. The aforementioned conventional charging gate driver 101 may be a three-bit conventional charging gate driver 101, but is not limited thereto. The conventional charging gate driver 101 may provide a constant conventional charging current within a cycle to the gate of the first power switch S1 when the first power switch S1 is turned on. In different cycles, the magnitude of the conventional charging current may also be adjusted by adjusting the number of bits of the conventional charging gate driver 101. Taking a three-bit conventional charging gate driver 101 as an example, the minimum number of bits in the three-bit conventional charging gate driver 101 can be, for example, 001, corresponding to the minimum conventional charging current, and the maximum number of bits in the three-bit conventional charging gate driver 101 can be, for example, 111, corresponding to the maximum conventional charging current. Of course, the above is only one possible example, and the actual types of conventional charging gate drivers 101, the actual number of bits in conventional charging gate drivers 101, and the correspondence between the actual conventional charging current and the number of bits in conventional charging gate drivers 101 are not limited to the above examples. In addition, the aforementioned conventional charging gate driver 101 can also provide a discharge path for the closing of the first power switch S1, for example. The specific discharge path can be adjusted and determined according to actual needs, and is not limited here.
[0085] The aforementioned precharge gate driver 102 can be, for example, a five-bit precharge gate driver 102. This precharge gate driver 102 can, for example, immediately provide a precharge current to the gate of the first power switch S1 for a preset duration (e.g., one nanosecond, but not limited thereto) upon receiving the high-order transistor excitation signal ФH. Furthermore, the magnitude of this precharge current can be adjusted, for example, by adjusting the number of bits in the precharge gate driver 102 within different cycles. Taking a five-bit precharge gate driver 102 as an example, the minimum number of bits in the five-bit precharge gate driver 102 can be, for example, 00000, corresponding to the minimum precharge current. The maximum number of bits in the three-bit conventional charging gate driver 101 can be, for example, 11111, corresponding to the maximum precharge current. Of course, the above is only one possible example; the actual types of conventional charging gate drivers 101, the actual number of bits in conventional charging gate drivers 101, and the correspondence between the actual conventional charging current and the number of bits in conventional charging gate drivers 101 are not limited to the examples described above.
[0086] It is understandable that the 0 mentioned above can represent a low potential of a digital signal, and the 1 mentioned above can represent a high potential of a digital signal.
[0087] After a preset duration (e.g., eight nanoseconds, but not limited thereto) after receiving the high-level transistor excitation signal ФH, the aforementioned gate-raising driver 103 can, for example, provide a raised charging current to the gate of the first power switch S1 until the first power switch S1 is fully turned on, and the current cycle ends.
[0088] That is, in the above process, the pre-charging current can be used, for example, to raise the VSW of the first power switch S1 to near the Miller plateau in a short time. At the same time, the conventional charging current needs to provide a low current intensity for the first power switch S1 while the VSW of the first power switch S1 is near the Miller plateau in order to reduce the rate of VSW rise. The lifting charging current needs to raise the VSW of the first power switch S1 to the value corresponding to full opening as quickly as possible after the VSW exceeds the Miller plateau. Therefore, the maximum pre-charging current should be much larger than the conventional charging current and similar in magnitude to the lifting charging current. However, the specific values and relationships of the conventional charging current, pre-charging current and lifting charging current can be adjusted and determined according to the actual situation, and are not limited here.
[0089] After multiple cycles of optimization and adjustment, for example, the PMT potential of the off-chip control circuit 004 can be set to a low potential, thereby causing the raised gate driver 103 to stop working during subsequent charging processes. The ramp-up raised gate driver 104 then replaces the raised gate driver 103 in providing the raised charging current to the gate of the first power switch S1. The raised charging current provided by the ramp-up raised gate driver 104 can gradually increase over time. Compared to using the raised gate driver 103 to provide the raised charging current, this can further optimize the EMI performance of the power switch drive circuit at the end of the Miller plateau.
[0090] Figure 5 This is a schematic diagram of the power switch drive circuit provided in another embodiment of this application. Optionally, please refer to... Figures 3-5 The aforementioned power switch drive circuit may include: a plurality of first boost level shifters and a plurality of second boost level shifters.
[0091] The input terminals of the aforementioned plurality of first boost level shifters are respectively connected to the plurality of first output terminals of the aforementioned external control circuit 004, and the output terminals of the aforementioned plurality of first boost level shifters are respectively connected to the plurality of second output terminals of the aforementioned external control circuit 004. The output terminals of the aforementioned plurality of first boost level shifters are respectively connected to the plurality of control pins of the aforementioned conventional charging gate driver 101, and the output terminals of the aforementioned plurality of second boost level shifters are respectively connected to the plurality of control pins of the aforementioned pre-charge gate driver 102.
[0092] The aforementioned multiple first boost level shifters can, for example, refer to Figure 5UpLS (Boost Level Shifter) 140-144 in the above-mentioned multiple second boost level shifters can refer to, for example, Figure 5 UpLS (Boost Level Shifter) 145-147.
[0093] Figure 6 This is a schematic diagram of the power switch drive circuit provided in another embodiment of this application. Additionally, as... Figures 3-6 As shown, the comparison circuit 003 includes a hysteresis comparator 0031 and a comparator 0032.
[0094] The output terminals of the first asynchronous sampling circuit 0021 and the second asynchronous sampling circuit 0022 are respectively connected to the two input terminals of the hysteresis comparator 0031, causing the hysteresis comparator 0031 to output a first comparison signal. The output terminals of the first asynchronous sampling circuit 0021 and the second asynchronous sampling circuit 0022 are respectively connected to the two input terminals of the comparator 0032, causing the comparator 0032 to output a second comparison signal.
[0095] The output terminals of the aforementioned hysteresis comparator 0031 and the aforementioned comparator 0032 are both connected to the two input terminals of the aforementioned off-chip control circuit 004.
[0096] Figure 7 and Figure 8 The above are schematic diagrams of the power switch drive circuit provided in another embodiment of this application. Further, please refer to... Figures 3-8 The aforementioned power switch drive circuit further includes: two third boost level shifters, two pulse generators 153, and two buck level shifters 152. The input terminals of the two third boost level shifters are connected to the two third output terminals of the aforementioned off-chip control circuit 004, the output terminals of the two third boost level shifters are connected to the first input terminals of the two pulse generators 153, and the second input terminals of the two pulse generators 153 are respectively connected to a preset high-voltage drive signal and a preset low-voltage drive signal.
[0097] The output terminals of the two pulse generators 153 are respectively connected to the control terminals of the first asynchronous sampling circuit 0021 and the second asynchronous sampling circuit 0022.
[0098] The output terminals of the aforementioned hysteresis comparator 0031 and the aforementioned comparator 0032 are respectively connected to the input terminals of the aforementioned two buck level shifters 152, and the output terminals of the aforementioned two buck level shifters 152 are respectively connected to the two input terminals of the aforementioned off-chip control circuit 004.
[0099] For example, the two first boost level shifters mentioned above can refer to... Figure 5UpLS (Boost Level Shifter) 149-150.
[0100] This invention also provides a power converter, please refer to... Figure 1 The power converter may include: a first power switch S1, a second power switch S2, an output inductor Lout, an output capacitor Cout, and any of the power switch drive circuits described in the foregoing embodiments.
[0101] The first gate drive circuit 0051 and the second gate drive circuit 0052 in the power switch drive circuit are respectively connected to the gate of the first power switch S1 and the gate of the second power switch S2.
[0102] The drain of the first power switch S1 is connected to the preset voltage input terminal to receive the preset input voltage. The source of the first power switch S1 is connected to the drain of the second power switch S2. The source of the second power switch S2 is grounded. The source of the first power switch S1 is a preset switch node VSW. The preset switch node VSW is connected to the preset voltage output terminal through the output inductor Lout. The preset voltage output terminal is also grounded through the output capacitor Cout.
[0103] For example, taking the first gate drive circuit 0051 as a three-stage gate driver, where the conventional charging gate driver 101 is a three-bit conventional charging gate driver 101 and the pre-charging gate driver 102 is a five-bit pre-charging gate driver 102, the EMI performance optimization process of this power converter can be as follows:
[0104] Step 1: Initial State Setup: Initialize the three-level gate driver using the external control circuit 004. Specifically, this can be done by setting the state of the conventional charging gate driver 101 to the three-bit digital signal '001' (e.g., corresponding to...). Figure 3 The pins INC2, INC1, and INC0 in the chip and the pins INC2in, INC1in, and INC0in of the external control circuit output signals correspond to the minimum normal charging current intensity; the state of the precharge gate driver 102 is set to the five-bit digital signal '00000' (for example, it can correspond to respectively). Figure 3The pins IPC4, IPC3, IPC2, IPC1, and IPC0 in the chip, and the pins IPC4in, IPC3in, IPC2in, IPC1in, and IPC0in for the output signals of the external control circuit, correspond to the minimum pre-charge current intensity. Simultaneously, the PMT control signal of the external control circuit 004 is set to a high level (e.g., output via the PMTIN pin) to enable the aforementioned raised gate driver 103 via the switching unit PMT. The external control circuit 004 outputs a first power switch S1 drive signal (e.g., ФHIN) and a second power switch S2 drive signal (e.g., ФLIN) with a duty cycle of approximately 25%, causing the power converter to enter steady-state operation.
[0105] Step 2, First Performance Parameter Sampling: After the circuit enters steady state, the external control circuit 004 sets the first sampling control signal (e.g., SH1IN) to a high level. This signal is then passed through the corresponding boost level shifter (e.g., a... Figure 5 After processing (149) in the above steps, a signal SH1_ is generated in the floating domain. When the SH1_ signal and the first power switch S1 drive signal ФH are both high, the pulse generator 153 connected to it is triggered to generate a sampling pulse (e.g., SH1) of a preset duration (e.g., 10 nanoseconds). This pulse then controls the first asynchronous sampling circuit 0021 to sample and hold the EMI detection signal (e.g., VOUT) output by the EMI detection circuit 001 in the current cycle. This sampled value is the first EMI performance detection parameter (e.g., performance 1) characterizing the EMI performance of the power converter under the current overall circuit state of the power switch drive circuit (e.g., state 1).
[0106] Step 3, Second Performance Parameter Sampling: After several cycles, the state of the pre-charge gate driver 102 is adjusted via the external control circuit 004, for example, by adjusting the five-bit digital signal to '00001'. The state of the regular charge gate driver 101 remains unchanged. Subsequently, the second sampling control signal (e.g., SH2IN) is set to a high level. Similar to Step 2, this signal is boosted and shifted by the corresponding level shifter (e.g., a...). Figure 5 The process of 150 and pulse generator 153 generates a sampling pulse (e.g., SH2) to control the second asynchronous sampling circuit 0022 to sample the EMI detection signal output by the EMI detection circuit 001 in the current cycle. This sampled value is the second EMI performance detection parameter (e.g., performance 2) characterizing the EMI performance of the power converter under the overall circuit state of another adjusted power switch drive circuit (e.g., state 2).
[0107] Step 4: Performance Comparison and State Update: The performance 1 from the first asynchronous sampling circuit 0021 and the performance 2 from the second asynchronous sampling circuit 0022 are compared by the comparison circuit 003. If the voltage values of the two are similar, the first comparison signal (e.g., the Near signal) output by the hysteresis comparator 0031 can be at a high level; if there is a significant difference, the second comparison signal (e.g., the Comp signal) output by the comparator 0032 can indicate the superiority relationship between performance 1 and performance 2 in the form of a digital signal, such as 0 or 1 (e.g., if the voltage of performance 2 is lower than that of performance 1, it can indicate that performance 2 corresponding to state 2 is superior). The Near signal and the Comp signal are converted by the corresponding buck level shifter 152 and then transmitted to the off-chip control circuit 004 as the NearOUT signal and the CompOUT signal. The off-chip control circuit 004 can, for example, make a judgment based on the CompOUT signal: if the performance 2 in state 2 is better, then the circuit state of the first gate drive circuit 0051 corresponding to the current state 2 is taken as the current optimal drive state; otherwise, the circuit state of the first gate drive circuit 0051 corresponding to state 1 is retained as the current optimal drive state.
[0108] Step 5: Iterative Optimization Until Optimal: Repeat steps 2 to 4 to form a loop iteration. The external control circuit 004 can gradually approach and lock the circuit state of the first gate drive circuit 0051 that optimizes EMI performance. When the NearOUT signal is high in multiple consecutive comparisons, or when the EMI performance of the power converter changes from continuous improvement to continuous decline based on the CompOUT signal, it can be determined that the power converter has reached the global or local optimal EMI performance.
[0109] After completing steps one through five above, the external control circuit 004 can set the PMT control signal to a low potential, controlling the switching unit PMT to stop the rise gate driver 103 from operating during the subsequent charging process. The ramp rise gate driver 104 then replaces the rise gate driver 103 in providing the rise charging current to the gate of the first power switch S1. The rise charging current provided by the ramp rise gate driver 104 can gradually increase over time. Compared to using the rise gate driver 103 to provide the rise charging current, this can further optimize the EMI performance of the power switch drive circuit at the end of the Miller platform.
[0110] Figure 9 This is a schematic diagram of the charging current waveform of a three-stage gate driver according to an embodiment of this application. Figure 10This diagram illustrates the relationship between the output voltage and pre-charge current of an EMI detection circuit according to an embodiment of this application, along with various case classifications. The blue bars represent the VSW rise rate; a lower VSW rise rate indicates better EMI performance of the corresponding power converter, and vice versa. Figures 11-13 This diagram illustrates the relationship between the charging current waveforms of different three-stage gate drivers and the Miller plateau, as provided in the embodiments of this application. The gate current intensity of the high-order transistor is the gate current intensity of the first power switch S1. To further explain the principle behind determining the EMI performance of the power converter, the following is combined with... Figures 9-13 Please elaborate.
[0111] like Figure 9 As shown, since the pre-charge current needs to raise the first power switch S1 to near the Miller plateau in a short time, and the regular charging current needs to provide a lower current intensity for the first power switch S1 during the Miller plateau stage to reduce the rise rate of VSW, and the rise current needs to raise the first power switch S1 to full opening as quickly as possible after the Miller plateau, the maximum intensity of the pre-charge current needs to be much greater than the intensity of the regular charging current and similar to the intensity of the rise current.
[0112] Please refer to Figure 11 , Figure 11 The diagram shows the charging current situation of a three-stage gate driver when the pre-charge current is too small and the normal charging current remains low. In this case, the first power switch S1 only enters the Miller plateau stage after the gate driver 103 supplies a large boost charging current to the gate, causing VSW to rise too quickly. Therefore, in Figure 11 In the case shown, the output voltage of the EMI detection circuit 001 is as follows: Figure 10 Case 1 shows a scenario where the power converter has poor EMI performance.
[0113] Please refer to Figure 12 , Figure 12 The diagram shows a three-stage gate driver charging current configuration with a moderate pre-charge current and a low conventional charging current. This three-stage gate driver charging current allows the first power switch S1 to enter the Miller plateau phase after the pre-charge current ends and leave the Miller plateau phase before the boost charging current begins, thereby controlling the VSW rise rate to remain at a low level. Figure 12 In the case shown, the output voltage of the EMI detection circuit 001 is as follows: Figure 10 Case 2 in the diagram shows the case where the power converter has better EMI performance.
[0114] Please refer to Figure 13 , Figure 13The diagram shows the charging current of a three-stage gate driver with excessively high pre-charge current. Such a charging current causes the first power switch S1 to enter the Miller plateau stage before the pre-charge current has finished charging, resulting in VSW rising too quickly. Therefore, in Figure 13 In the case shown, the output voltage of the EMI detection circuit 001 is as follows: Figure 10 Case 3 in the diagram illustrates a situation where the power converter has poor EMI performance.
[0115] In summary, the above method determines that the power converter has achieved globally or locally optimal EMI performance, i.e., iteratively searching for the optimal EMI performance. Figure 12 The charging current of the three-stage gate driver is shown.
[0116] Furthermore, if, under the current state of the conventional charging gate driver 101, a satisfactory optimal EMI performance is not found by traversing all the states of the pre-charge gate driver 102, the number of digital signal bits of the conventional charging gate driver 101 can be increased by the off-chip control circuit 004 (for example, adjusted from '001' to '010'), and the state of the pre-charge gate driver 102 can be recombined to form a new circuit state of the first gate drive circuit 0051. The above iterative process is then restarted until the circuit state of the first gate drive circuit 0051 corresponding to the system's globally optimal EMI performance is found.
[0117] It is understood that the above are merely possible examples, and the actual EMI performance optimization process for power converters may differ from the examples provided above, which is not limited here.
[0118] Of course, the above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
[0119] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.
Claims
1. A power switch drive circuit, characterized in that, include: The system includes an electromagnetic interference (EMI) detection circuit, a first asynchronous sampling circuit, a second asynchronous sampling circuit, a comparator circuit, an off-chip control circuit, a first gate drive circuit, and a second gate drive circuit; wherein the first gate drive circuit is used to connect to the gate of a first power switch in the power converter, and the second gate drive circuit is used to connect to the gate of a second power switch in the power converter. The input terminal of the EMI detection circuit is connected to a preset switching node between the first power switch and the second power switch to perform on-chip EMI detection on the switching voltage signal of the preset switching node to obtain an EMI detection signal. The output terminal of the EMI detection circuit is connected to the input terminal of the first asynchronous sampling circuit and the input terminal of the second asynchronous sampling circuit, so that the first asynchronous sampling circuit and the second asynchronous sampling circuit detect the EMI detection signal in different periods to obtain a first EMI performance detection parameter and a second EMI performance detection parameter. The output terminals of the first asynchronous sampling circuit and the second asynchronous sampling circuit are also connected to the comparison circuit, so that the comparison circuit compares the first EMI performance detection parameter and the second EMI performance detection parameter to obtain a comparison result; the comparison circuit is also connected to the off-chip control circuit, which is connected to the first gate drive circuit, so that the off-chip control circuit adjusts the first gate drive signal according to the comparison result, and adjusts the EMI performance of the power converter through the first gate drive signal.
2. The power switch drive circuit according to claim 1, characterized in that, The EMI detection circuit includes: a speed-up detection circuit and a peak detection circuit; The input terminal of the speed-up detection circuit is the input terminal of the EMI detection circuit, which is connected to the preset switch node to detect the speed-up of the switch voltage signal and obtain the speed-up detection signal. The output terminal of the speed-up detection circuit is connected to the input terminal of the peak detection circuit, so that the peak detection circuit performs peak detection on the speed-up detection signal to obtain the EMI detection signal. The output terminal of the peak detection circuit serves as the output terminal of the EMI detection circuit and is used to connect the first asynchronous sampling circuit and the second asynchronous sampling circuit.
3. The power switch drive circuit according to claim 2, characterized in that, The speed-up detection circuit includes: a first P-type current mirror, a feedback circuit, a high-voltage NMOS transistor, a first capacitor, a second capacitor, a third capacitor, and a Zener diode. Wherein, the power supply terminal of the first P-type current mirror is used to connect to the first preset power supply, the input terminal of the first P-type current mirror is connected to the drain of the high-voltage NMOS transistor, the gate of the high-voltage NMOS transistor is used to connect to the second preset power supply, the source of the high-voltage NMOS transistor is grounded through the first capacitor, the Zener diode is connected in parallel across the first capacitor, and the gate of the high-voltage NMOS transistor is also connected to the source through the second capacitor. The input terminal of the first P-type current mirror is connected to one end of the third capacitor, and the other end of the third capacitor is the input terminal of the speed-up detection circuit, which is used to connect to the preset switch node; the output terminal of the first P-type current mirror is connected to the input terminal of the feedback circuit, and the output terminal of the feedback circuit is connected as the output terminal of the speed-up detection circuit.
4. The power switch drive circuit according to claim 3, characterized in that, The feedback circuit includes an N-type current mirror and a first NMOS transistor. The power supply terminal of the N-type current mirror is connected to the other end of the third capacitor. The input terminal of the N-type current mirror is connected to the source of the first NMOS transistor. The output terminal of the N-type current mirror and the output terminal of the first P-type current mirror are connected in series as the output terminal of the feedback circuit. The output terminal of the feedback circuit is also connected to the gate of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the first preset power supply.
5. The power switch drive circuit according to claim 3, characterized in that, The peak detection circuit includes: a transconductance amplifier, a second P-type current mirror, a fourth capacitor, and a second NMOS transistor; The negative terminal of the transconductance amplifier is the input terminal of the peak detection circuit. The positive terminal of the transconductance amplifier is connected to the other end of the third capacitor. The output terminal of the transconductance amplifier is connected to the input terminal of the second P-type current mirror. The output terminal of the second P-type current mirror serves as the output terminal of the peak detection circuit. The output terminal of the second P-type current mirror is also connected to the other end of the third capacitor through the fourth capacitor. The drain of the second NMOS transistor is connected to the output terminal of the second P-type current mirror. The source of the second NMOS transistor is also connected to the other end of the third capacitor. The gate of the second NMOS transistor is also used to connect to a third preset power supply.
6. The power switch drive circuit according to claim 1, characterized in that, The first gate drive circuit is a three-stage gate driver, which includes: a conventional charging gate driver, a pre-charge gate driver, a raised gate driver, a ramp raised gate driver, and a switching unit; The conventional charging gate driver, the pre-charging gate driver, the raised gate driver, and the ramp raised gate driver are all connected to the gate of the first power switch. The input terminal of the switching unit is connected to the off-chip control circuit, and the two output terminals of the switching unit are respectively connected to the raised gate driver and the ramp raised gate driver.
7. The power switch drive circuit according to claim 6, characterized in that, The power switch drive circuit includes: a plurality of first boost level shifters and a plurality of second boost level shifters; The input terminals of the plurality of first boost level shifters are respectively connected to the plurality of first output terminals of the off-chip control circuit, and the output terminals of the plurality of first boost level shifters are respectively connected to the plurality of second output terminals of the off-chip control circuit; the output terminals of the plurality of first boost level shifters are respectively connected to the plurality of control pins of the conventional charging gate driver, and the output terminals of the plurality of second boost level shifters are respectively connected to the plurality of control pins of the pre-charge gate driver.
8. The power switch drive circuit according to claim 1, characterized in that, The comparison circuit includes: a hysteresis comparator and a comparator; The output terminals of the first asynchronous sampling circuit and the second asynchronous sampling circuit are respectively connected to the two input terminals of the hysteresis comparator, so that the hysteresis comparator outputs a first comparison signal; the output terminals of the first asynchronous sampling circuit and the second asynchronous sampling circuit are respectively connected to the two input terminals of the comparator, so that the comparator outputs a second comparison signal. The output of the hysteresis comparator and the output of the comparator are both connected to the two inputs of the off-chip control circuit.
9. The power switch drive circuit according to claim 8, characterized in that, The power switch drive circuit further includes: two third boost level shifters, two pulse generators, and two buck level shifters; the input terminals of the two third boost level shifters are connected to the two third output terminals of the off-chip control circuit, the output terminals of the two third boost level shifters are connected to the first input terminals of the two pulse generators, and the second input terminals of the two pulse generators are respectively connected to a preset high-voltage drive signal and a preset low-voltage drive signal; The output terminals of the two pulse generators are respectively connected to the control terminal of the first asynchronous sampling circuit and the control terminal of the second asynchronous sampling circuit; The output of the hysteresis comparator and the output of the comparator are respectively connected to the inputs of the two buck level shifters, and the outputs of the two buck level shifters are respectively connected to the two inputs of the off-chip control circuit.
10. A power converter, characterized in that, include: The first power switch, the second power switch, the output inductor, the output capacitor, and the power switch drive circuit according to any one of claims 1-9 above; The first gate driving circuit and the second gate driving circuit in the power switch driving circuit are respectively connected to the gate of the first power switch and the gate of the second power switch. The drain of the first power switch is connected to a preset voltage input terminal to receive a preset input voltage. The source of the first power switch is connected to the drain of the second power switch, and the source of the second power switch is grounded. The source of the first power switch is a preset switch node, and the preset switch node is connected to a preset voltage output terminal through the output inductor. The preset voltage output terminal is also grounded through the output capacitor.