Multi-channel cascaded arbitrary-order IIR digital filter based on FPGA
By designing a multi-channel cascaded arbitrary-order IIR digital filter in an FPGA, and adopting a second-order section structure and time-division multiplexing architecture, the problems of high resource consumption and high design complexity of high-order IIR filters in FPGA implementation are solved, realizing efficient utilization of hardware resources and flexible parameter configuration.
Patent Information
- Application Number
- CN202511580594.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-31
- Publication Date
- 2026-01-27
AI Technical Summary
In existing technologies, high-order IIR filters suffer from problems such as high hardware resource consumption, high design complexity, poor flexibility, and high power consumption when implemented on FPGAs, which are particularly difficult to solve effectively in multi-channel cascaded applications.
A novel second-order section structure was designed using a multi-channel cascaded arbitrary-order IIR digital filter based on FPGA. The filter is implemented through a time-division multiplexing architecture using a multiplexer, dual-port BRAM, DSP module, and control module, which reduces hardware resource consumption and design complexity and supports real-time updates of filter coefficients.
It achieves efficient utilization of hardware resources, reduces DSP resource consumption by more than 80%, simplifies design complexity, supports flexible parameter configuration, and expands the scope of engineering applications.
Smart Images
Figure CN121417853A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of digital filtering technology, and more specifically, relates to a multi-channel cascaded arbitrary-order IIR digital filter based on FPGA. Background Technology
[0002] Digital filters are core components of digital signal processing systems and are widely used in fields such as communications, audio processing, image processing, and measurement instruments. IIR filters are particularly favored because they can achieve steep frequency responses with relatively low order.
[0003] The time-domain equations of IIR can be expressed as:
[0004]
[0005] Structurally, there is feedback, meaning that the output of the current system is related to the inputs and outputs of the previous system, according to its difference equation. The transfer function of the IIR can be obtained as follows:
[0006]
[0007] in, express Shoot a time-lapse video.
[0008] Figure 1 This is a block diagram of a direct type I I I filter. (See diagram below.) Figure 1 As shown, the IIR filter with direct type I structure has a total of There are 10 delay units, and each delay unit corresponds to one multiplication operation. For The first-order IIR filter requires the most Multiplication and The addition method, while the most intuitive expression of the difference equation, suffers from the fact that IIR filters contain feedback loops. Direct implementation of high-order IIR filters is susceptible to pole location instability due to quantization errors. Therefore, second-order sub-modules are typically used to decompose high-order filters into lower-order modules, reducing error accumulation.
[0009] Equation (2) is The direct form expression of an IIR of order I is expanded as follows:
[0010]
[0011] The second-order section is The expression for the low-order IIR special structure at that time is:
[0012]
[0013] Will Factorize the numerator and denominator of the expression to obtain a second-order polynomial with matched real coefficients and conjugate complex roots, as shown in equation (5), where: Zero point As the extreme point, , , , are conjugate complex roots, and , .
[0014]
[0015] Will Factorize the numerator and denominator of the equation as shown in equation (6).
[0016]
[0017] Based on the form of equation (6), the numerator and denominator of equation (5) are paired and combined respectively to ensure that the coefficients are of appropriate order of magnitude. It can be represented as multiple The product in the form of:
[0018]
[0019] When the filter order When it is even, at this time =1, all subsystems are second-order elements, and When the filter order When it is an odd number, at this time It is a first-order section, and .
[0020] Based on the above theoretical content, in the subsequent design, it is only necessary to design the second-order and first-order section structures and cascade and multiplex them. Following this design approach, IIR filters of arbitrary order can theoretically be realized. Figure 2 It is an arbitrary-order SOS-type IIR signal flow graph. Figure 2 The dashed line represents a first-order section, indicating the order of the view filter. The parity of the property determines whether cascading is necessary, and it can be placed at any node in the cascade. Figure 2 The diagram shown is only for the last level.
[0021] This cascading configuration can achieve... The equivalent filtering effect has or The use of second-order IIR filters simplifies filter design. This design reduces quantization error, but the error accumulates as the number of cascaded stages increases. Therefore, it is necessary to control the number of IIR stages to reduce accumulated error. Generally, the total order of the IIR filter should not exceed 8 stages.
[0022] From equation (6), we can see that There are two poles, and each second-order section can be implemented using a direct type I structure, with the corresponding difference equation in the form of:
[0023]
[0024] As can be seen from the structure of equation (8), the structure of a single second-order section of an IIR filter is equivalent to the difference between two convolution operations in digital circuits. The fastest structure to implement this structure is parallel computation. Figure 3 This is a diagram of a second-order parallel structure. For example... Figure 3 As shown, implementing this operation requires simultaneously accessing 5 multipliers and 3 adders. Parallel architectures offer significant advantages due to their fast computation speed when high real-time performance and high throughput are required. Traditional parallel implementations require a dedicated DSP for each multiplication operation; when the filter order is high or the number of channels is large, hardware resource consumption increases linearly. Furthermore, the data dependencies between multiple DSPs are complex, timing constraints are strict, and design is challenging. Traditional fixed architectures struggle to adapt to different filter parameter requirements, lacking flexibility. Multi-core parallel operation leads to high power consumption, which is detrimental to low-power applications.
[0025] When throughput requirements are low, a serial structure can be used. This structure operates on the ADC sampling clock. Much smaller than the FPGA operating clock At this time, it has a great advantage and can greatly save DSP resources. Figure 4 This is the most basic second-order serial architecture diagram. This architecture only utilizes a single adder / multiplier resource. For each input data, it requires 5 multiplications and 4 additions. One multiplication-addition operation is counted as one computation cycle, and after 5 cycles, the result of one point is output. For a data acquisition system, the ADC cannot receive data signals from multiple points in time simultaneously, thus making parallel computation over 4 cycles impossible. The advantage of serial computation is low resource consumption, but its computational efficiency is also very low. Since the ADC's acquisition frequency is much lower than that of an FPGA, the actual time consumption of this method is not significant.
[0026] However, since IIR is a system with feedback loops, the calculation results need to be used in subsequent calculations. Therefore, this basic serial method requires the calculation results to be stored. Figure 5 This is a diagram of the second-order node computation and storage structure of a serial element. (See diagram for example.) Figure 5 As shown, although this structure saves a lot of DSP resources, it still requires a large amount of RAM space to store intermediate calculation results. These intermediate variables are real-time and constantly updated, which wastes RAM resources by occupying a lot of space. Summary of the Invention
[0027] The purpose of this invention is to overcome the shortcomings of the prior art and provide a multi-channel cascaded arbitrary-order IIR digital filter based on FPGA. A new elementary second-order section is designed to realize an arbitrary-order filter, improve resource utilization, and reduce control complexity.
[0028] To achieve the above-mentioned objectives, the present invention provides a multi-channel cascaded arbitrary-order IIR digital filter based on FPGA, comprising a multiplexer, a dual-port BRAM, a DSP module, and a control module configured within the FPGA, wherein:
[0029] The multiplexer is used to send the input data of the corresponding input channel to the dual-port BRAM for buffering under the control of the control module;
[0030] A dual-port BRAM is used to store IIR filter parameters and buffer input and output data. The configuration method for a dual-port BRAM is as follows:
[0031] Let the number of input channels of the IIR digital filter be... Determine based on actual needs The parameters of the IIR filter for each channel are converted into a second-order definite form, denoted as _i_th_channel_i ... The number of second-order sections in each IIR filter is , , No. The IIR filter of the nth generation Individual second-order section Zero-point coefficient Pole coefficient ,in It is always equal to 1;
[0032] In a dual-port BRAM, each element is a second-order section. Allocate a register set consisting of 10 registers, of which 3 are input data registers. It is used to shift and store input data under the control of the control module. The input data group is denoted as... , Indicates the current sampling point number; the two registers are output data registers. This is used to shift and store the calculation results, and the output data set is denoted as... The five registers are filter coefficient registers. Used to store the second-order element. coefficient group ;
[0033] Allocate a register in the dual-port BRAM as the intermediate value register AddZero;
[0034] The DSP module, under the control of the control module, reads the second-order elements corresponding to the current input channel from the dual-port BRAM. Given the input data and coefficients, the second-order units of each element are calculated sequentially. The input data is filtered; the second-order section of the single element is used to complete the filtering. The calculation is performed using an 11-step timing calculation process, as follows:
[0035] In the first clock cycle, execute step S1.1:
[0036] S1.1: Read the old memory from the corresponding address via port A of the BRAM. As input data ;
[0037] The second clock cycle executes steps S2.1 and S2.2 simultaneously:
[0038] S2.1: Read the old data from the corresponding address via port A of the BRAM. As input data ;
[0039] S2.2: Write input data to the corresponding address through the B port of the BRAM. =old ;
[0040] In the third clock cycle, steps S3.1 and S3.2 are executed simultaneously:
[0041] S3.1: Write new input data to the corresponding address through port A of the BRAM. ;
[0042] S3.2: Write input data to the corresponding address through the B port of the BRAM. =old ;
[0043] In the fourth clock cycle, steps S4.1 and S4.2 are executed simultaneously:
[0044] S4.1: Read input data from the corresponding address via port A of the BRAM. ;
[0045] S4.2: Read the coefficients from the corresponding address via the B port of the BRAM. ;
[0046] The fifth clock cycle executes steps S5.1, S5.2, and S5.3 simultaneously:
[0047] S5.1: Read input data from the corresponding address via port A of the BRAM. ;
[0048] S5.2: Read the coefficients from the corresponding address via the B port of the BRAM. ;
[0049] S5.3: Calculation ;
[0050] In the sixth clock cycle, steps S6.1, S6.2, and S6.3 are executed simultaneously:
[0051] S6.1: Read input data from the corresponding address via port A of the BRAM. ;
[0052] S6.2: Read the coefficients from the corresponding address via the B port of the BRAM. ;
[0053] S6.3: Calculation
[0054] During the 7th clock cycle, steps S7.1, S7.2, and S7.3 are executed simultaneously:
[0055] S7.1: Read output data from the corresponding address via port A of the BRAM. ;
[0056] S7.2: Read the coefficient from the corresponding address via the B port of the BRAM. ;
[0057] S7.3: Calculation The calculation result is then saved to the intermediate value register addZero.
[0058] During the 8th clock cycle, steps S8.1, S8.2, and S8.3 are executed simultaneously:
[0059] S8.1: Read output data from the corresponding address via port A of BRAM. ;
[0060] S8.2: Read the coefficient from the corresponding address via the B port of the BRAM. ;
[0061] S8.3: Calculation ;
[0062] The 9th clock cycle begins; calculations are performed. ;
[0063] On the 10th clock cycle, steps S10.1, S10.2, and S10.3 are executed simultaneously:
[0064] S10.1: For the pole term Invert the result to get ;
[0065] S10.2: Read old output data from the corresponding address via port A of BRAM. ;
[0066] S10.3: Calculation ;
[0067] In the 11th clock cycle, steps S11.1 and S11.2 are executed simultaneously:
[0068] S11.1: Write output data to the corresponding address via port A of the BRAM. ;
[0069] S11.2: Write output data to the corresponding address through the B port of the BRAM. =old ;
[0070] The control module is used to control the multiplexer to forward the input data of the corresponding input channel to the dual-port BRRAM according to the filtering instructions sent by the host computer, and then control the dual-port BRRAM and DSP module to complete the input data filtering of the corresponding input channel.
[0071] This invention relates to a multi-channel cascaded arbitrary-order IIR digital filter based on FPGA, comprising a multiplexer, a dual-port BRAM, a DSP module, and a control module configured within the FPGA. The multiplexer sends the input data of the corresponding input channel to the dual-port BRAM, which stores the IIR filter parameters and buffers the input and output data. A register group is allocated for each second-order element to buffer the input data, output data, zero coefficients, and pole coefficients. The DSP module performs the calculation of each second-order element serially using an 11-step timing calculation process. The control module controls the multiplexer, the dual-port BRAM, and the DSP module to complete the input data filtering.
[0072] The present invention has the following beneficial effects:
[0073] 1) This invention adopts an innovative single-DSP core time-division multiplexing architecture. Through an efficient resource sharing mechanism, it decouples hardware resource consumption from the number of channels and the filter order. Actual measurements show that it can save more than 80% of DSP resources and greatly improve hardware utilization.
[0074] 2) This invention employs an 11-step timing calculation process in a single second-order section, which simplifies the complex data dependencies in traditional designs and effectively reduces design complexity;
[0075] 3) This invention supports real-time updates of IIR filter coefficients, providing flexible reconfigurable capabilities for parameter configuration in different application scenarios;
[0076] 4) Theoretically, this invention can realize IIR filters of any order, thus expanding the scope of engineering applications. Attached Figure Description
[0077] Figure 1 This is a structural diagram of a direct type I I I filter;
[0078] Figure 2 It is an arbitrary-order SOS-type IIR signal flow graph;
[0079] Figure 3 It is a diagram of a second-order parallel structure;
[0080] Figure 4 It is the most basic second-order section serial structure diagram;
[0081] Figure 5 This is a diagram of the second-order computation and storage structure of the serial element;
[0082] Figure 6 This is a structural diagram of the multi-channel cascaded arbitrary-order IIR digital filter based on FPGA of the present invention;
[0083] Figure 7 This is a schematic diagram of a dual-port BRAM.
[0084] Figure 8 This is a schematic diagram of the second-order section input-output connection of an arbitrary-order IIR element in this invention;
[0085] Figure 9 This is a flowchart of the timing calculation of the second-order section in this invention;
[0086] Figure 10 This is the control flowchart of the control module in this embodiment.
[0087] Figure 11 This is a diagram showing the transition modes of the state machine in the control module of this invention;
[0088] Figure 12 These are waveforms of the signals to be filtered in each channel in this embodiment;
[0089] Figure 13 This is a waveform diagram of each channel after filtering and stabilization in this embodiment. Detailed Implementation
[0090] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.
[0091] To better illustrate the technical solution of the present invention, the structure of the single-element second-order section in the present invention will be briefly described first.
[0092] Depend on Figure 2 It can be seen that if the filter is of an odd order, This is a special form of second-order section, namely:
[0093]
[0094] Therefore, when When it is an odd number, it can still be used The IIR filter can be represented by a series of second-order cascaded elements. That is, regardless of whether the filter is of odd or even order, the form of the second-order element can be used as the elements that constitute the IIR filter. Once the structure of the second-order element is determined, filters of any order can also be designed.
[0095] Based on the above design requirements for the elementary second-order section, this invention designs a serial elementary second-order section architecture based on time-division multiplexing. Its design adopts a modular structure to achieve efficient resource utilization and timing control, thereby realizing multi-channel cascaded arbitrary-order IIR digital filters. Figure 6 This is a structural diagram of the multi-channel cascaded arbitrary-order IIR digital filter based on FPGA of this invention. Figure 6 As shown, the multi-channel cascaded arbitrary-order IIR digital filter based on FPGA of this invention includes a multiplexer (MUX), a dual-port BRAM, a DSP module, and a control module set in the FPGA. Each module will be described in detail below.
[0096] The multiplexer is used to send the input data of the corresponding input channel to the dual-port BRAM for buffering according to the data input command sent by the control module.
[0097] Dual-port BRAM is used to store IIR filter parameters and buffer input and output data. Figure 7 This is a schematic diagram of a dual-port BRAM. (Example:) Figure 7As shown, the dual-port BRAM has two input ports and two output ports, configured with coefficient storage areas and data storage areas respectively. Multiple second-order units are cascaded to form the address storage area of a complete IIR filter. A single second-order unit occupies only 10 BRAM address spaces. If the IIR filter is decomposed into K second-order units, then 10K BRAM address spaces are required. Parallel read / write mechanisms can then be used to meet the data throughput requirements of real-time processing. The configuration method of the dual-port BRAM in this invention is as follows:
[0098] Let the number of input channels of the IIR digital filter be... Determine based on actual needs The parameters of the IIR filter for each channel are converted into a second-order definite form, denoted as _i_th_channel_i ... The number of second-order sections in each IIR filter is , , No. The IIR filter of the nth generation Individual second-order section Zero-point coefficient Pole coefficient ,in It is always equal to 1, and then each coefficient is quantized to... Number of fixed points. In this embodiment, Number of fixed points includes digit integer, Two decimal places and one sign bit, i.e. Therefore, in this invention The capacity of an IIR filter coefficient can be expressed as:
[0099]
[0100] In practical applications, the above-described IIR filter coefficient calculation process can be implemented on a host computer using numerical calculation tools such as Matlab, and then sent to the dual-port BRAM via the control module, allowing the filter coefficients to be flexibly configured according to actual needs. The data bit width can also be customized, providing an adjustable balance mechanism between computational accuracy and resource consumption.
[0101] In a dual-port BRAM, each element is a second-order section. Allocate a register set consisting of 10 registers, of which 3 are input data registers. It is used to shift and store input data under the control of the control module. The input data group is denoted as... , Indicates the current sampling point number; the two registers are output data registers. This is used to cache and store the calculation results by shifting them. The output data set is denoted as... The five registers are filter coefficient registers. Used to store the second-order element. coefficient group Therefore, the number of registers in the second level of this invention is... .
[0102] Allocate a register in the dual-port BRAM as the intermediate value register AddZero.
[0103] This embodiment uses continuous register allocation, that is, each second-order element... The corresponding register addresses are consecutive. Table 1 is a list of BRAM address storage areas in this embodiment.
[0104]
[0105] Table 1
[0106] As can be seen, the base address of each second-order section register group in this embodiment is... The following formula is used for calculation:
[0107] (11)
[0108] The addresses of the 10 registers are respectively , Indicates register number hexadecimal, .
[0109] The DSP module, under the control of the control module, reads the second-order elements corresponding to the current input channel from the dual-port BRAM. Given the input data and coefficients, the second-order units of each element are calculated sequentially. The input data is filtered. It is evident that this invention only requires one DSP; this single-core operating mode achieves significant power consumption optimization. Testing shows that this invention reduces power consumption by more than 60% compared to traditional multi-core architectures. Figure 8 This is a schematic diagram of the second-order section input-output connection of an arbitrary-order IIR element in this invention. (See diagram below.) Figure 8 As shown, the first second-order section The data transmitted from the front end is used as input, and other second-order sections use the output of the previous second-order section as input.
[0110] To save time, this invention adopts the concept of pipeline design to design the computation timing. Figure 9 This is a flowchart of the 11-beat timing calculation for the second-order element in this invention. Figure 5In contrast, this structure achieves efficient utilization of hardware resources through time-division multiplexing, making it particularly suitable for multi-channel signal processing applications. It optimizes system power consumption and area efficiency while maintaining computational accuracy. Therefore, in this invention, a single-element second-order section... The specific calculation process is as follows:
[0111] In the first clock cycle, execute step S1.1:
[0112] S1.1: Access the corresponding address via port A of the BRAM ( Read the old As input data ;
[0113] The second clock cycle executes steps S2.1 and S2.2 simultaneously:
[0114] S2.1: Access the corresponding address via port A of the BRAM ( Read the old As input data ;
[0115] S2.2: Send data to the corresponding address via the B port of the BRAM ( Write input data =old ;
[0116] In the third clock cycle, steps S3.1 and S3.2 are executed simultaneously:
[0117] S3.1: Send data to the corresponding address via port A of the BRAM ( Write new input data ;
[0118] S3.2: Send data to the corresponding address via the B port of the BRAM ( Write input data =old .
[0119] As can be seen, the first three clock cycles are used for data shifting and updating the delay line, that is, the shifted input data to be calculated is stored in the dual-port BRAM.
[0120] In the fourth clock cycle, steps S4.1 and S4.2 are executed simultaneously:
[0121] S4.1: Access the corresponding address via port A of the BRAM ( Read input data ;
[0122] S4.2: Access the corresponding address via the B port of the BRAM ( Reading coefficients ;
[0123] The fifth clock cycle executes steps S5.1, S5.2, and S5.3 simultaneously:
[0124] S5.1: Access the corresponding address via port A of the BRAM ( Read input data ;
[0125] S5.2: Access the corresponding address via the B port of the BRAM ( Reading coefficients ;
[0126] S5.3: Calculation ;
[0127] In the sixth clock cycle, steps S6.1, S6.2, and S6.3 are executed simultaneously:
[0128] S6.1: Access the corresponding address via port A of the BRAM ( Read input data ;
[0129] S6.2: Access the corresponding address via the B port of the BRAM ( Reading coefficients ;
[0130] S6.3: Calculation .
[0131] The 4th to 6th clock cycles are the zero-point operation stage, which involves multiplying and adding the retrieved coefficients and the result after input shifting.
[0132] During the 7th clock cycle, steps S7.1, S7.2, and S7.3 are executed simultaneously:
[0133] S7.1: Access the corresponding address via port A of the BRAM ( Read output data ;
[0134] S7.2: Access the corresponding address via the B port of the BRAM ( Reading coefficients ;
[0135] S7.3: Calculation The calculation result is then saved to the intermediate value register addZero.
[0136] During the 8th clock cycle, steps S8.1, S8.2, and S8.3 are executed simultaneously:
[0137] S8.1: Access the corresponding address via port A of the BRAM ( Read output data ;
[0138] S8.2: Access the corresponding address via the B port of the BRAM ( Reading coefficients ;
[0139] S8.3: Calculation ;
[0140] The 9th clock cycle begins; calculations are performed. .
[0141] The 7th to 9th clock cycles belong to the pole operation stage, which involves multiplying and adding the retrieved coefficients and the output shifted result.
[0142] On the 10th clock cycle, steps S10.1, S10.2, and S10.3 are executed simultaneously:
[0143] S10.1: For the pole term Invert the result to get ;
[0144] S10.2: Access the corresponding address via port A of the BRAM ( Read old output data ;
[0145] S10.3: Calculation ;
[0146] In the 11th clock cycle, steps S11.1 and S11.2 are executed simultaneously:
[0147] S11.1: Send data to the corresponding address via port A of the BRAM ( Write output data ;
[0148] S11.2: Send data to the corresponding address via the B port of the BRAM ( Write output data =old .
[0149] The 10th and 11th clock cycles are the final calculation and output update phase. The pole terms are inverted, and the three output samples are shifted and stored in the BRAM.
[0150] Table 2 is a schematic diagram of 11-cycle data reading from a dual-port BRAM in this invention. Table 3 is a schematic diagram of 11-cycle data calculation from a single DSP in this invention.
[0151]
[0152] Table 2
[0153]
[0154] Table 3
[0155] The control module is used to control the multiplexer to forward the input data of the corresponding input channel according to the filtering instructions sent by the host computer. Then, a state machine is used to control the dual-port BRAM and DSP module to complete the filtering of the input data of the corresponding input channel. Figure 10 This is the control flowchart of the control module in this embodiment. For example... Figure 10 As shown, the control flow of the control module in this embodiment includes the following steps:
[0156] S101: Determine the filter channel:
[0157] The control module is used to determine the filtering channel based on the filtering instructions sent by the host computer. The control multiplexer forwards input data from the corresponding input channel to the dual-port BRRAM. In practical applications, the host computer can specify a filtering channel or send a traversal command, and the control module will filter each channel sequentially.
[0158] S102: Connection Individual second-order section:
[0159] The control module is based on the first Number of second-order sections corresponding to each IIR filter , control DSP module serial connection Individual second-order section That is, the first second-order input data is the input data received by the DSP module, and the second to third... The input data of the second-order section of each element is the output data of the second-order section of the previous element.
[0160] S103: Determine the base address:
[0161] Control module determined Individual second-order section The corresponding base address in the dual-port BRAM. In this embodiment, it is calculated according to formula (11).
[0162] S104: Second-order section number of the order element .
[0163] S105: Second-order section of computational element :
[0164] The control module controls the DSP module using an 11-step timing calculation process to calculate the second-order section of the element. .
[0165] S106: Determine if If yes, proceed to step S107; otherwise, the filtering of this channel ends.
[0166] S107: Order Return to step S105.
[0167] Since the control module in this invention is implemented in an FPGA, a state machine can be used to implement filtering control in practical applications. Figure 11 This is a diagram showing the transition patterns of the state machine in the control module of this embodiment. For example... Figure 11 As shown, the state machine of the control module in this embodiment includes an idle state (IDLE), a refresh state (REFRESH), and a filtering state (PROCESS). The control process is as follows:
[0168] In the IDLE state, when the filter enable signal is 0, it jumps to the REFRESH state; when the filter enable signal is 1, it checks the input data status, and when input data is detected, it jumps to the filter processing state.
[0169] In the REFRESH state, the filter coefficients are refreshed, and when the filter enable signal is 1, it jumps to the IDLE state.
[0170] In the PROCESS state of filtering, the second-order steps of each element are performed serially using an 11-step timing calculation process. The calculation is performed while counting the second-order elements of the computation. When the count of the second-order elements reaches... Jump to the idle state (IDLE); when the filter enable signal is 0, jump to the refresh state (REFRESH).
[0171] To better illustrate the technical effects of the present invention, a specific example is used to experimentally verify the present invention. In this embodiment, a Xilinx Artix-7 xc7a35tcsg324-2 FPGA is used as the target device, configured with 6 independent channels, each channel supporting up to 6 cascaded second-order segments (SOS), with a data bit width of 44 bits (synthetic configuration) or 48 bits (generated configuration), an internal storage depth of 1024 points, and a target operating frequency of 100MHz. The filter coefficients are loaded from the configuration file generated by Python, using a Butterworth bandpass filter design. Each channel is configured with 2-3 second-order segments according to different center frequencies (range from 50Hz to 10kHz), each second-order segment contains 5 state variables and 5 coefficient parameters, which are written to the hardware storage unit through the address mapping scheme of equation (11).
[0172] The simulation test used an input signal with a sampling rate of 200kHz and achieved a sampling interval of 500 clock cycles under a 100MHz system clock. The simulation process consists of two main stages: first, coefficient loading initialization is completed through a hardware reset of 10 clock cycles and a mode switching delay of 2 clock cycles, followed by the normal filtering processing stage.
[0173] The test data included signals with six different center frequencies (50Hz, 80Hz, 150Hz, 400Hz, 2kHz, and 10kHz), each with Gaussian white noise of 60dB signal-to-noise ratio and specific harmonic components (3rd and 5th harmonics with amplitudes of 0.1 and 0.05, respectively). Table 4 shows the test waveform parameters in this embodiment. Table 5 shows the filter coefficients corresponding to different cutoff frequencies in this embodiment.
[0174]
[0175] Table 4
[0176]
[0177] Table 5
[0178] Figure 12 These are the waveforms of the signals to be filtered in each channel of this embodiment. For example... Figure 12 As shown, in this embodiment, the length of the signal to be filtered is 1024 points, the time range is 0-5.12 ms, and it includes harmonics and noise components.
[0179] Figure 13 These are the waveforms of each channel after filtering and stabilization in this embodiment. (Comparison) Figure 12 and Figure 13 As can be seen from the waveform, the filtering effect of this invention is good.
[0180] In summary, the IIR filter of this invention can correctly load and apply the preset filter coefficients, functions normally in multi-channel parallel processing mode, and the output results show good consistency with the filtering effect reference data from Python simulation. Timing analysis after synthesis shows that the design meets the 100MHz operating frequency requirement, and the resource utilization on the target device is as expected. This experiment verifies the effectiveness of the cascaded serial IIR filter architecture in multi-channel signal processing. Its reasonable hardware parameter configuration and reliable simulation results lay a solid foundation for subsequent engineering applications, especially demonstrating good application prospects in real-time filtering scenarios that require simultaneous processing of multiple frequency band signals.
[0181] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.
Claims
1. A multi-channel cascaded arbitrary-order IIR digital filter based on FPGA, characterized in that... This includes a multiplexer, a dual-port BRAM, a DSP module, and a control module configured within the FPGA, wherein: The multiplexer is used to send the input data of the corresponding input channel to the dual-port BRAM for buffering under the control of the control module; A dual-port BRAM is used to store IIR filter parameters and buffer input and output data. The configuration method for a dual-port BRAM is as follows: Let the number of input channels of the IIR digital filter be... Determine based on actual needs The parameters of the IIR filter for each channel are converted into a second-order definite form, denoted as _i_th_channel_. The number of second-order sections in each IIR filter is , , No. The IIR filter of the nth generation Individual second-order section Zero-point coefficient Pole coefficient ,in It is always equal to 1; In a dual-port BRAM, each element is a second-order section. Allocate a register set consisting of 10 registers, of which 3 are input data registers. It is used to shift and store input data under the control of the control module. The input data group is denoted as... , Indicates the current sampling point number; the two registers are output data registers. This is used to shift and store the calculation results, and the output data set is denoted as... The five registers are filter coefficient registers. Used to store the second-order element. coefficient group ; Allocate a register in the dual-port BRAM as the intermediate value register AddZero; The DSP module, under the control of the control module, reads the second-order elements corresponding to the current input channel from the dual-port BRAM. Given the input data and coefficients, the second-order units of each element are calculated sequentially. The input data is filtered; the second-order section of the single element is used to complete the filtering. The calculation is performed using an 11-step timing calculation process, as follows: In the first clock cycle, execute step S1.1: S1.1: Read the old memory from the corresponding address via port A of the BRAM. As input data ; The second clock cycle executes steps S2.1 and S2.2 simultaneously: S2.1: Read the old data from the corresponding address via port A of the BRAM. As input data ; S2.2: Write input data to the corresponding address through the B port of the BRAM. =old ; In the third clock cycle, steps S3.1 and S3.2 are executed simultaneously: S3.1: Write new input data to the corresponding address through port A of the BRAM. ; S3.2: Write input data to the corresponding address through the B port of the BRAM. =old ; In the fourth clock cycle, steps S4.1 and S4.2 are executed simultaneously: S4.1: Read input data from the corresponding address via port A of the BRAM. ; S4.2: Read the coefficients from the corresponding address via the B port of the BRAM. ; The fifth clock cycle executes steps S5.1, S5.2, and S5.3 simultaneously: S5.1: Read input data from the corresponding address via port A of the BRAM. ; S5.2: Read the coefficients from the corresponding address via the B port of the BRAM. ; S5.3: Calculation ; In the sixth clock cycle, steps S6.1, S6.2, and S6.3 are executed simultaneously: S6.1: Read input data from the corresponding address via port A of the BRAM. ; S6.2: Read the coefficients from the corresponding address via the B port of the BRAM. ; S6.3: Calculation ; During the 7th clock cycle, steps S7.1, S7.2, and S7.3 are executed simultaneously: S7.1: Read output data from the corresponding address via port A of the BRAM. ; S7.2: Read the coefficient from the corresponding address via the B port of the BRAM. ; S7.3: Calculation The calculation result is then saved to the intermediate value register addZero. During the 8th clock cycle, steps S8.1, S8.2, and S8.3 are executed simultaneously: S8.1: Read output data from the corresponding address via port A of BRAM. ; S8.2: Read the coefficient from the corresponding address via the B port of the BRAM. ; S8.3: Calculation ; The 9th clock cycle begins; calculations are performed. ; On the 10th clock cycle, steps S10.1, S10.2, and S10.3 are executed simultaneously: S10.1: For the pole term Invert the result to get ; S10.2: Read old output data from the corresponding address via port A of BRAM. ; S10.3: Calculation ; In the 11th clock cycle, steps S11.1 and S11.2 are executed simultaneously: S11.1: Write output data to the corresponding address via port A of the BRAM. ; S11.2: Write output data to the corresponding address through the B port of the BRAM. =old ; The control module is used to control the multiplexer to forward the input data of the corresponding input channel to the dual-port BRRAM according to the filtering instructions sent by the host computer, and then control the dual-port BRRAM and DSP module to complete the input data filtering of the corresponding input channel.
2. The multi-channel cascaded arbitrary-order IIR digital filter according to claim 1, characterized in that... Each coefficient of the IIR filter is quantized as Bit fixed-point numbers, including digit integer, One decimal place and one sign bit, i.e. .
3. The multi-channel cascaded arbitrary-order IIR digital filter according to claim 1, characterized in that... The calculation process of the IIR filter parameters is implemented in the host computer using a numerical calculation tool, and then sent to the dual-port BRAM through the control module.
4. The multi-channel cascaded arbitrary-order IIR digital filter according to claim 1, characterized in that... The base address of each second-order segment register group The following formula is used for calculation: ； The addresses of the 10 registers are respectively , Indicates register number hexadecimal, .
5. The multi-channel cascaded arbitrary-order IIR digital filter according to claim 1, characterized in that, The control flow of the control module is as follows: S1: The control module is used to determine the filtering channel according to the filtering instructions sent by the host computer. The multiplexer is controlled to forward the input data of the corresponding input channel to the dual-port BRRAM; S2: The control module, according to the... Number of second-order sections corresponding to each IIR filter , control DSP module serial connection Individual second-order section ; S3: Control module determined Individual second-order section The corresponding base address in the dual-port BRAM; S4: Order number of second-order symmetric element ; S5: The control module controls the DSP module to calculate the second-order element using an 11-step timing calculation process. ; S6: Determine if If yes, proceed to step S7; otherwise, the filtering of this channel ends. S7: Order Return to step S5.
6. The multi-channel cascaded arbitrary-order IIR digital filter according to claim 1, characterized in that, The control module uses a state machine to implement filter control. The state machine includes an idle state (IDLE), a refresh state (REFRESH), and a filter processing state (PROCESS). The control process is as follows: In the IDLE state, when the filter enable signal is 0, it jumps to the REFRESH state; when the filter enable signal is 1, it checks the input data status, and when input data is detected, it jumps to the filter processing state. In the REFRESH state, the filter coefficients are refreshed, and when the filter enable signal is 1, it jumps to the IDLE state. In the PROCESS state of filtering, the second-order steps of each element are performed serially using an 11-step timing calculation process. The calculation is performed while counting the second-order elements of the computation. When the count of the second-order elements reaches... Jump to the idle state (IDLE); when the filter enable signal is 0, jump to the refresh state (REFRESH).