Efficient Manchester code decoding method for electromagnetic flaw detection logger

Abstract

The invention discloses a Manchester code efficient decoding method for an electromagnetic flaw detection logger, which comprises the following steps: step 1, Manchester code single-ended signal acquisition and underground pretreatment, step 2, single-ended signal conditioning, step 3, double-edge interruption triggering and composite synchronous head identification, step 4, pulse width timing recording, and step 5, pulse width decoding. Step 6, decoding based on pulse width; step 6, verifying and outputting decoded data; by adopting a double-edge triggering interruption mode, interruption can be triggered at the rising edge and the falling edge of a Manchester code single-end signal, and compared with traditional single-edge triggering interruption, the interruption waiting time is shortened. Meanwhile, the pulse width is recorded in real time through the timer module, decoding is directly carried out based on the pulse width, complex clock synchronization and signal sampling processing processes are not needed, the decoding process is greatly simplified, the decoding efficiency is effectively improved, and the requirement of electromagnetic flaw detection logging operation for data real-time processing can be met.

Description

Technical Field

[0001] This invention relates to the field of downhole detection technology in oil and gas exploration and development engineering, and in particular to an efficient method for decoding Manchester code in electromagnetic flaw detection logging tools. Background Technology

[0002] In electromagnetic flaw detection logging operations, Manchester code, as a commonly used digital encoding method, is widely applied to data transmission. It features strong self-synchronization capabilities, enabling the simultaneous transmission of clock and data signals during data transmission, ensuring data stability. However, current decoding methods for Manchester code in electromagnetic flaw detection logging tools have several shortcomings in practical applications.

[0003] For example, the Manchester decoding method based on a timing offset algorithm disclosed in Chinese invention patent No. 202310173313.6 relies on "dual timers (timed acquisition + pulse width statistics) + timing offset calculation" (timer 1 count value ÷ 2 count). Under a 10Mbps signal, the delay is ≥5μs, which easily leads to inter-symbol interference. The fault tolerance mechanism is redundant: verification failure triggers a full-process initialization reset, and continuous frame transmission easily results in the loss of entire data segments, affecting the continuity of oil casing defect judgment. Environmental adaptability is poor: dual timers run continuously (static current ≥200μA), without high-temperature pulse width compensation, resulting in a pulse width recognition error ≥15% at 125℃. Triggering flexibility is insufficient: it requires first obtaining the starting signal with "falling edge triggering" and then switching to dual-edge triggering, which can easily lead to initial misjudgment due to downhole electromagnetic interference. Most traditional decoding methods rely on single-edge triggering interruption. In the complex downhole environment of electromagnetic flaw detection logging, they are easily affected by electromagnetic interference, signal attenuation, and other factors, leading to inaccurate interruption triggering and subsequent decoding errors. Meanwhile, traditional methods lack precise recording and analysis of pulse width, and cannot adjust the decoding strategy in a timely manner according to changes in pulse width, resulting in low decoding efficiency and poor fault tolerance. When a small amount of noise interference or signal distortion occurs in the transmitted data, traditional decoding methods are prone to decoding failure, which seriously affects the real-time processing and subsequent analysis of electromagnetic flaw detection logging data, and is not conducive to ensuring the smooth progress of logging operations and the accuracy of logging results.

[0004] Therefore, developing a decoding method for Manchester codes in electromagnetic flaw detection logging tools that can improve decoding efficiency and fault tolerance has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide an efficient method for decoding Manchester codes in electromagnetic flaw detection logging tools, so as to solve the problems of low decoding efficiency and poor fault tolerance in the existing technology.

[0006] The technical solution of this invention: A method for efficient decoding of Manchester code in electromagnetic flaw detection logging tools, comprising the following steps:

[0007] Step 1: Manchester code single-ended signal acquisition and downhole preprocessing. The downhole Manchester code single-ended signal is acquired by the data acquisition module of the electromagnetic flaw detection logging tool, and the preprocessed Manchester code single-ended signal is transmitted to the signal conditioning module.

[0008] Step 2, Manchester code single-ended signal conditioning: The Manchester code single-ended analog signal acquired in Step 1 is filtered, amplified and level-converted to obtain the Manchester code single-ended digital signal.

[0009] Step 3: Dual-edge interrupt triggering and composite synchronization header identification. The microprocessor processes the acquired single-ended digital signal and configures an interrupt controller in the microprocessor. The interrupt triggering mode is set to dual-edge triggering. When the level of the single-ended digital Manchester code signal changes from high to low or from low to high, an interrupt request is triggered.

[0010] Step 4: Pulse width timing recording. The microprocessor integrates a timer module. When the interrupt controller detects a double-edge triggered interrupt, it immediately triggers the timer module to start timing. When the next double-edge triggered interrupt occurs, the timer module stops timing and records the time interval between the two interrupts. This time interval is the pulse width of the current Manchester code single-ended signal. The timer module stores the recorded pulse width data in the microprocessor's memory unit for subsequent decoding and analysis.

[0011] Step 5: Decoding based on pulse width. The microprocessor activates the fault tolerance mechanism to handle abnormal pulse widths according to the preset Manchester code encoding rules and pulse width threshold range, and analyzes and decodes the pulse width data recorded in the storage unit.

[0012] Step 6: Decoded data verification and output. The microprocessor verifies the decoded data, using methods such as cyclic redundancy check or parity check to detect whether there are errors in the decoded data.

[0013] Furthermore, in step one, the data acquisition module uses a 12-bit or higher ADC.

[0014] Furthermore, in step two, the filtering of the single-ended analog signal adopts an RC low-pass filter, the signal is processed by a low-temperature drift operational amplifier to avoid high-temperature amplification factor drift, and a Schmitt trigger is used for level conversion.

[0015] Furthermore, step two also includes temperature compensation for single-ended analog signals, using an integrated DS18B20 sensor to collect real-time temperature T and transmit it to the microprocessor, providing data support for pulse width threshold adjustment.

[0016] Furthermore, in step three, the microprocessor uses an STM32F4 series microcontroller, and the interrupt controller is an external interrupt controller EXTI. The external interrupt controller EXTI is set to be triggered by both rising and falling edges from the beginning, and a 10ns interference debouncing unit is added to avoid electromagnetic false triggering.

[0017] Furthermore, in step four, the timer module is a timer integrated inside the microprocessor and is set individually, calculating the pulse width through the counting frequency and the count value.

[0018] Furthermore, in step five, the pulse width-based decoding employs a reference threshold, temperature compensation, and current polarity three-dimensional judgment logic. The preset pulse width threshold range includes a standard narrow pulse width threshold range and a standard wide pulse width threshold range. The standard narrow pulse width corresponds to half a symbol period of Manchester code, and the standard wide pulse width corresponds to one symbol period.

[0019] Furthermore, in step five, the fault tolerance mechanism involves correlating and analyzing abnormal pulse width data with adjacent pulse width data, inferring symbolic elements by combining the self-synchronization characteristics of Manchester code, and then performing a second correction based on verification rules after decoding.

[0020] Furthermore, in step five, the cyclic redundancy check or parity check method is used to verify the decoded data.

[0021] The beneficial effects of this invention compared to the prior art are as follows:

[0022] 1. High decoding efficiency: This invention employs a dual-edge triggered interrupt method, enabling interrupts to be triggered on both the rising and falling edges of the Manchester code single-ended signal. Compared to traditional single-edge triggered interrupts, this reduces interrupt waiting time and increases the frequency and timeliness of interrupt triggering, allowing the microprocessor to respond more quickly to changes in the Manchester code single-ended signal. Simultaneously, the pulse width is recorded in real-time by a timer module, allowing decoding directly based on the pulse width. This eliminates the need for complex clock synchronization and signal sampling processes, greatly simplifying the decoding process and effectively improving decoding efficiency. This meets the real-time data processing requirements of electromagnetic flaw detection logging operations.

[0023] 2. High fault tolerance: During the decoding process, this invention not only presets a standard pulse width threshold range for accurate identification of symbol information, but also establishes a robust fault tolerance mechanism. When pulse width anomalies occur, by analyzing the correlation with adjacent pulse width data and combining the self-synchronization characteristics of Manchester codes and data verification rules, suspicious symbols can be inferred and corrected. This effectively reduces the decoding error rate caused by electromagnetic interference, signal attenuation, and other factors, improves the fault tolerance of the decoding method, and ensures the accuracy and reliability of electromagnetic flaw detection logging data decoding.

[0024] 3. High adaptability: By presetting different pulse width threshold ranges, this invention can be flexibly adjusted according to the different transmission rates and encoding standards of the Manchester code of the electromagnetic flaw detection logging tool. It is applicable to various specifications of electromagnetic flaw detection logging tools, has strong adaptability and versatility, and can meet different downhole logging environments and logging needs.

[0025] 4. Simplified data synchronization significantly reduces hardware and software overhead. In the Manchester code decoding scenario of electromagnetic flaw detection logging tools, this method breaks through the dependence of traditional decoding on independent synchronization clocks and constructs a lightweight synchronization mechanism with "synchronization head pulse width recognition" as its core. Specifically, in the preset decoding protocol, a pulse of a specific width is clearly defined as the synchronization head (for example, for Manchester code with a transmission rate of 1 Mbps, a 3μs wide pulse can be set as the synchronization head). The pulse width of this synchronization head is significantly different from the pulse width of conventional data bits (0.5μs narrow pulse or 1μs wide pulse), which can be quickly recognized by the microprocessor.

[0026] When the microprocessor records a pulse that falls within the synchronization header width threshold range via the timer module, it is considered the start signal for decoding a complete data word, eliminating the need for additional clock extraction circuitry or complex clock synchronization algorithms (such as phase-locked loops, delay-locked loops, etc.). From a hardware perspective, this eliminates the need for a dedicated clock generation chip or an internal clock synchronization module within the FPGA, reducing circuit design complexity and hardware costs. From a software perspective, it avoids real-time tracking and calibration of the synchronization clock, reducing the microprocessor's computational load and saving software development workload and code storage space. This simplified synchronization method is particularly well-suited to the limitations of downhole logging environments—downhole equipment has stringent requirements for hardware size, power consumption, and stability. By simplifying the synchronization logic, this method effectively reduces the hardware size and power consumption of the equipment while ensuring synchronization accuracy, thereby improving the reliability of the decoding system in complex downhole environments.

[0027] 5. Small cumulative error ensures overall data decoding accuracy. In traditional Manchester code decoding methods, if a data bit experiences a pulse width deviation due to signal interference, this deviation may be transmitted to subsequent data bits through the clock synchronization link, causing the error to accumulate continuously in a single byte (8 bits) or the entire data frame (containing multiple bytes), eventually leading to large-scale decoding errors. This method, based on an "independent pulse width determination" mechanism, fundamentally avoids the risk of error accumulation.

[0028] Specifically, this method decodes each data bit based on its own pulse width. The microprocessor records the pulse width corresponding to each data bit through a timer module and then compares it directly with a preset standard narrow / wide pulse width threshold range to determine the symbol information ("0" or "1") of the data bit. In this process, the pulse width determination of each data bit is independent of each other. Even if the pulse width of the previous data bit deviates due to factors such as electromagnetic interference or signal attenuation (e.g., the narrow pulse shifts from 0.5μs to 0.58μs), as long as the fault-tolerant mechanism completes the correction or determination of the data bit, the deviation is limited to the current data bit and will not affect the pulse width sampling and determination of subsequent data bits.

[0029] For electromagnetic logging operations, the accuracy of single-byte or whole-frame data directly affects the accuracy of downhole casing defect assessment (such as corrosion degree, crack size, etc.). This method controls the error within a single data bit range, avoiding the failure of the entire data segment due to error accumulation. This ensures that the decoded data can accurately reflect the downhole conditions, providing a reliable data foundation for subsequent logging data analysis and defect assessment.

[0030] 6. The software decoding architecture is simple and has low power consumption. With a single timer sleep mode and a microprocessor with low quiescent current, the power consumption is much lower than that of decoding solutions such as FPGA and dual timers. Therefore, it can be adapted to most logging tool downhole power supply systems. Attached Figure Description

[0031] Figure 1 This is a diagram showing the 1Mbps Manchester code pulse width and its composition in this invention.

[0032] Figure 2 This is a composition diagram of the 0.5μs pulse width of the present invention;

[0033] Figure 3 This is a composition diagram of the 1.0μs pulse width of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0035] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0036] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0037] See Figure 1-3 The present invention discloses an efficient Manchester code decoding method for electromagnetic flaw detection logging tools. This invention, through "composite synchronization head design + three-dimensional decoding (pulse width - polarity - temperature) + single-end dedicated conditioning + joint detection (synchronization head interval - CRC)," avoids the technical features of the aforementioned comparative documents while meeting the core downhole requirements.

[0038] See Figure 1 In this context, a valid data frame consists of a synchronization header (3 bits wide) + multiple data bits (10 bits in this example) + 1 parity bit.

[0039] This embodiment uses a certain type of electromagnetic flaw detection logging tool as an example. Its Manchester code transmission rate is 1 Mbps, and the encoding rules are as follows: A "1" symbol represents a high level in the first half of the cycle and a low level in the second half, i.e., a high-to-low level transition; a "0" symbol represents a low level in the first half of the cycle and a high level in the second half, i.e., a low-to-high level transition. The corresponding standard narrow pulse width (half a symbol cycle, i.e., half a bit width) is 0.5 μs; the corresponding standard wide pulse width (one symbol cycle, i.e., one bit width) is 1 μs. The standard narrow pulse width threshold range is set to 0.45 μs to 0.55 μs; the standard wide pulse width threshold range is set to 0.95 μs to 1.05 μs.

[0040] The specific steps are as follows:

[0041] Step 1: Manchester code single-ended signal acquisition and downhole preprocessing. The single-ended analog signal transmitted via a single-core cable is acquired through the data acquisition module of the electromagnetic flaw detection logging tool. A built-in 50Hz RC power frequency notch filter (attenuation ≥40dB) filters out dynamic interference, and a signal amplitude clamping unit (limited from 0V to 3.3V) suppresses spike pulses. The preprocessed single-ended analog signal is then transmitted to the signal conditioning module. The data acquisition module uses a 12-bit or higher ADC with a sampling rate no less than 10 times the Manchester code transmission rate.

[0042] Step 2: Single-ended signal conditioning. The single-ended analog signal is processed through four stages: filtering, low-temperature drift amplification, level conversion, and temperature compensation, to obtain a single-ended digital signal.

[0043] 1. Filtering: Second-order RC low-pass filter (cutoff frequency = 1.5 × transmission rate, e.g., 10Mbps corresponds to 15MHz), no mode transformer required, filters analog signals to remove high-frequency noise;

[0044] 2. Amplification: The low-temperature drift operational amplifier (AD8605, temperature drift ≤1μV / ℃) amplifies the signal to 0.5V~3V to avoid high-temperature amplification factor drift (gain set to 10 times) and amplifies the filtered signal to the amplitude range of 0V~3.3V.

[0045] 3. Level Conversion: The Schmitt trigger (threshold temperature drift ≤ 5mV / ℃) converts the analog signal to a digital single-ended signal (3.3V high / 0V low). The set Schmitt trigger converts the analog signal to a digital Manchester code single-ended signal (high level is 3.3V, low level is 0V).

[0046] 4. Temperature compensation: The integrated DS18B20 sensor (-55℃~125℃) collects real-time temperature T and transmits it to the microprocessor (STM32F4, static current ≤1.8μA) to provide data support for pulse width threshold adjustment;

[0047] Finally, the conditioned single-ended digital signal is transmitted to the microprocessor.

[0048] Step 3: Dual-edge interrupt triggering and composite synchronization header identification. The microprocessor processes the acquired single-ended digital signal and configures an interrupt controller in the microprocessor. The interrupt triggering mode is set to dual-edge triggering. When the level of the single-ended digital Manchester code signal changes from high to low or from low to high, an interrupt request is triggered.

[0049] 1. Dual-edge interrupt configuration: The external interrupt controller (EXTI) is initially set to "dual-edge triggering of rising and falling edges", and a 10ns interference debounce unit is added (level transition duration ≥10ns is considered valid) to avoid electromagnetic false triggering;

[0050] 2. Composite Synchronization Header Definition: Define a composite synchronization header of "2T low level + 3T high level" (T is the symbol period, T=1μs at 1Mbps, total duration 5μs). The level changes from high to low or from low to high, that is, whether the interrupt is a rising edge transition or a falling edge transition. Then, combined with the total duration of the counter, the composite synchronization header or data bit operation can be confirmed by the dual feature of "polarity alternation + total duration". The difference between the pulse width of the composite synchronization header and the pulse width of the data bit (0.5T~T) is ≥3 times, and it can still be accurately identified even with a 15% high temperature offset.

[0051] 3. Synchronization header determination logic: The timer records the pulse width and polarity of adjacent interrupts. Continuous detection of "low level 2T±5% + high level 3T±5%" triggers frame decoding. The first code is determined directly by the polarity and pulse width of the first pulse after the synchronization header.

[0052] Step 4: Pulse width timing recording. The microprocessor integrates a timer module. When the interrupt controller detects a double-edge triggered interrupt, the microcontroller responds to the interrupt and starts the TIM2 trigger timer module to begin timing. When the next double-edge triggered interrupt occurs, the microcontroller responds to the interrupt again, stops the TIM2 timer, reads the count value of TIM2, and records the time interval between the two interrupts. This time interval is the pulse width of the current Manchester code single-ended signal. The timer module stores the recorded pulse width data in the microprocessor's memory unit for subsequent decoding and analysis.

[0053] Pulse width recording is achieved using only a single timer within the microprocessor (such as TIM2 in STM32F4, with a clock frequency of 84MHz, a division factor of 83, and a counting frequency of 1MHz).

[0054] 1. Timer configuration: 84MHz clock → divided by 83 → counting frequency 1MHz (accuracy 1μs), no overflow interrupt;

[0055] 2. Pulse Width Recording Logic: Timing starts when a valid dual-edge interrupt is triggered and stops upon the next interrupt. The pulse width is then directly calculated (Pulse Width = Count Value × (1 / Counting Frequency)). For example, if the TIM2 count value is 500, then the pulse width = 500 × (1 / 10^6) = 0.5μs. Subsequently, the calculated pulse width data is stored in the microcontroller's on-chip Flash memory.

[0056] 3. Low power consumption optimization: Timer sleeps when there is no interruption, unlike the continuous operation of dual timers in comparison document 1 and the high power consumption of FPGA in comparison document 3.

[0057] At the same time, the "pulse width-temperature" data is bound and stored in the on-chip Flash memory for subsequent decoding.

[0058] Step 5: Based on pulse width decoding, the microprocessor activates a fault-tolerant mechanism to handle abnormal pulse widths according to the preset Manchester code encoding rules and pulse width threshold range. It also analyzes and decodes the pulse width data recorded in the storage unit, employing a three-dimensional judgment logic of "baseline threshold + temperature compensation + current polarity".

[0059] The STM32F4 microcontroller sequentially reads pulse width data from its on-chip Flash memory and compares it with preset standard narrow pulse width threshold ranges (0.45μs~0.55μs) and standard wide pulse width threshold ranges (0.95μs~1.05μs):

[0060] 1. Reference threshold and temperature compensation:

[0061] Reference threshold: At 1Mbps, narrow pulse 0.45μs~0.55μs (half a symbol), wide pulse 0.95μs~1.05μs (one symbol), "1" symbol is "high→low transition (falling edge)", "0" symbol is "low→high transition (rising edge)";

[0062] Temperature compensation coefficient: K=1+0.005×(T-25) (25℃ as the baseline, threshold ±5% for every 10℃ increase), K=1.5 at 125℃, narrow pulse threshold adjusted to 0.675μs~0.825μs;

[0063] 2. Three-dimensional decoding logic:

[0064] Read the "pulse width-temperature-polarity" data and calculate the real-time threshold range;

[0065] Narrow pulse: Combine polarity (rising edge → "0" half-symbol, falling edge → "1" half-symbol), match the polarity of the next pulse to determine the complete symbol;

[0066] Wide pulse: Combines polarity to split into two complete symbols (the first half of the previous symbol and the second half of the next symbol), without the need to compare the state machine loop in file 3;

[0067] Abnormal pulse width (exceeding threshold): Activate the three-level fault tolerance mechanism (avoiding reset / retry of three types of comparison files):

[0068] ① Level 1: Correlate with the average "pulse width-polarity" of the three adjacent normal pulses; if the deviation is ≤20%, complete the value.

[0069] ② Level 2: If the deviation is >20%, mark it as a "suspicious symbol" and continue decoding without interruption;

[0070] ③ Level 3: After decoding, suspicious code elements are corrected by reverse calculation using CRC-16 to avoid data loss.

[0071] Step 6: Decoded data verification and output. The microprocessor verifies the decoded data, using methods such as cyclic redundancy check or parity check to detect whether there are errors in the decoded data.

[0072] Replace the "delay timer reset" in comparison file 2 with "synchronization header interval + CRC-16":

[0073] 1. Frame end determination: If no "2T low + 3T high" synchronization header feature is detected after 10 consecutive pulses, the frame is determined to be over.

[0074] 2. CRC-16 checksum: Generator polynomial x¹ 6 +x¹ 5 +x²+1, the check covers "composite synchronization header + data bits + check bit", and the error location accuracy reaches a single symbol;

[0075] 3. Output logic:

[0076] Verification passed: The decoded oil casing defect data (such as corrosion depth and crack width) is transmitted to the data analysis module via a low-power serial port (idle sleep mode);

[0077] Verification failed: Suspicious code elements were corrected based on three levels of fault tolerance (up to 3 times). If it still failed, only "local code element abnormal" was output, without triggering a full reset (avoiding the full process restart of comparison file 1 / 2).

[0078] When a pulse width of 0.5μs is read, this data falls within the standard narrow pulse width threshold range. Based on the encoding rules, if the pulse is a narrow pulse recorded after a rising edge (low level in the first half of the cycle, high level in the second half of the cycle, or high level of a standard wide pulse), then the half-symbol corresponding to this pulse is determined to be the first half-symbol of "0". If another 0.5μs narrow pulse or a 1.0μs wide pulse (falling edge) subsequently appears, they combine to form a complete "0" symbol. Figure 2 As shown, the transition from low to high level indicated by the arrow represents the "0" symbol.

[0079] When a pulse width of 1.0 μs is read, this pulse width is within the standard pulse width threshold range. According to the encoding rules, a standard symbol consists of level transitions. When a pulse with a data bit width is recorded: the first half of the pulse width is half the pulse width of the previous symbol, and the second half of the pulse width is half the pulse width of the next symbol, each occupying 0.5 μs. For example... Figure 3 As shown, if the pulse is a wide pulse recorded after the falling edge, the high level of the first half of the pulse width and the preceding low pulse (0.5μs bit width) form a "0" symbol (low to high transition); the high level of the second half of the pulse width and the following low pulse form a "1" symbol (high to low transition).

[0080] If the pulse width data read is 0.6μs, which is neither within the standard narrow pulse width threshold range nor the standard wide pulse width threshold range, the microcontroller activates the fault tolerance mechanism. It checks the adjacent pulse width data, which is 0.48μs (within the standard narrow pulse width threshold range) and the pulse width data, which is 0.49μs (within the standard narrow pulse width threshold range). Considering the characteristic that the Manchester code "1" symbol is composed of two narrow pulses, it is inferred that the 0.6μs pulse width data is a slight distortion caused by signal interference. It is still regarded as the middle part of the "1" symbol, and the complete "1" symbol information is determined.

[0081] Step Six: Decoded Data Verification and Output. The microprocessor verifies the decoded data, using methods such as cyclic redundancy check (CRC) or parity check to detect errors. The STM32F4 microcontroller uses CRC-16 verification to check the decoded data, calculating the checksum using the CRC-16 algorithm and comparing it with the checksum carried in the Manchester code single-ended signal. If they match, the decoded data is error-free, and the valid data is transmitted to the data analysis module of the electromagnetic flaw detection logging tool via serial communication. If they do not match, the microcontroller uses the error detection capability of CRC-16 to determine the location of the error data. Combining the fault tolerance mechanism from Step Five, it re-analyzes and corrects the data at the error location, recalculating the CRC-16 checksum until it matches the carried checksum, and then outputs the decoded data. If the verification still fails after multiple corrections, a message "Decoding error, please re-acquire signal" is output via serial port.

[0082] Through the application of this embodiment, the decoding efficiency of the Manchester code high-efficiency decoding method for electromagnetic flaw detection logging tools is improved by more than 30% compared with the traditional method. In the downhole environment with certain electromagnetic interference, the decoding error rate is reduced to below 0.1%, which fully demonstrates its advantages of high efficiency and high fault tolerance, and can meet the actual needs of electromagnetic flaw detection logging operations.

[0083] Specifically, in step five, the fault tolerance mechanism involves correlating and analyzing abnormal pulse width data with adjacent pulse width data, inferring symbolic elements by combining the self-synchronization characteristics of Manchester code, and then performing a second correction based on verification rules after decoding.

[0084] Specifically, in step five, the cyclic redundancy check or parity check method is used to verify the decoded data.

[0085] In addition to the preferred embodiments described above, the present invention has other embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection claimed by the present invention.

Claims

1. A method for efficient decoding of Manchester code in electromagnetic flaw detection logging tools, characterized in that, Includes the following steps: Step 1: Manchester code single-ended signal acquisition and downhole preprocessing. The downhole Manchester code single-ended signal is acquired by the data acquisition module of the electromagnetic flaw detection logging tool, and the preprocessed Manchester code single-ended signal is transmitted to the signal conditioning module. Step 2: Manchester code single-ended signal conditioning. The single-ended analog signal acquired in Step 1 is filtered, amplified, and level-converted to obtain a Manchester code single-ended digital signal. Step 3: Dual-edge interrupt triggering and composite synchronization header identification. The microprocessor processes the acquired single-ended digital signal and configures an interrupt controller in the microprocessor. The interrupt triggering mode is set to dual-edge triggering. When the level of the single-ended digital Manchester code signal changes from high to low or from low to high, an interrupt request is triggered. Step 4: Pulse width timing recording. The microprocessor integrates a timer module. When the interrupt controller detects a double-edge triggered interrupt, it immediately triggers the timer module to start timing. When the next double-edge triggered interrupt occurs, the timer module stops timing and records the time interval between the two interrupts. This time interval is the pulse width of the current Manchester code single-ended signal. The timer module stores the recorded pulse width data in the microprocessor's memory unit for subsequent decoding and analysis. Step 5: Decoding based on pulse width. The microprocessor activates the fault tolerance mechanism to handle abnormal pulse widths according to the preset Manchester code encoding rules and pulse width threshold range, and analyzes and decodes the pulse width data recorded in the storage unit. Step 6: Decoded data verification and output. The microprocessor verifies the decoded data, using methods such as cyclic redundancy check or parity check to detect whether there are errors in the decoded data.

2. The method for efficient Manchester code decoding in electromagnetic flaw detection logging tools according to claim 1, characterized in that, In step one, the data acquisition module uses a 12-bit or higher ADC.

3. The method for efficient Manchester code decoding in electromagnetic flaw detection logging tools according to claim 1, characterized in that, In step two, the filtering of the single-ended analog signal adopts an RC low-pass filter, and the signal is processed by a low-temperature drift operational amplifier to avoid high-temperature amplification factor drift. A Schmitt trigger is used for level conversion.

4. The method for efficient Manchester code decoding in electromagnetic flaw detection logging tools according to claim 2, characterized in that, Step two also includes temperature compensation for single-ended analog signals. An integrated DS18B20 sensor is used to collect real-time temperature T and transmit it to a microprocessor to provide data support for pulse width threshold adjustment.

5. The method for efficient Manchester code decoding in electromagnetic flaw detection logging tools according to claim 1, characterized in that, In step three, the microprocessor uses an STM32F4 series microcontroller, and the interrupt controller is the microcontroller's external interrupt controller EXTI. The external interrupt controller EXTI is set to be triggered by both rising and falling edges from the beginning, and a 10ns interference debouncing unit is added to avoid electromagnetic false triggering.

6. The method for efficient Manchester code decoding in electromagnetic flaw detection logging tools according to claim 1, characterized in that, In step four, the timer module is a timer integrated inside the microprocessor and is set individually. The pulse width is calculated by the counting frequency and the count value.

7. The method for efficient Manchester code decoding in electromagnetic flaw detection logging tools according to claim 1, characterized in that, In step five, the pulse width-based decoding employs a reference threshold, temperature compensation, and current polarity three-dimensional judgment logic. The preset pulse width threshold range includes a standard narrow pulse width threshold range and a standard wide pulse width threshold range. The standard narrow pulse width corresponds to half a symbol period of Manchester code, and the standard wide pulse width corresponds to one symbol period.

8. The method for efficient Manchester code decoding in electromagnetic flaw detection logging tools according to claim 1, characterized in that, In step five, the fault tolerance mechanism involves correlating abnormal pulse width data with adjacent pulse width data, inferring symbolic elements by combining the self-synchronization characteristics of Manchester code, and then performing a second correction based on verification rules after decoding.

9. The method for efficient Manchester code decoding in electromagnetic flaw detection logging tools according to claim 1, characterized in that, In step five, the cyclic redundancy check or parity check method is used to verify the decoded data.

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