Semiconductor device and method of manufacturing the same

Abstract

This application relates to a semiconductor device and a method for manufacturing the same, comprising: a substrate, a first dielectric layer, a first gate structure, and a second dielectric layer, wherein a gate trench is formed in the substrate; the first dielectric layer covers the bottom and a sidewall of the gate trench near the bottom of the gate trench; the first gate structure is located at the bottom of the gate trench, and the first gate structure is in contact with a portion of the first dielectric layer located at the bottom of the gate trench; the second dielectric layer covers the top surface and a portion of the sidewall of the first gate structure, and exposes a portion of the sidewall of the first gate structure near the bottom of the gate trench; a gap is provided between the first dielectric layer and the second dielectric layer, and the gap is located on both sides of the first gate structure. This application improves the isolation between the first gate structure and the substrate, reduces the leakage current of the substrate, and achieves high control over the threshold voltage of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] The fully depleted silicon-on-insulator (FD-SOI) process addresses the body leakage problem by creating a buried oxide (BOX) layer, which allows the PN junction to remain on the buried oxide layer. As the size of FD-SOI devices is further reduced, the size of the PN junction and the gate linewidth of the metal gate (MG) are also reduced accordingly.

[0003] However, as the length of the metal gate decreases, the random roughness of the gate line increases accordingly, which is enough to make the uniformity of the gate line uncontrollable. At the same time, the presence of the thin-body region can easily lead to random dopant flux (RDF) of doped atoms. For example, when the channel length is too small, electrons between the source and drain may randomly enter the channel, causing changes in the channel concentration, which in turn makes the threshold voltage Vt of the semiconductor device uncontrollable. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device and its manufacturing method to achieve precise control of the current and voltage of the semiconductor device and reduce leakage current.

[0005] This application provides a semiconductor device, including:

[0006] A substrate in which gate trenches are formed;

[0007] A first dielectric layer covers the bottom of the gate trench and the sidewall of the gate trench near the bottom of the gate trench.

[0008] A first gate structure is located at the bottom of the gate trench, and the first gate structure is in contact with the portion of the first dielectric layer located at the bottom of the gate trench.

[0009] The second dielectric layer covers the top surface and part of the sidewalls of the first gate structure, and exposes part of the sidewalls of the first gate structure near the bottom of the gate trench.

[0010] Wherein, a gap is provided between the first dielectric layer and the second dielectric layer, and the gap is provided on both sides of the first gate structure.

[0011] In one embodiment, the first gate structure includes:

[0012] A first gate dielectric layer is located on the first dielectric layer;

[0013] A first gate is located on the first gate dielectric layer, and the portions of the top surface, sidewalls, and bottom surface of the first gate located on both sides of the first gate dielectric layer are all covered by the second dielectric layer.

[0014] In one embodiment, the semiconductor device further includes:

[0015] The substrate includes the substrate, the first dielectric layer, the second dielectric layer, the first gate structure, the gap, and the epitaxial layer, wherein the epitaxial layer is located above the first dielectric layer, the second dielectric layer, the first gate structure, and the gap and fills the gate trench;

[0016] A second gate structure is located on the substrate, and the orthographic projection of the second gate structure toward the substrate at least partially coincides with the orthographic projection of the first gate structure toward the substrate.

[0017] In one embodiment, the second gate structure includes:

[0018] A second gate dielectric layer is located on the substrate;

[0019] The second gate is located on the second gate dielectric layer;

[0020] A gate sidewall that covers the sidewall of the second gate.

[0021] In one embodiment, the semiconductor device further includes:

[0022] The source region is located within the substrate on one side of the second gate structure;

[0023] The drain region is located within the substrate on the side of the second gate structure away from the source region;

[0024] A metal silicide layer is located on top of the source region, the drain region, and the second gate structure;

[0025] An interlayer dielectric layer is located on the substrate, and the interlayer dielectric layer covers the second gate structure and the metal silicide layer;

[0026] An electrical connector extends through the interlayer dielectric layer and is connected to the source region, the drain region, and the metal silicide layer at the top of the second gate structure, respectively.

[0027] Accordingly, this application also provides a method for manufacturing a semiconductor device, comprising:

[0028] A substrate is provided in which a gate trench is formed, and a first dielectric layer is formed on the sidewalls and bottom of the gate trench;

[0029] A first gate structure is formed on the first dielectric layer, and the first gate structure is formed at the bottom of the gate trench;

[0030] A second dielectric layer is formed on the top surface and a portion of the sidewalls of the first gate structure, and the second dielectric layer exposes a portion of the sidewalls of the first gate structure near the bottom of the gate trench.

[0031] A portion of the first dielectric layer is removed, so that the remaining first dielectric layer is flush with the surface of the second dielectric layer, and a gap is formed between the first dielectric layer and the second dielectric layer, the gap being located on both sides of the first gate structure.

[0032] In one embodiment, the formation process of the first gate structure includes:

[0033] A first gate dielectric layer is formed on the first dielectric layer;

[0034] A first gate is formed on the first gate dielectric layer, and the first gate is formed at the bottom of the gate trench;

[0035] A portion of the first gate dielectric layer is removed, so that the remaining first gate dielectric layer contacts a portion of the bottom surface of the first gate. The first gate structure includes the first gate and the remaining first gate dielectric layer.

[0036] The second dielectric layer is formed on the surface of the portion of the first gate that is not in contact with the first gate dielectric layer.

[0037] In one embodiment, the process of removing a portion of the first gate dielectric layer includes:

[0038] The first gate dielectric layer is subjected to a main etching process to remove part of the first gate dielectric layer, so that the first gate dielectric layer after the main etching process is flush with the first gate.

[0039] The first gate dielectric layer is over-etched to further remove the portion of the first gate dielectric layer near the gate trench, so that the remaining first gate dielectric layer covers part of the bottom surface of the first gate and forms the gap between the first gate and the first dielectric layer.

[0040] Both the main etching process and the over-etching process are performed using a wet etching process.

[0041] In one embodiment, the process of removing a portion of the first dielectric layer includes:

[0042] A sacrificial layer is formed within the gate trench, the sacrificial layer filling the gap, covering the second dielectric layer, and exposing a portion of the first dielectric layer near the substrate surface.

[0043] Remove a portion of the first dielectric layer from the side closest to the substrate surface, so that the remaining first dielectric layer is flush with the top of the second dielectric layer;

[0044] Remove the sacrificial layer.

[0045] In one embodiment, when the sacrificial layer is an organic dielectric layer, the sacrificial layer is removed by any one of an ashing process, ozone combustion treatment, and developer immersion treatment.

[0046] In one embodiment, after removing a portion of the first dielectric layer, the method of manufacturing the semiconductor device further includes:

[0047] An epitaxial layer filling the gate trench is formed above the first dielectric layer, the second dielectric layer, the first gate structure, and the gap.

[0048] In one embodiment, after forming the epitaxial layer, the method of manufacturing the semiconductor device further includes:

[0049] A second gate structure is formed on a substrate, the substrate including at least the epitaxial layer and the substrate; a source region and a drain region are formed in the substrate on both sides of the second gate structure, respectively;

[0050] A metal silicide layer is formed on top of the source region, the drain region, and the second gate structure;

[0051] An interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covering the second gate structure and the metal silicide layer;

[0052] An electrical connector is formed within the interlayer dielectric layer, the electrical connector penetrating the interlayer dielectric layer and respectively connecting the metal silicide layer at the top of the source region, the drain region, and the second gate.

[0053] The unexpected effect of this application is that by setting the first gate structure in the substrate, the leakage current of the substrate is reduced, and the threshold voltage of the semiconductor device is highly controlled; by setting gaps in the substrate on both sides of the first gate structure, the dielectric constant and substrate capacitance of the substrate are effectively reduced, and the isolation between the first gate structure and the substrate is improved, thereby further reducing the leakage current of the substrate. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in one embodiment of this application.

[0056] Figure 2 This is a schematic diagram of the structure of the substrate in a semiconductor device provided in one embodiment of this application.

[0057] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application.

[0058] Figure 4 This is a schematic diagram of the structure corresponding to the step of providing a substrate in the manufacturing method of a semiconductor device according to one embodiment of this application.

[0059] Figure 5 This is a schematic diagram of the structure corresponding to the step of forming a gate trench in the substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0060] Figure 6 This is a schematic diagram of the structure corresponding to the step of forming a first dielectric layer in the gate trench in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0061] Figure 7 This is a schematic diagram of the structure corresponding to the step of forming a first gate dielectric layer on a first dielectric layer in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0062] Figure 8This is a schematic diagram of the structure corresponding to the step of filling the gate trench with gate material in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0063] Figure 9 This is a schematic diagram of the structure corresponding to the step of forming a first gate in a gate trench in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0064] Figure 10 This is a schematic diagram of the structure corresponding to the main etching step of the first gate dielectric layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0065] Figure 11 This is a schematic diagram of the structure corresponding to the step of etching the first gate dielectric layer and forming the first gate structure in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0066] Figure 12 This is a schematic diagram of the structure corresponding to the step of forming the second dielectric layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0067] Figure 13 This is a schematic diagram of the structure corresponding to the step of forming a sacrificial layer in the gate trench in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0068] Figure 14 This is a schematic diagram of the structure corresponding to the step of thinning the sacrificial layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0069] Figure 15 This is a schematic diagram of the structure corresponding to the step of removing the portion of the first dielectric layer near the substrate surface in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0070] Figure 16 This is a schematic diagram of the structure corresponding to the step of removing the sacrificial layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0071] Figure 17 This is a schematic diagram of the structure corresponding to the step of forming an epitaxial layer in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0072] Figure 18 This is a schematic diagram of the structure corresponding to the step of removing the first hard mask layer and the second hard mask layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0073] Figure 19This is a schematic diagram of the structure corresponding to the step of forming a well region in the substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0074] Figure 20 This is a schematic diagram of the structure corresponding to the step of forming a shallow trench isolation structure in the substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0075] Figure 21 This is a schematic diagram of the structure corresponding to the step of forming a P-well in the substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0076] Figure 22 This is a schematic diagram of the structure corresponding to the step of forming a second gate dielectric layer on a substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0077] Figure 23 This is a schematic diagram of the structure corresponding to the step of forming a second gate and a first sidewall on a second gate dielectric layer in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0078] Figure 24 This is a schematic diagram of the structure corresponding to the step of forming a lightly doped region in the P-well in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0079] Figure 25 This is a schematic diagram of the structure corresponding to the step of forming a second sidewall, a source region, a drain region, and a metal silicide layer in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0080] Figure 26 This is a schematic diagram of the structure corresponding to the step of forming an interlayer dielectric layer and an electrical connector in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0081] The reference numerals in the figures include: 100-substrate; 100a-first hard mask layer; 100b-second hard mask layer; 100c-first photoresist layer; 100d-sacrificial layer; 100e-protective layer; 100f-third hard mask layer; 100g-third photoresist layer; 101-gate trench; 102-first dielectric layer; 103-second dielectric layer; 104-epitaxy layer; 110-first gate structure; 111-first gate dielectric layer; 112-first gate; 120-well region; 121-P-well; 12 2-N well; 130-shallow trench isolation structure; 131-isolation trench; 132-isolation layer; 140-second gate structure; 141-second gate dielectric layer; 142-second gate; 143-gate sidewall; 143a-first sidewall; 143b-second sidewall; 150-lightly doped region; 150a-fifth photoresist layer; 151-source region; 152-drain region; 160-metal silicide layer; 170-interlayer dielectric layer; 180-electrical connector; 181-metal layer; A-void; B-substrate. Detailed Implementation

[0082] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be more thorough and complete.

[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0084] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0085] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0086] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0087] Typical gate structures are semiconductor structures composed of a high-k dielectric material layer and a metal gate (MG) (i.e., HKMG structure). When the gate oxide capacitance Cox of the HKMG structure is large enough, the subthreshold leakage current at the channel surface and the drain-induced barrier low (DIBL) leakage current should not be a problem. At this time, the main leakage current in the semiconductor device comes from the PN junction and the well region, which are far away from the channel surface.

[0088] With the rapid development of integrated circuits, 28nm and below process technologies have gradually given rise to the Fully Depleted Silicon-On-Insulator (FD-SOI) process. This process involves fabricating a buried oxide (BOX) layer, allowing the PN junction to remain on the buried oxide layer, thus solving the body leakage problem. As the size of FD-SOI devices is further reduced, for example to ultra-thin-body (UTB) FD-SOI devices, the size of the PN junction and the gate linewidth of the metal gate (MG) are also reduced accordingly.

[0089] However, as the length of the metal gate decreases, the random roughness of the gate linewidth increases accordingly, leading to uncontrollable gate linewidth uniformity. Simultaneously, the presence of the thin-body region easily causes random dopant flux (RDF) of doped atoms. For example, when the channel length is too small, electrons between the source and drain may randomly enter the channel, causing changes in the channel concentration and thus making the threshold voltage Vt of the semiconductor device uncontrollable.

[0090] Therefore, it is necessary to provide a semiconductor device and its manufacturing method to achieve precise control of the current and voltage of the semiconductor device and reduce leakage current.

[0091] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in one embodiment of this application. See also... Figure 1One embodiment of this application provides a semiconductor device including a substrate 100, a first dielectric layer 102, a first gate structure 110, and a second dielectric layer 103; wherein, a gate trench 101 is formed in the substrate 100, the first dielectric layer 102 covers the bottom of the gate trench 101 and the side of the sidewall near the bottom of the gate trench 101; the first gate structure 110 is located at the bottom of the gate trench 101, and the first gate structure 110 is in contact with a portion of the first dielectric layer 102 located at the bottom of the gate trench 101; the second dielectric layer 103 covers the top surface and part of the sidewall of the first gate structure 110, and exposes part of the sidewall of the first gate structure 110 near the bottom of the gate trench 101; wherein, a gap A is provided between the first dielectric layer 102 and the second dielectric layer 103, and the gap A is provided on both sides of the first gate structure 110.

[0092] As described above, the semiconductor device reduces the leakage current of the substrate by setting a first gate structure in the substrate, thereby achieving high control over the threshold voltage of the semiconductor device. By setting gaps in the substrate on both sides of the first gate structure, the dielectric constant and substrate capacitance of the substrate are effectively reduced, and the isolation between the first gate structure and the substrate is improved, thereby further reducing the leakage current of the substrate.

[0093] Continue reading Figure 1 In one embodiment, the first gate structure 110 includes a first gate dielectric layer 111 located on the first dielectric layer 102 and a first gate 112 located on the first gate dielectric layer 111, wherein the top surface, sidewalls, and bottom surface of the first gate 112 located on both sides of the first gate dielectric layer 111 are all covered by a second dielectric layer 103. Optionally, the substrate 100 is made of silicon; the first dielectric layer 102 and the second dielectric layer 103 are both made of silicon oxide. Optionally, the first gate dielectric layer 111 is made of silicon nitride, and the first gate 112 is made of polysilicon.

[0094] Figure 2 This is a schematic diagram of the substrate structure in a semiconductor device according to one embodiment of this application. See also... Figure 2 In one embodiment, the semiconductor device further includes a substrate B, which includes a substrate 100, a first dielectric layer 102, a second dielectric layer 103, a first gate structure 110, a gap A, and an epitaxial layer 104. The epitaxial layer 104 is located above the first dielectric layer 102, the second dielectric layer 103, the first gate structure 110, and the gap A, and fills the gate trench 101. Optionally, the material of the epitaxial layer 104 is the same as the material of the substrate 100; for example, both the epitaxial layer 104 and the substrate 100 are made of silicon.

[0095] Continue reading Figure 1 and Figure 2The semiconductor device further includes a second gate structure 140 located on the substrate B, and the orthographic projection of the second gate structure 140 toward the substrate B at least partially coincides with the orthographic projection of the first gate structure 110 toward the substrate B. Optionally, the orthographic projection of the first gate structure 110 toward the substrate B completely falls within the orthographic projection of the second gate structure 140 toward the substrate B.

[0096] See Figure 1 In one embodiment, the second gate structure 140 includes a second gate dielectric layer 141, a second gate 142, and a gate sidewall 143, wherein the second gate dielectric layer 141 is located on the substrate B; the second gate 142 is located on the second gate dielectric layer 141; and the gate sidewall 143 covers the sidewall of the second gate 142. Optionally, the material of the second gate dielectric layer 141 includes silicon oxide; the material of the second gate 142 includes polysilicon; and the material of the gate sidewall 143 includes at least one of silicon oxide and silicon nitride. Optionally, the gate sidewall 143 includes a first sidewall 143a and a second sidewall 143b, wherein the first sidewall 143a covers the sidewall of the second gate 142, and the second sidewall 143b covers the sidewall of the first sidewall 143a away from the second gate 142. Optionally, both the first sidewall 143a and the second sidewall 143b include at least one silicon oxide layer and a silicon nitride layer. For example, the first sidewall 143a and the second sidewall 143b are both stacked structures made of silicon oxide and silicon nitride layers.

[0097] Continue reading Figure 1 and Figure 2 In one embodiment, the semiconductor device further includes a well region 120, which is located within the epitaxial layer 104 above the first gate structure 110 and the substrate 100 on both sides of the epitaxial layer 104. The well region 120 includes alternately arranged P-wells 121 and N-wells 122, and a shallow trench isolation structure 130 (STI) is provided between adjacent P-wells 121 and N-wells 122. Optionally, the P-wells 121 are located above the first gate structure 110.

[0098] See Figure 1 In one embodiment, the semiconductor device further includes a lightly doped region 150, which is located within the P-wells 121 on both sides of the second gate structure 140. Optionally, a source region 151 and a drain region 152 are disposed within the lightly doped region 150, wherein the source region 151 is located within the lightly doped region 150 on one side of the second gate structure 140, and the drain region 152 is located within the lightly doped region 150 on the side of the second gate structure 140 away from the source region 151.

[0099] Continue reading Figure 1In one embodiment, the semiconductor device further includes a metal silicide layer 160, an interlayer dielectric layer 170, and an electrical connector 180. The metal silicide layer 160 is located on top of the source region 151, the drain region 152, and the second gate structure 140. The interlayer dielectric layer 170 is located on the substrate B and covers the second gate structure 140 and the metal silicide layer 160. The electrical connector 180 penetrates the interlayer dielectric layer 170 and is connected to the metal silicide layer 160 on top of the source region 151, the drain region 152, and the second gate structure 140. Optionally, the metal silicide layer 160 is made of nickel-platinum silicide (NiPtSi2), the interlayer dielectric layer 170 includes at least one of a silicon oxide layer and a silicon nitride layer, and the electrical connector 180 is made of tungsten.

[0100] Figure 3 This application provides a method for manufacturing a semiconductor device according to one embodiment. Accordingly, see [link to relevant documentation]. Figure 3 The method for manufacturing a semiconductor device provided in one embodiment of this application can be used to manufacture, for example, a semiconductor device. Figure 1 or Figure 2 The semiconductor device, the method for manufacturing the semiconductor device includes the following steps S01 to S04.

[0101] Step S01: Provide a substrate in which a gate trench is formed, and form a first dielectric layer on the sidewalls and bottom of the gate trench.

[0102] Step S02: A first gate structure is formed on the first dielectric layer, and the first gate structure is formed at the bottom of the gate trench.

[0103] It should be noted that the first gate structure is formed at the bottom of the gate trench. This indicates the specific location of the first gate structure and emphasizes that the first gate structure does not fill the gate trench but is located at the bottom of the gate trench so that an epitaxial layer can be formed on top of the first gate structure in subsequent process steps, so that the first gate structure is buried in the substrate, thereby helping to reduce leakage current in the substrate.

[0104] Step S03: A second dielectric layer is formed on the top surface and a portion of the sidewalls of the first gate structure, and the second dielectric layer exposes a portion of the sidewalls of the first gate structure near the bottom of the gate trench.

[0105] It should be noted that the second dielectric layer mainly covers the surface of the first gate exposed in the first gate structure to ensure good isolation of the first gate and ensure the normal operation of the semiconductor device.

[0106] Step S04: Remove a portion of the first dielectric layer, making the remaining first dielectric layer flush with the surface of the second dielectric layer, and forming a gap between the first dielectric layer and the second dielectric layer, the gap being formed on both sides of the first gate structure.

[0107] The semiconductor device manufacturing method described above reduces the leakage current of the substrate by forming a first gate structure in the substrate, thereby achieving high control over the threshold voltage of the semiconductor device. By forming gaps in the substrate on both sides of the first gate structure, the dielectric constant and substrate capacitance of the substrate are effectively reduced, and the isolation between the first gate structure and the substrate is improved, thereby further reducing the leakage current of the substrate.

[0108] Figures 4 to 26 This is a schematic diagram showing the structure of each step in the manufacturing method of a semiconductor device according to one embodiment of this application. The following is in conjunction with... Figures 4 to 26 This application provides a detailed description of the specific process of manufacturing the semiconductor device.

[0109] See Figures 4 to 6 In step S01, a substrate 100 is provided, in which a gate trench 101 is formed, and a first dielectric layer 102 is formed on the sidewalls and bottom of the gate trench 101. The specific formation process of the gate trench 101 and the first dielectric layer 102 is as follows.

[0110] First, refer to Figure 4 A substrate 100 is provided, on which a first hard mask layer 100a, a second hard mask layer 100b, and a patterned first photoresist layer 100c are sequentially formed. The patterned first photoresist layer 100c is used to define the location and shape of the gate trench. Optionally, the substrate 100 is made of, for example, silicon, the first hard mask layer 100a is made of silicon oxide, and the second hard mask layer 100b is made of silicon nitride.

[0111] Continue reading Figure 4 In one embodiment, the process of sequentially forming a first hard mask layer 100a, a second hard mask layer 100b, and a patterned first photoresist layer 100c on a substrate 100 includes: firstly, forming the first hard mask layer 100a on the substrate 100 using any one of thermal oxidation, furnace oxidation, or deposition processes; then, forming the second hard mask layer 100b on the first hard mask layer 100a using a deposition process; subsequently, forming the first photoresist layer 100c on the second hard mask layer 100b using a spin coating process, and exposing and developing the first photoresist layer 100c to form the patterned first photoresist layer 100c. Optionally, the first photoresist layer 100c is a negative photoresist layer.

[0112] See Figure 5 Using a first photoresist layer 100c as a mask, a second hard mask layer 100b, a first hard mask layer 100a, and a substrate 100 are sequentially etched to form a gate trench 101 within the substrate 100. In one embodiment, a dry etching process is used to etch the second hard mask layer 100b, the first hard mask layer 100a, and the substrate 100. Optionally, after forming the gate trench 101, an ashing process can be used to remove the first photoresist layer 100c, followed by a wet cleaning process to remove any residual polymer from the dry etching and ashing processes.

[0113] It should be noted that during the etching process of the gate trench 101, the etching depth usually needs to be greater than a set value, and this set value can be the sum of the implantation depth of the first hard mask layer 100a, the second hard mask layer 100b and the subsequent well region formed in the substrate 100, so as to ensure that the semiconductor device formed in the end functions normally.

[0114] See Figure 6 A first dielectric layer 102 is formed on the sidewalls and bottom of the gate trench 101. In one embodiment, the first dielectric layer 102 is formed using an in-situ steam generation (ISSG) process within a furnace tube process or a rapid temperature processing (RTP) process. Optionally, the material of the first dielectric layer 102 includes silicon oxide.

[0115] It should be noted that by forming the first dielectric layer 102, the damage to the substrate 100 caused by the etching process of the gate trench 101 can be repaired, and the first dielectric layer 102 can serve as an isolation layer to isolate the substrate 100 from the subsequently formed first gate, thereby ensuring the normal operation of the semiconductor device.

[0116] See Figures 7 to 11 Step S02 is executed to form a first gate structure 110 on the first dielectric layer 102, and the first gate structure 110 is formed at the bottom of the gate trench 101. The specific formation process of the first gate structure 110 is as follows.

[0117] First, refer to Figure 7 A first gate dielectric layer 111 is formed on the first dielectric layer 102. In one embodiment, the first gate dielectric layer 111 is formed using a chemical vapor deposition (CVD) process. Optionally, the material of the first gate dielectric layer 111 includes silicon nitride.

[0118] Next, refer to Figure 8A gate material is deposited within the gate trench 101, and the gate material is planarized to ensure that it precisely fills the gate trench 101. In one embodiment, a furnace tube process is used to deposit the gate material within the gate trench 101, and a chemical mechanical polishing (CMP) process is used to planarize the gate material. Optionally, end-point detection (EDP) technology can be used to determine the stopping point of the planarization process to ensure that the planarized gate material precisely fills the gate trench 101, and that the surface of the gate material is flush with the surface of the second hard mask layer 100b at this point. Optionally, the gate material includes polysilicon.

[0119] Then refer to Figure 9 A portion of the gate material is removed to form a first gate 112 located at the bottom of the gate trench 101. Optionally, a dry etching process is used to remove a portion of the gate material. Optionally, the thickness of the first gate 112 ranges from 500 Å to 800 Å.

[0120] Next, refer to Figure 10 and Figure 11 A portion of the first gate dielectric layer 111 is removed, so that the remaining first gate dielectric layer 111 contacts a portion of the bottom surface of the first gate 112. The first gate structure 110 includes the first gate 112 and the remaining first gate dielectric layer 111.

[0121] In one embodiment, the process of removing a portion of the first gate dielectric layer 111 includes: (Refer to...) Figure 10 The first gate dielectric layer 111 is subjected to a main etching process to remove a portion of the first gate dielectric layer 111 (i.e., remove the portion of the first gate dielectric layer 111 that is higher than the first gate 112), so that the first gate dielectric layer 111 after the main etching process is flush with the first gate 112; then, refer to Figure 11 The first gate dielectric layer 111 is over-etched to further remove the portion of the first gate dielectric layer 111 near the gate trench 101, so that the remaining first gate dielectric layer 111 covers a portion of the bottom surface of the first gate 112, forming a gap A between the first gate 112 and the first dielectric layer 102. Optionally, both the main etching process and the over-etching process of the first gate dielectric layer 111 are performed using a wet etching process, and the etchant used in the wet etching process includes a phosphoric acid solution.

[0122] It should be noted that by forming the first gate 112 and the first gate dielectric layer 111, a first gate structure 110 (the first gate structure 110 includes the first gate dielectric layer 111 and the first gate 112) is formed within the substrate 100. At the same time, by removing part of the first gate dielectric layer 111, gaps A are formed on both sides of the first gate structure 110, which effectively reduces the dielectric constant and substrate capacitance of the substrate and improves the isolation between the first gate structure 110 and the substrate 100.

[0123] Then refer to Figure 12 In step S03, a second dielectric layer 103 is formed on the top surface and part of the sidewalls of the first gate structure 110, and the second dielectric layer 103 exposes part of the sidewalls of the first gate structure 110 near the bottom of the gate trench 101.

[0124] It should be noted that the second dielectric layer 103 is formed on the exposed surface of the first gate 112 in the first gate structure 110 (i.e., the second dielectric layer 103 is formed on the surface of the first gate 112 that is not in contact with the first gate dielectric layer 111), to ensure good isolation of the first gate 112, thereby ensuring the normal operation of the semiconductor device. In one embodiment, the second dielectric layer 103 can be formed using a rapid temperature processing (RTP) process. Optionally, the material of the second dielectric layer 103 includes silicon oxide. It should be emphasized that using a rapid temperature processing method to form the second dielectric layer 103 can also repair the damage caused to the first gate 112 by the dry etching process, thereby helping to improve the performance of the finally formed semiconductor device.

[0125] Next, refer to Figures 13 to 16 In step S04, a portion of the first dielectric layer 102 is removed, making the remaining first dielectric layer 102 flush with the surface of the second dielectric layer 103, and a gap A is formed between the first dielectric layer 102 and the second dielectric layer 103, with the gap A located on both sides of the first gate structure 110. The process of removing a portion of the first dielectric layer 102 is as follows.

[0126] First, refer to Figure 13 A sacrificial layer 100d is formed within the gate trench 101, filling the void A and the gate trench 101. In one embodiment, the sacrificial layer 100d is an organic dielectric layer (ODL). Optionally, a spin-coating process is used to fill the gate trench 101 with a sacrificial material (e.g., an organic dielectric material), and the sacrificial material is planarized to form a sacrificial layer 100d that exactly fills the gate trench 101.

[0127] Next, refer to Figure 14 A portion of the sacrificial layer 100d is removed, leaving the remaining sacrificial layer 100d covering the second dielectric layer 103 while exposing a portion of the first dielectric layer 102 near the surface of the substrate 100. Optionally, a dry etching process or a wet etching process is used to remove the portion of the sacrificial layer 100d.

[0128] Then refer to Figure 15 The portion of the first dielectric layer 102 closest to the surface of the substrate 100 is removed, leaving the remaining first dielectric layer 102 flush with the top of the second dielectric layer 103. In one embodiment, a wet etching process is used to remove a portion of the first dielectric layer 102. Optionally, the etchant used in the wet etching process includes a DHF solution.

[0129] Next, refer to Figure 16 The sacrificial layer 100d is removed. In one embodiment, when the sacrificial layer 100d is an organic dielectric layer, it is removed by any one of the following methods: ashing, ozone combustion, and developer immersion. It should be noted that after removing the sacrificial layer 100d, a gap A is formed again on both sides of the first gate structure 110, and the gap A is located between the first dielectric layer 102 and the second dielectric layer 103.

[0130] See Figure 17 After removing a portion of the first dielectric layer 102, the semiconductor device manufacturing method further includes forming an epitaxial layer 104 that fills the gate trench 101 over the first dielectric layer 102, the second dielectric layer 103, the first gate structure 110, and the gap A. In one embodiment, the epitaxial layer 104 can be formed by laterally epitaxially processing the substrate 100 exposed above the first dielectric layer 102 using a single-crystal silicon epitaxial process.

[0131] See Figure 18 After forming the epitaxial layer 104, the semiconductor device manufacturing method further includes: removing the first hard mask layer 100a and the second hard mask layer 100b to form a substrate B, wherein the substrate B includes a substrate 100, a first dielectric layer 102, a second dielectric layer 103, an epitaxial layer 104, a first gate structure 110, and a void A. In one embodiment, a wet etching process can be used to remove the first hard mask layer 100a and the second hard mask layer 100b. Optionally, if the first hard mask layer 100a is a silicon oxide layer and the second hard mask layer 100b is a silicon nitride layer, the second hard mask layer 100b can be removed first using phosphoric acid, and then the first hard mask layer 100a can be removed using a DHF solution.

[0132] Continue reading Figure 18It should be emphasized that by forming a substrate B including a first gate structure 110 and a gap A, the dielectric constant and substrate capacitance of the substrate 100 can be effectively reduced, and the isolation between the first gate 112 and the substrate 100 can be improved, thereby greatly reducing the leakage current of the substrate 100.

[0133] Furthermore, one embodiment of this application provides a semiconductor device including a dual-gate MOS structure formed on substrate B (see [reference]). Figure 1 (The following is combined with...) Figures 18 to 26 This document details the specific process of forming a dual-gate MOS structure based on substrate B.

[0134] First, refer to Figure 19 A protective layer 100e is formed on the surface of substrate B, and an ion implantation process is performed on substrate B to form a well region 120 within epitaxial layer 104 and the substrate 100 on both sides of epitaxial layer 104. In one embodiment, a furnace tube process is used to form the protective layer 100e, and the protective layer 100e is a silicon oxide layer to prevent damage to the surface of substrate B during the ion implantation process of well region 120. Optionally, the thickness of the protective layer 100e is, for example, 55 Å. Optionally, the well region 120 is a deep N-well (DNW).

[0135] Next, refer to Figure 20 A shallow trench isolation structure 130 (STI) is formed that penetrates the protective layer 100e and extends into the substrate B, and the shallow trench isolation structure 130 extends into the substrate 100 below the well region 120.

[0136] In one embodiment, the process of forming the shallow trench isolation structure 130 includes: forming a third hard mask layer 100f and a second photoresist layer (not shown) on the protective layer 100e, and patterning the second photoresist layer; then, etching the third hard mask layer 100f, the protective layer 100e and the substrate B using the patterned second photoresist layer as a mask to form an isolation trench 131; subsequently, removing the patterned second photoresist layer; and filling the isolation trench 131 with an isolation layer 132 to form a shallow trench isolation structure 130 including the isolation trench 131 and the isolation layer 132.

[0137] In one embodiment, the third hard mask layer 100f is made of silicon nitride; the second photoresist layer can be removed by a wet etching process, and the polymer remaining during the etching of the isolation trench 131 can be removed by a wet cleaning process. Optionally, the wet cleaning process for the second photoresist layer and the wet cleaning process for the polymer remaining after etching the isolation trench 131 can be combined into a single process step to save costs and improve production efficiency.

[0138] In one embodiment, a deposition process can be used to fill the isolation trench 131 with isolation material. After the deposition process is completed, an annealing process can be performed at a certain temperature to make the deposited isolation material more dense. Subsequently, the isolation material is planarized to form an isolation layer 132 that exactly fills the isolation trench 131. Optionally, the isolation material used for the isolation layer 132 includes an oxide material, for example, tetraethyl orthosilicate (TEOS). Optionally, a chemical mechanical polishing process is used to planarize the isolation material, and an endpoint detection method is used to control the timing of the planarization process to make the surface of the isolation layer 132 flush with the surface of the third hard mask layer 100f.

[0139] Continue reading Figure 20 In one embodiment, after removing the second photoresist layer and before filling the isolation layer 132 into the isolation trench 131, a rapid thermal treatment can be used to perform an oxidation repair treatment on the inner wall of the isolation trench 131 to form a thin oxide layer (not shown in the figure) on the inner wall of the isolation trench 131, thereby repairing the etching damage to the substrate B caused during the etching process of the isolation trench 131.

[0140] See Figure 21 After forming the shallow trench isolation structure 130, the portion of the third hard mask layer 100f and the portion of the isolation layer 132 above the protective layer 100e is removed. Next, a patterned third photoresist layer 100g is formed on the protective layer 100e and the shallow trench isolation structure 130. Using the third photoresist layer 100g as a mask, an ion implantation process is performed on the substrate B to form a P-well 121 within the well region 120. It should be noted that while forming the P-well 121, the portion of the well region 120 located below the third photoresist layer 100g is the N-well 122, and the P-well 121 and the N-well 122 are separated by the shallow trench isolation structure 130 to ensure the normal operation of the semiconductor device.

[0141] In one embodiment, a wet etching process is used to remove the portion of the third hard mask layer 100f and the isolation layer 132 above the protective layer 100e. Optionally, the etchant used in the wet etching process of the third hard mask layer 100f and the isolation layer 132 includes phosphoric acid and DHF solution.

[0142] In one embodiment, the ions implanted in the ion implantation process of P-trap 121 include boron ions (B) and boron difluoride ions (BF2). It should be noted that, because boron ions are relatively light, ion implantation can be performed in four steps, with each implantation reaching a different depth, to form P-trap 121.

[0143] Then refer to Figure 22 After forming P-well 121 and N-well 122, the third photoresist layer 100g and the protective layer 100e are removed, and a second gate dielectric layer 141 is formed on the substrate B. In one embodiment, the third photoresist layer 100g is removed by an ashing process, and the protective layer 100e is removed by a wet etching process to expose the surface of the substrate B.

[0144] In one embodiment, a second gate dielectric layer 141 is formed on the surface of substrate B using a furnace tube process or an in-situ steam generation (ISSG) process. When the semiconductor device is a low-voltage device, the thickness of the second gate dielectric layer 141 ranges from 15 Å to 30 Å. In other embodiments of this application, the specific thickness of the second gate dielectric layer 141 can be adjusted according to the type of semiconductor device and actual process requirements, and this application does not impose any limitations on this.

[0145] Next, refer to Figure 23 A second gate 142 is formed on the second gate dielectric layer 141; a first sidewall 143a is formed on the sidewall of the second gate 142; and the portion of the second gate dielectric layer 141 not covered by the second gate 142 and the first sidewall 143a is removed.

[0146] In one embodiment, the process of forming a second gate 142 on the second gate dielectric layer 141 includes: forming a second gate material layer (not shown) on the second gate dielectric layer 141, and sequentially forming a fourth hard mask layer (not shown), an anti-reflection layer (not shown), and a patterned fourth photoresist layer (not shown) on the second gate material layer; etching the anti-reflection layer, the fourth hard mask layer, and the second gate material layer using the fourth photoresist layer as a mask to form the second gate 142; and removing the fourth photoresist layer, the anti-reflection layer, and at most a portion of the fourth hard mask layer. Optionally, the material of the second gate material layer includes polysilicon; the fourth hard mask layer includes a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a stacked structure composed of any combination thereof.

[0147] In one embodiment, after forming the second gate 142 and removing up to a portion of the fourth hard mask layer, the remaining fourth hard mask layer on the second gate 142 is a silicon oxide layer. Optionally, a wet etching process is used to remove a portion of the fourth hard mask layer, wherein the removed portion of the fourth hard mask layer includes silicon nitride, and the etchant of the fourth hard mask layer includes phosphoric acid.

[0148] In one embodiment, after the second gate 142 is formed, a silicon oxide layer (not shown in the figure) is formed on the sidewall of the second gate 142 by rapid thermal processing to repair the etching damage to the sidewall of the second gate 142 caused during the etching of the second gate material layer and the formation of the second gate 142. At the same time, the silicon oxide layer formed on the sidewall of the second gate 142 can also serve as part of the subsequently formed first sidewall 143a to ensure the normal operation of the semiconductor device.

[0149] In one embodiment, after forming the second gate 142 and removing up to a portion of the fourth hard mask layer, a first sidewall material layer is formed on the remaining fourth hard mask layer, and the first sidewall material layer covers the sidewall of the second gate 142 and the second gate dielectric layers 141 on both sides of the second gate 142; a dry etching process is used to remove a portion of the first sidewall material layer, the remaining fourth hard mask layer, and the portion of the second gate dielectric layer 141 covered by the first sidewall material layer, to form a first sidewall 143a covering the sidewall of the second gate 142.

[0150] Then refer to Figure 24 A fifth photoresist layer 150a is formed covering a portion of the substrate B, and the fifth photoresist layer 150a exposes the portion of the P-well 121 not covered by the second gate 142 and the first sidewall 143a. Using the fifth photoresist layer 150a as a mask, an ion implantation process is performed to form a lightly doped region 150 in the exposed P-well 121. In one embodiment, at least one of germanium ions (Ge), carbon ions (C), boron ions (B), nitrogen ions (N), phosphorus ions (P), and arsenic ions (As) can be implanted sequentially to a certain depth to form an N-type lightly doped region 150 (LDD).

[0151] Next, refer to Figure 25 After forming the lightly doped region 150, the fifth photoresist layer 150a is removed; a second sidewall 143b is formed on the sidewall of the first sidewall 143a away from the second gate 142 to form a second gate structure 140. The second gate structure 140 includes a second gate dielectric layer 141, a second gate 142, and a gate sidewall 143 (the gate sidewall 143 includes the first sidewall 143a and the second sidewall 143b); then, a source region 151 and a drain region 152 are formed in the lightly doped regions 150 on both sides of the second gate structure 140, respectively; subsequently, a metal silicide layer 160 is formed on the second gate 142, the source region 151, and the drain region 152.

[0152] In one embodiment, the formation process of the second sidewall 143b includes: forming a second sidewall material layer (not shown) on the substrate B, the second gate 142, and the first sidewall 143a, and removing the second sidewall material layer above the second gate 142 and the substrate B to form the second sidewall 143b, wherein the second sidewall 143b covers the sidewall of the first sidewall 143a away from the second gate 142. Optionally, both the first sidewall 143a and the second sidewall 143b include at least one of a silicon oxide layer and a silicon nitride layer. For example, both the first sidewall 143a and the second sidewall 143b are stacked structures composed of a combination of silicon oxide layers and silicon nitride layers.

[0153] In one embodiment, after forming the second gate structure 140, ion implantation can be performed on the lightly doped regions 150 on both sides of the second gate structure 140 to form the source region 151 and the drain region 152, respectively. Optionally, at least one of germanium ions (Ge), phosphorus ions (P), arsenic ions (As), and fluorine ions (F) can be implanted sequentially to a certain depth to form the source region 151 and the drain region 152.

[0154] In one embodiment, after forming the source region 151 and drain region 152, a spike annealing process can be performed to fix the implanted ions in the source region 151 and drain region 152 within a certain area. Optionally, the process temperature of the spike annealing process can be 1050°C. In other embodiments of this application, the specific process temperature of the spike annealing process can be adjusted according to actual needs, and this application does not impose any limitations on it.

[0155] Continue reading Figure 25 In one embodiment, the process of forming a metal silicide layer 160 on the second gate 142, source region 151, and drain region 152 includes: forming a mask layer (not shown) on the substrate B and the second gate structure 140, such that the mask layer exposes the second gate 142, source region 151, and drain region 152 and covers other portions of the substrate B and the second gate structure 140; and employing a silicon cobalt nickel pre-cleaning process (SiCoNi). Pre-cleaning removes the native oxide; then, a platinum nickel oxide layer (NiPt, not shown in the figure) is deposited, and a titanium nitride layer (TiN, not shown in the figure) is formed on the platinum nickel oxide layer; next, a first rapid thermal treatment is performed to form a high-resistivity metal silicide (e.g., Ni2PtSi) at the junction of the platinum nickel oxide layer and the second gate 142, source region 151 and drain region 152; then, a second rapid thermal treatment is performed to form a low-resistivity metal silicide (e.g., NiPtSi2); then, the portion of the platinum nickel oxide layer that has not been converted into a metal silicide layer is removed to form a metal silicide layer 160.

[0156] In one embodiment, the thickness of the platinum nickelate layer is, for example, 120 Å, and the thickness of the titanium nitride layer is, for example, 50 Å. Optionally, the first rapid thermal treatment process temperature is 290°C, and the process time is 30 s. In other embodiments of this application, the process method, process parameters, and the materials and thickness ranges of each film layer used in the formation of the metal silicide layer 160 can be adjusted according to actual needs, and this application does not impose any limitations on them.

[0157] See Figure 26 After forming the metal silicide layer 160, an interlayer dielectric layer 170 is formed on the substrate B, the metal silicide layer 160, and the second gate structure 140, and an electrical connection 180 is formed penetrating the interlayer dielectric layer 170 and connected to the metal silicide layer 160. In one embodiment, the interlayer dielectric layer comprises a stacked structure of a silicon nitride layer (not shown) and multiple oxide layers (not shown), and the oxide layer material comprises tetraethyl orthosilicate (TEOS). Optionally, the thickness of the silicon nitride layer in the interlayer dielectric layer 170 is, for example, 300 Å, and the total thickness of the multiple oxide layers is 2700 Å.

[0158] In one embodiment, the formation process of the electrical connector 180 includes: forming a patterned sixth photoresist layer (not shown) on the interlayer dielectric layer 170; etching the interlayer dielectric layer 170 using the patterned sixth photoresist layer as a mask to form a contact hole (CT, not labeled in the figure) penetrating the interlayer dielectric layer 170, wherein the contact hole exposes a portion of the surface of the metal silicide layer 160 above the second gate 142, source region 151, and drain region 152; then, removing residual polymer in the contact hole using a wet cleaning process; subsequently, forming the electrical connector 180 within the contact hole. Optionally, the material of the electrical connector 180 includes tungsten (W).

[0159] In one embodiment, after forming the contact hole and before forming the electrical connector 180 within the contact hole, a metal layer 181 may be formed on the inner wall and bottom of the contact hole to improve the connection performance between the electrical connector 180 and the metal silicide layer 160. Optionally, the metal layer 181 is a stacked structure composed of a titanium (Ti) layer and a titanium nitride (TiN) layer, wherein the thickness of the titanium layer is 100 Å and the thickness of the titanium nitride layer is 50 Å. In other embodiments of this application, other materials may be used to prepare the metal layer 181 and the electrical connector 180, and the specific structure and parameters of the metal layer 181 may be adjusted according to actual needs, which is not limited in this application.

[0160] Continue reading Figure 26One embodiment of this application provides a method for manufacturing a semiconductor device, which reduces the leakage current of the substrate 100 by forming a first gate structure 110 in the substrate 100, thereby achieving high control over the threshold voltage of the semiconductor device; by providing gaps A in the substrate 100 on both sides of the first gate structure 110, the dielectric constant and substrate capacitance of the substrate 100 are effectively reduced, and the isolation between the first gate structure 110 and the substrate 100 is improved, thereby further reducing the leakage current of the substrate 100.

[0161] Furthermore, by forming a second gate structure 140 on the substrate, a dual-gate MOS structure is formed, enabling precise control of the current and voltage of the semiconductor device, improving the performance of the semiconductor device, reducing noise, and extending the bandwidth. Moreover, compared with conventional semiconductor devices, the dual-gate MOS structure fabricated by the semiconductor device manufacturing method provided in this application is more suitable for application in radio frequency and microwave circuits.

[0162] The unexpected effect of this application is that by setting the first gate structure in the substrate, the leakage current of the substrate is reduced, and the threshold voltage of the semiconductor device is highly controlled; by setting gaps in the substrate on both sides of the first gate structure, the dielectric constant and substrate capacitance of the substrate are effectively reduced, and the isolation between the first gate structure and the substrate is improved, thereby further reducing the leakage current of the substrate.

[0163] Furthermore, the semiconductor device includes a first gate structure disposed within a substrate and a second gate structure disposed on the substrate, enabling precise control of the current and voltage of the semiconductor device, improving the performance of the semiconductor device, reducing noise, and extending the bandwidth.

[0164] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0165] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0166] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided in which a gate trench is formed, and a first dielectric layer is formed on the sidewalls and bottom of the gate trench; A first gate structure is formed on the first dielectric layer, and the first gate structure is formed at the bottom of the gate trench; A second dielectric layer is formed on the top surface and part of the sidewalls of the first gate structure, and the second dielectric layer exposes part of the sidewalls of the first gate structure near the bottom of the gate trench. A gap is formed between the first dielectric layer and the second dielectric layer, and the gap is located on both sides of the first gate structure. Remove a portion of the first dielectric layer so that the remaining first dielectric layer is flush with the surface of the second dielectric layer; The process of removing a portion of the first dielectric layer includes: A sacrificial layer is formed within the gate trench, the sacrificial layer filling the gap, covering the second dielectric layer, and exposing a portion of the first dielectric layer near the substrate surface. Remove a portion of the first dielectric layer from the side closest to the substrate surface, so that the remaining first dielectric layer is flush with the top of the second dielectric layer; Remove the sacrificial layer.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The formation process of the first gate structure includes: A first gate dielectric layer is formed on the first dielectric layer; A first gate is formed on the first gate dielectric layer, and the first gate is formed at the bottom of the gate trench; A portion of the first gate dielectric layer is removed, so that the remaining first gate dielectric layer contacts a portion of the bottom surface of the first gate. The first gate structure includes the first gate and the remaining first gate dielectric layer. The second dielectric layer is formed on the surface of the portion of the first gate that is not in contact with the first gate dielectric layer.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The process of removing part of the first gate dielectric layer includes: The first gate dielectric layer is subjected to a main etching process to remove part of the first gate dielectric layer, so that the first gate dielectric layer after the main etching process is flush with the first gate. The first gate dielectric layer is over-etched to further remove the portion of the first gate dielectric layer near the gate trench, so that the remaining first gate dielectric layer covers part of the bottom surface of the first gate and forms a gap between the first gate and the first dielectric layer. Both the main etching process and the over-etching process are performed using a wet etching process.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, When the sacrificial layer is an organic dielectric layer, the sacrificial layer is removed by any one of the following methods: ashing process, ozone combustion treatment, and developer immersion treatment.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After removing a portion of the first dielectric layer, the method for manufacturing the semiconductor device further includes: An epitaxial layer filling the gate trench is formed above the first dielectric layer, the second dielectric layer, the first gate structure, and the gap.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, After forming the epitaxial layer, the method for manufacturing the semiconductor device further includes: A second gate structure is formed on a substrate, wherein the substrate includes at least the epitaxial layer and the substrate; A source region and a drain region are formed in the substrate on both sides of the second gate structure, respectively; A metal silicide layer is formed on top of the source region, the drain region, and the second gate structure; An interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covering the second gate structure and the metal silicide layer; An electrical connector is formed within the interlayer dielectric layer, the electrical connector penetrating the interlayer dielectric layer and respectively connecting the metal silicide layer at the top of the source region, the drain region, and the second gate.

7. A semiconductor device, manufactured using the semiconductor device manufacturing method according to any one of claims 1 to 6, characterized in that, include: A substrate in which gate trenches are formed; A first dielectric layer covers the bottom of the gate trench and the sidewall of the gate trench near the bottom of the gate trench. A first gate structure is located at the bottom of the gate trench, and the first gate structure is in contact with the portion of the first dielectric layer located at the bottom of the gate trench. The second dielectric layer covers the top surface and part of the sidewalls of the first gate structure, and exposes part of the sidewalls of the first gate structure near the bottom of the gate trench. Wherein, a gap is provided between the first dielectric layer and the second dielectric layer, and the gap is provided on both sides of the first gate structure.

8. The semiconductor device according to claim 7, characterized in that, The first gate structure includes: A first gate dielectric layer is located on the first dielectric layer; A first gate is located on the first gate dielectric layer, and the portions of the top surface, sidewalls, and bottom surface of the first gate located on both sides of the first gate dielectric layer are all covered by the second dielectric layer.

9. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes: The substrate includes the substrate, the first dielectric layer, the second dielectric layer, the first gate structure, the void, and the epitaxial layer, wherein the epitaxial layer is located above the first dielectric layer, the second dielectric layer, the first gate structure, and the void and fills the gate trench; A second gate structure is located on the substrate, and the orthographic projection of the second gate structure toward the substrate at least partially coincides with the orthographic projection of the first gate structure toward the substrate.

10. The semiconductor device according to claim 9, characterized in that, The second gate structure includes: A second gate dielectric layer is located on the substrate; The second gate is located on the second gate dielectric layer; A gate sidewall that covers the sidewall of the second gate.

11. The semiconductor device according to claim 9, characterized in that, The semiconductor device further includes: The source region is located within the substrate on one side of the second gate structure; The drain region is located within the substrate on the side of the second gate structure away from the source region; A metal silicide layer is located on top of the source region, the drain region, and the second gate structure; An interlayer dielectric layer is located on the substrate, and the interlayer dielectric layer covers the second gate structure and the metal silicide layer; An electrical connector extends through the interlayer dielectric layer and is connected to the source region, the drain region, and the metal silicide layer at the top of the second gate structure, respectively.

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