Display device

Abstract

A display device according to the present disclosure may include a substrate, a plurality of driving chips disposed on the substrate, a plurality of light-emitting elements disposed on the driving chips and electrically connected to each of the driving chips, an optical insulating layer covering the plurality of light-emitting elements, a first overcoat layer disposed on the optical insulating layer; and a second overcoat layer disposed on the first overcoat layer, and a refractive index of the first overcoat layer may be lower than a refractive index of the second overcoat layer.

Description

Technical Field

[0001] This disclosure relates to an apparatus, and more specifically, for example, and not limitingly, to a display apparatus. Background Technology

[0002] Display devices are used in a variety of electronic devices such as TVs, mobile phones, laptops, and tablets.

[0003] Display devices can be classified into organic light-emitting display (OLED) devices, which have self-emissive properties, and liquid crystal display (LCD) devices, which require a separate light source.

[0004] Recently, display devices including light-emitting diodes (LEDs) (hereinafter referred to as "light-emitting elements") have attracted attention as the next generation of display devices. Because light-emitting elements are made of inorganic materials rather than organic materials, they can emit light faster than liquid crystal displays or organic light-emitting displays, have excellent luminous efficiency, and display high-brightness images. Summary of the Invention

[0005] Typically, display devices may include a polarizing layer to improve outdoor visibility. Light emitted from a light source within the display device can be emitted to the outside through the polarizing layer. Some light incident on the polarizing layer may be lost due to total internal reflection and not emitted to the outside.

[0006] As the amount of light undergoing total internal reflection in the polarization layer increases, the amount of light lost also increases, and the light extraction efficiency decreases. Therefore, in order to reduce the amount of light lost in the polarization layer, it is necessary to reduce the amount of light undergoing total internal reflection in the polarization layer.

[0007] As an example, one could consider a method to control the angle of incidence of light incident on the polarization layer. Specifically, since total internal reflection occurs for incident light with an angle of incidence greater than the angle of total internal reflection at the polarization layer, one could consider a method to reduce the angle of incidence of light toward the polarization layer to be less than the angle of total internal reflection.

[0008] Therefore, light with a large incident angle can undergo total internal reflection between the polarization layer and the light source before reaching the polarization layer. Light that has already undergone total internal reflection can then be incident on the polarization layer at an angle adjusted to be smaller than the angle of total internal reflection at the polarization layer.

[0009] By reducing the proportion of total internal reflection at the polarization layer in this way, the amount of light emitted to the outside through the polarization layer can be increased, thereby improving the light extraction efficiency.

[0010] For example, by placing a low-refractive-index layer between the light source and the polarizing layer, the angle of incidence of light incident on the polarizing layer can be controlled. However, in the optical process used to form the low-refractive-index layer, curing may not occur properly along the edge portions of the low-refractive-index layer, which can lead to undercuts. Similarly, undercuts can become pathways for moisture penetration or cause problems such as cracks.

[0011] In other words, one could consider setting a low-refractive-index layer on the light source to improve light extraction efficiency; however, setting a low-refractive-index layer may cause another problem, as the undercut portion may appear along the edge portion of the low-refractive-index layer.

[0012] In view of the above, the inventors of this disclosure have invented a display device with improved light extraction efficiency and high resistance to the appearance of undercut portions through a series of experiments.

[0013] The objective of one embodiment of this disclosure is to provide a display device with improved light extraction efficiency and high reliability.

[0014] Another objective of one embodiment of this disclosure is to provide a display device capable of improving light extraction efficiency.

[0015] Another objective of one embodiment of this disclosure is to provide a display device including a novel configuration that can prevent or reduce the causes of undercut portions becoming defects.

[0016] Another objective of the embodiments of this disclosure is to provide a display device that has increased bonding strength between insulating layers provided with different materials.

[0017] In addition to the foregoing, this disclosure may also have other purposes that will be readily apparent to those skilled in the art from the following description.

[0018] A display device according to one embodiment of the present disclosure may include: a substrate; a plurality of driving chips disposed on the substrate; a plurality of light-emitting elements disposed on one of the driving chips and electrically connected to the one driving chip; an optical insulating layer covering the plurality of light-emitting elements; a first outer coating disposed on the optical insulating layer; and a second outer coating disposed on the first outer coating, wherein the refractive index of the first outer coating is lower than the refractive index of the second outer coating.

[0019] A display device according to one embodiment of the present disclosure may include: a substrate; a plurality of driving chips disposed on the substrate; a plurality of light-emitting elements disposed on one of the driving chips and electrically connected to the one driving chip; an optical insulating layer covering the plurality of light-emitting elements; a first outer coating layer located on the optical insulating layer and including an undercut portion formed along an edge portion of the first outer coating layer; and a second outer coating layer filling the undercut portion.

[0020] According to one embodiment of this disclosure, the proportion of light undergoing total internal reflection at the interface between the upper diffusion film and the first outer coating having a low refractive index can be increased. This allows the angle of incidence of light incident on the polarizing layer to be smaller than the angle of total internal reflection, thereby improving light extraction efficiency. The improved light extraction efficiency may lead to the provision of display devices capable of being driven with low power consumption.

[0021] Furthermore, according to one embodiment of this disclosure, a second outer coating having a high refractive index can be disposed in the undercut portion formed on the edge portion of a first outer coating having a low refractive index, thereby preventing or reducing the occurrence of problems with the undercut portion. Therefore, the reliability of the display device can be improved.

[0022] Furthermore, according to one embodiment of this disclosure, a second outer coating having a high refractive index can be configured to surround the edge portion of a first outer coating having a low refractive index, thereby increasing the bonding strength between insulating layers disposed of different materials. Therefore, defects caused by delamination between insulating layers can be prevented or reduced.

[0023] Furthermore, according to one embodiment of this disclosure, a second outer coating having a high refractive index can be disposed on the uppermost portion of the organic layer, thereby preventing or reducing the appearance of undercut portions at the edge portions of the second outer coating. Therefore, the reliability of the display device can be improved.

[0024] Therefore, one embodiment of this disclosure can not only improve the light extraction efficiency in the display area, but also realize a display device with high reliability.

[0025] In addition to the foregoing, this disclosure may also provide other effects that a person skilled in the art may clearly recognize from the claims.

[0026] Other systems, methods, features, and advantages will be apparent to those skilled in the art upon examination of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included within this specification, within the scope of this disclosure, and protected by the appended claims. Nothing in this section should be construed as limiting those claims. Further aspects and advantages are discussed below in conjunction with embodiments of this disclosure.

[0027] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0028] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0029] Figure 1 This is an exploded perspective view of a display device according to one embodiment of the present disclosure.

[0030] Figure 2 This is a plan view of a display device according to one embodiment of the present disclosure.

[0031] Figure 3 This is an enlarged view of a display device according to one embodiment of the present disclosure.

[0032] Figure 4 This is a diagram illustrating a circuit structure according to one embodiment of the present disclosure.

[0033] Figure 5 This is a plan view of a display device according to one embodiment of the present disclosure.

[0034] Figure 6 This is a plan view of a display device according to one embodiment of the present disclosure.

[0035] Figure 7 This is a plan view of a display device according to one embodiment of the present disclosure.

[0036] Figure 8 This is a cross-sectional view of a display device according to one embodiment of the present disclosure.

[0037] Figure 9 This is a cross-sectional view of a display device according to one embodiment of the present disclosure.

[0038] Figures 10 to 13 This is a diagram illustrating an apparatus for applying a display device according to an embodiment of the present disclosure.

[0039] Figure 14 This is a plan view of a display device according to another embodiment of the present disclosure.

[0040] Figure 15 This illustrates a configuration according to another embodiment of the present disclosure. Figure 14 A plan view of one of the regions in a plurality of pixel driving circuits.

[0041] Figure 16 This is a view illustrating touch operation of a display device according to another embodiment of the present disclosure.

[0042] Figure 17 This is a diagram illustrating, by way of example, a signal waveform diagram when driving a display device according to one embodiment of the present disclosure.

[0043] Figure 18 This illustrates another embodiment according to the present disclosure. Figure 15 An enlarged plan view of region 7 in the image.

[0044] Figure 19 It is according to another embodiment of this disclosure along Figure 18 The cross-sectional view taken from line 8-8 in the diagram.

[0045] Figure 20 This illustrates another embodiment according to the present disclosure. Figure 19 A cross-sectional view of region 9 in the diagram.

[0046] Figure 21 This illustrates another embodiment according to the present disclosure. Figure 20 A plan view of the joint portion.

[0047] Figure 22 It is according to another embodiment of this disclosure along Figure 14 The cross-sectional view taken from line 11-11 in the diagram.

[0048] Figure 23 This is an enlarged cross-sectional view of the conical region according to another embodiment of the present disclosure.

[0049] Figure 24 The display device according to another embodiment of this disclosure is along Figure 14 The cross-sectional view taken by cutting line 13-13 in the figure.

[0050] Figure 25 This is a diagram illustrating the mechanism of the appearance of the undercut portion according to another embodiment of this disclosure.

[0051] Figure 26 This is a plan view showing the display panel of a display device according to another embodiment of the present disclosure.

[0052] Figure 27 It is according to another embodiment of this disclosure along Figure 26 The cross-sectional view taken by cutting line 16-16 in the figure.

[0053] Figure 28 It is along Figure 26 The cross-sectional view taken by cutting line 17-17 in the figure.

[0054] Figure 29 This is a plan view showing the display panel of a display device according to another embodiment of the present disclosure.

[0055] Figure 30 It is along Figure 29 The cross-sectional view taken by cutting line 19-19 in the figure.

[0056] Figure 31 It is along Figure 29 The cross-sectional view taken by cutting line 20-20 in the diagram. Detailed Implementation

[0057] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted or may be briefly discussed where it is determined that such detailed descriptions would unnecessarily obscure the essential points of the inventive concept. The described process steps and / or order of operations are exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The same reference numerals always refer to the same elements. The names of the corresponding elements used in the following explanation may be chosen solely for the convenience of writing the specification and may therefore differ from those used in actual products.

[0058] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become apparent when referring to the following detailed description of embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but can be embodied in various different forms. Therefore, these embodiments are only intended to complete this disclosure and to fully inform those skilled in the art to which this disclosure pertains.

[0059] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative sizes and depictions of these elements may be enlarged. The described process steps and / or operation sequence is an example; however, the order of steps and / or operations is not limited to that described herein, and may be modified as is known in the art, except for steps and / or operations that must occur in a specific order. The same reference numerals refer to the same elements throughout the text. The names of the various elements used in the following description are chosen solely for ease of writing and may therefore differ from the names used in actual products.

[0060] The shapes, sizes, ratios, angles, quantities, etc., disclosed in the accompanying drawings to illustrate embodiments of the present disclosure are illustrative, and the present disclosure is not limited thereto. Throughout the detailed description, the same reference numerals refer to the same components. Furthermore, in describing the present disclosure, detailed descriptions of related known technologies will be omitted if it is determined that such detailed descriptions may unnecessarily obscure the gist of the present disclosure. When the terms "comprising," "including," "having," "constituting," etc., are used in this disclosure, the presence or addition of other elements is permissible unless the term "only" is used. When a component is described using a singular form, it may include the meaning of the plural form unless explicitly stated to the contrary.

[0061] Any implementation described in this article as an "example" is not necessarily to be interpreted as preferred or advantageous over other implementations.

[0062] It should be noted that even if there is no explicit description, any component will be interpreted as including tolerances or error ranges.

[0063] When describing the positional relationship between two elements, for example, when using "above", "over", "below", "below" and "adjacent", one or more other elements may be inserted between the two elements unless the terms "exactly", "directly" or "close" are used.

[0064] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may also be included unless the terms “only” or “direct” are used.

[0065] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the technical spirit of this disclosure, a first element referred to below may mean a second element. In describing the components herein, terms such as first, second, A, B, (a), or (b) may be used. These terms are only intended to distinguish one component from another and do not limit the nature, order, sequence, or number of components.

[0066] When a component is described as “connected to,” “linked to,” “accessed to,” or “attached to” another component, such a component may be directly connected to, linked to, in contact with, or attached to the other component. However, it should be understood that, unless explicitly stated otherwise, they may be indirectly connected to, linked to, accessed to, or attached to each other with another component interposed between them.

[0067] When a component or layer is described as being in contact with or overlapping another component or layer, such a component or layer may be in direct contact with or overlapping the other component or layer. However, it should be understood that, unless explicitly stated otherwise, they may also be in contact with or overlapping each other indirectly, with another component or layer interspersed between them.

[0068] The phrase "at least one" should be understood as including any combination of one or more associated components. For example, "at least one of the first component, the second component, and the third component" means not only that the first component, the second component, or the third component may be included, but also any combination of two or more of the first component, the second component, or the third component.

[0069] The terms “first direction”, “second direction”, “third direction”, “X-axis direction”, “Y-axis direction” and “Z-axis direction” should not be interpreted merely as geometric relationships in which they are perpendicular to each other, but can mean a wider range of directions within which the configurations of this disclosure can function functionally.

[0070] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, as one of ordinary skill in the art will understand, the terms “component” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described functions.

[0071] In contrast, these embodiments may be provided to make this disclosure sufficiently thorough and complete to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0072] The various features of the various embodiments of this disclosure may be partially or wholly linked or combined with each other and interconnected and operated in various technical ways, and each embodiment may be implemented independently of each other or together in an associated relationship.

[0073] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0074] Figure 1 This is a perspective view showing a display device according to one embodiment of the present disclosure. Figure 2 This is a plan view of a display device according to one embodiment of the present disclosure. Figure 3 This is an enlarged view of a display device according to one embodiment of the present disclosure.

[0075] Reference Figures 1 to 3 According to one embodiment of the present disclosure, the display device 1000 may include a display panel 100, a polarizing layer 293, an adhesive layer 295, a cover member 155, a support substrate 145, a flexible circuit board 157, and a printed circuit board 160.

[0076] For example, the display device 1000 may include a substrate 110. The substrate 110 may be a component supporting other components of the display device 1000. The substrate 110 may be provided with an insulating material. For example, the substrate 110 may include components described later. Figure 19 The material of the substrate 200.

[0077] The display panel 100 can display information, video, and / or images to be provided to the user. For example, the display panel 100 may include a display area AA and a non-display area NA. For example, the substrate 110 may include a display area AA and a non-display area NA. The description of the display area AA and the non-display area NA is not limited to the substrate 110, but can be applied to the entire display device 1000.

[0078] The display area AA can be an area for displaying an image. The display area AA can include multiple pixels PX. Each of the multiple pixels PX can be composed of multiple sub-pixels. At each of the multiple sub-pixels, multiple light-emitting elements can be provided. The multiple light-emitting elements can be configured differently depending on the type of display device 1000. For example, if the display device 1000 is an inorganic light-emitting display device, the light-emitting elements can be LEDs (light-emitting diodes), micro LEDs (micro-light-emitting diodes), or mini LEDs (mini-light-emitting diodes), but the embodiments of this disclosure are not limited to these.

[0079] The non-display area NA can be an area where no image is displayed. Various wiring and circuits for driving multiple pixels PX in the display area AA can be set in the non-display area NA. For example, a pad component PAD can be set in the non-display area NA, on which various wiring and driving circuits can be mounted, and integrated circuits and printed circuits are connected to the pad component PAD; however, embodiments of this disclosure are not limited thereto.

[0080] For example, the driving circuit can be a data driving circuit and / or a gating driving circuit, but embodiments of this disclosure are not limited thereto. In the non-display area NA, wiring can be provided therethrough to supply control signals for controlling the driving circuit. For example, the control signals can include various timing signals comprising synchronization signals, input data enable signals, and clock signals, but embodiments of this disclosure are not limited thereto. The control signals can be received via pad components PAD. For example, in the non-display area NA, link wiring LL for transmitting signals can be provided. For example, driving components such as flexible circuit board 157 and printed circuit board 160 can be connected to the pad components PAD.

[0081] According to this disclosure, the non-display area NA may include a first non-display area NA1, a curved area BA, and a second non-display area NA2. For example, the first non-display area NA1 may be a region surrounding at least a portion of the display area AA. The curved area BA may be a flexible region extending from at least one of the plurality of sides of the first non-display area NA1. The second non-display area NA2 may be a region extending from the curved area BA, and a pad component PAD may be disposed in this region. For example, the curved area BA may be in a curved state, and the remaining area of ​​the substrate 110 other than the curved area BA may be in a flat state. In this case, when the curved area BA is bent, the second non-display area NA2 may be located on the rear surface of the display area AA. However, embodiments of this disclosure are not limited thereto.

[0082] According to the design of the display device 1000, the substrate 110 or the display area AA of the display device 1000 can be configured in various shapes. For example, the display area AA can be configured as a rectangular shape with four rounded corners, but the embodiments of this disclosure are not limited to this. As another example, the display area AA can be configured as a rectangular shape with four right angles, a circular shape, etc., but the embodiments of this disclosure are not limited to this.

[0083] According to this disclosure, the width of the second non-display area NA2, in which multiple pad electrodes PE are provided, can be greater than the width of the curved area BA, which only has multiple link wirings LL. Additionally, the width of the display area AA, in which multiple sub-pixels are provided, can be greater than the width of the curved area BA, which only has multiple link wirings LL. Although the width of the curved area BA is depicted in the drawings as being smaller than the width of other areas of the substrate 110, the shape of the substrate 110 including such a curved area BA is given only as an example, and embodiments of this disclosure are not limited thereto.

[0084] Reference Figure 3 In the display area AA, multiple pixel driving circuits PD can be provided. The multiple pixel driving circuits PD can be circuits for driving the light-emitting elements of multiple sub-pixels. Each of the multiple pixel driving circuits PD may include multiple transistors including driving transistors, storage capacitors, etc., and can control the light-emitting operation of the multiple light-emitting elements by providing control signals, power, and driving current to the light-emitting elements of the multiple sub-pixels. For example, the pixel driving circuit PD may include power wiring and signal wiring for controlling the on / off and / or light-emitting time of the light-emitting elements. For example, the multiple pixel driving circuits PD may be a driver fabricated on a semiconductor substrate using MOSFET (Metal-Oxide-Silicon Field-Effect Transistor) manufacturing process, but the embodiments of this disclosure are not limited thereto. The driver may include multiple pixel driving circuits PD and can drive multiple sub-pixels. For example, the multiple pixel driving circuits PD may include a micro-driver μDriver, but the embodiments of this disclosure are not limited thereto. For example, the multiple pixel driving circuits PD may include a driver chip, but the embodiments of this disclosure are not limited thereto.

[0085] Refer to together Figure 1 The flexible circuit board 157 and the printed circuit board 160 can be disposed on the underside of the display panel 100. The flexible circuit board 157 and the printed circuit board 160 can be disposed on at least one edge of the display panel 100, but embodiments of this disclosure are not limited thereto. The flexible circuit board 157 can be attached to the display panel 100 on one side and to the printed circuit board 160 on the other side, but embodiments of this disclosure are not limited thereto. The flexible circuit board 157 can be configured with a flexible film, but embodiments of this disclosure are not limited thereto.

[0086] In the second non-display area NA2, a pad component PAD, including multiple pad electrodes PE, can be provided. A driving assembly including one or more flexible circuit boards (or flexible films) 157 and printed circuit boards 160 can be attached or bonded to the pad component PAD. The multiple pad electrodes PE of the pad component PAD can be electrically connected to one or more flexible circuit boards (or flexible films) 157 to transmit various signals or power from the printed circuit board 160 and the flexible circuit boards (or flexible films) 157 to multiple pixel driving circuits PD in the display area AA.

[0087] The flexible circuit board (or flexible film) 157 may be configured with a film whose base film is flexible and on which various components are disposed. For example, the flexible circuit board (or flexible film) 157 may be provided with a driver IC such as a gating driver IC or a data driver IC disposed thereon, but embodiments of the present disclosure are not limited thereto. The driver IC may be a component that processes data and drive signals for displaying images. Depending on the mounting method, the driver IC may be disposed in a manner such as chip on glass (COG), chip on film (COF), or tape-on-carrier (TCP), but embodiments of the present disclosure are not limited thereto. The flexible circuit board (or flexible film) 157 may be attached or bonded to a plurality of pad electrodes PE via a conductive adhesive layer, but embodiments of the present disclosure are not limited thereto.

[0088] The printed circuit board 160 can be a component electrically connected to one or more flexible circuit boards (or flexible films) 157 to provide signals to the driver IC. The printed circuit board 160 can be disposed on one side of the flexible circuit board (or flexible film) 157 for electrical connection to the flexible circuit board (or flexible film) 157. A series of components for providing various signals to the driver IC can be disposed on the printed circuit board 160. For example, various components including a timing controller, power supply, memory, processor, etc., can be disposed on the printed circuit board 160. For example, the printed circuit board 160 can be provided with a power management integrated circuit (PMIC), but embodiments of this disclosure are not limited thereto.

[0089] The printed circuit board 160 may include at least one hole 180, but embodiments of the present disclosure are not limited thereto. In the area corresponding to the at least one hole 180, internal components for detecting ambient light, temperature, etc., may be provided, and these components may include multiple sensors. For example, the internal components may include an ambient light sensor (ALS) or a temperature sensor, but embodiments of the present disclosure are not limited thereto. For example, the hole 180 may be a permeable hole, but embodiments of the present disclosure are not limited thereto.

[0090] Reference Figure 1The polarization layer 293 can be disposed on the display panel 100. The polarization layer 293 can prevent or mitigate the phenomenon that light generated by an external light source enters the interior of the display panel 100 and affects the light-emitting elements, etc.

[0091] A cover member 155 may be disposed on the polarization layer 293. The cover member 155 may be a component for protecting the display panel 100. An adhesive layer 295 may be disposed between the polarization layer 293 and the cover member 155. The cover member 155 can be attached to the display panel 100 via the adhesive layer 295. The adhesive layer 295 may include optically transparent adhesive (OCA), optically transparent resin (OCR), pressure-sensitive adhesive (PSA), etc., but embodiments of this disclosure are not limited thereto.

[0092] A support substrate 145 may be disposed between the display panel 100 and the printed circuit board 160. The support substrate 145 may enhance the rigidity of the display panel 100. The support substrate 145 may be a back plate, but the embodiments disclosed herein are not limited thereto.

[0093] Reference Figures 1 to 3 Multiple link wirings LL can be disposed in the non-display area NA. These link wirings LL can be wirings that transmit various signals from one or more flexible circuit boards (or flexible films) 157 and printed circuit boards 160 to the display area AA. The link wirings LL can extend from multiple pad electrodes PE in the second non-display area NA2 toward the curved area BA and the first non-display area NA1 to electrically connect to multiple drive wirings VL in the display area AA. Multiple pixel drive circuits PD can be driven by receiving signals from one or more flexible circuit boards (or flexible films) 157 and printed circuit boards 160 via the drive wirings VL in the display area AA and the link wirings LL in the non-display area NA.

[0094] For example, multiple drive lines VL can be used, together with multiple link lines LL, to transmit signals output from the flexible circuit board (or flexible film) 157 and the printed circuit board 160 to multiple pixel driving circuits PD. The multiple drive lines VL can be positioned in the display area AA to electrically connect to each of the multiple pixel driving circuits PD. The multiple drive lines VL can extend from the display area AA toward the non-display area NA to electrically connect to the multiple link lines LL. Therefore, signals output from the flexible circuit board (or flexible film) 157 and the printed circuit board 160 can be transmitted to each of the multiple pixel driving circuits PD via the multiple link lines LL and the multiple drive lines VL.

[0095] When the bending region BA bends, portions of the multiple link wirings LL may also bend together. Stress may concentrate on a portion of the bent link wirings LL, which could lead to cracks in the link wirings LL. Therefore, the multiple link wirings LL can be configured with a conductive material having excellent ductility to reduce cracking when the bending region BA bends. For example, the multiple link wirings LL can be configured with a conductive material having excellent ductility, such as gold (Au), silver (Ag), aluminum (Al), etc., but embodiments of this disclosure are not limited thereto. Alternatively, the multiple link wirings LL can be configured with one of various conductive materials used in the display region AA. For example, the multiple link wirings LL can be configured with an alloy of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and silver (Ag) and magnesium (Mg), or any alloy thereof, but embodiments of this disclosure are not limited thereto. The multiple link wirings LL can be configured as a multilayer structure including various conductive materials. For example, multiple link wiring LL can be configured as a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but the embodiments of this disclosure are not limited thereto.

[0096] Multiple link wires LL can be configured in various shapes to reduce stress. At least a portion of the multiple link wires LL disposed on the curved region BA can extend in the same direction as the extending direction of the curved region BA, or in a direction different from the extending direction of the curved region BA, to reduce stress. For example, when the curved region BA extends in one direction from the first non-display region NA1 toward the second non-display region NA2, at least a portion of the link wires LL disposed on the curved region BA can extend in a direction transverse to that direction. As another example, at least a portion of the multiple link wires LL can be configured as a pattern of various shapes. For example, at least a portion of the multiple link wires LL disposed on the curved region BA can have a shape in which a conductive pattern having at least one shape selected from rhombus shape, oblique square shape, trapezoidal wave shape, triangular wave shape, sawtooth wave shape, sine wave shape, circular shape, and omega (Ω) shape can be repeatedly disposed, but embodiments of this disclosure are not limited thereto.

[0097] Figure 4 This is a diagram illustrating a circuit structure according to one embodiment of the present disclosure.

[0098] exist Figure 4 In the example shown, an ED (Emitting Light-Emitting Element) is connected to a microdriver (μDriver); however, this is not exhaustive. For instance, a microdriver (μDriver) can control multiple pixels arranged in 16 columns × 16 rows (16 × 16) on a substrate. Multiple pixels can include multiple EDs.

[0099] A microdriver (μDriver) can be implemented as a chip. For example, a chip-based microdriver (μDriver) may include a driving transistor T. DR and light-emitting transistor T EM The circuit.

[0100] For example, the driving transistor T in the micro-driver μDriver DR It can have a first electrode to which a high-potential power supply voltage VDD is applied and connected to a light-emitting transistor T. EM The first electrode, the second electrode, and the gate electrode to which the scan signal SC is applied. This is applied to the driving transistor T. DR The scan signal SC of the gate electrode can be a direct current (DC) power supply and a fixed reference voltage (Vref) can be applied per frame, but the embodiments disclosed herein are not limited thereto.

[0101] Light-emitting transistor T EM It can have a connection to the driving transistor T DR The second electrode consists of the first electrode of the second electrode, the second electrode connected to the light-emitting element ED, and the gate electrode to which the light-emitting signal EM is applied. The signal is applied to the light-emitting transistor T. EM The light emission signal EM of the gate electrode can be a pulse width modulation (PWM) signal that varies per frame, but the embodiments disclosed herein are not limited thereto.

[0102] The light-emitting element ED can have a connection to the light-emitting transistor T EM The second electrode is a first electrode and a second electrode connected to ground. For example, the first electrode can be an anode electrode and the second electrode can be a cathode electrode, but the embodiments of this disclosure are not limited thereto.

[0103] Drive transistor T DR and light-emitting transistor T EM They can each be either n-type transistors or p-type transistors.

[0104] In the microdriver μDriver, the driving transistor T DR The LED can be turned on by the scan signal SC applied from the timing controller T-CON, and the LED T... EM It can be turned on by emitting a light signal EM. Therefore, the drive current can be applied to the drive transistor T. DR The high potential power supply voltage VDD of the first electrode is driven by transistor T. DR and light-emitting transistor T EM An application is made to the light-emitting element ED, causing the light-emitting element ED to emit light.

[0105] Figures 5 to 7 This is a plan view of a display device according to one embodiment of the present disclosure.

[0106] For example, Figure 5 It is a magnified planar view of a display area that includes multiple pixels. For example, Figure 6 It is a magnified planar view of a display area including one pixel. For example, Figure 7 It is a magnified planar view of a display area that includes multiple pixels. For example, Figure 8 This is a cross-sectional view of the display area AA, the first non-display area NA, the curved area BA, and the second non-display area NA2. For example, Figure 9 It is a cross-sectional view of the display area including a sub-pixel SP1. Figure 5 and Figure 6 The present invention only illustrates multiple signal wirings TL, multiple communication wirings NL, multiple first electrodes CE1, multiple embankments BNK, and multiple light-emitting elements ED, but the embodiments of the present invention are not limited thereto. Figure 7 It is relative to Figure 5 An enlarged plan view showing the additional configuration of multiple second electrodes CE2.

[0107] Reference Figure 5 , Figure 6 and Figure 9 Multiple pixels PX, each configured with multiple subpixels, can be disposed in a display area AA. Each of the multiple subpixels may include a light-emitting element ED and can emit light independently. The multiple subpixels may be arranged in a matrix to form multiple rows and multiple columns, but the embodiments disclosed herein are not limited thereto.

[0108] The plurality of sub-pixels may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For example, one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be a red sub-pixel, another may be a green sub-pixel, and the remaining one may be a blue sub-pixel. The types of the plurality of sub-pixels are given by way of example only, and the embodiments of this disclosure are not limited thereto.

[0109] Each of a plurality of pixels PX may include one or more first sub-pixels SP1, one or more second sub-pixels SP2, and one or more third sub-pixels SP3. For example, a pixel PX may include a pair of first sub-pixels SP1, a pair of second sub-pixels SP2, and a pair of third sub-pixels SP3. The pair of first sub-pixels SP1 may be configured with a first first sub-pixel SP1a and a first second sub-pixel SP1b. The pair of second sub-pixels SP2 may be configured with a second first sub-pixel SP2a and a second second sub-pixel SP2b. The pair of third sub-pixels SP3 may be configured with a third first sub-pixel SP3a and a third second sub-pixel SP3b. For example, a pixel PX may include first first sub-pixels SP1a and first second sub-pixels SP1b, second first sub-pixels SP2a and second second sub-pixels SP2b, and third first sub-pixels SP3a and third second sub-pixels SP3b, but the embodiments of this disclosure are not limited thereto.

[0110] The multiple subpixels constituting a pixel PX can be arranged in various ways. For example, in a pixel PX, a pair of first subpixels SP1 can be arranged in the same column, a pair of second subpixels SP2 can be arranged in the same column, and a pair of third subpixels SP3 can be arranged in the same column. The first subpixels SP1, second subpixels SP2, and third subpixels SP3 can be arranged in the same row. The number and arrangement of the multiple subpixels constituting a pixel PX are given by way of example only, and the embodiments of this disclosure are not limited thereto.

[0111] Multiple signal traces TL can be positioned in the region between multiple sub-pixels. The multiple signal traces TL can extend in the column direction between the multiple sub-pixels. The multiple signal traces TL can be traces that transmit anode voltage from pixel driving circuit PD to multiple sub-pixels. For example, the multiple signal traces TL can be electrically connected to the first electrode CE1 of multiple sub-pixels and multiple pixel driving circuits PD. The anode voltage output from the pixel driving circuit PD can be transmitted to the first electrode CE1 of multiple sub-pixels via the multiple signal traces TL. For example, the first electrode CE1 can be an electrode electrically connected to the anode electrode 134 of the light-emitting element ED. Thus, the anode voltage from the signal traces TL can be transmitted to the anode electrode 134 of the light-emitting element ED via the first electrode CE1.

[0112] Therefore, instead of forming multiple transistors and storage capacitors in each of the multiple sub-pixels, the structure of the display device 1000 can be simplified by using a pixel drive circuit PD in which multiple pixel circuits are integrated. Furthermore, since the circuits provided in each of the multiple sub-pixels are integrated into a single pixel drive circuit PD, high-efficiency and low-power driving can be achieved.

[0113] Multiple signal traces TL may include a first signal trace TL1, a second signal trace TL2, a third signal trace TL3, a fourth signal trace TL4, a fifth signal trace TL5, and a sixth signal trace TL6. Each of the first signal trace TL1 and the second signal trace TL2 may be electrically connected to each of a pair of first sub-pixels SP1. Each of the third signal trace TL3 and the fourth signal trace TL4 may be electrically connected to each of a pair of second sub-pixels SP2. Each of the fifth signal trace TL5 and the sixth signal trace TL6 may be electrically connected to each of a pair of third sub-pixels SP3.

[0114] A first signal wiring TL1 can be disposed on one side of a pair of first sub-pixels SP1, and a second signal wiring TL2 can be disposed on the other side of the pair of first sub-pixels SP1. The first signal wiring TL1 can be electrically connected to the first electrode CE1 of one of the first sub-pixels SP1 (e.g., first sub-pixel SP1a). A second signal wiring TL2 can be electrically connected to the first electrode CE1 of the remaining first sub-pixels SP1 (e.g., first sub-pixel SP1b) of the pair of first sub-pixels SP1.

[0115] A third signal wiring TL3 can be disposed on one side of a pair of second sub-pixels SP2, and a fourth signal wiring TL4 can be disposed on the other side of the pair of second sub-pixels SP2. For example, the third signal wiring TL3 can be disposed adjacent to the second signal wiring TL2. The third signal wiring TL3 can be electrically connected to the first electrode CE1 of one of the second sub-pixels SP2 of the pair of second sub-pixels SP2 (e.g., the second first sub-pixel SP2a). The fourth signal wiring TL4 can be electrically connected to the first electrode CE1 of the remaining second sub-pixels SP2 of the pair of second sub-pixels SP2 (e.g., the second second sub-pixel SP2b).

[0116] The fifth signal wiring TL5 can be located on one side of a pair of third sub-pixels SP3, and the sixth signal wiring TL6 can be located on the other side of the pair of third sub-pixels SP3. For example, the fifth signal wiring TL5 can be located adjacent to the fourth signal wiring TL4. The sixth signal wiring TL6 can be located adjacent to the first signal wiring TL1 connected to the adjacent pixel PX. The fifth signal wiring TL5 can be electrically connected to the first electrode CE1 of one of the third sub-pixels SP3 of the pair of third sub-pixels SP3 (e.g., the third first sub-pixel SP3a). The sixth signal wiring TL6 can be electrically connected to the first electrode CE1 of the remaining third sub-pixels SP3 of the pair of third sub-pixels SP3 (e.g., the third second sub-pixel SP3b).

[0117] Multiple signal traces TL can be configured with conductive materials. For example, multiple signal traces TL can be configured with conductive materials such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but the embodiments of this disclosure are not limited thereto. As another example, multiple signal traces TL can be formed from a multilayer structure of conductive materials. For example, multiple signal traces TL can be configured as a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) / indium tin oxide (ITO), but the embodiments of this disclosure are not limited thereto.

[0118] Multiple communication lines NL can be disposed in the region between multiple pixels PX. Multiple communication lines NL can be configured to extend in the row direction within the region between multiple pixels PX. Multiple communication lines NL can be disposed in the region between multiple second electrodes CE2, and may not overlap with the multiple second electrodes CE2. For example, multiple communication lines NL can be wiring for short-range communication such as near field communication (NFC). Multiple communication lines NL can be used as antennas. For example, multiple communication lines NL can be multiple connection lines, etc., but embodiments of this disclosure are not limited thereto.

[0119] According to this disclosure, a dammed area (BNK) can be disposed in each of a plurality of sub-pixels. The plurality of dammed areas (BNKs) can be a structure on which a plurality of light-emitting elements (EDs) are mounted. The plurality of dammed areas (BNKs) can guide the position of the plurality of light-emitting elements (EDs) during the transfer process of transferring the plurality of EDs to the display device 1000. During the transfer process of the plurality of EDs, the plurality of EDs can be transferred onto the plurality of dammed areas (BNKs). The plurality of dammed areas (BNKs) can be dammed patterns, dammed layers, or structures, but embodiments of this disclosure are not limited thereto.

[0120] The dam portions BNK of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be spaced apart from each other. Therefore, the dam portions BNK of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, which have transferred different types of light-emitting elements (EDs), can be easily identified.

[0121] The dam portion BNK of the first sub-pixel SP1a and the dam portion BNK of the first second sub-pixel SP1b can be connected to each other, or they can be spaced apart or separated from each other. For example, considering design requirements for the transfer process, the dam portion BNK of the first sub-pixel SP1a and the dam portion BNK of the first second sub-pixel SP1b, which are provided with the same type of light-emitting element ED, can be connected to each other, or they can be spaced apart or separated from each other. Furthermore, the dam portion BNK of the second first sub-pixel SP2a and the dam portion BNK of the second second sub-pixel SP2b can be connected to each other, or they can be spaced apart or separated from each other. The dam portion BNK of the third first sub-pixel SP3a and the dam portion BNK of the third second sub-pixel SP3b can be connected to each other, or they can be spaced apart or separated from each other. Therefore, the dam portion BNK of a pair of first sub-pixels SP1, a pair of second sub-pixels SP2, and a pair of third sub-pixels SP3 can be formed in various ways, and therefore the embodiments of this disclosure are not limited thereto.

[0122] For example, the multiple dam sections BNK can be configured with organic insulating materials. The multiple dam sections BNK can be configured as a single-layer or multi-layer structure of organic insulating materials. For example, the multiple dam sections BNK can be configured with photoresist, polyimide (PI) or acrylic-based materials, etc., but the embodiments of this disclosure are not limited thereto.

[0123] A first electrode CE1 may be disposed on each of a plurality of sub-pixels. The first electrode CE1 may be disposed on a dam BNK. The first electrode CE1 may be electrically connected to one of a plurality of signal wirings TL. At least a portion of the first electrode CE1 may extend outside the dam BNK to be electrically connected to the signal wiring TL closest to the first electrode CE1. For example, a portion of the first electrode CE1 of a first sub-pixel SP1a may extend to one side of the first sub-pixel SP1a to be electrically connected to a first signal wiring TL1, and a portion of the first electrode CE1 of a first second sub-pixel SP1b may extend to the other side of the first second sub-pixel SP1b to be electrically connected to a second signal wiring TL2. A portion of the first electrode CE1 of a second first sub-pixel SP2a may extend to one side of the second first sub-pixel SP2a to be electrically connected to a third signal wiring TL3, and a portion of the first electrode CE1 of a second second sub-pixel SP2b may extend to the other side of the second second sub-pixel SP2b to be electrically connected to a fourth signal wiring TL4. A portion of the first electrode CE1 of the third first sub-pixel SP3a may extend to one side of the third first sub-pixel SP3a to be electrically connected to the fifth signal wiring TL5, and a portion of the first electrode CE1 of the third second sub-pixel SP3b may extend to the other side of the third second sub-pixel SP3b to be electrically connected to the sixth signal wiring TL6.

[0124] The first electrode CE1 can be electrically connected to the anode electrode 134 of the light-emitting element ED to send the anode voltage from the pixel driving circuit PD to the light-emitting element ED via signal wiring TL. For each of the multiple sub-pixels, a different voltage can be applied to the first electrode CE1, depending on the image to be displayed. For example, different voltages can be applied to the first electrode CE1 of each of the multiple sub-pixels. Thus, the first electrode CE1 can be a pixel electrode, and embodiments of this disclosure are not limited thereto.

[0125] The first electrode CE1 may be configured with a conductive material. For example, the first electrode CE1 may be configured as a body having multiple signal wirings TL. For example, the first electrode CE1 may be configured with the same conductive material as the multiple signal wirings TL, but the embodiments of this disclosure are not limited thereto. For example, the first electrode CE1 may be configured with conductive materials such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but the embodiments of this disclosure are not limited thereto. As another example, the first electrode CE1 may be configured as a multilayer structure of conductive material. For example, multiple first electrodes CE1 may be configured as a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) / indium tin oxide (ITO), but the embodiments of this disclosure are not limited thereto.

[0126] A light-emitting element (ED) can be disposed in each of a plurality of sub-pixels. The plurality of EDs can be disposed on the embankment BNK and the first electrode CE1. The plurality of EDs can be disposed on the first electrode CE1 and electrically connected to the first electrode CE1. Therefore, the EDs can emit light by receiving the anode voltage from the pixel driving circuit PD via signal wiring TL and the first electrode CE1.

[0127] Multiple light-emitting elements (EDs) may include a first light-emitting element 130, a second light-emitting element 140, and a third light-emitting element 150. The first light-emitting element 130 may be disposed in a first sub-pixel SP1. The second light-emitting element 140 may be disposed in a second sub-pixel SP2. The third light-emitting element 150 may be disposed in a third sub-pixel SP3. For example, one of the first light-emitting element 130, the second light-emitting element 140, and the third light-emitting element 150 may be a red light-emitting element, another may be a green light-emitting element, and the remaining one may be a blue light-emitting element, but the embodiments of this disclosure are not limited thereto. Therefore, by combining red, green, and blue light emitted from multiple light-emitting elements (EDs), various colors of light (including white) can be achieved. The types of multiple light-emitting elements (EDs) are given only as examples, and the embodiments of this disclosure are not limited thereto.

[0128] The first light-emitting element 130 may include a first first light-emitting element 130a disposed in a first first sub-pixel SP1a and a first second light-emitting element 130b disposed in a first second sub-pixel SP1b. The second light-emitting element 140 may include a second first light-emitting element 140a disposed in a second first sub-pixel SP2a and a second second light-emitting element 140b disposed in a second second sub-pixel SP2b. The third light-emitting element 150 includes a third first light-emitting element 150a disposed in a third first sub-pixel SP3a and a third second light-emitting element 150b disposed in a third second sub-pixel SP3b.

[0129] Refer to together Figure 5 , Figure 6 , Figure 7 and Figure 9 The second electrode CE2 can be disposed on each of the multiple sub-pixels. The second electrode CE2 can be disposed on the light-emitting element ED. The second electrode CE2 can be electrically connected to the pixel driving circuit PD through multiple contact electrodes CCE.

[0130] For example, the second electrode CE2 can be electrically connected to the cathode electrode 135 of the light-emitting element ED to send the cathode voltage from the pixel driving circuit PD to the light-emitting element ED. The same cathode voltage can be applied to the second electrode CE2 of each of the plurality of sub-pixels. For example, the same voltage can be applied to the cathode electrode 135 of the light-emitting element ED and the second electrode CE2 of each of the plurality of sub-pixels. Thus, the second electrode CE2 can be a common electrode, but embodiments of this disclosure are not limited thereto.

[0131] At least some of the multiple sub-pixels can share the second electrode CE2. At least some of the second electrodes CE2 in the multiple corresponding sub-pixels can be electrically connected to each other. When the same voltage is applied to the second electrode CE2, the second electrode CE2 can be shared for at least some sub-pixels. For example, the second electrodes CE2 of at least some of the multiple pixels PX in the same row can be connected to each other. For example, one second electrode CE2 can be provided on multiple pixels PX. One second electrode CE2 can be provided for every n sub-pixels.

[0132] For example, some of the second electrodes CE2 of a plurality of corresponding sub-pixels can be configured to be spaced apart or separated from each other. For example, the second electrode CE2 connected to pixel PX in row n and the second electrode CE2 connected to pixel PX in row n+1 can be configured to be spaced apart or separated from each other. For example, a plurality of second electrodes CE2 can be configured to be spaced apart from each other, with a plurality of communication wirings NL inserted therebetween and extending therebetween in the row direction. Therefore, the number of a plurality of sub-pixels can be greater than the number of a plurality of second electrodes CE2. As another example, all the second electrodes CE2 of a plurality of sub-pixels can be connected to each other such that only one second electrode CE2 is placed on substrate 110, but embodiments of the present disclosure are not limited thereto.

[0133] The plurality of second electrodes CE2 may be configured with a transparent conductive material, but embodiments of the present disclosure are not limited thereto. The plurality of second electrodes CE2 may be configured with a transparent conductive material so that light emitted from the light-emitting element ED can be guided toward the upper side of the second electrodes CE2. For example, the second electrodes CE2 may be configured with a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but embodiments of the present disclosure are not limited thereto.

[0134] Multiple contact electrodes CCE can be disposed on the substrate 110. For example, the multiple contact electrodes CCE can be configured to be spaced apart from multiple embankments BNK and multiple signal traces TL. Each of the multiple second electrodes CE2 can overlap with at least one contact electrode CCE. For example, one second electrode CE2 can overlap with multiple contact electrodes CCE.

[0135] For example, multiple contact electrodes CCE can be electrically connected to multiple second electrodes CE2. The multiple contact electrodes CCE can be disposed between the substrate 110 and the multiple second electrodes CE2 to send the cathode voltage from the pixel driving circuit PD to the second electrodes CE2.

[0136] For example, when micro-LEDs are used as light-emitting elements (EDs), multiple micro-LEDs can be formed on a wafer, and the micro-LEDs can be transferred to the substrate 110 of the display device 1000 to manufacture the display device 1000. During the process of transferring multiple light-emitting elements (EDs) with microscale dimensions from the wafer to the substrate 110, various defects may occur. For example, in some sub-pixels, non-transfer defects may occur where the light-emitting element (ED) is not transferred, and in other sub-pixels, defects may occur where the light-emitting element (ED) is transferred outside its intended position due to alignment errors. Furthermore, even if the transfer process is performed normally, the transferred light-emitting element (ED) itself may be defective. Therefore, taking into account the defects generated during the transfer process of multiple light-emitting element (EDs), multiple light-emitting element (EDs) of the same type can be transferred to a single sub-pixel. Illumination tests can be performed on multiple light-emitting element (EDs), and only the one light-emitting element (ED) ultimately determined to be normal can be used.

[0137] For example, a first light-emitting element 130a and a first second light-emitting element 130b can be transferred together to a pixel PX and can be tested to detect defects. If both the first light-emitting element 130a and the first second light-emitting element 130b are determined to be normal, only the first light-emitting element 130a can be used, and the first second light-emitting element 130b can be omitted. As another example, if only the first second light-emitting element 130b is determined to be normal, the first light-emitting element 130a can be omitted, and only the first second light-emitting element 130b can be used. Therefore, even if multiple light-emitting elements ED of the same type are transferred to a pixel PX, ultimately only one light-emitting element ED can be used.

[0138] Therefore, one of a pair of light-emitting elements (EDs) can be the primary or main ED, and the other ED can be a redundant ED. The redundant ED can be a backup ED that has been transferred in preparation for a failure of the primary ED. In the event of a failure of the primary ED, the redundant ED can be used as its replacement. Therefore, by transferring both the primary and redundant EDs together to a single pixel (PX), the degradation of display quality due to defects in either the primary or redundant EDs can be minimized or reduced.

[0139] For example, the first first light-emitting element 130a, the second first light-emitting element 140a, and the third first light-emitting element 150a transferred to a pixel PX can be used as the main light-emitting element ED, while the first second light-emitting element 130b, the second second light-emitting element 140b, and the third second light-emitting element 150b can be used as redundant light-emitting elements ED.

[0140] Figure 8 It is along Figure 3 The cross-sectional view of the display device is taken by line VIII-VIII'. Figure 9 This is a cross-sectional view of a display device according to one embodiment of the present disclosure. For example, Figure 8 This is a cross-sectional view of the display area AA, the first non-display area NA, the curved area BA, and the second non-display area NA2. For example, Figure 9 This is a cross-sectional view of the display area including one sub-pixel SP1. Furthermore, for ease of explanation, Figure 3 Lines VIII-VIII' in the diagram are exemplified as not overlapping with drive wiring VL and link wiring LL, but Figure 3 The lines VIII-VIII' in the diagram are intended to indicate the same location as the adjacent drive wiring VL and link wiring LL.

[0141] Reference Figure 8 In the remaining area of ​​the substrate 110, excluding the bending region BA, a first buffer layer 111a and a second buffer layer 111b may be provided.

[0142] The first buffer layer 111a and the second buffer layer 111b can be disposed in the display area AA, the first non-display area NA1, and the second non-display area NA2. The first buffer layer 111a and the second buffer layer 111b can reduce the penetration of moisture or impurities into the substrate 110. The first buffer layer 111a and the second buffer layer 111b can be configured with an inorganic insulating material. For example, the first buffer layer 111a and the second buffer layer 111b can be configured as a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but the embodiments of this disclosure are not limited thereto.

[0143] For example, a portion of the first buffer layer 111a and the second buffer layer 111b on the bending region BA can be removed. The upper surface of the substrate 110 located in the bending region BA can be exposed from the first buffer layer 111a and the second buffer layer 111b. By removing the first buffer layer 111a and the second buffer layer 111b, which are configured with inorganic insulating material, from the bending region BA, cracks that may occur in the first buffer layer 111a and the second buffer layer 111b during bending can be minimized or reduced.

[0144] Between the first buffer layer 111a and the second buffer layer 111b, a plurality of alignment keys MK can be provided. The plurality of alignment keys MK can be configured to identify the position of the pixel driving circuit PD during the manufacturing process of the display device 1000. For example, the plurality of alignment keys MK can be configured to align the position of the pixel driving circuit PD transferred on the adhesive layer 112. As another example, the plurality of alignment keys MK can be omitted.

[0145] An adhesive layer 112 may be disposed on the second buffer layer 111b. The adhesive layer 112 may be disposed in the display area AA, the first non-display area NA1, the curved area BA, and the second non-display area NA2. As another example, at least a portion of the adhesive layer 112 may be removed from the non-display area NA, which includes the curved area BA. For example, the adhesive layer 112 may be configured with any of the following: adhesive polymer, epoxy resin, UV-curable resin, polyimide series, acrylate series, urethane series, and polydimethylsiloxane (PDMS), but embodiments of this disclosure are not limited thereto.

[0146] A pixel driving circuit PD can be disposed on the adhesive layer 112 in the display area AA. When the pixel driving circuit PD is implemented using a drive driver, the drive driver can be mounted on the adhesive layer 112 by a transfer process, but the embodiments disclosed herein are not limited thereto.

[0147] A first protective layer 113a and a second protective layer 113b may be provided on the adhesive layer 112 and the pixel driving circuit PD. The first protective layer 113a and the second protective layer 113b may be configured to surround the side surface of the pixel driving circuit PD, but embodiments of this disclosure are not limited thereto. For example, the second protective layer 113b may be configured to cover at least a portion of the upper surface of the pixel driving circuit PD. For example, at least one of the first protective layer 113a and the second protective layer 113b provided on the curved region BA may be omitted. For example, the first protective layer 113a may be completely provided in the display area AA and the non-display area NA, and the second protective layer 113b may be partially provided in the display area AA, the first non-display area NA1, and the second non-display area NA2. For example, a portion of the second protective layer 113b in the curved region BA may be removed. However, embodiments of this disclosure are not limited thereto.

[0148] The first protective layer 113a and the second protective layer 113b may be configured with organic insulating materials, but the embodiments of this disclosure are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b may be configured with photoresist, polyimide (PI), or photoacryloyl materials, etc., but the embodiments of this disclosure are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b may be an outer coating or an insulating layer, but the embodiments of this disclosure are not limited thereto.

[0149] According to this disclosure, multiple first connection wirings 121 can be provided on the second protective layer 113b in the display area AA. The multiple first connection wirings 121 can be wirings used to electrically connect the pixel driving circuit PD to another component. For example, the pixel driving circuit PD can be electrically connected to multiple signal wirings TL, multiple contact electrodes CCE, etc., through the multiple first connection wirings 121. For example, the multiple first connection wirings 121 may include a first first connection wiring 121a, a first second connection wiring 121b, a first third connection wiring 121c, and a first fourth connection wiring 121d, but embodiments of this disclosure are not limited thereto.

[0150] For example, multiple first connection wires 121a can be disposed on the second protective layer 113b. These multiple first connection wires 121a can be electrically connected to the pixel driving circuit PD. The multiple first connection wires 121a can send the voltage output from the pixel driving circuit PD to the first electrode CE1 or the second electrode CE2.

[0151] For example, a third protective layer 114 may be disposed on the second protective layer 113b. The third protective layer 114 may be completely disposed in the display area AA and the non-display area NA. In the curved area BA, the third protective layer 114 may cover or surround the side surface of the second protective layer 113b and the upper surface of the first protective layer 113a. The third protective layer 114 may be configured with an organic insulating material. For example, the third protective layer 114 may be configured with photoresist, polyimide (PI), or photoacryloyl materials, etc., but the embodiments of this disclosure are not limited thereto. For example, the first protective layer 113a, the second protective layer 113b, and the third protective layer 114 may be configured with the same material, but the embodiments of this disclosure are not limited thereto.

[0152] Multiple first and second connection wires 121b can be provided on the third protective layer 114. These multiple first and second connection wires 121b can be connected to or directly connected to the pixel driving circuit PD. For example, a portion of the first and second connection wires 121b can be directly connected to the pixel driving circuit PD through contact holes in the third protective layer 114. Another portion of the first and second connection wires 121b can be electrically connected to the first connection wire 121a through contact holes in the third protective layer 114. However, embodiments of this disclosure are not limited to this. The voltage output from the pixel driving circuit PD can be sent to the first electrode CE1 or the second electrode CE2 through the multiple first and second connection wires 121b and another connection wire.

[0153] A first insulating layer 115a may be disposed on multiple first and second connecting wires 121b. The first insulating layer 115a may be disposed entirely in the display area AA and the non-display area NA, but embodiments of the present disclosure are not limited thereto. The first insulating layer 115a may be configured with an organic insulating material, but embodiments of the present disclosure are not limited thereto. For example, the first insulating layer 115a may be configured with photoresist, polyimide (PI), or photoacryloyl material, but embodiments of the present disclosure are not limited thereto.

[0154] Multiple first and third connection wires 121c can be provided on the first insulating layer 115a. The multiple first and third connection wires 121c can be electrically connected to multiple first and second connection wires 121b. For example, the first and third connection wires 121c can be electrically connected to the first and second connection wires 121b through contact holes in the first insulating layer 115a.

[0155] A second insulating layer 115b may be disposed on multiple first and third connecting wires 121c. The second insulating layer 115b may be disposed in the remaining areas except for the bending region BA, but embodiments of this disclosure are not limited thereto. The second insulating layer 115b may be disposed in the display region AA, the first non-display region NA1, and the second non-display region NA2, but embodiments of this disclosure are not limited thereto. For example, a portion of the second insulating layer 115b disposed in the bending region BA may be removed. The second insulating layer 115b may be configured with an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the second insulating layer 115b may be configured with photoresist, polyimide (PI), or photoacryloyl materials, but embodiments of this disclosure are not limited thereto.

[0156] Multiple first and fourth connection wires 121d can be provided on the second insulating layer 115b. The multiple first and fourth connection wires 121d can be electrically connected to multiple first and third connection wires 121c. For example, the first and fourth connection wires 121d can be electrically connected to the first and third connection wires 121c through contact holes in the second insulating layer 115b.

[0157] According to this disclosure, multiple second connection lines 122 can be provided on the second protective layer 113b in the non-display area NA. The multiple second connection lines 122 can be used to send signals from the flexible circuit board (or flexible film) 157 and the printed circuit board 160 (see [link to relevant documentation]) to the pixel driving circuit PD in the display area AA. Figure 1 The wiring of signals sent to the pad component PAD. For example, multiple second connection wirings 122 can be electrically connected to multiple pad electrodes PE to receive signals from the flexible circuit board (or flexible film) 157 and the printed circuit board.

[0158] For example, multiple second connection lines 122 can extend from the pad component PAD toward the display area AA to transmit signals to the display area AA. In this case, the multiple second connection lines 122 can be used as link lines LL. The multiple second connection lines 122 may include a second first connection line 122a, a second second connection line 122b, a second third connection line 122c, and a second fourth connection line 122d.

[0159] Multiple second first connection lines 122a can be provided on the second protective layer 113b. These multiple second first connection lines 122a can extend from the second non-display area NA2 to the curved area BA and the first non-display area NA1. The multiple second first connection lines 122a can send signals from the flexible circuit board (or flexible film) 157 and the printed circuit board to the pad component PAD in the pixel driving circuit PD of the display area AA.

[0160] Multiple second connection wires 122b can be disposed on the third protective layer 114. These multiple second connection wires 122b can be disposed in the second non-display area NA2. The second connection wires 122b can be electrically connected to the second first connection wire 122a through contact holes in the third protective layer 114. Therefore, signals from the flexible circuit board (or flexible film) 157 and the printed circuit board can be transmitted to the second first connection wire 122a through the second connection wires 122b.

[0161] A second and third connection wiring 122c may be disposed on the first insulating layer 115a. The second and third connection wiring 122c may be disposed in the second non-display area NA2. The second and third connection wiring 122c may be electrically connected to the second connection wiring 122b through contact holes in the first insulating layer 115a. Therefore, signals from the flexible circuit board (or flexible film) 157 and the printed circuit board may be transmitted to the second connection wiring 122a through the second and third connection wiring 122c and the second connection wiring 122b.

[0162] A second fourth connection wiring 122d can be disposed on the second insulating layer 115b. The second fourth connection wiring 122d can be disposed in the second non-display area NA2. The second fourth connection wiring 122d can be electrically connected to the second third connection wiring 122c through contact holes in the second insulating layer 115b. Therefore, signals from the flexible film FF and the printed circuit board can be transmitted to the second first connection wiring 122a through the second fourth connection wiring 122d, the second third connection wiring 122c, and the second second connection wiring 122b.

[0163] The plurality of first connecting wires 121 and the plurality of second connecting wires 122 can be formed using any of the various conductive materials used in the display area AA or conductive materials with excellent ductility. For example, the second connecting wires, which are partially disposed in the curved area, can be configured with conductive materials with excellent ductility such as gold (Au), silver (Ag), aluminum (Al), etc., but embodiments of the present disclosure are not limited thereto. As another example, the plurality of first connecting wires 121 and the plurality of second connecting wires 122 can be configured with alloys of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and silver (Ag) and magnesium (Mg), or any alloy thereof, but embodiments of the present disclosure are not limited thereto.

[0164] A third insulating layer 115c may be disposed on multiple first connecting wires 121 and multiple second connecting wires 122. The third insulating layer 115c may be disposed in the remaining areas excluding the bending region BA, but embodiments of this disclosure are not limited thereto. The third insulating layer 115c may be disposed in the display region AA, the first non-display region NA1, and the second non-display region NA2. A portion of the third insulating layer 115c in the bending region BA may be removed. The third insulating layer 115c may be configured with an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the third insulating layer 115c may be configured with photoresist, polyimide (PI), or photoacryloyl-based materials, but embodiments of this disclosure are not limited thereto.

[0165] Multiple embankment BNKs can be disposed on the third insulating layer 115c in the display area AA. The multiple embankment BNKs can be configured to overlap with each of the multiple sub-pixels. One or more light-emitting elements ED of the same type can be disposed on the upper side of each of the multiple embankment BNKs.

[0166] Multiple signal traces TL can be configured on the third insulating layer 115c in the display area AA. These multiple signal traces TL can be configured in the area between multiple dikes BNK. For example, the multiple signal traces TL can be configured to be adjacent to any one of the multiple dikes BNK.

[0167] Multiple contact electrodes CCE can be disposed on the third insulating layer 115c in the display area AA. The multiple contact electrodes CCE can provide the cathode voltage from the pixel driving circuit PD to the second electrode CE2.

[0168] A first electrode CE1 may be provided on the embankment BNK. For example, the first electrode CE1 may be configured to extend from the adjacent signal wiring TL toward the upper side of the embankment BNK. The first electrode CE1 may be provided on the upper surface and the side surface of the embankment BNK. For example, the first electrode CE1 may be configured to extend from the signal wiring TL on the upper surface of the third insulating layer 115c to the side surface and the upper surface of the embankment BNK.

[0169] Reference Figure 9 The first electrode CE1 may be configured with multiple conductive layers. For example, the first electrode CE1 may include a first conductive layer CE1a, a second conductive layer CE1b, a third conductive layer CE1c, and a fourth conductive layer CE1d, but the embodiments of this disclosure are not limited thereto.

[0170] The first conductive layer CE1a can be disposed on the embankment BNK. The second conductive layer CE1b can be disposed on the first conductive layer CE1a. The third conductive layer CE1c can be disposed on the second conductive layer CE1b. The fourth conductive layer CE1d can be disposed on the third conductive layer CE1c. For example, each of the first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d can be configured with titanium (Ti), molybdenum (Mo), aluminum (Al), or titanium (Ti) and indium tin oxide (ITO), but the embodiments of this disclosure are not limited thereto.

[0171] According to this disclosure, among the plurality of conductive layers constituting the first electrode CE1, some of the conductive layers with good reflectivity can be configured as alignment keys and / or reflectors for aligning the light-emitting element ED. For example, among the plurality of conductive layers of the first electrode CE1, the second conductive layer CE1b may include a reflective material. For example, the second conductive layer CE1b may include aluminum (Al), but embodiments of this disclosure are not limited thereto. Therefore, the second conductive layer CE1b can constitute a reflector. In addition, due to the high reflectivity of the second conductive layer CE1b, it can be easily identified during the manufacturing process, and therefore the position or relocation position of the light-emitting element ED can be aligned based on the second conductive layer CE1b.

[0172] For example, to form the second conductive layer CE1b as a reflector, the fourth conductive layer CE1d and the third conductive layer CE1c covering the second conductive layer CE1b can be partially removed or etched. For example, a portion of the third conductive layer CE1c and the fourth conductive layer CE1d disposed on the embankment BNK can be removed or etched to expose the upper surface of the second conductive layer CE1b. For example, the central and boundary or edge portions of the third conductive layer CE1c and the fourth conductive layer CE1d can be left, and the remaining portions can be removed, wherein the solder pattern SDP is placed on the central portion. For example, the boundary or edge portions of each of the third conductive layer CE1c configured with titanium (Ti) and the fourth conductive layer CE1d configured with indium tin oxide (ITO) can be left unetched. Therefore, the corrosion of other conductive layers of the first electrode CE1 by the TMAH (tetramethylammonium hydroxide) solution used in the masking process of the first electrode CE1 can be prevented or reduced.

[0173] According to this disclosure, the first conductive layers CE1a and CE1c may comprise titanium (Ti) or molybdenum (Mo). The second conductive layer CE1b may comprise aluminum (Al). The fourth conductive layer CE1d may comprise a transparent conductive oxide layer such as indium tin oxide (ITO) or indium zinc oxide (IZO), which has good adhesion to the solder pattern SDP and is corrosion-resistant and acid-resistant. However, embodiments of this disclosure are not limited thereto.

[0174] The first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d can be deposited sequentially and then patterned by performing photolithography and etching processes, but the embodiments disclosed herein are not limited thereto.

[0175] According to this disclosure, the signal wiring TL, contact electrode CCE, and pad electrode PE disposed on the same layer as the first electrode CE1 can be configured as a multilayer structure of conductive material, but the embodiments of this disclosure are not limited thereto. For example, the signal wiring TL, contact electrode CCE, and pad electrode PE can be formed as a multilayer structure of indium tin oxide (ITO) / titanium (Ti) / aluminum (Al) / titanium (Ti), but the embodiments of this disclosure are not limited thereto.

[0176] According to this disclosure, a solder pattern SDP can be disposed on a first electrode CE1 in each of a plurality of sub-pixels. The solder pattern SDP can electrically connect the first electrode CE1 to the light-emitting element ED by bonding the light-emitting element ED to the first electrode CE1. The anode electrode 134 of the light-emitting element ED and the first electrode CE1 can be electrically connected via eutectic bonding using the solder pattern SDP, but embodiments of this disclosure are not limited thereto. For example, if the solder pattern SDP is configured with indium (In) and the anode electrode (134) of the light-emitting element ED is configured with gold (Au), the solder pattern SDP and the anode electrode 134 can be bonded by applying heat and pressure during the transfer process of the light-emitting element ED. Through eutectic bonding, the light-emitting element ED can be bonded to the solder pattern SDP and the first electrode CE1 without a separate adhesive material. For example, the solder pattern SDP can be configured with indium (In), tin (Sn), or alloys thereof, but embodiments of this disclosure are not limited thereto. For example, the solder pattern SDP can be a bonding pad or a connection pad, but embodiments of this disclosure are not limited thereto.

[0177] According to this disclosure, a passivation layer 116 can be disposed on multiple signal traces TL, multiple first electrodes CE1, multiple contact electrodes CCE, and a third insulating layer 115c. For example, the passivation layer 116 can be disposed in the display area AA, the first non-display area NA1, and the second non-display area NA2. A portion of the passivation layer 116 disposed in the curved area BA can be removed. A portion of the passivation layer 116 covering the multiple pad electrodes PE in the second non-display area NA2 can be removed. The passivation layer 116 can be configured to cover the remaining area except for the curved area BA, the multiple pad electrodes PE, and the area where the solder pattern SDP is disposed, thus reducing the penetration of moisture or impurities into the light-emitting element ED. For example, the passivation layer 116 can be configured as a single-layer or multi-layer structure of silicon oxide (SiOx) or silicon nitride (SiNx), but embodiments of this disclosure are not limited thereto. For example, the passivation layer 116 can be a protective layer or an insulating layer, but embodiments of this disclosure are not limited thereto. For example, the passivation layer 116 may include holes through which the solder pattern SDP is exposed.

[0178] In each of the plurality of sub-pixels, a light-emitting element ED can be disposed on a solder pattern SDP. A first light-emitting element 130 can be disposed in the first sub-pixel SP1. A second light-emitting element 140 can be disposed in the second sub-pixel SP2. A third light-emitting element 150 can be disposed in the third sub-pixel SP3.

[0179] Light-emitting elements (EDs) can be formed on silicon wafers by methods such as metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), sputtering, etc., but the embodiments disclosed herein are not limited thereto.

[0180] Reference Figure 9 The first light-emitting element 130 may include an anode electrode 134, a first semiconductor layer 131, an active layer 132, a second semiconductor layer 133, a cathode electrode 135, and a sealing film 136, but the embodiments disclosed herein are not limited thereto. For example, the first light-emitting element 130 may not include the sealing film 136.

[0181] A first semiconductor layer 131 may be disposed on the solder pattern SDP. A second semiconductor layer 133 may be disposed on the first semiconductor layer 131.

[0182] For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 can be a compound semiconductor of group III-V, group II-VI, etc., and can be doped with impurities or dopants. For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 can be a semiconductor layer doped with n-type impurities, and the other can be a semiconductor layer doped with p-type impurities, but the embodiments of this disclosure are not limited thereto. For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 can be a layer in which n-type or p-type impurities are doped in a material such as gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), indium aluminum phosphide (InAlP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), aluminum gallium arsenide (AlGaAs), or gallium arsenide (GaAs), but the embodiments of this disclosure are not limited thereto. For example, n-type impurities can be silicon (Si), germanium (Ge), selenium (Se), carbon (C), tellurium (Te), tin (Sn), etc., but the embodiments of this disclosure are not limited to these. For example, p-type impurities can be magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), beryllium (Be), etc., but the embodiments of this disclosure are not limited to these.

[0183] For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be a nitride semiconductor containing n-type impurities and a nitride semiconductor containing p-type impurities, respectively, but the embodiments of this disclosure are not limited thereto. For example, the first semiconductor layer 131 may be a nitride semiconductor containing p-type impurities, and the second semiconductor layer 133 may be a nitride semiconductor containing n-type impurities, but the embodiments of this disclosure are not limited thereto.

[0184] An active layer 132 may be disposed between a first semiconductor layer 131 and a second semiconductor layer 133. The active layer 132 emits light by receiving holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. For example, the active layer 132 may be configured as one of a single-well structure, a multi-well structure, a single quantum well structure, a multiple quantum well (MQW) structure, a quantum dot structure, and a quantum wiring structure, but embodiments of this disclosure are not limited thereto. For example, the active layer 132 may be composed of indium gallium nitride (InGaN) or gallium nitride (GaN), but embodiments of this disclosure are not limited thereto.

[0185] As another example, the active layer 132 may include a multiple quantum well (MQW) structure having a well layer and a barrier layer having a higher bandgap than the well layer. For example, the active layer 132 may be composed of an InGaN layer as the well layer and an AlGaN layer as the barrier layer, but embodiments of this disclosure are not limited thereto.

[0186] An anode electrode 134 may be disposed between the first semiconductor layer 131 and the solder pattern SDP. For example, the anode electrode 134 may electrically connect the first semiconductor layer 131 to the first electrode CE1. The anode voltage output from the pixel driving circuit PD may be applied to the first semiconductor layer 131 through signal wiring TL, the first electrode CE1, and the anode electrode 134. For example, the anode electrode 134 may be made of a conductive material capable of eutectic bonding with the solder pattern SDP, but embodiments of this disclosure are not limited thereto. For example, the anode electrode 134 may be composed of gold (Au), tin (Sn), tungsten (W), silicon (Si), silver (Ag), titanium (Ti), iridium (Ir), chromium (Cr), indium (In), zinc (Zn), lead (Pb), nickel (Ni), platinum (Pt), and copper (Cu), or any alloy thereof, but embodiments of this disclosure are not limited thereto.

[0187] A cathode electrode 135 may be disposed on the second semiconductor layer 133. For example, the cathode electrode 135 may electrically connect the second semiconductor layer 133 to the second electrode CE2. The cathode voltage output from the pixel driving circuit PD may be applied to the second semiconductor layer 133 through the contact electrode CCE, the second electrode CE2, and the cathode electrode 135. The cathode electrode 135 may be made of a transparent conductive material so that light emitted from the light-emitting element ED can be guided to the upper side of the light-emitting element ED, but the embodiments of this disclosure are not limited thereto. For example, the cathode electrode 135 may be configured with materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but the embodiments of this disclosure are not limited thereto.

[0188] The sealing film 136 may be disposed on at least a portion of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135. For example, the sealing film 136 may surround at least a portion of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135.

[0189] For example, the sealing film 136 can protect the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133. For example, the sealing film 136 can be disposed on the side surface of the first semiconductor layer 131, the side surface of the active layer 132, and the side surface of the second semiconductor layer 133.

[0190] For example, the sealing film 136 may be disposed on at least a portion of the anode electrode 134 and the cathode electrode 135 (e.g., an edge portion or boundary portion or one side of the anode electrode 134 and an edge portion or boundary portion or one side of the cathode electrode 135). At least a portion of the anode electrode 134 may be exposed from the sealing film 136 so that the anode electrode 134 and the solder pattern SDP can be connected to each other. For example, at least a portion of the cathode electrode 135 may be exposed from the sealing film 136 so that the cathode electrode 135 and the second electrode CE2 can be connected to each other. For example, the sealing film 136 may be configured with an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), but embodiments of this disclosure are not limited thereto.

[0191] As another example, the sealing film 136 may be configured as a resin layer in which reflective material is dispersed, but embodiments of the present disclosure are not limited thereto. For example, the sealing film 136 may be manufactured as a reflector having various structures, but embodiments of the present disclosure are not limited thereto. Light emitted from the active layer 132 can be reflected to the upper side by the sealing film 136, thereby improving light extraction efficiency. For example, the sealing film 136 may be a reflective layer, but embodiments of the present disclosure are not limited thereto.

[0192] According to this disclosure, the light-emitting element (ED) is described as having a vertical structure, but the embodiments of this disclosure are not limited to this. For example, the light-emitting element (ED) may have a lateral structure or a flip-chip structure.

[0193] Although it has been referenced Figure 9 The first light-emitting element 130 has been described, but the second light-emitting element 140 and the third light-emitting element 150 may have a structure that is substantially the same as that of the first light-emitting element 130. For example, the second light-emitting element 140 and the third light-emitting element 150 may be substantially the same as the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, the cathode electrode 135, and the sealing film 136 of the first light-emitting element 130.

[0194] According to this disclosure, a first optical layer 117a may be provided around a plurality of light-emitting elements ED in the display area AA. For example, the first optical layer 117a may be configured to cover a plurality of light-emitting elements ED and a dam portion BNK in a region of a plurality of sub-pixels. For example, the first optical layer 117a may cover a portion of the dam portion BNK, a part of the passivation layer 116, and the gaps between the plurality of light-emitting elements ED. The first optical layer 117a may cover or be provided between the plurality of light-emitting elements ED and between the plurality of dam portions BNK included in a pixel PX. For example, the first optical layer 117a may extend in a first direction (X) and be spaced apart from each other in a second direction (Y). For example, the first optical layer 117a may be configured to surround the side portion of the dam portion BNK and the light-emitting elements ED between the passivation layer 116 and the second electrode CE2, but the embodiments of this disclosure are not limited thereto. For example, the first optical layer 117a may be a first optical insulating layer, a diffusion layer, or a sidewall diffusion layer, but the embodiments of this disclosure are not limited thereto.

[0195] The first optical layer 117a may include an organic insulating material in which fine particles are dispersed, but embodiments of this disclosure are not limited thereto. More details will follow later. Figure 19 The explanation for this is given in the text.

[0196] For example, the first optical layer 117a may be disposed in each of the plurality of pixels PX, or may be disposed in common for some pixels PX disposed in the same row, but the embodiments of this disclosure are not limited thereto. For example, the first optical layer 117a may be disposed in each of the plurality of pixels PX, or the plurality of pixels PX may share a first optical layer 117a. As another example, each of the plurality of sub-pixels may each include the first optical layer 117a, but the embodiments of this disclosure are not limited thereto.

[0197] According to this disclosure, a second optical layer 117b may be disposed on the passivation layer 116 in the display area AA. For example, the second optical layer 117b may be disposed around the first optical layer 117a. For example, the second optical layer 117b may be in contact with the side surface of the first optical layer 117a. For example, the second optical layer 117b may be disposed in the area between a plurality of pixels PX. However, the embodiments of this disclosure are not limited thereto. For example, the second optical layer 117b may be a second optical insulating layer, a diffusion layer, a diffusion layer window, or a window diffusion layer, but the embodiments of this disclosure are not limited thereto.

[0198] The second optical layer 117b may be composed of an organic insulating material, but the embodiments disclosed herein are not limited thereto. The second optical layer 117b may also be made of the same material as the first optical layer 117a, but the embodiments disclosed herein are not limited thereto. More details will follow later. Figure 19The explanation for this is given in the text.

[0199] According to this disclosure, the second electrode CE2 can be disposed on the first optical layer 117a and the second optical layer 117b. For example, the second electrode CE2 can be electrically connected to multiple contact electrodes CCE through contact holes in the second optical layer 117b. For example, the second electrode CE2 can be disposed on multiple light-emitting elements ED. For example, the second electrode CE2 can include a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), but embodiments of this disclosure are not limited thereto. For example, the second electrode CE2 can be configured to contact the cathode electrode 135. For example, the second electrode CE2 can overlap with the first optical layer 117a. For example, it can cover the outer plane of the first optical layer 117a.

[0200] The second electrode CE2 can extend continuously in the first direction of the substrate 110. Therefore, it can be commonly connected to a plurality of pixels PX arranged in the first direction of the substrate 110. For example, the second electrode CE2 can be commonly connected to a plurality of pixels PX.

[0201] According to this disclosure, the second electrode CE2 can extend continuously above the first optical layer 117a, the second optical layer 117b, and the light-emitting element ED. The region where the first optical layer 117a is disposed may include a recessed portion that is more recessed inward than the upper surface of the second optical layer 117b. Therefore, the first portion of the second electrode CE2 disposed on the first optical layer 117a is disposed along the recessed portion, and thus can be disposed at a lower position than the second portion of the second electrode CE2 disposed on the second optical layer 117b.

[0202] A third optical layer 117c may be disposed on the second electrode CE2. The third optical layer 117c may be configured to overlap with the plurality of light-emitting elements ED and the first optical layer 117a. Since the third optical layer 117c is disposed on the second electrode CE2 and the plurality of light-emitting elements ED, it can mitigate the appearance of stains (mura) that may occur on some of the plurality of light-emitting elements ED. For example, when the plurality of light-emitting elements ED are transferred onto the substrate 110 of the display device 1000, process variations, etc., may cause areas with uneven spacing between the plurality of light-emitting elements ED. If the spacing between the plurality of light-emitting elements ED is uneven, the light-emitting areas of the plurality of corresponding light-emitting elements ED may be unevenly disposed, which may in turn make the stains (mura) visible to the user. To solve this problem, the third optical layer 117c is constructed above the plurality of light-emitting elements ED so as to be configured to uniformly diffuse light, and thus can mitigate the phenomenon that the light emitted from some of the light-emitting elements ED appears as stains. Therefore, since the light emitted from the multiple light-emitting elements ED is uniformly diffused by the third optical layer 117c and extracted to the outside of the display device 1000, the brightness uniformity of the display device 1000 can be improved.

[0203] The third optical layer 117c may be composed of an organic insulating material in which fine particles are dispersed, but embodiments of the present disclosure are not limited thereto. For example, the third optical layer 117c may be composed of a siloxane having fine particles (e.g., titanium dioxide (TiO2) particles) dispersed therein, but embodiments of the present disclosure are not limited thereto. For example, the third optical layer 117c may be composed of the same material as the first optical layer 117a, but embodiments of the present disclosure are not limited thereto. For example, the third optical layer 117c may be a diffusion layer or an upper surface diffusion layer, but embodiments of the present disclosure are not limited thereto.

[0204] According to this disclosure, light from multiple light-emitting elements (EDs) can be emitted to the outside of the display device 1000 in a state of being scattered by fine particles dispersed in the third optical layer 117c. The third optical layer 117c can uniformly mix the light emitted from the multiple light-emitting elements (EDs) to further improve the brightness uniformity of the display device 1000. In addition, the light extraction efficiency of the display device 1000 can be improved by the light scattered by the multiple fine particles, thereby enabling the display device 1000 to be driven at low power.

[0205] A black matrix BM can be disposed on the second electrode CE2, the first optical layer 117a, the second optical layer 117b, and the third optical layer 117c in the display area AA. For example, the black matrix BM can fill the contact holes in the second optical layer 117b. The black matrix BM can be formed to cover the display area AA, thereby reducing color mixing and external light reflection from multiple sub-pixels. For example, since the black matrix BM can also be disposed within the contact holes where the second electrode CE2 and the contact electrode CCE are connected to each other, light leakage between multiple adjacent sub-pixels can be prevented or reduced.

[0206] For example, the black matrix BM can be composed of an opaque material, but the embodiments of this disclosure are not limited thereto. For example, the black matrix BM can be an organic insulating material with added black pigment or black dye, but the embodiments of this disclosure are not limited thereto.

[0207] A capping layer 118 may be disposed on the black matrix BM in the display area AA. The capping layer 118 can protect the configuration beneath it. For example, the capping layer 118 may be made of an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the capping layer 118 may be configured with photoresist, polyimide (PI), or photoacryloyl material, etc., but embodiments of this disclosure are not limited thereto. For example, the capping layer 118 may be an outer coating or an insulating layer, but embodiments of this disclosure are not limited thereto.

[0208] On the capping layer 118, the polarizing layer 293 may be disposed via the first adhesive layer 291. On the polarizing layer 293, the capping member 155 may be disposed via the second adhesive layer 295. For example, the first adhesive layer 291 and the second adhesive layer 295 may include an optically transparent adhesive (OCA), an optically transparent resin (OCR), or a pressure-sensitive adhesive (PSA), but embodiments of this disclosure are not limited thereto.

[0209] According to this disclosure, a plurality of pad electrodes PE can be disposed on the third insulating layer 115c in the second non-display area NA2. For example, at least a portion of the plurality of pad electrodes PE can be exposed from the passivation layer 116. For example, the plurality of pad electrodes PE can be electrically connected to the second and fourth connection wiring 122d through contact holes in the third insulating layer 115c.

[0210] An adhesive layer ACF can be disposed on multiple pad electrodes PE. The adhesive layer ACF may be an adhesive layer in which conductive balls are dispersed in an insulating material, but embodiments of the present disclosure are not limited thereto. When heat or pressure is applied to the adhesive layer ACF, the conductive balls may be electrically connected in the portion to which heat or pressure is applied, thereby providing conductive properties. By placing the adhesive layer ACF between the multiple pad electrodes PE and the flexible circuit board (or flexible film) 157, the flexible circuit board (or flexible film) 157 may be attached to or bonded to the multiple pad electrodes PE. For example, the adhesive layer ACF may be an anisotropic conductive film ACF, but embodiments of the present disclosure are not limited thereto.

[0211] A flexible circuit board (or flexible film) 157 can be disposed on the adhesive layer ACF. The flexible circuit board (or flexible film) 157 can be electrically connected to multiple pad electrodes PE through the adhesive layer ACF. Therefore, signals output from the flexible circuit board (or flexible film) 157 and the printed circuit board can be transmitted to the pixel driving circuit PD in the display area AA through the multiple pad electrodes PE, the second and fourth connection wiring 122d, the second and third connection wiring 122c, the second and second connection wiring 122b, and the second and first connection wiring 122a.

[0212] Figures 10 to 13 This is a diagram illustrating an apparatus for applying a display device according to an embodiment of the present disclosure.

[0213] Reference Figures 10 to 13 The display device 1000 according to embodiments of the present disclosure can be included in various devices or electronic devices. For example, see reference to... Figures 10 to 13 Various electronic devices may include wearable devices 1100, mobile devices 1200, laptops 1300 and monitors or TVs 1400, but the embodiments disclosed herein are not limited thereto.

[0214] According to reference Figures 1 to 9 The embodiments described in this disclosure may include wearable device 1100, mobile device 1200, notebook computer 1300, and monitor or TV 1400, each of which may include housing 1005, 1010, 1015, 1020, display panel 100, and display device 1000.

[0215] For example, a display device according to one embodiment of this disclosure can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation systems, vehicle display devices, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptops, monitors, cameras, camcorders, home appliances, etc.

[0216] Figure 14 This is a plan view of a display device according to another embodiment of the present disclosure. Figure 15 It shows that there are settings. Figure 14 A plan view of one of the regions in a plurality of pixel driving circuits. Figure 16 This is a schematic diagram illustrating touch operation of a display device according to another embodiment of the present disclosure.

[0217] Reference Figure 14 and Figure 15 According to another embodiment of the present disclosure, the display area AA of the display device 1000 may include a plurality of driving chips 210 as pixel driving circuits, and a plurality of pixels PX1, PX2, PX3...PX16 including a plurality of light-emitting elements electrically connected to the driving chips 210. Each driving chip 210 can control the light-emitting operation of the plurality of light-emitting elements by providing control signals and power to the plurality of light-emitting elements.

[0218] The substrate 200 may have a shape in which one side is longer than the other. For example, the substrate 200 may include a long side that is longer than the other side and a short side that is shorter than the long side. The short side may be disposed in a first direction X of the substrate 200, and the long side may be disposed in a second direction Y of the substrate 200; however, this is not exhaustive.

[0219] One or more crack detection lines PCDL and PCDR can be positioned in some areas outside the display area NA. Each of the one or more crack detection lines PCDL and PCDR can be positioned along the outer portion of the display area AA to detect defects (e.g., cracks) that may occur in the outer portion of the display area AA. The one or more crack detection lines PCDL and PCDR can be positioned around at least a portion of the side areas, upper area, and lower area of ​​the display area AA. For example, the one or more crack detection lines PCDL and PCDR may include a first crack detection line PCDL and a second crack detection line PCDR.

[0220] The first crack detection line PCDL can be disposed along the left long side of the substrate 200, spanning between the upper and lower corners, and extending at both ends in the upper short side direction and the lower short side direction, respectively. The second crack detection line PCDR can be disposed along the right long side opposite to the first crack detection line PCDL, spanning between the upper and lower corners, and extending at both ends in the upper short side direction and the lower short side direction, respectively. The first crack detection line PCDL and the second crack detection line PCDR can be configured to be spaced apart from each other.

[0221] The first crack detection line PCDL and the second crack detection line PCDR can be configured to overlap with some of the multiple driver chips 210 at the corners. The driver chip configured to overlap with the first crack detection line PCDL and the second crack detection line PCDR can be a passive driver chip 210_n.

[0222] Because it is positioned to overlap with the first crack detection line PCDL or the second crack detection line PCDR at the corner of the substrate 200, the passive driver chip 210_n can be non-electrically connected to at least some of the power wiring or signal wiring. Therefore, the passive driver chip 210_n can be a non-functional driver chip that cannot control multiple light-emitting elements. The passive driver chip 210_n may include at least eight driver chips from a plurality of driver chips 210 disposed in the outermost region along the corner of the substrate 200.

[0223] The substrate 200 may include a trimming line (TRL) outside the non-display area NA. The trimming line (TRL) may refer to a cut area laser-cut during a scribing process to separate multiple individual unit display panels 100 from the substrate 200. The outer side of the trimming line (TRL) can be removed by the scribing process.

[0224] Multiple alignment key patterns 101, 103 may be provided outside the trimming line TRL. These multiple alignment key patterns 101, 103 may include, but are not limited to, a first alignment key pattern 101 and a second alignment key pattern 103. Since the multiple alignment key patterns 101, 103 are provided outside the trimming line TRL, they can be removed during the scribing process.

[0225] The first alignment key pattern 101 can be used for Figure 1 The alignment pattern between the display panel 100 and the cover member 155. A plurality of first alignment key patterns 101 may be provided at the outer region of each corner of the trim line TRL facing the substrate 200. For example, the plurality of first alignment key patterns 101 may include four alignment key patterns, each alignment key pattern being provided at a corresponding one of the four corners of the substrate 200.

[0226] The second alignment key pattern 103 may include various alignment key patterns for aligning components disposed in different layers (e.g., multiple signal lines, contact holes, and multiple drive drivers disposed on the substrate 200) to the correct positions. The second alignment key pattern 103 may include a metallic material. Therefore, the second alignment key pattern 103 may be disposed in the display area AA or the non-display area NA and formed together with multiple signal lines including a metallic material; however, it is only given as an example.

[0227] Multiple driver chips 210, serving as pixel driving circuits, can be arranged on the display area AA of the substrate 200. For example, the multiple driver chips 210 can be arranged in a matrix shape; however, this is not exhaustive.

[0228] On multiple driver chips 210, multiple pixels, including multiple light-emitting elements, can be arranged in a matrix shape. The multiple pixels can be arranged to be spaced apart from each other in a first direction and a second direction intersecting the first direction. The first direction can be the X-axis direction of the display panel 100, and the second direction can be the Y-axis direction of the substrate 200; however, this is not exhaustive. For example, the first direction can be the horizontal or row direction of the substrate 200, and the second direction can be the vertical or column direction of the substrate 200.

[0229] Each of the plurality of pixels may have sub-pixels emitting different colors that are alternately arranged in a first direction of the substrate 200. Additionally, sub-pixels emitting the same color may be arranged in a second direction of the substrate 200. For example, first pixels PX1 to sixteenth pixels PX16 may be arranged in a row direction, which is the first direction. A single pixel PX may include a red R sub-pixel, a green G sub-pixel, and a blue B sub-pixel.

[0230] Multiple light-emitting elements can be arranged corresponding to each sub-pixel. At least one light-emitting element can be arranged in a sub-pixel. For example, two light-emitting elements can be arranged in a sub-pixel. One of the two light-emitting elements can be a primary light-emitting element, and the other can be a redundant light-emitting element. The light-emitting elements can be micro LEDs (μLEDs). Therefore, in the first direction, which is the row direction, the sub-pixels of red (R), green (G), and blue (B) can be arranged in a repeating order.

[0231] Alternatively, sub-pixels emitting the same color can be set in the second direction (i.e., the column direction). For example, sub-pixels of one of the colors red (R), green (G), or blue (B) can be set in the second direction (i.e., the column direction). Sub-pixels emitting the same color can be electrically connected to each other via a first electrode AND_P, AND_R.

[0232] The first electrode AND may include a first line AND_P and a second line AND_R. The first line AND_P and the second line AND_R may be spaced apart from each other in a first direction of the substrate 200. The first line AND_P of the first electrode AND may be connected to a main light-emitting element, and the second line AND_R of the first electrode AND may be connected to a redundant light-emitting element.

[0233] Each of the plurality of second electrodes CTHs may extend in a first direction. Additionally, each of the plurality of second electrodes CTHs may be arranged to be spaced apart from each other in a second direction. Therefore, each second electrode CTH may extend in the first direction to connect to each of the first pixels PX1 to the sixteenth pixels PX16 in each of the plurality of rows (Row1, Row2, Row3, ..., Row16).

[0234] Each of the plurality of driver chips 210 includes a plurality of driver circuits and drives a plurality of light-emitting elements. A single driver chip 210 can be connected to a plurality of first electrodes AND and second electrodes CTH connected to a plurality of pixels PX1, PX2, ..., PX16. For example, one driver chip 210 can drive a plurality of light-emitting elements arranged on the first row (Row1) to the sixteenth row (Row16). In other words, one driver chip 210 can be electrically connected to a plurality of light-emitting elements arranged on the first row (Row1) to the sixteenth row (Row16) via the first electrodes AND and the second electrodes CTH, and the light-emitting operation of the plurality of light-emitting elements can be controlled by providing control signals and power via the first electrodes AND and the second electrodes CTH.

[0235] Multiple first electrodes AND connected to at least one driver chip 210 can be radially connected to connect a first pixel PX1 located at a first position in a first row 210 and a sixteenth pixel PX16 located at a sixteenth position opposite to the first pixel PX1 to the driver chip 210, respectively. For example, rows 1 through 8 can be commonly connected to a single first electrode AND, and rows 9 through 16 can be commonly connected to a different first electrode AND than the one to which rows 1 through 8 are connected. For example, when viewed in a plan view, the shape of the multiple first electrode AND connections can be a rhombus shape or an 'I' shape.

[0236] A display device according to one embodiment of the present disclosure may have an in-unit touch structure that uses each of a plurality of second electrodes CTH as a touch electrode instead of forming a separate touch electrode. Therefore, since a separate touch electrode is not formed, the thickness of the display panel can be reduced.

[0237] Reference Figure 16When a user touches the cover member 155, changes in the first capacitance C1 between the plurality of second electrodes CTH disposed on the display panel 100 and the cover member 155, as well as changes in the second capacitance C2 between the plurality of second electrodes CTH and the plurality of signal wirings M_SL, can be detected and provided to the driver chip 210. The driver chip 210 can then perform touch control functions to provide control signals for operation to the plurality of light-emitting elements based on the touch input. A grounding component GND can be provided on the side opposite to the cover member 155.

[0238] This touch sensing method for capacitive substrates can include a mutual capacitance driving method and a self-capacitance driving method that sense touch by detecting capacitance changes between two types of touch sensors.

[0239] According to one embodiment of the present disclosure, the display device 10 can perform touch sensing and touch driving in a self-capacitance-based touch sensing manner, or it can perform touch sensing and touch driving in a mutual capacitance-based touch sensing manner.

[0240] Figure 17 This is a diagram illustrating a signal waveform diagram when driving a display device according to one embodiment of the present disclosure.

[0241] Reference Figure 17 According to one embodiment of the present disclosure, the display device can perform light emission operation in units of one frame.

[0242] A frame can include a touch area A and a display area B.

[0243] A frame 1 can operate at, for example, a frequency of 60 Hz. In this case, touch segment A can operate at, for example, a frequency of 60 Hz for a first time period, and display segment B can operate at, for example, a frequency of 60 Hz for a second time period longer than the first time period. Therefore, the operation time of touch segment A and the operation time of display segment B within a frame 1 can be different from each other. For example, the operation time of touch segment A can be shorter than the operation time of display segment B.

[0244] Display segment B may include sixteen subframes.

[0245] For example, in a display panel, if eight micro-light-emitting elements (μLEDs) are connected to each anode electrode line serving as the first electrode, then a subframe segment C may include eight pulse signals 1-Row, 2-Row, 3-Row, 4-Row, 5-Row, 6-Row, 7-Row, and 8-Row. That is, embodiments of this disclosure can operate eight micro-light-emitting elements (μLEDs) during a subframe.

[0246] Therefore, in the embodiments of this disclosure, since a frame 1-Frame includes sixteen sub-frames and a sub-frame includes eight pulse signals, 128 micro-light-emitting elements μLEDs can be operated during a frame 1-Frame.

[0247] Embodiments of this disclosure are not limited thereto. For example, if sixteen micro-light-emitting elements (μLEDs) are connected to an anode electrode line serving as the first electrode, a subframe segment C may include sixteen pulse signals. In this case, 256 micro-light-emitting elements (μLEDs) can be operated during a frame 1-Frame.

[0248] A pulse signal (e.g., 5-row) drives a miniature light-emitting element (μLED). A pulse signal period D can include a high-signal segment and a low-signal segment. At this point, the duration of the low-signal segment can be longer than the duration of the high-signal segment.

[0249] In one embodiment of this disclosure, the driving time of the micro light-emitting element μLED can be controlled by applying a timer to the light-emitting transistor T. EM The gate electrode emits a light signal EM to control it.

[0250] The micro-driver (μDriver) can control the application time of the light-emitting signal (EM) using the pulse width (PW). For example, a pulse signal (e.g., 5-row) is applied to a light-emitting transistor (T) with a pulse width (PW). EM In the case of a gate electrode, it can be referred to as 1 grayscale.

[0251] The micro-driver μDriver can control the application time of the luminescent signal EM by adjusting the pulse width PW from at least 1 gray level (Min) to at most 32 gray levels (Max) for a pulse signal (e.g., 5-Row).

[0252] Therefore, the micro-driver μDriver can apply a pulse signal with a pulse width PW adjusted from at least 1 gray level (Min) to at most 32 gray levels (Max) to the light-emitting transistor T. EMThe gate electrode is used to control the emission time of the micro LED corresponding to each sub-pixel of red (R), green (G), or blue (B).

[0253] Figure 18 This illustrates another embodiment according to the present disclosure. Figure 15 An enlarged plan view of region 7 in the image. Figure 19 It is along Figure 18 The cross-sectional view taken from line 8-8 in the diagram. Figure 20 It is shown Figure 19 A cross-sectional view of region 9 in the diagram. And... Figure 21 It is shown Figure 20 A plan view of the joint portion. For ease of explanation, Figure 18 Only the first electrode AND, the second electrode CTH, multiple light-emitting elements 260, the dam layer 250, and the optical insulating layers 271 and 273 are shown.

[0254] Reference Figures 18 to 20 According to another embodiment of the present disclosure, the display device may include a plurality of first electrodes AND disposed on a substrate 200, a plurality of bonding pads 257 disposed on the plurality of first electrodes AND, a plurality of light-emitting elements 260 electrically connected to the plurality of first electrodes AND, optical insulating layers 271, 273, a plurality of second electrodes CTH disposed on the plurality of light-emitting elements 260, and contact electrodes 274.

[0255] Each of the plurality of first electrodes AND can be arranged to be spaced apart from each other in a first direction of the substrate 200. The plurality of first electrodes AND can extend in a second direction intersecting the first direction. The first direction can be the X-axis direction of the substrate 200, and the second direction can be the Y-axis direction of the substrate 200; however, this is not exhaustive. For example, the first direction can be the horizontal or row direction of the substrate 200, and the second direction can be the vertical or column direction of the substrate 200.

[0256] The plurality of first electrodes AND may include a first line AND_P and a second line AND_R. The first line AND_P and the second line AND_R may be configured to be spaced apart from each other in a first direction of the substrate 200. The first line AND_P and the second line AND_R may each include an extension AND_E electrically connected to the light-emitting element 260.

[0257] Each of the first line AND_P and the second line AND_R of the plurality of first electrodes AND can be connected to the bonding pad 257. A plurality of light-emitting elements 260 can be placed on the plurality of bonding pads 257.

[0258] Multiple second electrodes CTH can be disposed on multiple light-emitting elements 260. Each of the multiple second electrodes CTH can be arranged to be spaced apart from each other in a second direction of the substrate 200.

[0259] Multiple second electrodes CTH can extend in a first direction intersecting the second direction. The first direction can be the X-axis direction of the substrate 200, and the second direction can be the Y-axis direction of the substrate 200; however, this is not exhaustive. For example, the first direction can be the horizontal or row direction of the substrate 200, and the second direction can be the vertical or column direction of the substrate 200.

[0260] Multiple first electrodes AND can be referred to as pixel electrodes. Multiple second electrodes CTH can also be referred to as common electrodes. However, this is not exhaustive. For example, multiple first electrodes AND can be Figure 8 The first electrode is CE1. Additionally, multiple second electrodes CTH can be... Figure 8 The second electrode CE2 in the middle.

[0261] Multiple pixels PX can be disposed on the substrate 200. Each of the multiple pixels PX can be provided with a separating region between them. A single pixel can include multiple sub-pixels that emit light of different colors. For example, the multiple sub-pixels can include a first sub-pixel 260R that emits red light, a second sub-pixel 260G that emits green light, and a third sub-pixel 260B that emits blue light.

[0262] Multiple opening regions 281 can be set in the separating area between adjacent pixels PX. For example... Figure 19 As shown, multiple opening regions 281 can be formed by light-blocking patterns 280. Multiple opening regions 281 can be positioned corresponding to the ambient light sensor (ALS; ambient light system).

[0263] Reference Figure 19 The substrate 200 may be an insulating substrate comprising flexible plastic or polymer materials. For example, the substrate 200 may comprise a single-layer or multi-layer structure comprising polyimide, polycarbonate, or polyethylene terephthalate; however, this is not exhaustive. The substrate 200 may be a silicon substrate or a glass substrate.

[0264] A carrier substrate 201 may be disposed on the rear surface of the substrate 200. The carrier substrate 201 may be made of a material that is relatively harder than that of the flexible substrate 200. The carrier substrate 201 may be omitted. Alternatively, the carrier substrate 201 may be removed thereafter.

[0265] On the front surface opposite the rear surface of the substrate 200, a plurality of chip alignment patterns 203 may be formed. The plurality of chip alignment patterns 203 may specify the location where the driver chip 210 will be formed. The plurality of chip alignment patterns 203 may include a metallic material.

[0266] A buffer layer 205 may be disposed on the substrate 200 and the plurality of chip alignment patterns 203. The buffer layer 205 may cover the plurality of chip alignment patterns 203 to flatten the steps caused by the plurality of chip alignment patterns 203. The buffer layer 205 may be formed by stacking single or multiple layers of organic or inorganic insulating materials. For example, organic insulating materials may include (but are not limited to) acrylic resin or photosensitive polyimide. Inorganic insulating materials may include, but are not limited to, silicon oxide (SiOx) or silicon nitride (SiNx). The buffer layer 205 may include a multilayer structure in which organic and inorganic insulating materials are alternately stacked.

[0267] An adhesive layer 207 may be disposed on the buffer layer 205. The adhesive layer 207 may include an acrylic adhesive material.

[0268] Multiple driver chips 210 can be disposed on the adhesive layer 207. The multiple driver chips 210 may include multiple driver circuits to drive multiple light-emitting elements. Therefore, multiple light-emitting elements can be driven according to the same control signal provided from the driver chips 210.

[0269] Multiple driver chips 210 may be included on the pad electrodes 211 on the upper side.

[0270] On the adhesive layer 207, a planarization layer 220 covering multiple driver chips 210 can be provided. The planarization layer 220 may include a first planarization layer 213 and a second planarization layer 215. A protective film 214 may be provided between the first planarization layer 213 and the second planarization layer 215.

[0271] The first planarization layer 213 may be configured to have a thickness equal to a portion of the side surfaces of the plurality of driver chips 210. The first planarization layer 213 may include an organic insulating material. For example, the first planarization layer 213 may include (but is not limited to) a photoactive compound (PAC).

[0272] The protective film 214 may include a first portion 214a disposed on the upper surface of the first planarization layer 213, a third portion 214c disposed on the upper edge portion of each of the plurality of driver chips 210, and a second portion 214b disposed between the first portion 214a and the third portion 214c. The second portion 214b may connect the first portion 214a and the third portion 214c and cover the side surface portion of each of the plurality of driver chips 210.

[0273] The protective film 214 enhances the adhesion between the multiple driver chips 210 and the planarization layer 220 to prevent or reduce gaps between them. By preventing or reducing gaps, problematic situations such as moisture or chemical solutions penetrating into the multiple driver chips 210 during the manufacturing process can be prevented or reduced. The protective film 214 may include an inorganic insulating material. For example, the protective film 214 may include silicon nitride (SiN).

[0274] A second planarization layer 215 may be disposed on the protective film 214. The second planarization layer 215 may include openings that expose the pad electrodes 211 of a plurality of driver chips 210 while covering a third portion 214c of the protective film 214. The second planarization layer 215 may include an organic insulating material. For example, the second planarization layer 215 may include (but is not limited to) a photoactive compound (PAC).

[0275] Multiple wiring patterns 223 can be formed on the second planarization layer 215. The multiple wiring patterns 223 can be formed on the same layer as the pad electrodes 211 of the multiple driver chips 210. The multiple wiring patterns 223 can also be referred to as multiple first connection wirings.

[0276] On the second planarization layer 215, at least one insulating layer 225, 230, 235, 239 covering multiple driver chips 210 can be provided. At least one or more insulating layers 225, 230, 235, 239 may include, but are not limited to, a first insulating layer 225, a second insulating layer 230, a third insulating layer 235, and a fourth insulating layer 239.

[0277] A first insulating layer 225 may be disposed on a second planarization layer 215 and includes first contact holes 226 exposing pad electrodes 211 of each of a plurality of driver chips 210 and a plurality of wiring patterns 223. A second insulating layer 230 may be disposed on the first insulating layer 225 and includes a second contact hole 232. A third insulating layer 235 may be disposed on the second insulating layer 230 and includes a third contact hole 236. A fourth insulating layer 239 may be disposed on the third insulating layer 235 and includes a fourth contact hole 240. The first contact hole 226, the second contact hole 232, the third contact hole 236, and the fourth contact hole 240 may be configured not to overlap with each other in the vertical direction; however, this is not exhaustive.

[0278] Each of at least one or more insulating layers 225, 230, 235, 239 may include multiple signal wirings 227, 233, 237, 241 that electrically connect multiple driver chips 210 and multiple light-emitting elements 260.

[0279] Multiple signal wirings 227, 233, 237, and 241 may include a first signal wiring 227, a second signal wiring 233, a third signal wiring 237, and a fourth signal wiring 241.

[0280] A first signal trace 227 can be disposed on a first contact hole 226 of a first insulating layer 225 and electrically connected to a pad electrode 211 and a plurality of trace patterns 223. A second signal trace 233 can be disposed on a second contact hole 232 of a second insulating layer 230 and electrically connected to the first signal trace 227. A third signal trace 237 can be disposed on a third contact hole 236 of a third insulating layer 235 and electrically connected to the second signal trace 233. A fourth signal trace 241 can be disposed on a fourth contact hole 240 of a fourth insulating layer 239 and electrically connected to the third signal trace 237.

[0281] The first signal wiring 227, the second signal wiring 233, the third signal wiring 237, and the fourth signal wiring 241 can be connected to each other in the vertical direction to electrically connect multiple driver chips 210 and multiple light-emitting elements 260. The fourth signal wiring 241 can be electrically connected to the second electrode CTH. Therefore, control signals provided from the multiple driver chips 210 can be sent to the multiple light-emitting elements 260 to drive them.

[0282] When multiple signal traces 227, 233, 237, and 241 are formed, they can be formed together. Figure 14 At least one of the plurality of alignment key patterns 101, 103 shown. For example, when forming the third signal wiring 237 and the fourth signal wiring 241, a plurality of second alignment key patterns 103 may be formed.

[0283] Multiple dike layers 250 can be disposed on the fourth insulating layer 239. Multiple dike layers 250 can distinguish adjacent sub-pixels from each other. A dike layer can also be referred to as a dike section.

[0284] Multiple first electrodes AND can be disposed on multiple layers 250. Multiple light-emitting elements 260 can be disposed on the multiple first electrodes AND, and the multiple light-emitting elements 260 are electrically connected to the multiple first electrodes AND via bonding pads 257. The bonding pads 257 may also be referred to as solder patterns.

[0285] On each of the plurality of embankment layers 250, at least one or more light-emitting elements 260 may be provided. For example, on one embankment layer 250, two light-emitting elements 260a and 260b emitting the same color may be provided. One of the two light-emitting elements 260a and 260b may be the main light-emitting element 260a, and the other may be the redundant light-emitting element 260b.

[0286] Reference Figure 20On the first electrode, bonding pads 257 may be provided. Bonding pads 257 may be configured with, but are not limited to, TiO2 or tin (Sn) or alloys thereof. For example, see... Figure 9 The bonding pad 257 can be a solder pattern SDP. The bonding pad 257 can be connected to the first connection electrode 267 of the light-emitting element 260. The first connection electrode 267 can be referred to as the anode electrode.

[0287] The first electrode AND may include a multilayer structure comprising a first metal layer 251a, a second metal layer 253, a third metal layer 251b, and a fourth metal layer 254. For example, each component of the first electrode AND may be coupled with... Figure 9 Each component of the first electrode CE1 is identical. For example, the first metal layer 251a may be the first conductive layer CE1a, and the second metal layer 253 may be the second conductive layer CE1b. In addition, the third metal layer 251b may be the third conductive layer CE1c, and the fourth metal layer 254 may be the fourth conductive layer CE1d.

[0288] The second metal layer 253 may have some areas exposed by patterning the fourth metal layer 254 and the third metal layer 251b. For example, refer to Figure 21 The second metal layer 253 may have the shape of four sides surrounding the bonding pads 257 to which the light-emitting element 260 is connected. Viewed in plan view, the fourth metal layer 254 may include a first pattern 254-1 surrounding the outer side of the second metal layer 253, and a second pattern 254-2 extending into the embankment layer 250. The second pattern 254-2 of the fourth metal layer 254 may extend along one side surface of the embankment layer 250. The second pattern 254-2 of the fourth metal layer 254 may be an extension of the first electrode AND, AND_E; however, this is not exhaustive. For example, the extension of the first electrode AND, AND_E, may be a multilayer structure including the first metal layer 251a, the second metal layer 253, the third metal layer 251b, and the fourth metal layer 254.

[0289] Passivation layer 255 may be disposed on the first electrode AND, the dam layer 250, and the fourth insulating layer 239. Passivation layer 255 may include an opening that exposes the bonding pad 257.

[0290] Each of the plurality of light-emitting elements 260 may be disposed on a bonding pad 257 for electrical connection thereto. The light-emitting element 260 may be a micro-light-emitting element μLED, which is a micro-sized light-emitting element.

[0291] The light-emitting element 260 may include a first semiconductor layer 261, an active layer 263 and a second semiconductor layer 265 sequentially deposited on one surface of the first semiconductor layer 261. A first connection electrode 267 may be disposed on one surface of the first semiconductor layer 261, and a second connection electrode 269 may be disposed on one surface of the second semiconductor layer 265. The first connection electrode 267 may be an anode electrode, and the second connection electrode 269 may also be referred to as a cathode electrode.

[0292] Refer again Figure 18 and Figure 19 On the passivation layer 255, optical insulating layers 271 and 273 covering multiple light-emitting elements 260 and the dam layer 250 can be provided. The optical insulating layers 271 and 273 may include a first optical insulating layer 271 and a second optical insulating layer 273. The first optical insulating layer 271 may be referred to as the first optical layer, and the second optical insulating layer 273 may be referred to as the second optical layer.

[0293] The first optical insulating layer 271 may cover some areas of the embankment layer 250, the passivation layer 255, and the area between the plurality of light-emitting elements 260. For example, the first optical insulating layer 271 may cover each of the plurality of sub-pixels. The first optical insulating layer 271 may inclusively cover at least the light-emitting region EA.

[0294] The second optical insulating layer 273 can cover the remaining area except for the area where the first optical insulating layer 271 is disposed. Therefore, the first optical insulating layer 271 can be implemented as an island shape divided for each sub-pixel.

[0295] The first thickness of the first optical insulating layer 271 may be less than the second thickness of the second optical insulating layer 273. Therefore, when viewed from a flat surface, the area where the first optical insulating layer 271 is disposed may include a recessed portion that is recessed more inward than the upper surface of the second optical insulating layer 273.

[0296] The first optical insulating layer 271 may comprise an organic insulating material having a plurality of scattering particles dispersed therein. For example, the plurality of scattering particles may include, but are not limited to, titanium dioxide (TiO2) particles. The organic insulating material may comprise a siloxane resin. The first optical insulating layer 271 can scatter light incident from the plurality of light-emitting elements 260 through the plurality of scattering particles, and allows the scattered light to be emitted toward the light-emitting region EA. Light extraction efficiency can be improved by utilizing the scattering particles to scatter light.

[0297] The second optical insulating layer 273 may be an organic insulating material surrounding the first optical insulating layer 271. The second optical insulating layer 273 may be an organic insulating material that does not contain scattering particles. For example, the second optical insulating layer 273 may include a silicone resin.

[0298] The second electrode CTH can be disposed on multiple light-emitting elements 260. The second electrode CTH may include a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). The second electrode CTH can be configured to contact the second connection electrode 269 of each of the multiple light-emitting elements 260.

[0299] The second electrode CTH can extend continuously in the first direction of the substrate 200. Therefore, it can be commonly connected to a plurality of pixels PX arranged in the first direction of the substrate 200.

[0300] The second electrode CTH can extend continuously above the second optical insulating layer 273, the first optical insulating layer, and the light-emitting element 260. The region where the first optical insulating layer 271 is disposed may include a recessed portion that is more recessed inward than the upper surface of the second optical insulating layer 273. Therefore, the first portion of the second electrode CTH disposed on the first optical insulating layer 271 is disposed along the recessed portion, and thus can be disposed at a lower position than the second portion of the second electrode CTH disposed on the second optical insulating layer 273.

[0301] An upper diffusion film 275 may be disposed on the second electrode CTH. The upper diffusion film 275 may comprise an organic insulating material having a plurality of scattering particles dispersed therein. For example, the plurality of scattering particles may include, but are not limited to, titanium dioxide (TiO2) particles. The organic insulating material may include a siloxane resin. The upper diffusion film 275 may be, but is not limited to, the same material as the first optical insulating layer 271. The upper diffusion film 275 may also be referred to as a third optical layer.

[0302] The refractive index of the upper diffuser 275 can be in the range of 1.50 to 1.55. In one example, the refractive index of the upper diffuser 275 can be 1.53.

[0303] The upper diffuser film 275 can scatter light incident from multiple light-emitting elements 260 through multiple scattering particles, and allows the scattered light to be emitted to the outside. The light extraction efficiency of the display device can be improved by utilizing the scattering particles to scatter light. Therefore, the display device can be driven with low power.

[0304] A light-blocking pattern 280 may be formed on the upper diffusion film 275. The light-blocking pattern 280 may be, but is not limited to, an organic insulating material including black pigment. The light-blocking pattern 280 may fill the contact holes 272 formed on the second optical insulating layer 273. The light-blocking pattern 280 may be referred to as a black matrix.

[0305] When the main light-emitting element 260a is operating normally, the light-blocking pattern 280 can cover the redundant light-emitting element 260b in a sub-pixel. As another example, when the main light-emitting element 260a is defective, the light-blocking pattern 280 can include an opening area that exposes the redundant light-emitting element 260b.

[0306] The light-blocking pattern 280 may include multiple opening regions 281. When a light-blocking pattern 280 with multiple opening regions 281 is formed, it can be as follows: Figure 14 The diagram shows the formation of multiple first alignment key patterns 101. For example, during a process for patterning multiple opening regions 281, second alignment key patterns 101 may be formed. The first alignment key patterns 101 may be used for... Figure 1 The alignment pattern between the display panel 100 and the cover member 155.

[0307] Figure 22 It is along Figure 14 The cross-sectional view taken from line 11-11 in the diagram. Figure 22 In the middle, it will be directed to the reference Figures 14 to 21 The same components described are given the same reference numerals, and their descriptions will be simplified or omitted. Additionally, in Figure 18 Multiple light-emitting elements 260R, 260G, and 260B are shown in the direction of the cutting line 11-11.

[0308] Reference Figure 22 The display panel may include display areas AA and I, fan-out area II, curved area IV, tapered area III, and pad area V. See [link / reference]. Figure 8 Fan-out region II and cone region III can be set in the first non-display region NA1, and see Figure 8 The pad area V can be set in the second non-display area NA2.

[0309] In display areas AA and I, multiple light-emitting elements 260R, 260G, and 260B, as well as multiple driver chips 210 electrically connected to the multiple light-emitting elements 260R, 260G, and 260B, can be disposed. To electrically connect the multiple light-emitting elements 260R, 260G, 260B and the multiple driver chips 210, multiple signal wirings 227, 233, 237, and 241 can be formed and disposed on each of at least one or more insulating layers 225, 230, 235, and 239. The multiple signal wirings 227, 233, 237, and 241 may include a first signal wiring 227, a second signal wiring 233, a third signal wiring 237, and a fourth signal wiring 241. However, this is not exhaustive. For example, the first signal wiring 227, the second signal wiring 233, the third signal wiring 237 and the fourth signal wiring 241 can be referred to as the first and second connecting wiring, the first and third connecting wiring, the first and fourth connecting wiring and the contact electrode, respectively.

[0310] Multiple light-emitting elements 260R, 260G, and 260B may be covered with a first optical insulating layer 271. A second electrode CTH may be disposed on the multiple light-emitting elements 260R, 260G, 260B and the first optical insulating layer 271. An upper diffusion film 275 having multiple scattering particles dispersed therein may be present on the second electrode CTH.

[0311] A light-blocking pattern 280 may be formed on the upper diffusion film 275. A first outer coating 290 may be formed on the light-blocking pattern 280 and the upper diffusion film 275. The first outer coating 290 will be described later. The first outer coating 290 may be referred to as a capping layer.

[0312] On the first outer coating 290, the polarizing layer 293 can be disposed via the first adhesive layer 291. On the polarizing layer 293, the cover member 155 can be disposed via the second adhesive layer 295.

[0313] Fan-out area II can be the area in which multiple wiring patterns 223 and multiple signal wirings 227, 233, 237, 241 provided on display area AA extend to multiple link wirings SL1, SL2, SL3, SL4, SL5 in pad area V. The multiple link wirings SL1, SL2, SL3, SL4, SL5 can be provided in different layers of at least one or more insulating layers 225, 230, 235, 239.

[0314] Multiple link cablings SL1, SL2, SL3, SL4, and SL5 may include a first link cabling SL1, a second link cabling SL2, a third link cabling SL3, a fourth link cabling SL4, and a fifth link cabling SL5.

[0315] Multiple link traces SL1, SL2, SL3, SL4, and SL5 can be formed together with multiple wiring patterns 223 and multiple signal traces 227, 233, 237, and 241, and disposed on the same layer. For example, the first link trace SL1 can be disposed on the same layer as the multiple wiring patterns 223, and the second link trace SL2 can be disposed on the same layer as the first signal trace 227. Furthermore, the third link trace SL3 can be disposed on the same layer as the second signal trace 233, and the fourth link trace SL4 can be disposed on the same layer as the fourth signal trace 237. Additionally, the fifth link trace SL5 can be disposed on the same layer as the fifth signal trace 241.

[0316] In a plurality of link traces SL1, SL2, SL3, SL4, and SL5, a portion of the first link trace SL1 can extend to the pad area V via the bend region IV; however, this is not exhaustive. For example, multiple link traces SL1, SL2, SL3, SL4, and SL5 can extend to the pad area V via the bend region IV. The portion of the first link trace SL1 that extends to the pad area V can be defined as the signal connection trace TRE.

[0317] On the substrate 200 in the bending region IV, a stacked structure including an adhesive layer 207, a first planarization layer 213, multiple signal connection wiring TRE, a first insulating layer 225, a second insulating layer 230 and a third insulating layer 235 can be provided.

[0318] The pad area V may include a first pad trace 226p, a second pad trace 233p, a third pad trace 237p, and a fourth pad trace 241p that are electrically connected to the signal connection traces TRE extending from the display areas AA and I. A pad portion 300 may be provided on the fourth pad trace 241p. The pad portion 300 may be connected to... Figure 14 The flexible circuit board 157 is connected to the printed circuit board 160. Various signals can be sent from the printed circuit board 160 to the display areas AA and I through the pad portion 300, or various signals can be provided from the display areas AA and I to the printed circuit board 160.

[0319] The first pad routing 226p, the second pad routing 233p, the third pad routing 237p, and the fourth pad routing 241p can be formed simultaneously when forming multiple signal routings 227, 233, 237, and 241, and can be disposed on the same layer. For example, the first pad routing 226p can be disposed on the same layer as the first signal routing 227, and the second pad routing 233p can be disposed on the same layer as the second signal routing 233. In addition, the third pad routing 237p can be disposed on the same layer as the third signal routing 237, and the fourth pad routing 241p can be disposed on the same layer as the fourth signal routing 241.

[0320] Furthermore, to prevent or reduce the degradation of the bonding properties of one or more insulating layers and to prevent defects such as delamination or cracking during bending operations in bending region IV, the thickness of the insulating layers can be gradually reduced in tapered region III. In the following text, reference will be made to... Figure 23 Provide a description.

[0321] Figure 23 This is an enlarged cross-sectional view of the conical region according to another embodiment of the present disclosure.

[0322] Reference Figure 23 According to another embodiment of this disclosure, the conical region III may be a section in which the thickness difference between the fan-out region II and the curved region IV gradually decreases. The conical region III may include a first step-reduction region III-1, a second step-reduction region III-2, and a third step-reduction region III-3.

[0323] In another embodiment, the first step-reduction region III-1 can be the region closest to the fan-out region II. For example, on the substrate 200 in the first step-reduction region III-1, a first layer stack structure including an adhesive layer 207, a planarization layer 220, a signal connection wiring TRE, a fourth insulating layer 239, a third insulating layer 235, a second insulating layer 230, and a first insulating layer 225 can be provided. Therefore, it has the largest first thickness.

[0324] In the second step-reduction region III-2, a second layer stack structure including an adhesive layer 207, a signal connection wiring TRE, a fourth insulating layer 239, a third insulating layer 235, a second insulating layer 230, and a first insulating layer 225 can be provided. In the second step-reduction region III-2, the planarization layer 220 can be omitted. Therefore, the second step-reduction region III-2 can have a second thickness less than the first thickness. On the substrate 200 in the third step-reduction region III-3, a third layer stack structure including an adhesive layer 207, a signal connection wiring TRE, a third insulating layer 235, a second insulating layer 230, and a first insulating layer 225 can be provided. In the third step-reduction region III-3, the fourth insulating layer 239 can be omitted. Therefore, the third step-reduction region III-3 can have a third thickness less than the second thickness.

[0325] On the substrate 200 in the bending region IV, a fourth layer stack structure including an adhesive layer 207, a signal connection wiring TRE, a second insulating layer 230, and a first insulating layer 225 can be provided. In the bending region IV, the fourth insulating layer 239 and the third insulating layer 235 can be omitted. Thus, the bending region IV can have a fourth thickness that is less than the third thickness and is minimal.

[0326] The layered structure of the insulating layers can be configured such that the thickness gradually decreases from the tapered region III to the bending region IV. In the bending region IV, the bonding properties between one or more insulating layers can be prevented or reduced from deteriorating during the bending operation. Therefore, defects such as delamination and cracks between one or more insulating layers can be prevented or reduced. Consequently, defects that may occur when moisture penetrates into the signal connection wiring TRE through cracks, etc., can be prevented or reduced, thus preventing short circuits or disconnections in the signal connection wiring TRE.

[0327] Figure 24 The display device according to another embodiment of this disclosure is along Figure 14 The cross-sectional view taken by cutting line 13-13 in the figure. Figure 25 This is a diagram illustrating the mechanism by which the undercut portion appears. Figure 24 In the middle, stubbornness and reference Figures 14 to 23 The same components described are given the same reference symbols, and their repeated descriptions will be omitted.

[0328] Reference Figure 24 A first outer coating layer 290 may be disposed on the light-blocking pattern 280 and the optical insulating layers 271 and 273. A polarizing layer 293 may be disposed on the first outer coating layer 290 via a first adhesive layer 291. A cover member 155 may be disposed on the polarizing layer 293 via a second adhesive layer 295.

[0329] The first outer coating 290 can at least cover the area where multiple light-emitting elements 260R, 260G, and 260B are disposed. One surface of the first outer coating 290 can be configured to contact the upper diffusion film 275. The first outer coating 290 can cover the display areas AA and I while extending to the fan-out area II; however, this is not exhaustive.

[0330] The first outer coating 290 may include an organic insulating material. The first outer coating 290 may include a first polymeric insulating material having a plurality of scattering particles dispersed therein. For example, the first polymeric insulating material may include an organosiloxane resin, and the plurality of scattering particles may include hollow silica. Hollow silica has particles with empty spaces on its surface and inside, and therefore has a relatively low refractive index compared to solid particles with internal filling. Therefore, an organosiloxane resin having hollow silica dispersed therein may have a relatively low refractive index than a single organosiloxane resin.

[0331] The first outer coating 290 may have a first refractive index that is relatively smaller than that of the upper diffusion film 275. The first refractive index of the first outer coating 290 may be less than 1.4. The first refractive index may be in the range of 1.37 to 1.39. In one example, the refractive index of the first outer coating 290 may be 1.38.

[0332] Light emitted from the multiple light-emitting elements 260R, 260G, and 260B, which serve as light sources, can pass through the upper diffusion film 275, the first outer coating 290, the polarizing layer 293, and the cover member 155 to be emitted to the outside.

[0333] A portion of the light incident on polarization layer 293 (with an incident angle greater than the total internal reflection angle) is not emitted to the outside but disappears through total internal reflection. As the amount of light undergoing total internal reflection in polarization layer 293 increases, the amount of light disappearing also increases, thereby reducing light extraction efficiency. In view of the above, light needs to be incident on polarization layer 293 at an incident angle smaller than the total internal reflection angle to reduce the amount of light undergoing total internal reflection in polarization layer 293.

[0334] To this end, a first outer coating 290 with a first refractive index lower than that of the upper diffuser 275 can be provided. By providing a first outer coating 290 with a refractive index lower than that of the upper diffuser 275, the proportion of light undergoing total internal reflection at the boundary can be increased.

[0335] Light that is completely reflected at the boundary surface of the upper diffusion film 275 can be recycled and incident on the polarization layer 293 through a process such as re-reflection. In this case, the light incident on the polarization layer 293 is incident at an angle of incidence smaller than the angle of total internal reflection, which reduces the amount of light undergoing total internal reflection in the polarization layer 293. As a result, the amount of light emitted from the polarization layer 293 to the outside increases, thereby improving the light extraction efficiency.

[0336] However, the first outer coating 290 with a low refractive index may have an undercut portion 400 formed along the edge.

[0337] Reference Figure 25 Because of the difference in curing degree between corresponding areas of the first outer coating 290 during the execution of the photoprocess to pattern the first outer coating 290, the undercut portion 400 can be formed and the edge portion removed.

[0338] A mask M, including an opening, can be disposed on the first outer coating 290, and a photolithography process can be performed thereon. Figure 25 (a)). The area corresponding to the opening may be the area where the first outer coating 290 is retained. The area corresponding to the mask M may be the area where the first outer coating 290 has been removed. For example, the area corresponding to the mask M may be the outer side of the edge portion of the first outer coating 290.

[0339] The first outer coating 290 may include a first polymeric insulating material having a plurality of scattering particles dispersed therein. The first polymeric insulating material may include an organosiloxane resin, and the plurality of scattering particles may include hollow silica.

[0340] When photolithography is performed on the first outer coating 290 through an opening in the mask M, the area corresponding to the opening can be illuminated using the exposure required for curing. However, diffracted light can penetrate into some areas blocked by the mask M. In the portion of the first outer coating 290 where diffracted light is transmitted, the diffracted light disappears as it travels towards the lower end, resulting in a reduced exposure compared to the upper end. For example, the exposure may be further reduced in the lower portion as the light is scattered by multiple scattering particles dispersed within the first polymer insulating material.

[0341] It can be used as a post-exposure processing ( Figure 25 (b) Heat treatment is performed to cure portions of the first outer coating 290 that have already been exposed. Regions corresponding to the openings of the mask M can be fully cured when they receive sufficient exposure. However, portions blocked by the transmitted diffracted light from the mask M may receive insufficient exposure, resulting in inadequate curing. For example, the edge portion 290E of the first outer coating 290 may have insufficient curing.

[0342] If the curing degree of the 290E edge portion is insufficient, the developing solution is used to perform the developing process. Figure 25 (c) can then be removed by developing a solution to remove the edge portion 290E, thereby forming the undercut portion 400. Figure 25 (d)

[0343] The undercut portion 400 may become a penetration path susceptible to moisture penetration, or may cause cracks in the first outer coating 290 during subsequent processes.

[0344] To prevent or reduce the occurrence of undercut portions 400, the first outer coating 290 will be formed without any scattering particles dispersed therein, which will result in a high refractive index; however, the light extraction efficiency will be reduced.

[0345] For example, if a first outer coating 290 with a high refractive index (containing no dispersed scattering particles) is applied to the upper diffuser 275, there will be no difference in refractive index between the upper diffuser 275 and the first outer coating 290, causing most of the light to not be completely reflected at the boundary surface of the upper diffuser 275. Then, the amount of light undergoing total internal reflection in the polarization layer 293 will increase, thus increasing the amount of light lost and resulting in reduced light extraction efficiency.

[0346] In view of the above, another embodiment of the present disclosure provides a multilayer structure in which a plurality of outer coatings are formed to have different refractive indices to improve light extraction efficiency while preventing or reducing defects caused by undercut portions.

[0347] Figure 26 This is a plan view showing the display panel of a display device according to another embodiment of the present disclosure. Figure 27 It is along Figure 26 The cross-sectional view taken by cutting line 16-16 in the figure. Figure 28 It is along Figure 26 The cross-sectional view taken by cutting line 17-17 in the figure.

[0348] For ease of explanation, Figure 26 In this example, only a plurality of driver chips 210, a first outer coating 450, and a second outer coating 460 are illustrated on the display panel 100. Figures 26 to 28 In the middle, it will be directed to reference Figures 14 to 23 The same components described are given the same reference symbols, and their repeated descriptions will be omitted.

[0349] Reference Figures 26 to 28A first outer coating layer 450 may be disposed on the light-blocking pattern 280 and the optical insulating layers 271 and 273. A second outer coating layer 460 may be disposed on the first outer coating layer 450. A first adhesive layer 291 may be disposed on one surface of the second outer coating layer 460. A polarizing layer 293 may be disposed on the first adhesive layer 291. The cover member 155 may be disposed on the polarizing layer 293 via the second adhesive layer 295.

[0350] The display panel 100 may include a top side, a bottom side, a left side, and a right side. In the bottom direction adjacent to the curved region IV, a first outer coating 450 may be disposed on the display regions AA and I and in the non-display areas outside the display regions AA and I. In areas other than the curved region IV (e.g., in the top, left, and right directions), the first outer coating 450 may be disposed in the non-display areas outside the display regions AA and I.

[0351] Reference Figure 27 In the downward direction adjacent to the curved region IV, a first outer coating 450 may be disposed on the light-blocking pattern 280 and the optical insulating layers 271, 273. The first outer coating 450 may at least cover the area where multiple light-emitting elements 260R, 260G, 260B are disposed. One surface of the first outer coating 450 may be configured to contact the upper diffusion film 275. The first outer coating 450 may extend from the display regions AA, I to the fan-out region II; however, this is not exhaustive.

[0352] Reference Figure 28 In areas other than the curved region IV (e.g., in the upper, left, and right directions), the first outer coating 450 can be disposed in a non-display area outside the display areas AA and I. Therefore, one surface of the first outer coating 450 can be configured to contact the fourth insulating layer 239 in areas other than the curved region IV.

[0353] The first outer coating 450 may include an organic insulating material. The first outer coating 450 may include a first polymeric insulating material having a plurality of scattering particles dispersed therein. For example, the first polymeric insulating material may include an organosiloxane resin, and the plurality of scattering particles may include hollow silica.

[0354] The first refractive index of the first outer coating 450 can be relatively smaller than the refractive index of the upper diffusion film 275. The first refractive index of the first outer coating 290 can be less than 1.4. The first refractive index can be in the range of 1.37 to 1.39. In one example, the refractive index of the first outer coating 450 can be 1.38.

[0355] Because the first outer coating 450 has a low refractive index, which is lower than that of the upper diffuser 275, total internal reflection at the interface between the upper diffuser 285 and the first outer coating 450 is increased, thereby improving light emission efficiency. However, in the case where the first outer coating 450 has a low refractive index and does not contain dispersed scattering particles, an undercut portion 400 may be formed along the edge portion.

[0356] The undercut portion 400 may be formed on the lower surface of the edge portion of the outer end portion of the first outer coating 450. The undercut portion 400 may be shaped to be further recessed inward than the outer end portion of the first outer coating 450. The first outer coating 450 on which the undercut portion 400 is formed may include a lower surface 450b, an upper surface 450t opposite to the lower surface 450b, a side surface 450s connecting the lower surface 450b and the upper surface 450t, and an inclined surface 450i inclined from the side surface 450s toward the lower surface 450b.

[0357] The inclined surface 450i of the first outer coating 450 can have a straight shape, a curved shape, or a non-uniform shape.

[0358] The undercut portion 400 may be the space between the inclined surface 450i of the first outer coating 450 and the second optical insulating layer 273. Alternatively, in regions other than the curved region IV, the undercut portion 400 may be the space between the inclined surface 450i of the first outer coating 450 and the fourth insulating layer 239. In one example, the height of the undercut portion 400 may decrease from the outer end of the first outer coating 450 toward the inward side.

[0359] The undercut portion 400 may become a penetration path susceptible to moisture penetration, or may cause cracks in the first outer coating 450 during subsequent processes.

[0360] For example, the undercut portion 400 may be formed at a location where it overlaps with the fourth signal wiring 241, which is one of the multiple signal wirings 227, 233, 237, 241 disposed on the uppermost display area I. In this case, a portion of the surface of the fourth signal wiring 241 may be exposed by the undercut portion 400. If moisture or the like penetrates into the exposed portion of the surface, the metallic material of the fourth signal wiring 241 may oxidize and corrode. Consequently, signals may not be delivered to the display area, thus problematically reducing the reliability of the display device.

[0361] Additionally, when subjected to external physical impact, cracks may appear in the undercut portion 400, forming a space between the inclined surface 450i of the first outer coating 450 and the second optical insulating layer 273. If the crack propagates toward the display area I, a defect will appear in the display area I.

[0362] In view of the above, according to one embodiment of the present disclosure, a second outer coating 460 may be provided on the first outer coating 450 to prevent or reduce defects caused by the undercut portion 400. The second outer coating 460 may fill the undercut portion 400 formed along the edge portion of the first outer coating 450. For example, the undercut portion 400 may be formed continuously along at least one edge portion of the first outer coating 450; however, this is not exhaustive. The undercut portion 400 may be formed discontinuously along the edge portion of the first outer coating 450.

[0363] The edge portion can include the top edge portion, the bottom edge portion, the left edge portion, and the right edge portion.

[0364] The second outer coating 460 may be shaped to surround the edge portion of the first outer coating 450, which includes the undercut portion 400. The first outer coating 450 and the second outer coating 460 may be in contact with each other. For example, the second outer coating 460 may be in contact with at least a portion of the upper surface 450t of the first outer coating 450, the side surface 450s connecting the lower surface 450b and the upper surface 450t, and the inclined surface 450i that slopes from the side surface 450s toward the lower surface 450b.

[0365] The second outer coating 460 may include an extension protruding into a space in the lower region of the edge portion of the first outer coating 450. The extension of the second outer coating 460 may be shaped to insert into the undercut portion 400. The extension of the second outer coating 460 may be shaped to be further recessed inward than the outer end portion of the first outer coating 450.

[0366] The second outer coating 460 can be formed to surround the edge portion of the first outer coating 450. Therefore, the contact area of ​​the second outer coating 460 with the inclined surface 450i of the first outer coating 450 can be increased. By increasing the contact area between the first outer coating 450 and the second outer coating 460, the bonding strength between the different organic insulating layers can be increased. Therefore, the occurrence of defects caused by delamination between the first outer coating 450 and the second outer coating 460 can be prevented or reduced.

[0367] The inclined surface 450i of the first outer coating 450 can have a straight shape, a curved shape, or a non-uniform shape. Therefore, the contact area of ​​the second outer coating 460 with the inclined surface 450i of the first outer coating 450 can be further increased.

[0368] The second outer coating 460 may include an organic insulating material. The second outer coating 460 may also be a second polymer insulating material. For example, the second polymer insulating material may include an acrylic resin. The second outer coating 460 contains no scattering particles within the second polymer insulating material to prevent or reduce undercutting.

[0369] The second outer coating 460 may have a second refractive index that is relatively greater than the first refractive index of the first outer coating 450. The second refractive index of the second outer coating 460 may be in the range of 1.5 to 1.6.

[0370] The second outer coating 460 has a higher refractive index than the first outer coating 450, thereby preventing or reducing undercut portions at the edges of the second outer coating 460. Therefore, the reliability of the display device can be improved.

[0371] For example, in performing a photolithography process for patterning the second outer coating 460, the photolithography process can be performed with a mask in place. The area corresponding to the opening of the mask can be the area where the second outer coating 460 is retained, and the area corresponding to the mask can be the area where the second outer coating 460 has been removed. For example, the area corresponding to the mask can be the outer side of the edge portion of the second outer coating 460.

[0372] When the second outer coating 460 is irradiated with light through the opening of the mask, the area corresponding to the opening can be irradiated with the exposure required for curing. Furthermore, the second outer coating 460 can be a second polymer insulating material without any dispersed scattering particles. Therefore, a portion of the area blocked by the mask of transmitted diffracted light can be irradiated with the exposure required for curing without reducing the total exposure.

[0373] In the heat treatment process following the photolithography process, the second outer coating 460 does not exhibit regional differences in its curing degree; therefore, even when the development process is performed, its edge portions are retained without being removed. Thus, undercut portions in the edge portions of the second outer coating 460 can be prevented or reduced.

[0374] Therefore, according to another embodiment of this disclosure, not only can the light extraction efficiency be improved, but the causes of the undercut portion becoming a defect can also be prevented or reduced, thereby realizing a display device with reliability.

[0375] In another embodiment of this disclosure, a configuration in which two layers (i.e., a first outer coating 450 and a second outer coating 460) are stacked is described; however, this is not exhaustive. For example, each of the first outer coating 450 and the second outer coating 460 may include three or more layers.

[0376] Figure 29 This is a plan view showing the display panel of a display device according to another embodiment of the present disclosure. Figure 30 It is along Figure 29 The cross-sectional view taken by cutting line 19-19 in the figure. Figure 31 It is along Figure 29The cross-sectional view taken by cutting line 20-20 in the diagram.

[0377] For ease of explanation, Figure 29 In this example, only the driver chip 210, the first outer coating 450, and the second outer coating 460 are shown on the display panel 100. Figures 29 to 31 In the middle, it will be directed to reference Figures 14 to 23 The same components described are given the same reference symbols, and their descriptions are simplified or omitted.

[0378] Reference Figures 29 to 31 A first outer coating 450 may be disposed on the display panel 100. The display panel 100 may include an upper side, a lower side, a left side, and a right side. In the lower direction adjacent to the curved region IV, the first outer coating 450 may be disposed on the display regions AA and I and in the non-display areas outside the display regions AA and I. In areas other than the curved region IV (e.g., in the upper direction, the left direction, and the right direction), the first outer coating 450 may be disposed in the non-display areas outside the display regions AA and I.

[0379] Reference Figure 30 In the downward direction adjacent to the curved region IV, a first outer coating 450 may be disposed on the light-blocking pattern 280 and the optical insulating layers 271, 273. The first outer coating 450 may at least cover the area where multiple light-emitting elements 260R, 260G, 260B are disposed. One surface of the first outer coating 450 may be configured to contact the upper diffusion film 275.

[0380] Reference Figure 31 In areas other than the curved region IV (e.g., in the upper, left, and right directions), the first outer coating 450 can be disposed in a non-display area outside the display areas AA and I. Therefore, one surface of the first outer coating 450 can be configured to contact the fourth insulating layer 239 in areas other than the curved region IV.

[0381] The first refractive index of the first outer coating 450 can be a low refractive index, lower than that of the upper diffuser 275. Therefore, total internal reflection increases at the interface between the upper diffuser 285 and the first outer coating 450, allowing light incident on the polarizing layer 293 to be incident at an angle smaller than the angle of total internal reflection. This reduces the amount of light lost through total internal reflection in the polarizing layer 293, thereby improving luminous efficiency. The first outer coating 450 with a low refractive index can have an undercut portion 400 formed along its edge.

[0382] The undercut portion 400 may be provided on the lower surface of the edge portion of the outer end portion of the first outer coating 450. The undercut portion 400 may be shaped to be further recessed inward than the outer end portion of the first outer coating 450. The first outer coating 450 on which the undercut portion 400 is formed may include a lower surface 450b, an upper surface 450t opposite to the lower surface 450b, a side surface 450s connecting the lower surface 450b and the upper surface 450t, and an inclined surface 450i inclined from the side surface 450s toward the lower surface 450b.

[0383] A second outer coating 460 may be provided outside the end of the side surface 450b of the first outer coating 450. In one example, the first outer coating 450 and the second outer coating 460 may have the same upper surface height. In another example, the second outer coating 460 may partially cover the edge portion of the upper surface 450t of the first outer coating 450.

[0384] The second outer coating 460 may fill the undercut portion 400 formed along the edge portion of the first outer coating 450. For example, the undercut portion 400 may be formed continuously along at least one edge portion of the first outer coating 450; however, this is not exhaustive. The undercut portion 400 may be formed discontinuously along the edge portion of the first outer coating 450.

[0385] The first outer coating 450 and the second outer coating 460 may be in contact with each other. For example, the second outer coating 460 may be in contact with at least the side surface 450s connecting the lower surface 450b and the upper surface 450t of the first outer coating 450, and the inclined surface 450i inclined from the side surface 450s toward the lower surface 450b.

[0386] The second outer coating 460 may include an extension protruding into a space in the lower region of the edge portion of the first outer coating 450. The extension of the second outer coating 460 may be shaped to insert into the undercut portion 400. The extension of the second outer coating 460 may be shaped to be further recessed inward than the outer end portion of the first outer coating 450.

[0387] Since the second outer coating 460 is disposed along the outer side of the end of the side surface 450b of the first outer coating 450, the first adhesive layer 291 can be disposed on one surface of the first outer coating 450. A polarizing layer 293 can be disposed on the first adhesive layer 291. The cover member 155 can be disposed on the polarizing layer 293 via the second adhesive layer 295.

[0388] According to another embodiment of this disclosure, the second outer coating 460 may be partially formed in the portion of the first outer coating 450 in which the undercut portion 400 is formed, thereby reducing manufacturing costs.

[0389] According to another embodiment of this disclosure, not only can the light extraction efficiency be improved, but the causes of the undercut portion becoming a defect can also be prevented or reduced, thereby realizing a display device with reliability.

[0390] The display device according to various embodiments of the present disclosure can be described as follows.

[0391] A display device according to one embodiment of the present disclosure may include: a substrate; a plurality of driving chips disposed on the substrate; a plurality of light-emitting elements disposed on the driving chips and electrically connected to each of the driving chips; an optical insulating layer covering the plurality of light-emitting elements; a first outer coating disposed on the optical insulating layer; and a second outer coating disposed on the first outer coating, wherein the refractive index of the first outer coating may be lower than the refractive index of the second outer coating.

[0392] According to various embodiments of this disclosure, the first outer coating may at least cover the area in which a plurality of light-emitting elements are disposed.

[0393] According to various embodiments of the present disclosure, the first outer coating may include a first polymer insulating material having a plurality of scattering particles dispersed therein, and the second outer coating may be configured with a second polymer insulating material.

[0394] According to various embodiments of this disclosure, the plurality of scattering particles may include hollow silicon dioxide.

[0395] According to various embodiments of this disclosure, the first polymer insulating material may include an organosiloxane resin, and the second polymer insulating material may include an acrylic resin.

[0396] According to various embodiments of this disclosure, the second outer coating may include an extension in the lower region that protrudes into the edge portion of the first outer coating.

[0397] According to various embodiments of this disclosure, the extension portion may be further recessed inward than the outer end portion of the first outer coating.

[0398] According to various embodiments of this disclosure, multiple light-emitting elements may include micro light-emitting elements.

[0399] According to various embodiments of this disclosure, the first outer coating and the second outer coating can be in contact with each other.

[0400] A display device according to one embodiment of the present disclosure may include: a substrate; a plurality of driving chips disposed on the substrate; a plurality of light-emitting elements disposed on the driving chips and electrically connected to each of the plurality of driving chips; an optical insulating layer covering the plurality of light-emitting elements; a first outer coating layer located on the optical insulating layer and including an undercut portion formed along its edge portion; and a second outer coating layer filling the undercut portion.

[0401] According to various embodiments of this disclosure, the second outer coating may surround the edge portion of the first outer coating, including the undercut portion.

[0402] According to various embodiments of this disclosure, the undercut portion can be positioned further inside than the outer end portion of the second outer coating.

[0403] According to various embodiments of this disclosure, the undercut portion may be further recessed inward than the outer end portion of the first outer coating.

[0404] According to various embodiments of this disclosure, the undercut portion may be disposed along the lower surface of the edge portion of the first outer coating.

[0405] According to various embodiments of the present disclosure, the first outer coating may include a lower surface, an upper surface opposite to the lower surface, a side surface connecting the lower surface and the upper surface, and an inclined surface that slopes from the side surface toward the lower surface, and the undercut portion may be the space between the inclined surface and the optical insulating layer.

[0406] According to various embodiments of this disclosure, the second outer coating may contact the upper surface, side surface and inclined surface of the first outer coating.

[0407] According to various embodiments of this disclosure, the second outer coating may contact the side surface and inclined surface of the first outer coating.

[0408] According to various embodiments of this disclosure, the refractive index of the first outer coating may be lower than that of the second outer coating.

[0409] According to various embodiments of the present disclosure, the first outer coating may include a first polymer insulating material having a plurality of scattering particles dispersed therein, and the second outer coating may be configured with a second polymer insulating material.

[0410] According to various embodiments of this disclosure, the first polymer insulating material may include an organosiloxane resin, and the plurality of scattering particles may include hollow silicon dioxide.

[0411] According to various embodiments of this disclosure, multiple light-emitting elements may include micro light-emitting elements.

[0412] According to various embodiments of this disclosure, multiple light-emitting elements may include micro light-emitting elements having a vertical structure.

[0413] According to various embodiments of the present disclosure, the display device may further include: a dam, on which a plurality of light-emitting elements are disposed; a first electrode, disposed between the dam and one side of each light-emitting element and electrically connected to a plurality of pixel driving circuits; and a second electrode, disposed on the other side of each light-emitting element and opposite to the first electrode.

[0414] According to various embodiments of this disclosure, each light-emitting element can be electrically connected to the first electrode via eutectic bonding.

[0415] Although embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, those skilled in the art should understand that the present disclosure is not necessarily limited to the above embodiments, and that the above embodiments can be modified without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical concept of the present disclosure, but rather to explain the technical concept of the present disclosure, and the scope of the technical concept of the present disclosure is not limited to these embodiments. Therefore, it should be understood that the above embodiments are given by way of example only in all respects and are not for limiting purposes.

Claims

1. A display device, the display device comprising: substrate; Multiple driver chips are disposed on the substrate; A plurality of light-emitting elements are disposed on one of the plurality of driving chips, and the plurality of light-emitting elements are electrically connected to the one of the plurality of driving chips; An optical insulating layer covering the plurality of light-emitting elements; A first outer coating layer is disposed on the optical insulating layer; as well as A second outer coating is applied over the first outer coating. The refractive index of the first outer coating is lower than that of the second outer coating.

2. The display device according to claim 1, wherein, The first outer coating covers at least the area where the plurality of light-emitting elements are disposed.

3. The display device according to claim 1, wherein, The first outer coating comprises a first polymer insulating material having a plurality of scattering particles dispersed therein, and The second outer coating comprises a second polymer insulating material.

4. The display device according to claim 3, wherein, The plurality of scattering particles comprise hollow silicon dioxide.

5. The display device according to claim 3, wherein, The first polymer insulating material comprises an organosiloxane resin, and The second polymer insulating material includes acrylic resin.

6. The display device according to claim 1, wherein, The second outer coating includes an extension in the lower region that protrudes into the edge portion of the first outer coating.

7. The display device according to claim 6, wherein, The extended portion is further recessed inward than the outer end portion of the first outer coating.

8. The display device according to claim 1, wherein, The plurality of light-emitting elements includes at least one micro light-emitting element.

9. The display device according to claim 1, wherein, The first outer coating and the second outer coating are in contact with each other.

10. A display device, the display device comprising: substrate; Multiple driver chips are disposed on the substrate; A plurality of light-emitting elements are disposed on one of the plurality of driving chips, and the plurality of light-emitting elements are electrically connected to the one of the plurality of driving chips; An optical insulating layer covering the plurality of light-emitting elements; A first outer coating layer is located on the optical insulating layer, and the first outer coating layer includes an undercut portion formed along an edge portion of the first outer coating layer; as well as A second outer coating is applied to fill the undercut portion.

11. The display device according to claim 10, wherein, The second outer coating surrounds the edge portion of the first outer coating, the edge portion of the first outer coating including the undercut portion.

12. The display device according to claim 10, wherein, The undercut portion of the first outer coating is positioned further inside than the outer end portion of the second outer coating.

13. The display device according to claim 10, wherein, The undercut portion of the first outer coating is further recessed inward than the outer end portion of the first outer coating.

14. The display device according to claim 10, wherein, The undercut portion of the first outer coating is disposed along the lower surface of the edge portion of the first outer coating.

15. The display device according to claim 10, wherein, The first outer coating includes: Lower surface; The upper surface is opposite to the lower surface; Side surface, the side surface connecting the lower surface and the upper surface; and An inclined surface, the inclined surface being inclined from the side surface toward the lower surface, and Wherein, the undercut portion of the first outer coating is the space between the inclined surface and the optical insulating layer.

16. The display device according to claim 15, wherein, The second outer coating is in contact with the upper surface of the first outer coating, the side surface of the first outer coating, and the inclined surface of the first outer coating.

17. The display device according to claim 15, wherein, The second outer coating is in contact with the inclined surface of the first outer coating and the side surface of the first outer coating.

18. The display device according to claim 10, wherein, The refractive index of the first outer coating is lower than that of the second outer coating.

19. The display device according to claim 18, wherein, The first outer coating comprises a first polymer insulating material having a plurality of scattering particles dispersed therein. The second outer coating comprises a second polymer insulating material, and The first polymer insulating material comprises an organosiloxane resin, and the plurality of scattering particles comprise hollow silicon dioxide.

20. The display device according to claim 10, wherein, The plurality of light-emitting elements include micro light-emitting elements.

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