A method for burn-in testing of a multi-chip package

Abstract

The present application relates to the technical field of chip package aging test, in particular to a kind of aging test method of multi-chip package.The present application is related to the abnormal characteristics of real-time analysis current waveform and is associated with high-resolution temperature distribution change, and then realize before calculating core particle completely failure, accurately determine its " near scrap period " state, so that test system can actively stop aging test to critical device, avoid sample damage or burn due to excessive failure, preserve complete, valuable sample for subsequent nondestructive analysis, secondly, the present application adopts the strategy of current and thermal imaging data fusion analysis, through the double criterion of " current abnormal risk value " and " temperature deterioration index ", greatly reduce the misjudgment and omission caused by single parameter monitoring, first through current abnormality lock suspicious computing core particle, then determine the temperature deterioration index of suspicious computing core particle, temperature is the main factor leading to computing core particle failure.

Description

Technical Field

[0001] This invention relates to the field of chip packaging aging test technology, and more specifically, to an aging test method for multi-chip packages. Background Technology

[0002] In multi-chip packaging, the quality of the microbump connections between the chip and the package substrate or interposer directly determines the lifespan and performance of the entire package. Under long-term stress from thermal cycling, electromigration, and other factors, defects such as solder voids and cracks in the microbumps will gradually worsen, eventually leading to device failure.

[0003] Aging tests on multi-chip packages to screen for early failures are a common industry practice. Traditional aging test methods mainly rely on long-term testing under high temperature and high pressure stress, followed by functional testing to determine the device's quality. This method is essentially a binary "pass / fail" screening, which has significant limitations: First, it cannot provide real-time, continuous assessment and early warning of the device's health status during the aging process, and cannot identify "critical state" devices that are deteriorating but have not yet completely failed; second, when a device ultimately fails the test, its internal components may have already suffered secondary damage such as burn-out due to complete failure, making subsequent failure analysis and root cause location extremely difficult. Summary of the Invention

[0004] The purpose of this invention is to provide an aging test method for multi-chip packages, so as to improve the problem that the existing aging test only performs a binary screening of pass or fail, and cannot provide real-time and continuous assessment and early warning of health status.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions: This application provides an aging test method for multi-chip packages, applicable to an aging test system. The system includes an aging furnace, a data acquisition module, a thermal imaging module, and a data analysis platform. The method includes: at the beginning of the aging test, recording the initial average current and initial thermal image of each computing chip on the multi-chip package; during the aging test, continuously acquiring the current waveform of each computing chip through a current sensor, updating it every minute through the thermal imaging module to obtain temperature distribution slices of multiple multi-chip package products based on time series, and then according to the temperature fluctuation distribution map of each computing chip; based on the current waveform fluctuation and temperature fluctuation distribution map of each computing chip, analyzing the deterioration state of each computing chip, and stopping the aging test when the deterioration state of any computing chip is determined to be near the end of its service life, acquiring the welding void structure of the computing chip determined to be near the end of its service life through X-Ray, and generating corresponding process adjustment suggestions based on the welding void structure.

[0006] Optionally, the aging furnace is equipped with an aging board test stand for placing multi-chip packaged products; the data acquisition module includes multiple current sensors integrated on the power rails of the computing chips, the current sensors being used to acquire current fluctuations of multiple computing chips on the multi-chip packaged products; and a thermal imaging module is located inside the aging furnace, directly above the customized aging board and covering the entire aging board.

[0007] Optionally, based on the current waveform fluctuations and temperature fluctuation distribution of each computational core, the deterioration state of each computational core is analyzed, including: In real time, waveform sub-regions that exceed the reasonable fluctuation range in the current waveform are extracted, and the current anomaly risk value corresponding to the core particle is calculated by combining the initial average current. If the current anomaly risk value is greater than the first risk threshold, the corresponding calculated core particle is marked as a suspected abnormal particle. Retrieve the temperature fluctuation distribution map corresponding to the suspected abnormal particles, and extract multiple temperature distribution sub-slices for the corresponding time period from the temperature fluctuation distribution map. Analyze each temperature distribution sub-slice for the time series to determine if there are isolated hot spots. Calculate the temperature deterioration index based on the area of ​​the isolated hot spots. If the temperature deterioration index is greater than the preset deterioration threshold, determine that the current calculated core particle is in the early stage of nearing scrapping.

[0008] Optionally, a waveform sub-region exceeding the reasonable fluctuation range in the current waveform is extracted in real time, and the current anomaly risk value corresponding to the core is calculated by combining it with the initial average current, including: A reasonable fluctuation range is constructed based on ±3% to 5% of the initial average current. Waveform sub-regions that exceed the reasonable fluctuation range are extracted in real time. The abnormal current amplitude corresponding to each waveform sub-region is calculated based on the average current and duration of the most recent 4 to 6 waveform sub-regions. The start and end interval between two adjacent waveform sub-regions is calculated, that is, the interval between the end of the previous waveform sub-region and the start of the next waveform sub-region. Thus, the average start and end interval of the most recent 4 to 6 waveform sub-regions is obtained. Based on the increase slope of the abnormal current amplitude corresponding to the most recent 4 to 6 waveform sub-regions and the average start and end interval duration, a weighted algorithm is used to comprehensively evaluate and calculate the current abnormality risk value corresponding to the core particle. If the current abnormality risk value is greater than the first risk threshold, the corresponding calculated core particle is marked as a suspected abnormal particle.

[0009] Optionally, based on the time series, each temperature distribution sub-slice is analyzed to determine whether isolated hotspots exist, and a temperature deterioration index is calculated based on the area of ​​the isolated hotspots, including: Retrieve the temperature fluctuation distribution map corresponding to the suspected abnormal particles, and extract multiple temperature distribution sub-slices from the time intervals corresponding to the most recent 4 to 6 waveform sub-regions in the temperature fluctuation distribution map. Based on the time series analysis, each temperature distribution sub-slice is analyzed to determine whether there are isolated hot spots. If so, the area corresponding to each isolated hot spot is calculated. The isolated hot spot is defined as having a temperature value of 105% to 110% of the temperature value of the initial thermal image. The maximum and minimum areas of isolated hot spots are selected from multiple temperature distribution sub-slices to obtain the area difference. Based on the percentage of the area difference to the current calculated core surface and the duration corresponding to the most recent 4 to 6 waveform sub-regions, the temperature deterioration index is calculated.

[0010] Optionally, based on the welded void structure, corresponding process adjustment suggestions are generated, including: If the welding void structure is annular and distributed around the calculation chip bumps, it is determined that the pressure during chip and substrate mounting is insufficient, resulting in poor coplanarity between the chip and substrate, and a chip mounting equipment pressure warning command is generated.

[0011] Optionally, based on the welded void structure, corresponding process adjustment suggestions are generated, including: If the size of the weld void structure is different and randomly distributed, it is determined that the solder ball itself is oxidized or contaminated, generating an abnormality warning for the cleanliness of the solder ball and substrate pad, and an abnormality warning for the solder ball storage environment.

[0012] The beneficial effects of this invention are as follows: The aging test method for multi-chip packages described in this invention analyzes the abnormal characteristics of the current waveform (such as abnormal amplitude and fluctuation frequency) in real time and correlates them with high-resolution temperature distribution changes. This enables the system to accurately determine the "near-discard" state of the chip before calculating complete chip failure, allowing the test system to actively stop the aging test of critical devices. This avoids damage or burnout of the sample due to excessive failure and preserves a complete and valuable sample for subsequent non-destructive analysis.

[0013] Secondly, this invention adopts a strategy of fusing current and thermal imaging data for analysis. By using the dual criteria of "current anomaly risk value" and "temperature deterioration index", it greatly reduces the misjudgment and omission that may be caused by monitoring a single parameter. First, suspicious computing cores are identified by current anomalies, and then the temperature deterioration index of the suspicious computing cores is determined. Temperature is the main factor that causes computing core failure.

[0014] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing embodiments of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of an aging test method for a multi-chip package as described in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of an aging test device for a multi-chip package as described in an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0018] It should be noted that similar reference numerals or letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0019] Example 1: A single PCB board typically contains multiple chips (computing chips) with different functions. The principles and methods for conducting aging tests on these computing chips are explained below. Real-time power supply current monitoring: Test method: During aging tests or system operation, continuously monitor the power supply current of each computing chip.

[0020] Abnormality judgment criteria: Current fluctuation / jumping. Micro-bump cracks may initially cause intermittent continuity, resulting in abnormal and rapid fluctuations in the power supply current. This is a typical sign of intermittent connection. Secondly, the current abnormally increases: If the crack reduces the effective connection area, the resistance at the connection point will increase. According to Joule's law P = I²R, more heat will be generated at this point when the same current flows through, resulting in a slight increase in overall power consumption and current.

[0021] Thermal imaging analysis: Test method: Use a high-resolution infrared thermal imager (other thermal imaging devices can also be used, which are not limited here) to take pictures of the chip surface while it is in operation.

[0022] Judgment criteria: Local hot spot - a (high-resistance) microbump nearing failure will become a strong heat source, which will be seen as an abnormal, isolated bright spot on the thermal image.

[0023] like Figure 1 As shown, this embodiment provides an aging test method for multi-chip packages, which is applicable to an aging test system. The system includes an aging furnace, a data acquisition module, a line thermal imaging module, and a data analysis platform. The aging furnace is equipped with an aging board test stand for placing multi-chip packaged finished products; The data acquisition module includes multiple current sensors integrated on the power rails of the computing chips. These current sensors are used to acquire current fluctuations in the multiple computing chips on the multi-chip package. The above methods are conventional techniques in this field, and the specific implementation may be as follows: Designers integrate precision sampling resistors and operational amplifier circuits into each critical power rail of each device under test to form a current sensing amplifier. The current flowing through the sampling resistor will generate a small voltage drop. The sensing amplifier amplifies this voltage drop and converts it into a voltage signal that can be read by the test system's data acquisition card. Through calibration, the system can restore the current value on the power rail in real time with high accuracy. The above methods are conventional techniques in this field and will not be elaborated here. The thermal imaging module is located inside the aging oven, directly above the customized aging board and covering the entire aging board. The method includes steps S100, S200 and S300.

[0024] Step S100: At the beginning of the aging test: During the 20-40 minute operation of the calculation chip, when the temperature and current tend to stabilize, record the initial average current and initial thermal image of each calculation chip on the multi-chip package. This is the initial sample, which can be understood as the state sample comparison parameters when the calculation chip is working normally. In step S200, during the aging test, the current waveform of each computing chip is continuously acquired by a current sensor and updated every minute by a thermal imaging module to obtain temperature distribution slices of multiple multi-chip packaged products based on time series. The temperature fluctuation distribution map of each computing chip is then generated. In this embodiment, the thermal imaging module is not real-time due to the limitations of the overall algorithm processing logic. Instead, it uses periodic sampling. The imaging data of the thermal imaging module is only activated when the computing chip is determined to be close to the end of its service life. If the data of each computing chip is recorded in real time, on the one hand, a large amount of high-precision thermal imaging pattern data will be generated, which will occupy a large amount of memory bandwidth. On the other hand, most of these pattern data will not be used. Step S300: Based on the current waveform fluctuation and temperature fluctuation distribution of each computing core, analyze the deterioration state of each computing core, and when the deterioration state of any computing core is determined to be close to the early stage of scrapping, stop the aging test, obtain the welding void structure of the computing core determined to be close to the early stage of scrapping through X-Ray, and generate corresponding process adjustment suggestions based on the welding void structure.

[0025] The step S300, which analyzes the deterioration state of each computational core based on the current waveform fluctuation and temperature fluctuation distribution of each core, includes: Criteria for judging abnormal current waveform fluctuations: Step S310: Construct a reasonable fluctuation range based on ±3% to 5% of the initial average current, and extract waveform sub-regions in the current waveform that exceed the reasonable fluctuation range in real time. Calculate the abnormal current amplitude corresponding to each waveform sub-region based on the average current and duration of the most recent 4 to 6 waveform sub-regions. This abnormal current amplitude is not the amplitude of the traditional waveform diagram, but rather an assessment of the total overcurrent of the current waveform sub-region. It is the product of time and average current, used to indirectly quantify the area of ​​the waveform sub-region. Calculate the start-end interval between two adjacent waveform sub-regions. The start-end interval specifically refers to the time between the end of the previous waveform sub-region and the beginning of the next waveform sub-region, thus obtaining the average start-end interval of the most recent 4 to 6 waveform sub-regions. The abnormal current amplitude and start-end interval are used to quantify the intermittent connection phenomenon of the current fluctuation / jumping described above. Step S320: Based on the increase slope of the abnormal current amplitude corresponding to the most recent 4 to 6 waveform sub-regions and the average start and end interval duration, the current abnormality risk value corresponding to the core particle is comprehensively evaluated and calculated by weighted algorithm. If the current abnormality risk value is greater than the first risk threshold, the corresponding calculated core particle is marked as a suspected abnormal particle. The slope of the abnormal current amplitude is used to quantify the abnormal rapid fluctuation of the current. At the same time, if the current has a continuous and slow upward trend compared to the reasonable fluctuation range (e.g., a cumulative increase of 5% to 10%), and the frequency of occurrence is high, it can be judged as a suspected abnormal particle.

[0026] Criteria for judging abnormal temperature fluctuations: Step S330: Retrieve the temperature fluctuation distribution map corresponding to the suspected abnormal particles, and extract multiple temperature distribution sub-slices from the time intervals corresponding to the most recent 4 to 6 waveform sub-regions in the temperature fluctuation distribution map. Step S310: Analyze each temperature distribution sub-slice sequentially based on the time series to see if there are isolated hot spots. If so, calculate the area corresponding to each isolated hot spot. The isolated hot spot is defined as a temperature value of 105% to 110% of the temperature value of the initial thermal image. That is, when the current fluctuates or jumps frequently, theoretically, a new, isolated "hot spot" will appear on the core. The temperature of this point will be significantly higher than the temperature of its surroundings and will scatter in all directions. The larger the heat dissipation area (the area with a temperature value of 105% to 110% of the temperature value of the initial thermal image) of the hot spot, the better. Step S340: Select the maximum and minimum areas of isolated hot spots from multiple temperature distribution sub-slices to obtain the area difference. Based on the percentage of the area difference relative to the surface of the current calculated core particle, combined with the duration of the most recent 4 to 6 waveform sub-regions, calculate the temperature deterioration index. The temperature deterioration index is a quantitative indicator of the temperature rise trend. The area difference is used to indirectly reflect the temperature difference. The reason for using the area difference is mainly due to the limited detection accuracy of the finished thermal imaging module. That is, within a small area, it only displays the highest temperature point and cannot display the temperature value corresponding to each pixel. Therefore, the area difference is used. The change in this area can also specifically indicate the defect location, providing a reference for subsequent X-Ray detection. When the temperature deterioration index is greater than the preset deterioration threshold, the current calculated core particle is determined to be in the early stage of near scrapping.

[0027] The specific implementation method of the process adjustment suggestion based on the welding void structure generation in step S300 is as follows: Step S350: If the welding void structure is annular and distributed around the calculated chip bumps, it is determined that the pressure during chip and substrate mounting is insufficient, resulting in poor coplanarity between the chip and substrate, and a chip mounting equipment pressure warning command is generated.

[0028] Step S360: If the size of the welding void structure is different and randomly distributed, it is determined that the solder ball itself is oxidized or contaminated, generating a cleaning abnormality warning for the solder ball and substrate pad and an abnormality warning for the solder ball storage environment; the above-mentioned defect types and associated process defects are conventional technical means and will not be elaborated here.

[0029] The aging test method for multi-chip packages described in this embodiment analyzes the abnormal characteristics of the current waveform (such as abnormal amplitude and fluctuation frequency) in real time and correlates them with high-resolution temperature distribution changes. This enables the system to accurately determine the "near-discard" state of the chip before calculating complete chip failure. This allows the test system to actively stop the aging test of critical devices, avoiding damage or burnout of the sample due to excessive failure and preserving a complete and valuable sample for subsequent non-destructive analysis.

[0030] Secondly, this embodiment adopts a strategy of fusing current and thermal imaging data. By using the dual criteria of "current anomaly risk value" and "temperature deterioration index", it greatly reduces the misjudgment and omission that may be caused by monitoring a single parameter. First, suspicious computing cores are identified by current anomalies, and then the temperature deterioration index of the suspicious computing cores is determined. Temperature is the main factor that causes computing core failure.

[0031] Example 3: Corresponding to the above method embodiments, this disclosure also provides an aging test device for multi-chip packages. The aging test device for multi-chip packages described below and the aging test method for multi-chip packages described above can be referred to in correspondence.

[0032] Figure 2 This is a block diagram illustrating a multi-chip packaged aging test electronic device according to an exemplary embodiment. Figure 2 As shown, the electronic device 800 may include a processor 801 and a memory 802. The electronic device 800 may also include one or more of a multimedia component 803, an I / O interface 804, and a communication component 805.

[0033] The processor 801 controls the overall operation of the electronic device 800 to complete all or part of the steps in the aforementioned aging test method for multi-chip packages. The memory 802 stores various types of data to support the operation of the electronic device 800. This data may include, for example, instructions for any application or method operating on the electronic device 800, and application-related data such as contact data, sent and received messages, pictures, audio, video, etc. The memory 802 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. Multimedia component 803 may include a screen and an audio component. The screen may be, for example, a touchscreen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in memory 802 or transmitted via communication component 805. The audio component also includes at least one speaker for outputting audio signals. I / O interface 804 provides an interface between processor 801 and other interface modules, such as a keyboard, mouse, buttons, etc. These buttons may be virtual or physical buttons. Communication component 805 is used for wired or wireless communication between the electronic device 800 and other devices. Wireless communication may include Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, or 4G, or a combination of these. Therefore, the corresponding communication component 805 may include a Wi-Fi module, a Bluetooth module, or an NFC module.

[0034] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above-described aging test method for multi-chip packages.

[0035] In another exemplary embodiment, a computer-readable storage medium including program instructions is also provided, which, when executed by a processor, implement the steps of the multi-chip package aging test method described above. For example, the computer-readable storage medium may be the memory 802 including the program instructions described above, which may be executed by the processor 801 of the electronic device 800 to complete the multi-chip package aging test method described above.

[0036] Example 3: Corresponding to the above method embodiments, this disclosure also provides a readable storage medium. The readable storage medium described below and the aging test method for a multi-chip package described above can be referred to in relation to each other.

[0037] A readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the aging test method for a multi-chip package described in the above method embodiments.

[0038] Specifically, the readable storage medium can be a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other readable storage medium capable of storing program code.

[0039] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An aging test method for multi-chip packages, applicable to an aging test system, the system comprising an aging oven, a data acquisition module, a thermal imaging module, and a data analysis platform, characterized in that, The method includes: At the beginning of the aging test, the initial average current and initial thermal image of each computing chip on the multi-chip package were recorded. During the aging test, the current waveform of each computing chip is continuously acquired by the current sensor and updated every minute by the thermal imaging module, thereby obtaining temperature distribution slices of multiple multi-chip packaged products based on time series, and generating temperature fluctuation distribution map of each computing chip according to each computing chip. Based on the current waveform fluctuations and temperature fluctuation distribution of each computational core, the deterioration state of each computational core is analyzed, specifically including: The waveform sub-regions that exceed the reasonable fluctuation range in the current waveform are captured in real time, and the current anomaly risk value corresponding to the core particle is calculated by combining the initial average current. The current anomaly risk value is calculated by comprehensively evaluating the increase slope of the abnormal current amplitude and the average start and end interval of the most recent 4 to 6 waveform sub-regions through a weighted algorithm. If the current anomaly risk value is greater than the first risk threshold, the corresponding calculated core particle is marked as a suspected abnormal particle. Retrieve the temperature fluctuation distribution map corresponding to the suspected abnormal particles, and extract multiple temperature distribution sub-slices for the corresponding time period from the temperature fluctuation distribution map. Analyze each temperature distribution sub-slice sequentially based on the time series to determine if there are isolated hot spots. If so, calculate the area of ​​each isolated hot spot. The isolated hot spot is the region where the temperature value is between 105% and 110% of the initial thermal image temperature value. Select the maximum and minimum areas of the isolated hot spots from the multiple temperature distribution sub-slices to obtain the area difference. Calculate the temperature deterioration index based on the percentage of the area difference relative to the surface of the current calculated core particle, combined with the duration corresponding to the most recent 4 to 6 waveform sub-regions. If the temperature deterioration index is greater than a preset deterioration threshold, determine that the current calculated core particle is in the pre-disposal stage. When the deterioration state of any compute core is determined to be near the end of its service life, the aging test is stopped, and the weld void structure of the compute core determined to be near the end of its service life is obtained via X-Ray. Based on the weld void structure, corresponding process adjustment suggestions are generated, specifically including: If the welding void structure is annular and distributed around the calculation chip bump, it is determined that the pressure during chip and substrate mounting is insufficient, resulting in poor coplanarity between the chip and substrate, and a chip mounting equipment pressure warning command is generated. If the size of the weld void structure is different and randomly distributed, it is determined that the solder ball itself is oxidized or contaminated, generating an abnormality warning for the cleanliness of the solder ball and substrate pad, and an abnormality warning for the solder ball storage environment.

2. The aging test method for multi-chip packages according to claim 1, characterized in that, The aging furnace is equipped with an aging board test stand for placing multi-chip packaged products; the data acquisition module includes multiple current sensors integrated on the power rails of the computing chips, which are used to acquire the current fluctuations of multiple computing chips on the multi-chip packaged products; the thermal imaging module is located inside the aging furnace, directly above the customized aging board and covering the entire aging board.

3. The aging test method for multi-chip packages according to claim 1, characterized in that, Real-time extraction of waveform sub-regions exceeding the reasonable fluctuation range from the current waveform, combined with the initial average current, to comprehensively assess and calculate the corresponding current anomaly risk value for the core, including: A reasonable fluctuation range is constructed based on ±3% to 5% of the initial average current. Waveform sub-regions that exceed the reasonable fluctuation range are extracted in real time. The abnormal current amplitude corresponding to each waveform sub-region is calculated based on the average current and duration of the most recent 4 to 6 waveform sub-regions. The start and end interval of two adjacent waveform sub-regions is calculated, and the average start and end interval of the most recent 4 to 6 waveform sub-regions is obtained.

4. The aging test method for multi-chip packages according to claim 1, characterized in that, Based on time series analysis, each temperature distribution sub-slice is analyzed to determine if isolated hotspots exist, and the temperature deterioration index is calculated based on the area of ​​the isolated hotspots, including: Retrieve the temperature fluctuation distribution map corresponding to the suspected abnormal particles, and extract multiple temperature distribution sub-slices from the time intervals corresponding to the most recent 4 to 6 waveform sub-regions in the temperature fluctuation distribution map. Based on the time series, analyze each temperature distribution sub-slice sequentially to determine if there are isolated hot spots. If so, calculate the area corresponding to each isolated hot spot.

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