Dual-differential 2d hall integrated magnetic sensor chip and packaging structure thereof

Abstract

The application provides a double-differential 2D Hall integrated magnetic sensing chip and a packaging structure thereof. A plurality of magnetic concentrators arranged in a right-angle area outside a Hall chip can effectively improve isolation between detection sensitive axes in design. Meanwhile, in process, the precision advantage of a surface mounting process in angle can be used to ensure the precision of the detection sensitive axis direction under the condition of large translation position tolerance, thereby ensuring the isolation between the sensitive axes. In addition, the plurality of magnetic concentrators can also increase the convergence effect on the horizontal magnetic field, thereby increasing the sensitivity of the device. Furthermore, for each differential Hall pair, since the two identical Hall chips are closely adjacent on the same manufacturing wafer, the influence of the environmental interference signal can be completely eliminated, and the zero point offset can still be cancelled out, thereby realizing low zero point offset, low drift and anti-interference of the device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of magnetic sensing technology design and manufacturing technology, in particular to a double-differential 2D Hall integrated magnetic sensing chip and its packaging structure. BACKGROUND

[0002] A Hall element is a sensor that works based on the Hall Effect, used to detect the presence and changes of a magnetic field. The working principle of a Hall element is that when the charge carriers in a conductor or semiconductor material pass through a magnetic field perpendicular to the current direction, the carriers will be deflected by the Lorentz force, thereby forming a transverse voltage difference on both sides of the conductor, which is called the Hall voltage. Traditional Hall chips can only detect changes in the magnetic field in a single direction, while 2D (two-dimensional plane) Hall chips that can simultaneously sense the magnetic field in two directions can achieve the detection of two-dimensional magnetic fields in the plane, which has broad application prospects in mobile phone navigation, unmanned aerial vehicle attitude measurement and control, and position detection.

[0003] The existing mainstream planar 2D Hall chip technology uses a magnetic concentrator to twist the horizontal plane direction magnetic field that cannot be sensed by the Hall chip to the vertical direction that can be sensed through its edge area. This type of implementation has the disadvantages of large volume and high cost. More importantly, the long-term drift of the Hall signal with the environment and time will cause system instability and inaccurate measurement.

[0004] Based on the existing scheme, the connection mode of horizontal parallel differential Hall pairs can significantly reduce zero offset, zero drift, and improve anti-interference performance, but it will cause large cross-talk between the two sensitive axes xy of the 2D measurement plane, and the magnetic concentrator is difficult to install and has small tolerance.

[0005] It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art merely because they are described in the background section of the present application. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a double-differential 2D Hall integrated magnetic sensing chip and its packaging structure, which solves the problem of large cross-talk between the two sensitive axes xy of the 2D measurement plane caused by the planar 2D Hall chip technology in the prior art while solving zero offset, zero drift and high anti-interference.

[0007] To achieve the above object and other related objects, the present application provides a double differential 2D Hall integrated magnetic sensing chip, which comprises:

[0008] two groups of differential Hall pairs and square magnetic concentrators located on the two groups of differential Hall pairs; wherein the two groups of differential Hall pairs are located in the same plane to measure the magnetic field in two mutually perpendicular directions in the plane;

[0009] Each group of differential Hall pairs includes two identical cross-shaped Hall chips closely adjacent on a manufacturing wafer; each of the two Hall chips includes two first electrodes arranged in a first direction and two second electrodes arranged in a second direction, the first direction being perpendicular to the second direction; the first electrode of one of the Hall chips is used to apply a voltage, and the second electrode is used to generate a first Hall potential; the second electrode of the other Hall chip is used to apply a voltage, and the first electrode is used to generate a second Hall potential; the first Hall potential and the second Hall potential are realized by parallel connection to output signals;

[0010] The two magnetic concentrators on each group of differential Hall pairs are arranged without rotation on the opposite outer straight angles of the two Hall chip cross regions, and the rotation process error of the magnetic concentrators on each Hall chip relative to the Hall chip is within ±0.2°.

[0011] Optionally, the two first electrodes of one of the Hall chips in each group of differential Hall pairs are connected to the two second electrodes of the other Hall chip, and the two second electrodes of the Hall chip are connected to the two first electrodes of the other Hall chip.

[0012] Optionally, the two groups of differential Hall pairs are arranged side by side in the same plane; or the two groups of differential Hall pairs are arranged in the same direction in sequence in the same plane.

[0013] Further, the two Hall chips adjacent to the two groups of differential Hall pairs share one magnetic concentrator above them, and the remaining two Hall chips each have one magnetic concentrator above them.

[0014] Further, the size of the independently arranged magnetic concentrator is not greater than the size of the commonly arranged magnetic concentrator.

[0015] Optionally, one magnetic concentrator is arranged above each of the four Hall chips of the two groups of differential Hall pairs, and the two magnetic concentrators above the two Hall chips of each group of differential Hall pairs are the same size.

[0016] Further, the four magnetic concentrators above the four Hall chips of the two groups of differential Hall pairs are the same size.

[0017] Optionally, the projection of the magnetic concentrator on the horizontal plane of each Hall chip is clamped at the edge of the corresponding Hall chip cross-shaped functional area.

[0018] Optionally, the thickness of the magnetic concentrator is 100 μm-800 μm.

[0019] Optionally, the two groups of differential Hall pairs are applied with the same voltage.

[0020] The application further provides a packaging structure of the double-differential 2D Hall integrated magnetic sensing chip, which comprises the double-differential 2D Hall integrated magnetic sensing chip, a conditioning circuit, a circuit board, a packaging body and external pins according to any one of the above.

[0021] The double-differential 2D Hall integrated magnetic sensing chip and the conditioning circuit are arranged on the circuit board, and the electrodes of the double-differential 2D Hall integrated magnetic sensing chip are connected to the conditioning circuit through metal wire bonding.

[0022] The packaging body encapsulates the double-differential 2D Hall integrated magnetic sensing chip, the conditioning circuit and the circuit board.

[0023] The external pins are used for outputting and outputting electrical signals.

[0024] As described above, the double-differential 2D Hall integrated magnetic sensing chip and the packaging structure thereof can effectively improve the isolation degree between the detection sensitive axes by using multiple magnetic concentrators arranged in the right-angle area outside the Hall chip in the design, and can utilize the precision advantage of the planar mounting process in the angle to ensure the precision of the detection sensitive axis direction under the condition of large translation position tolerance, thereby ensuring the isolation degree between the sensitive axes. In addition, the use of multiple magnetic concentrators can also increase the convergence effect on the horizontal magnetic field and increase the sensitivity of the device. Furthermore, for each differential Hall pair, since the two identical Hall chips are closely adjacent on the same manufacturing wafer, the influence of environmental temperature changes or environmental interference signals on the two Hall chips is more similar, and the two Hall chips closely adjacent (generally with a spacing of less than 100 μm) will change in the same way, thereby completely eliminating the influence of environmental interference signals, and the zero point offset can still be cancelled out, thereby realizing low zero point offset, low drift and anti-interference of the device. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A structural schematic diagram of a first example of the double-differential 2D Hall integrated magnetic sensing chip of the application is shown.

[0026] Figure 2 A structural schematic diagram of a group of differential Hall pairs in the double-differential 2D Hall integrated magnetic sensing chip of the application is shown.

[0027] Figure 3 A structural schematic diagram of a fourth example of a double differential 2D Hall integrated magnetic sensing chip with pads is shown.

[0028] Figure 4 A structural schematic diagram of a third example of a double differential 2D Hall integrated magnetic sensing chip is shown.

[0029] Figure 5 A structural schematic diagram of a fourth example of a double differential 2D Hall integrated magnetic sensing chip with pads is shown. Figure 1

[0030] A structural schematic diagram of a fourth example of a double differential 2D Hall integrated magnetic sensing chip with pads is shown. Figure 6 Figure 5 A structural schematic diagram of a fourth example of a double differential 2D Hall integrated magnetic sensing chip with pads is shown.

[0031] Figure 7 A structural schematic diagram of a fourth example of a double differential 2D Hall integrated magnetic sensing chip with pads is shown.

[0032] Figure 8 A structural schematic diagram of a fourth example of a double differential 2D Hall integrated magnetic sensing chip with pads is shown. Figure 3

[0033] A structural schematic diagram of a fourth example of a double differential 2D Hall integrated magnetic sensing chip with pads is shown. Figure 9 Figure 8 A structural schematic diagram of a fourth example of a double differential 2D Hall integrated magnetic sensing chip with pads is shown.

[0034] Figure 10 A structural schematic diagram of a fourth example of a double differential 2D Hall integrated magnetic sensing chip with pads is shown.

[0035] A structural schematic diagram of a fourth example of a double differential 2D Hall integrated magnetic sensing chip with pads is shown. Figure 11 Element number explanation

[0036]

[0037] DETAILED DESCRIPTION The present application is herein described, by way of example only, with the assistance of specific details to facilitate a thorough understanding of the application. The application is not limited to these details, but can be practiced with the described embodiments, or with equivalents thereto, without departing from the spirit and scope of the application. Details of the application are described herein with the understanding that the

[0038]

[0039] ​​It should be emphasized that the term "comprises / comprising" when used in this specification is taken to mean the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

[0040] Features described and / or illustrated for one implementation can be used in one or more other implementations in the same or similar manner, in combination with or in place of features of the other implementations.

[0041] As will be understood by those familiar with the art, the figures to be discussed below, which show device structures, are presented using a plan view format. Plan views are not necessarily to scale and are presented for purposes of illustration and explanation only. In actual fabrication, three-dimensional spatial dimensions should be considered.

[0042] For convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. It will be understood that these spatial relationship words are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers can also be present.

[0043] In the context of this application, a structure described as having a first feature "on" a second feature can encompass embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features such that the first and second features can not be in direct contact.

[0044] It should be noted that the drawings provided in the embodiments are only schematic and are not drawn to scale. They are merely intended to conceptually illustrate the structures in the application. Therefore, the actual number of components, the actual shapes of the components, and the actual arrangement of the components can be different from those shown in the drawings.

[0045] As shown in Figures 1 to 9 The embodiment provides a double differential 2D Hall integrated magnetic sensing chip, which comprises two groups of differential Hall pairs 1 and square magnetic concentrators 16 located on the two groups of differential Hall pairs 1; wherein the two groups of differential Hall pairs 1 are located in the same plane to measure the magnetic field in two mutually perpendicular directions in the plane. Figure 1In the embodiment, the differential Hall pair 1 is located in the XOY plane formed by the orthogonal X-axis and Y-axis, wherein the differential Hall pair 1 on the right measures the magnetic field in the X-axis direction, and the differential Hall pair 1 on the left measures the magnetic field in the Y-axis direction, and the combination of the two can realize the measurement of the magnetic field in the XOY plane. Specifically, as shown in Figure 1 the XOY plane, the X-axis and Y-axis magnetic field directions are deflected to the magnetic field direction perpendicular to the XOY plane, i.e. the Z-axis direction.

[0046] Each differential Hall pair 1 includes two identical cross-shaped Hall chips closely adjacent on a manufacturing wafer; both of the Hall chips include two first electrodes arranged in a first direction and two second electrodes arranged in a second direction, the first direction being perpendicular to the second direction; the first electrode of one of the Hall chips is used to apply a voltage, and the second electrode is used to generate a first Hall potential, and the second electrode of the other Hall chip is used to apply a voltage, and the first electrode is used to generate a second Hall potential, and the first Hall potential and the second Hall potential are realized by parallel connection. As Figure 2 In the embodiment, each differential Hall pair 1 includes two identical cross-shaped Hall chips closely adjacent on a manufacturing wafer, denoted as a first Hall chip 10 and a second Hall chip 11; the two first electrodes of the first Hall chip 10 arranged in a first direction are denoted as a first left end electrode 102 and a first right end electrode 103, and the two second electrodes arranged in a second direction are denoted as a first upper end electrode 100 and a first lower end electrode 101; the two first electrodes of the second Hall chip 11 arranged in a first direction are denoted as a second left end electrode 112 and a second right end electrode 113, and the two second electrodes arranged in a second direction are denoted as a second upper end electrode 110 and a second lower end electrode 111. Of course, Figure 2 The first direction and the second direction in the embodiment can also be interchanged, as long as they are perpendicular to each other.

[0047] The two magnetic concentrators 16 on each differential Hall pair 1 are arranged above the opposite outer right angles of the two Hall chip cross areas without rotation, and the process error of the rotation of the magnetic concentrator 16 on each Hall chip relative to the Hall chip is within ±0.2°. It should be noted that the outer right angles of the Hall chip cross area refer to the four outer right angle regions outside the functional area of the cross-shaped Hall chip, for example Figure 1The four outer edge right-angle regions of the first Hall chip 10 in the figure include the upper left, lower left, upper right and lower right four outer edge right-angle regions, and the magnetic concentrator 16 is arranged on the upper left outer edge right-angle region. In addition, the relative rotation-free arrangement of the magnetic concentrator 16 means that the magnetic concentrator 16 is directly placed above the corresponding Hall chip, that is, the side length extension direction of the magnetic concentrator 16 is parallel to the side length extension direction of the Hall chip below the magnetic concentrator 16. If the side length extension direction of the magnetic concentrator 16 is not parallel to the side length extension direction of the Hall chip below the magnetic concentrator 16, that is, a relative rotation occurs between the two. In the present embodiment, the process tolerance requirement is relatively high during the process of attaching the magnetic concentrator 16 above the Hall chip, that is, the process error of the rotation between the two should be within ±0.2°.

[0048] The double-differential 2D Hall integrated magnetic sensing chip of the present embodiment uses a square magnetic concentrator which is directly placed above the Hall chip in a relative rotation-free manner to realize the gathering and deflection of the magnetic field to the 45° direction of the Hall chip. Each differential Hall pair is only sensitive to the magnetic field in one direction, and the sensitive axis of each differential Hall pair is in the diagonal direction of the square magnetic concentrator projected to the plane of the Hall chip, pointing to the center of the Hall chip. The two are orthogonal to realize the detection of the planar magnetic field. Figure 1 In the left differential Hall pair 1, the magnetic concentrator 16 on the first Hall chip 10 is arranged on the upper left outer edge right-angle region of the first Hall chip 10, and the magnetic concentrator 16 on the second Hall chip 11 is arranged on the lower right outer edge right-angle region of the second Hall chip 11. The direction of the diagonal line A of the two magnetic concentrators 16 towards the center of the corresponding Hall chip is the Y direction, that is, the sensitive axis of the left differential Hall pair 1 is the Y axis, that is, the detection of the Y-axis magnetic field is realized. In the right differential Hall pair 1, the magnetic concentrator 16 on the third Hall chip 12 is arranged on the upper right outer edge right-angle region of the third Hall chip 12, and the magnetic concentrator 16 on the fourth Hall chip 13 is arranged on the lower left outer edge right-angle region of the fourth Hall chip 13. The direction of the diagonal line B of the two magnetic concentrators 16 towards the center of the corresponding Hall chip is the X direction, that is, the sensitive axis of the right differential Hall pair 1 is the X axis, that is, the detection of the X-axis magnetic field is realized. The X axis and the Y axis are orthogonal, realizing the detection of the planar magnetic field. Figure 3In the right differential Hall pair 1, the magnetic concentrator 16 on the first Hall chip 10 is arranged in the outer right-angle region below the first Hall chip 10, the magnetic concentrator 16 on the second Hall chip 11 is arranged in the outer right-angle region above the second Hall chip 11, and the directions of the two magnetic concentrators 16 towards the diagonal line A of the center of the corresponding Hall chip are Y directions, that is, the sensitive axis of the right differential Hall pair 1 is the Y axis, that is, the detection of the Y-axis magnetic field is realized; in the left differential Hall pair 1, the magnetic concentrator 16 on the third Hall chip 12 is arranged in the outer right-angle region above the third Hall chip 12, the magnetic concentrator 16 on the fourth Hall chip 13 is arranged in the outer right-angle region below the fourth Hall chip 13, and the directions of the two magnetic concentrators 16 towards the diagonal line B of the center of the corresponding Hall chip are X directions, that is, the sensitive axis of the left differential Hall pair 1 is the X axis, that is, the detection of the X-axis magnetic field is realized, the X axis and the Y axis are orthogonal, and the detection of the planar magnetic field is realized.

[0049] The applicant finds that the isolation degree between the sensitive axes (that is, the XY axes) on the detection plane depends on the system design and process error, and the design of the plurality of small magnetic concentrators in the embodiment can effectively improve the isolation degree. In addition, for the magnetic concentrators, the semiconductor mounting process is usually used to attach above the Hall chip, and the semiconductor mounting process can guarantee good accuracy in the rotation angle when the element is small, as described above, which can reach a high level of within ±0.2°, so the detection direction of the differential Hall pair can reach a high accuracy to ensure the isolation degree between the sensitive axes. Although the mounting position of the magnetic concentrators has an uncertainty of several microns to tens of microns due to the limitation of mechanical precision repeatability, the translation error of the magnetic concentrators relative to the Hall chip has little effect on the sensitive axis direction. Therefore, the design of the plurality of magnetic concentrators arranged on the outer right-angle regions of the Hall chips in the embodiment can effectively improve the isolation degree between the detection sensitive axes, and the process can use the accuracy advantage of the planar mounting process in the angle to ensure the accuracy of the detection sensitive axis direction under the condition of large translation position tolerance, thereby ensuring the isolation degree between the sensitive axes. In addition, the use of multiple magnetic concentrators can increase the convergence effect on the horizontal magnetic field and increase the sensitivity of the device. Furthermore, for each differential Hall pair, since the two identical Hall chips are closely adjacent on the same manufacturing wafer, the influence of environmental temperature changes or environmental interference signals on the two Hall chips is more similar, and the two Hall chips closely adjacent (generally with a spacing of less than 100 μm) will change in the same way, thereby completely eliminating the influence of the environmental interference signal, and the zero point offset can also be cancelled out, thereby realizing low zero point offset, low drift and anti-interference of the device.

[0050] The first Hall potential and the second Hall potential are realized by a wiring structure in parallel, as shown in Figure 2As shown in FIG. 1, as an example, two first electrodes of one of the Hall chips in each of the differential Hall pairs 1 are connected to two second electrodes of another Hall chip through the connecting lines 14, while the two second electrodes of the Hall chip are connected to two first electrodes of another Hall chip through the connecting lines 14. Specifically, as shown in FIG. 1, two first electrodes, i.e., the first left end electrode 102 and the first right end electrode 103, of the first Hall chip 10 are connected to two second electrodes, i.e., the second lower end electrode 111 and the second upper end electrode 110, of the second Hall chip 11 through the connecting lines 14; and two second electrodes, i.e., the first upper end electrode 100 and the first lower end electrode 101, of the first Hall chip 10 are connected to two first electrodes, i.e., the second right end electrode 113 and the second left end electrode 112, of the second Hall chip 11 through the connecting lines 14. Figure 2

[0051] As a preferred example, as shown in FIG. 2, two first electrodes of one of the Hall chips in each of the differential Hall pairs 1 are connected to two second electrodes of another Hall chip through the connecting lines 14, while the two second electrodes of the Hall chip are connected to two first electrodes of another Hall chip through the connecting lines 14. Specifically, as shown in FIG. 2, two first electrodes, i.e., the first left end electrode 202 and the first right end electrode 203, of the first Hall chip 20 are connected to two second electrodes, i.e., the second lower end electrode 211 and the second upper end electrode 210, of the second Hall chip 21 through the connecting lines 14; and two second electrodes, i.e., the first upper end electrode 200 and the first lower end electrode 201, of the first Hall chip 20 are connected to two first electrodes, i.e., the second right end electrode 213 and the second left end electrode 212, of the second Hall chip 21 through the connecting lines 14. Figure 1 Figure 4 As shown in FIG. 3, two groups of the differential Hall pairs 1 are arranged side by side in the same plane; or as shown in FIG. 4, two groups of the differential Hall pairs 1 are arranged in the same direction in sequence in the same plane. These two arrangement modes can effectively reduce the area of the magnetic sensing chip. At this time, the magnetic concentrators arranged above the four Hall chips of the two groups of the differential Hall pairs 1 can be independently arranged; or the magnetic concentrators arranged above the two adjacent Hall chips of the two groups of the differential Hall pairs can be arranged as a common square magnetic concentrator, and the magnetic concentrators arranged above the other two Hall chips are independently arranged. For example, as shown in FIG. 3, a square magnetic concentrator is independently arranged above each of the four Hall chips of the two groups of the differential Hall pairs 1; for example, as shown in FIG. 4, a common square magnetic concentrator is arranged above the lower right outer corner region of the differential Hall pair 1 on the left and the lower left outer corner region of the differential Hall pair 1 on the right. Figure 3 Figure 4 Figure 1 Figure 1 Figure 3

[0052] ​​​​​​​As an example, when the two groups of the magnetic concentrators 16 above the four Hall chips of the differential Hall pair 1 are arranged independently, the two magnetic concentrators 16 above the two Hall chips of each differential Hall pair 1 are of the same size. More preferably, as shown in Figure 4 the four magnetic concentrators 16 above the four Hall chips of the two differential Hall pairs 1 are of the same size.

[0053] As a preferred example, the projection of the magnetic concentrator 16 on the horizontal plane of each Hall chip is clamped to the edge of the corresponding Hall chip cross-shaped functional area, i.e. the outer edges of the two are just connected.

[0054] As an example, the magnetic concentrator 16 can be selected as a ferrite with a magnetic permeability greater than 100, and the thickness is generally 100 μm to 800 μm, which can be adhered to the corresponding Hall chip through an adhesive layer.

[0055] As an example, the two differential Hall pairs 1 use the same working voltage, as shown in Figures 5 to 9 the electrical connection can be achieved through the solder pad 15, the wire 18 and the jumper 17.

[0056] For example Figure 5 and Figure 6 As shown in the first Hall chip 10, the second Hall chip 11, the third Hall chip 12 and the fourth Hall chip 13, the output of the six independent electrodes is achieved through the solder pad 15, the wire 18 and the jumper 17, specifically: one second electrode of the first Hall chip 10, one first electrode of the second Hall chip 11, one first electrode of the third Hall chip 12 and one second electrode of the fourth Hall chip 13 are connected with the first solder pad 151 through the connecting line 14 and the wire; the other second electrode of the first Hall chip 10, the other first electrode of the second Hall chip 11, the other first electrode of the third Hall chip 12 and the other second electrode of the fourth Hall chip 13 are connected with the second solder pad 152 through the connecting line 14, the wire and the jumper; one first electrode of the first Hall chip 10 and one second electrode of the second Hall chip 11 are connected with the third solder pad 153 through the connecting line 14 and the jumper; the other first electrode of the first Hall chip 10 and the other second electrode of the second Hall chip 11 are connected with the fourth solder pad 154 through the connecting line 14, the wire and the jumper; one second electrode of the third Hall chip 12 and one first electrode of the fourth Hall chip 13 are connected with the fifth solder pad 155 through the connecting line 14; the other second electrode of the third Hall chip 12 and the other first electrode of the fourth Hall chip 13 are connected with the sixth solder pad 156 through the connecting line 14 and the jumper; wherein the first solder pad 151 and the second solder pad 152 are the pressure applying ends of the working voltage of the two differential Hall pairs, the third solder pad 153 and the fourth solder pad 154 are the Hall potential output ends of the left differential Hall pair 1, and the fifth solder pad 155 and the sixth solder pad 156 are the Hall potential output ends of the right differential Hall pair 1.

[0057] For example Figure 7 As shown in FIG. 15, the output of the eight independent electrodes is realized by the eight pads 15, specifically: a first pad 151 is arranged on the connecting line of one first electrode of the first Hall chip 10 and one second electrode of the second Hall chip 11; a second pad 152 is arranged on the connecting line of another first electrode of the first Hall chip 10 and another second electrode of the second Hall chip 11; a third pad 153 is arranged on the connecting line of one second electrode of the first Hall chip 10 and one first electrode of the second Hall chip 11; a fourth pad 154 is arranged on the connecting line of another second electrode of the first Hall chip 10 and another first electrode of the second Hall chip 11; a fifth pad 155 is arranged on the connecting line of one first electrode of the third Hall chip 12 and one second electrode of the fourth Hall chip 13; a sixth pad 156 is arranged on the connecting line of another first electrode of the third Hall chip 12 and another second electrode of the fourth Hall chip 13; a seventh pad 157 is arranged on the connecting line of one second electrode of the third Hall chip 12 and one first electrode of the fourth Hall chip 13; and an eighth pad 158 is arranged on the connecting line of another second electrode of the third Hall chip 12 and another first electrode of the fourth Hall chip 13. In the subsequent packaging process, four corresponding pads among the eight pads can be selected as the pressure application ends of the working voltage, and the remaining four pads can be used as the Hall potential output ends.

[0058] For example Figure 8 and Figure 9As shown in the figure, the output of the six independent electrodes is realized by the soldering pads 15, the wire 18 and the jumper 17, specifically: one second electrode of the first Hall chip 10, one first electrode of the second Hall chip 11, one first electrode of the third Hall chip 12 and one second electrode of the fourth Hall chip 13 are connected with the first soldering pad 151 through the connecting wire 14 and the wire; the other second electrode of the first Hall chip 10, the other first electrode of the second Hall chip 11, the other first electrode of the third Hall chip 12 and the other second electrode of the fourth Hall chip 13 are connected with the second soldering pad 152 through the connecting wire 14 and the jumper; one first electrode of the first Hall chip 10 and one second electrode of the second Hall chip 11 are connected with the third soldering pad 153 through the connecting wire 14; the other first electrode of the first Hall chip 10 and the other second electrode of the second Hall chip 11 are connected with the fourth soldering pad 154 through the connecting wire 14; one second electrode of the third Hall chip 12 and one first electrode of the fourth Hall chip 13 are connected with the fifth soldering pad 155 through the connecting wire 14; the other second electrode of the third Hall chip 12 and the other first electrode of the fourth Hall chip 13 are connected with the sixth soldering pad 156 through the connecting wire 14; wherein the first soldering pad 151 and the second soldering pad 152 are used as the voltage applying ends of the two groups of differential Hall pairs, the third soldering pad 153 and the fourth soldering pad 154 are used as the Hall potential output ends of the left differential Hall pair 1, and the fifth soldering pad 155 and the sixth soldering pad 156 are used as the Hall potential output ends of the right differential Hall pair 1.

[0059] As shown in the figure, Figure 10 and Figure 11 The embodiment also provides a packaging structure of the double-differential 2D Hall integrated magnetic sensing chip, which is used for packaging the double-differential 2D Hall integrated magnetic sensing chip, and comprises the double-differential 2D Hall integrated magnetic sensing chip 2, the conditioning circuit 3, the circuit board 4, the packaging body 5 and the external pin 6; wherein,

[0060] The double-differential 2D Hall integrated magnetic sensing chip 2 and the conditioning circuit 3 are arranged on the circuit board 4, and the electrodes of the double-differential 2D Hall integrated magnetic sensing chip 2 are connected with the conditioning circuit 3 through the metal wire;

[0061] The packaging body 5 is used for packaging the double-differential 2D Hall integrated magnetic sensing chip 2, the conditioning circuit 3 and the circuit board 4;

[0062] The external pin 6 is used for the output and the output of the electrical signal.

[0063] As an example, Figure 10 is to Figure 7The packaging structure is packaged with the double-differential 2D Hall integrated magnetic sensing chip 2, and is formed as an 8-pin device. Electrodes of the double-differential 2D Hall integrated magnetic sensing chip 2 are connected to the conditioning circuit 3 through metal wire bonding, and the conditioned signals after the conditioning circuit 3 are output through external pins 6.

[0064] As an example, Figure 11 is to Figure 8 The packaging structure is packaged with the double-differential 2D Hall integrated magnetic sensing chip 2, and is formed as a single-side 6-pin device. In practice, two ground electrodes of the double-differential 2D Hall integrated magnetic sensing chip 2 are combined through a jumper to prepare a 6-electrode chip core functional area.

[0065] In summary, the present application provides a double-differential 2D Hall integrated magnetic sensing chip and its packaging structure. A plurality of magnetic concentrators placed directly in the right-angle area outside the Hall chip can effectively improve the isolation between the detection sensitive axes in the design. At the same time, in the process, the precision advantage in the angle can be used to ensure the precision of the detection sensitive axis direction under the condition of large translation position tolerance, thereby ensuring the isolation between the sensitive axes. In addition, the use of multiple magnetic concentrators can also increase the convergence effect on the horizontal magnetic field and increase the sensitivity of the device. Furthermore, for each differential Hall pair, since it is two identical Hall chips closely adjacent on the same manufacturing wafer, the influence of environmental temperature changes or environmental interference signals on the two Hall chips is more similar. The two Hall chips closely adjacent (generally with a spacing of less than 100 μm) will change in the same way, thereby completely eliminating the influence of environmental interference signals, while the zero point offset can still be cancelled out, thereby realizing low zero point offset, low drift and anti-interference of the device. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0066] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A dual-differential 2D Hall integrated magnetic sensing chip, characterized in that, The dual-differential 2D Hall integrated magnetic sensing chip includes: Two sets of differential Hall pairs and a square magnet located on the two sets of differential Hall pairs; wherein the two sets of differential Hall pairs are located in the same plane to measure the magnetic fields in two mutually perpendicular directions in the plane; Each differential Hall pair comprises two identical cross-shaped Hall chips closely adjacent to each other on a fabricated wafer; each of the two Hall chips includes two first electrodes arranged along a first direction and two second electrodes arranged along a second direction, the first direction and the second direction being perpendicular to each other; the first electrode of one Hall chip is used to apply a voltage and the second electrode is used to generate a first Hall potential, the second electrode of the other Hall chip is used to apply a voltage and the first electrode is used to generate a second Hall potential, the first Hall potential and the second Hall potential are connected in parallel to achieve signal extraction; The two magnets on each differential Hall pair are positioned relative to each other without rotation, above the outer right angles of the cross regions of the two Hall chips, and the process error of the rotation of the magnets on each Hall chip relative to the Hall chip is within ±0.2°.

2. The dual-differential 2D Hall integrated magnetic sensing chip according to claim 1, characterized in that: The two first electrodes of one Hall chip in each differential Hall pair are respectively connected to the two second electrodes of another Hall chip, and the two second electrodes of the Hall chip are respectively connected to the two first electrodes of another Hall chip.

3. The dual-differential 2D Hall integrated magnetic sensing chip according to claim 1, characterized in that: The two sets of differential Hall pairs are arranged side by side in the same plane; or the two sets of differential Hall pairs are arranged sequentially in the same plane along the same direction.

4. The dual-differential 2D Hall integrated magnetic sensing chip according to claim 3, characterized in that: The two sets of differential Hall pairs share a common magnet above the two adjacent Hall chips, while the other two Hall chips each have a magnet above them.

5. The dual-differential 2D Hall integrated magnetic sensing chip according to claim 4, characterized in that: The size of the independently set magnet is not greater than the size of the shared magnet.

6. The dual-differential 2D Hall integrated magnetic sensing chip according to claim 3, characterized in that: Each of the four Hall chips in the two sets of differential Hall pairs is provided with a magnet, and the two magnets above the two Hall chips in each set of differential Hall pairs are of the same size.

7. The dual-differential 2D Hall integrated magnetic sensing chip according to claim 6, characterized in that: The four magnets above the four Hall chips of the two sets of differential Hall pairs are all the same size.

8. The dual-differential 2D Hall integrated magnetic sensing chip according to claim 1, characterized in that: The projection of the magnet on the horizontal plane of each Hall chip is positioned at the edge of the corresponding cross-shaped functional area of ​​the Hall chip.

9. The dual-differential 2D Hall integrated magnetic sensing chip according to claim 1, characterized in that: The thickness of the magnet is 100μm~800μm.

10. The dual-differential 2D Hall integrated magnetic sensing chip according to claim 1, characterized in that: The same voltage is applied to both sets of differential Hall pairs.

11. A packaging structure for a dual-differential 2D Hall integrated magnetic sensing chip, characterized in that, The packaging structure includes: a dual differential 2D Hall integrated magnetic sensor chip, a conditioning circuit, a circuit board, a package, and external pins as described in any one of claims 1 to 10; wherein... The dual differential 2D Hall integrated magnetic sensing chip and the conditioning circuit are disposed on the circuit board, and the electrodes of the dual differential 2D Hall integrated magnetic sensing chip are connected to the conditioning circuit through metal wire bonding. The package encapsulates the dual differential 2D Hall integrated magnetic sensor chip, the conditioning circuit, and the circuit board. The external pins are used for outputting and transmitting electrical signals.

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