Starting method and device of SMP equipment, equipment and storage medium

Abstract

The invention is suitable for the technical field of embedded systems, and provides an SMP device starting method, device and equipment and a storage medium, and the method comprises the following steps: after the SMP device is powered on, reading a CPU scheme configuration file to a shared memory area in an SRAM through a first CPU of the SMP device, enabling at least one second CPU through the first CPU according to configuration information in the CPU scheme configuration file, and starting the at least one second CPU through the first CPU. According to a partition starting mechanism in configuration information, corresponding CPU tasks are executed in parallel through the first CPU and the second CPU, after the second CPU completes the CPU tasks and enters a sleep mode, an SMP is enabled through the first CPU, and ramfs which are read completely are mounted to complete equipment starting, so that through the customizable partition starting mechanism, multi-CPU resources are fully utilized, and equipment starting efficiency is improved. Therefore, the starting performance before the kernel runs is more efficient, the system starting time is saved, and the multi-CPU system starting speed is increased.

Description

Technical Field

[0001] This invention belongs to the field of embedded system technology, and in particular relates to a boot method, apparatus, device and storage medium for an SMP device. Background Technology

[0002] Rapid startup of embedded devices is crucial for systems with stringent boot time requirements, especially in industrial or medical device applications. In recent years, with the implementation of artificial intelligence technology, there is also a demand for rapid system startup and application operation in consumer electronics fields such as home security, vehicle monitoring, and smart hardware, while also prioritizing user experience. For example, current dictionary pens need to complete the entire process from power-on to Optical Character Recognition (OCR) within 2 seconds, while smart door locks need to achieve facial recognition unlocking within 1 second. Therefore, optimizing the startup process of embedded systems to accelerate application execution has become an important research direction. For smart hardware products, due to the complexity of the algorithms, using a single processor would result in a high CPU resource consumption; therefore, solutions often choose main controllers that support Symmetrical Multi-Processing (SMP). Furthermore, to improve startup performance and user experience, Serial Peripheral Interface (SPI) non-volatile storage media has become the preferred storage solution. A typical startup process for existing embedded systems is as follows: Figure 1 As shown, the process mainly includes the following stages: • CROM (Chip Read-Only Memory) stage: After the system is powered on, the CROM firmware runs, which is mainly used to read the SPL (Second Program Loader) image from the storage medium and run it in SRAM (Static Random Access Memory). • SPL stage: This stage mainly completes the initialization of SoC (System on Chips), DRAM (Dynamic Random Access Memory), and reads DTB (Device Tree Binary) and kernel compressed image from storage medium into DRAM for execution; • Linux / RTOS (Real Time Operating System) stage: The kernel first runs the self-extracting program, then enters the system startup stage, which mainly includes kernel initialization and driver initialization. SMP is enabled during the kernel initialization stage. Finally, the rootfs (root file system) is mounted, completing the reading, decompression and mounting of image data. • Application startup phase: After the rootfs is successfully mounted, the application is finally run.

[0003] However, the boot process of SMP-based smart hardware products has several shortcomings: First, the boot process before kernel execution does not fully utilize CPU resources, resulting in inefficient boot performance. Furthermore, the system only enables CPU0, causing the reading of the SPL image, DTB image, and kernel compressed image, as well as the execution of the SPL program, to consume a portion of the system boot time, leading to inefficiency and resource waste. Second, the entire boot process cannot read multiple image data simultaneously; each storage medium can only respond to one control command at a time. Therefore, the DTB file, kernel compressed file, and rootfs file must be read sequentially, and reading them in advance or simultaneously is not supported. First, the data retrieval and startup processes have dependencies. While waiting for data to be read, the CPU cannot continue executing other software processes, resulting in a significant portion of the startup time being spent waiting for data to be read. Second, the application's executable binary file is stored in the rootfs. When the application runs, it needs to read the executable binary file from the storage medium into memory. At the same time, in order for the application to run correctly, its dependent dynamic libraries, resource files, etc., also need to be read from the storage medium into memory. The main time consumption in this part is in the read operations of the storage medium, and the read operations are multi-batch and relatively scattered, which has certain system overhead and ultimately affects the application startup time. Summary of the Invention

[0004] The purpose of this invention is to provide a boot method, apparatus, device, and storage medium for SMP devices, aiming to solve the problems of slow system boot and poor user experience caused by existing technologies.

[0005] In a first aspect, the present invention provides a method for starting up an SMP device, the method comprising the following steps: When the SMP device is powered on, the first CPU of the SMP device reads the CPU scheme configuration file into the shared memory area of ​​SRAM. According to the configuration information in the CPU scheme configuration file, at least one second CPU is enabled by the first CPU; According to the partition boot mechanism in the configuration information, the first CPU and the second CPU execute their respective CPU tasks in parallel. The CPU tasks include initializing the SoC and DRAM, loading the SPL image, DTB image, kernel compressed image and ramfs image. After the second CPU completes its corresponding CPU task and enters hibernation mode, the first CPU enables SMP and mounts the read ramfs to complete the startup of the SMP device.

[0006] In some embodiments, the partitioned boot mechanism is composed of basic configuration information, partition information, and CPU task information in the configuration information. The basic configuration information includes the number of running CPUs and the memory address of the shared memory region. The partition information defines the location of the image on different storage media. The CPU task information defines the core task list of each CPU and the dependencies between tasks.

[0007] In some embodiments, the step of executing corresponding CPU tasks in parallel by the first CPU and the second CPU according to the partition boot mechanism in the configuration information includes: Using a first SPI controller connected to the first CPU, the SPL image is read from the first SPI storage medium into the SRAM by the first CPU, and the SPL image located in the SRAM is run. The SoC and the DRAM are initialized using the first CPU; Using a second SPI controller connected to the second CPU, the second CPU reads the DTB image and the ramfs image from the second SPI storage medium into the SRAM and the DRAM, respectively. Using the first SPI controller, the first CPU reads the kernel compressed image from the first SPI storage medium into the DRAM, and runs the kernel compressed image located in the DRAM.

[0008] In some embodiments, the step of using a first SPI controller connected to the first CPU to read the SPL image from the first SPI storage medium into the SRAM and running the SPL image located in the SRAM includes: When the task of the CPU task information is SPL, the first CPU obtains the offset address and length information of the SPL image in the first SPI storage medium from the partition information. Based on the offset address and the length information, the first CPU reads the SPL image from the first SPI storage medium into the SRAM; When it is confirmed that the SPL image read operation has been completed, the SPL image is run in the SRAM by the first CPU.

[0009] In some embodiments, the step of executing corresponding CPU tasks in parallel by the first CPU and the second CPU according to the partition boot mechanism in the configuration information further includes: The execution status identifiers of the CPU tasks of the first CPU and the second CPU are updated to the shared memory area in real time; Based on the execution status identifier, the first CPU and the second CPU confirm whether their respective current tasks meet the execution conditions.

[0010] In a second aspect, the present invention provides a startup device for an SMP device, the device comprising: The file reading unit is used to read the CPU scheme configuration file into the shared memory area of ​​SRAM through the first CPU of the SMP device after the SMP device is powered on. A CPU enabling unit is used to enable at least one second CPU through the first CPU according to the configuration information in the CPU scheme configuration file. The task execution unit is used to execute corresponding CPU tasks in parallel through the first CPU and the second CPU according to the partition boot mechanism in the configuration information. The CPU tasks include initializing SoC and DRAM, loading SPL image, DTB image, kernel compressed image and ramfs image. The root file mounting unit is used to enable SMP through the first CPU and mount the read ramfs after the second CPU completes its corresponding CPU task and enters hibernation mode, so as to complete the startup of the SMP device.

[0011] In some embodiments, the partitioned boot mechanism is composed of basic configuration information, partition information, and CPU task information in the configuration information. The basic configuration information includes the number of running CPUs and the memory address of the shared memory region. The partition information defines the location of the image on different storage media. The CPU task information defines the core task list of each CPU and the dependencies between tasks.

[0012] In some embodiments, the task execution unit includes: The first image loading unit is used to read the SPL image from the first SPI storage medium into the SRAM through the first CPU using the first SPI controller connected to the first CPU, and to run the SPL image located in the SRAM. A system initialization unit is used to initialize the SoC and the DRAM through the first CPU; The second image loading unit is used to read the DTB image and the ramfs image from the second SPI storage medium into the SRAM and the DRAM respectively through the second CPU using the second SPI controller connected to the second CPU; The third image loading unit is used to use the first SPI controller to read the kernel compressed image from the first SPI storage medium into the DRAM through the first CPU, and to run the kernel compressed image located in the DRAM.

[0013] Thirdly, the present invention also provides an SMP device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method described above.

[0014] Fourthly, the present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method described above.

[0015] In this embodiment of the invention, after the SMP device is powered on, the first CPU of the SMP device reads the CPU scheme configuration file into the shared memory area of ​​SRAM. According to the configuration information in the CPU scheme configuration file, the first CPU enables at least one second CPU. According to the partition boot mechanism in the configuration information, the first CPU and the second CPU execute their respective CPU tasks in parallel. The CPU tasks include initializing the SoC and DRAM, loading the SPL image, DTB image, kernel compressed image, and ramfs image. After the second CPU completes its corresponding CPU task and enters hibernation mode, the first CPU enables SMP and mounts the read ramfs to complete the boot of the SMP device. Thus, through the customizable partition boot mechanism, the multi-core processor resources are fully utilized, making the boot performance before kernel operation more efficient, saving system boot time, improving the boot speed of the SMP device, and thereby improving the user experience. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the traditional startup process of an embedded system; Figure 2 This is a flowchart illustrating a startup method for an SMP device provided in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the startup framework of a startup method for an SMP device provided in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the structure of a startup device for an SMP device provided in Embodiment 2 of the present invention; Figure 5 This is a schematic diagram of the SMP device provided in Embodiment 3 of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described feature, integral, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. Furthermore, the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. The terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Words such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Above," "below," "left," "right," etc., are used only to indicate relative positional relationships, which may change accordingly when the absolute position of the described object changes. The term "a plurality" refers to two or more, and other quantifiers are similar.

[0019] To keep the following description of the embodiments of the present invention clear and concise, detailed descriptions of some known functions and known components are omitted in this specification.

[0020] The specific implementation of the present invention will be described in detail below with reference to specific embodiments: Example 1: Figure 2 The implementation flow of a startup method for an SMP device according to Embodiment 1 of the present invention is shown. For ease of explanation, only the parts related to the embodiments of the present invention are shown, and are described in detail below: In step S201, after the SMP device is powered on, the CPU scheme configuration file is read into the shared memory area of ​​SRAM by the first CPU of the SMP device.

[0021] In this embodiment of the invention, the SMP device / system / platform integrates multiple central processing units (CPUs). After the SMP device is powered on, the main control chip containing the first CPU (referred to as CPU0) is powered on, and the CROM stage of the boot process is entered. CPU0, as the default boot CPU, starts running the chip firmware program embedded in the CROM (this program is the initial boot program pre-installed at the chip factory, such as the Bootloader). During the execution of the chip firmware program, CPU0 reads the CPU scheme configuration file from a preset address of the first SPI storage medium connected to the first SPI controller through the first SPI controller it controls, and loads it into the shared memory area of ​​SRAM (e.g., the area starting at address 0x80005000). This shared memory area provides unified access permissions for each CPU of the SMP device / system / platform, supporting all CPUs to access the CPU scheme configuration file simultaneously to achieve task state synchronization and communication between multiple cores. The CPU scheme configuration file is a user-customizable file, the contents of which include, but are not limited to: dynamically configuring the location information of partition image data on different storage media, dynamically configuring the task list of CPUs at each stage of startup, and managing the execution state synchronization dependency relationship between SMP multi-tasks.

[0022] In step S202, at least one second CPU is enabled by the first CPU according to the configuration information in the CPU scheme configuration file.

[0023] In this embodiment of the invention, according to the configuration information in the CPU scheme configuration file, CPU0 enables at least one second CPU (represented as CPU1) in the CROM stage to enter the multi-core collaborative working mode. Specifically, according to the "number of CPUs running" instruction in the configuration information, CPU0 activates the corresponding number of second CPUs one by one through hardware register operations to ensure that the subsequent stages can be completed by CPU0 and CPU1 working together.

[0024] In a feasible embodiment, the configuration information in the CPU scheme configuration file includes basic configuration information, partition information, and CPU task information. The basic configuration information includes the number of running CPUs and shared memory addresses. The partition information defines the location of the image on different storage media. The CPU task information defines the core task list of each CPU and the dependencies between tasks.

[0025] In one specific embodiment, the basic configuration information includes the number of running CPUs and the shared memory address. The number of running CPUs and the shared memory address are represented by the fields CPU_NUM and LOAD_ADDR, respectively. The specific configuration content of the basic configuration information is shown in Table 1: Table 1 In one specific embodiment, the partition information mainly consists of the partition name, partition start address, partition length, and partition file. The partition information on the storage medium is configured according to the following rules: ① Each CPU corresponds to a different storage medium. If the number of CPUs is 2 (that is, the value of CPU_NUM in the basic configuration information is 2), then 2 storage media and their corresponding partition information need to be configured, and so on. ② The partition location information on different storage media is determined by the timing of image file reading and the actual size of the image. For example, the SPL image that CPU0 needs to read in the CROM stage is located at the beginning of storage medium 0, while the DTB image that CPU1 reads in the SPL stage needs to be located at the beginning of storage medium 1. Based on the above configuration rules, the specific configuration details of the partition information are shown in Table 2: Table 2 In one specific embodiment, the CPU task information mainly consists of the SPI storage medium serial number, the task completion identifier, and the task list array. The SPI storage medium serial number, the task completion identifier, and the task list array are represented by the fields spi_flash_idx, task_run_done, and Task_list, respectively. The specific configuration content of the CPU task information is shown in Table 3. Table 3 The CPU serial number is a unique identifier for each independent CPU in the SMP device, used to distinguish different CPUs so that tasks can be accurately allocated during the startup process. At the same time, the range of its serial number (such as 0~N-1) corresponds to the CPU_NUM value (such as its value is N) in the basic information configuration. The SPI storage medium serial number corresponds to the storage medium number in the partition information. If CPU0 needs to read data from storage medium 0, then the controller ID is 0.

[0026] In one specific embodiment, the key fields of the task list array mainly include task name (task_name), read status flag (need_load), read start flag (load_start), read completion flag (load_done), read dependent task name (load_depends_task), read dependency flag (load_depends_flag), run status flag (need_run), run start flag (run_start), run completion flag (run_done), run dependent task name (run_depends_task), and run dependency flag (run_depends_flag). The values ​​and definitions of each field are shown in Table 4. Table 4 Understandably, there is no limit to the number of tasks that each CPU can execute, and more can be added according to the needs of the solution. The task name for tasks with image files needs to be consistent with the partition name in the corresponding storage medium. This is so that the CPU can obtain partition information from the partition table in Table 2 based on the task name. The read start, read complete, run start, and run complete flags are mainly modified by the CPU during task execution to achieve status information synchronization.

[0027] In step S203, according to the partition boot mechanism in the configuration information, the first CPU and the second CPU execute their respective CPU tasks in parallel. The CPU tasks include initializing the SoC and DRAM, loading the SPL image, DTB image, kernel compressed image and ramfs image.

[0028] In this embodiment of the invention, the chip controller supports a dual-channel SPI controller (i.e., two independent SPI interfaces that can be connected to different SPI storage media or different areas of the same media), providing independent access channels for CPU0 and CPU1, enabling them to concurrently access different storage media. This fundamentally avoids bus contention and provides a hardware foundation for parallel operation. Based on this hardware support and according to the partitioned boot mechanism in the configuration information, CPU0 and CPU1 simultaneously execute their assigned CPU tasks through their respective SPI controllers. The CPU tasks include, but are not limited to, initializing the SoC, initializing DRAM, loading the SPL image, loading the DTB image, loading the kernel compressed image, and loading the ramfs (ram filesystem) image. The partitioned boot mechanism is defined by the basic configuration information, partition information, and CPU task information in the configuration information, and is used to dynamically establish the mapping and dependency relationships between each CPU task and the SPI controller, storage media, and partitions. This allows for flexible customization of personalized boot mechanisms according to the boot scenario, thereby shortening the system boot time.

[0029] In a feasible embodiment, parallel execution of CPU tasks is achieved through the following steps: (S203.1) Using the first SPI controller connected to the first CPU, the SPL image is read from the first SPI storage medium into the SRAM by the first CPU, and the SPL image located in the SRAM is run. (S203.2) Initialize the SoC and DRAM using the first CPU; (S203.3) Using the second SPI controller connected to the second CPU, the DTB image and ramfs image are read from the second SPI storage medium into SRAM and DRAM respectively by the second CPU; (S203.4) Using the first SPI controller, the first CPU reads the kernel compressed image from the first SPI storage medium into the DRAM and runs the kernel compressed image located in the DRAM.

[0030] In this embodiment of the invention, after CPU1 is enabled, according to the default configuration of the CPU scheme configuration file, CPU0 reads the SPL image from the first SPI storage medium into SRAM through the first SPI controller and runs it. At this point, the system startup process enters the SPL stage. In this stage, CPU0 is first responsible for initializing the SoC, and under the default configuration of the CPU scheme configuration file, CPU0 continues to be responsible for initializing the DRAM. At the same time, CPU1 is responsible for reading the DTB image from the second SPI storage medium into SRAM through the second SPI controller. Finally, CPU0 reads the kernel compressed image from the first SPI storage medium into DRAM through the first SPI controller and runs it. At the same time, CPU1 reads the ramfs image data from the second SPI storage medium into DRAM through the second SPI controller. Thus, by introducing dual SPI controllers and dual SPI storage media, it is possible to support the simultaneous reading of multiple image data, saving the time consumed by sequential image reading. It also supports the early reading of image data, reducing the waiting time for dependent items to wait for data reading to complete, and greatly shortening the system startup time. The image names, reading order, and number read by CPU0 and CPU1 can be modified by the user according to the actual situation and saved in the CPU scheme configuration file.

[0031] In a feasible embodiment, when the first CPU and the second CPU execute their respective CPU tasks in parallel according to the partition startup mechanism in the configuration information, the execution status identifiers of the CPU tasks of the first CPU and the second CPU are updated to the shared memory area in real time. Based on the execution status identifiers, the first CPU and the second CPU confirm whether their current tasks meet the execution conditions.

[0032] In this embodiment of the invention, during the execution of a task, CPU0 and / or CPU1 will write the real-time updated execution status identifiers to the shared memory area of ​​SRAM. The execution status identifiers include, but are not limited to, read start identifier, read complete identifier, run start identifier, and run complete identifier, which correspond to the progress of task execution, respectively. CPU0 and CPU1 will query the execution status identifiers of other CPU tasks associated with their current task in the shared memory area to confirm whether their current task meets the execution conditions, so as to ensure that tasks are executed collaboratively according to their dependencies.

[0033] In one feasible embodiment, the SPL image is read and run through the following steps: (S203.1.1) When the task of the CPU task information is SPL, the first CPU obtains the offset address and length information of the SPL image in the first SPI storage medium from the partition information; (S203.1.2) Based on the offset address and length information, the SPL image is read from the first SPI storage medium into the SRAM by the first CPU; (S203.1.3) When it is confirmed that the SPL image reading operation has been completed, the SPL image is run in SRAM by the first CPU.

[0034] In this embodiment of the invention, in the CPU task information corresponding to SPL, the `need_load` and `need_run` values ​​in its task list array are configured to 1. This is because the SPL task has a mirror image and needs to be run. The `load_depends_task` and `load_depends_flag` values ​​are default values ​​because SPL is the first task and reading data does not depend on any other items. `run_depends_task` is configured to SPL, and `run_depends_flag` is configured to `load_done` because the running operation depends on the completion of mirror data reading. This configuration ensures that CPU0 can correctly identify the dependencies and execute the reading and running operations sequentially. Based on this configuration, when CPU0 obtains a task name of SPL from the CPU task information... At that time, CPU0 obtains the offset address and length information of the SPL image in the first SPI storage medium from the partition information, and sets load_start in the task list array to 1 when it starts reading data. Then, according to the offset address and length information, CPU0 reads the SPL image from the first SPI storage medium into SRAM. After reading is completed, it sets load_done in the task list array to 1. CPU0 confirms that the reading operation of the SPL image has been completed by querying the load_done flag (until the flag value is 1). Then, it sets run_start to 1 when it starts running and runs the SPL image in SRAM. After running is completed, it sets run_done to 1. In this way, by updating the execution status flag in the shared memory in real time, it provides a synchronization basis for other CPUs that may depend on this task.

[0035] In one specific embodiment, when CPU0 executes the task of loading the kernel compressed image, in the CPU task information corresponding to the kernel, the `need_load` and `need_run` values ​​in the task list array are configured to be 1. This is because the kernel task has an image and needs to run. `load_depends_task` is DRAM, and `load_depends_flag` is `run_done`, because the task needs to ensure successful DRAM initialization before reading the image. `run_depends_part` is kernel, and `run_depends_flag` is `load_done`, because the task needs to ensure that the image data is read correctly before running. Based on this configuration, when CPU0 reads the task name as kernel, CPU0 obtains the kernel data from the partition information. The offset address and length information of the kernel compressed image in the first SPI storage medium are used. Before reading data, CPU0 queries the run_done flag of the DRAM task. Data reading only begins when the flag value is 1. When data reading begins, load_start in the task list array is set to 1. Subsequently, according to the offset address and length information, CPU0 reads the kernel compressed image from the first SPI storage medium into DRAM. After reading, load_done in the task list array is set to 1. CPU0 confirms that the kernel compressed image reading operation has been completed by querying the load_done flag of the kernel task (until the flag value is 1). Then, when running, run_start is set to 1, and the kernel compressed image is run in DRAM. After running, run_done is set to 1.

[0036] In step S204, after the second CPU completes its corresponding CPU task and enters hibernation mode, the first CPU enables SMP and mounts the read ramfs to complete the startup of the SMP device.

[0037] In this embodiment of the invention, during the SPL stage of the system startup process, the SoC and DRAM have been initialized, and the DTB image, kernel compressed image, and ramfs image have been loaded. Subsequently, the system startup process enters the Linux / RTOS stage. In this stage, CPU0 first runs the kernel self-extracting program, and then enters the system startup stage: kernel initialization and driver initialization. During kernel initialization, CPU0 waits for CPU1 to complete its task and enter idle (sleep) mode before enabling SMP. Finally, the ramfs that has been read in the SPL stage is decompressed and mounted. After the ramfs is successfully mounted, the application is finally run, and the system startup is completed.

[0038] In one specific embodiment, Figure 3 The diagram shows the startup process framework corresponding to steps S201 to S204 above. Specifically: • CROM stage: When the system is powered on, CPU0 runs the CROM chip firmware program. First, CPU0 reads the scheme configuration file from the storage medium into SRAM, and then enables CPU1. Under the default configuration of the scheme configuration file, CPU0 is then responsible for reading the SPL image data from the storage medium into SRAM and running it. • SPL Phase: In this phase, CPU0 is first responsible for initializing the SoC. Under the default configuration of the solution configuration file, CPU0 is responsible for initializing DRAM, while CPU1 is responsible for reading DTB file data into SRAM. Finally, CPU0 reads the kernel compressed file into DRAM and runs it. At the same time, CPU1 reads ramfs image data into DRAM, thereby loading the application and its dependent resources into memory at once. This will inevitably reduce the system overhead during the reading of storage media, improve the loading efficiency of the application, and thus achieve the goal of starting the application faster. The image name, reading order, and number read by CPU0 and CPU1 can be modified by the user according to the actual situation and saved in the solution configuration file. • Linux / RTOS stage: In this stage, CPU0 first runs the kernel self-extracting program, then enters the system boot stage. During the kernel initialization stage, CPU0 waits for CPU1 to complete its task and enter idle (sleep) mode before enabling SMP. Finally, ramfs is mounted. The ramfs image data has already been read in the SPL stage. At this point, only the data decompression and mounting steps need to be performed. • Application startup phase: After the ramfs is successfully mounted, the application will finally run.

[0039] Compared to Figure 1 The traditional startup process shown is from Figure 3As can be seen, this invention moves some tasks originally executed in the Linux stage to the SPL stage. The SPL stage synchronously performs DRAM initialization and reads the DTB file, kernel compressed file, and ramfs file. Therefore, the actual time consumed in the SPL stage is only the longest single-task time after parallel execution of "CPU0 initializing DRAM + reading the kernel compressed image" and "CPU1 reading DTB + ramfs" (rather than the serial summation time of the traditional process). Upon entering the Linux / RTOS stage, only a small amount of time is added for "waiting for CPU1 to enter idle mode." The time spent reading the rootfs image in the Linux stage, as well as the time spent loading applications and dependent resources in the application stage, has been moved to the SPL stage and completed in parallel by CPU1 and other tasks. The Linux stage only needs to perform the decompression and mounting of the ramfs (no further time-consuming reading is required). Overall, by "task pre-positioning + multi-core parallelism," the serial time consumed in each stage is effectively compressed, ultimately saving system startup time.

[0040] In this embodiment of the invention, when the SMP device is powered on, the first CPU of the SMP device reads the CPU scheme configuration file into the shared memory area of ​​SRAM. According to the configuration information in the CPU scheme configuration file, the first CPU enables at least one second CPU. According to the partition boot mechanism in the configuration information, the first CPU and the second CPU execute their respective CPU tasks in parallel. The CPU tasks include initializing the SoC and DRAM, loading the SPL image, DTB image, kernel compressed image, and ramfs image. After the second CPU completes its corresponding CPU task and enters hibernation mode, the first CPU enables SMP and mounts the read ramfs to complete the boot of the SMP device. Thus, through the customizable partition boot mechanism, the multi-core processor resources are fully utilized, making the boot performance before kernel operation more efficient, saving system boot time, improving the boot speed of the SMP device, and thereby improving the user experience.

[0041] Example 2: Figure 4 The structure of a startup device for an SMP device according to Embodiment 2 of the present invention is shown. For ease of explanation, only the parts related to the embodiments of the present invention are shown, including: The file reading unit 41 is used to read the CPU scheme configuration file into the shared memory area of ​​SRAM through the first CPU of the SMP device after the SMP device is powered on. CPU enable unit 42 is used to enable at least one second CPU through the first CPU according to the configuration information in the CPU scheme configuration file. The task execution unit 43 is used to execute the corresponding CPU tasks in parallel through the first CPU and the second CPU according to the partition boot mechanism in the configuration information. The CPU tasks include initializing SoC and DRAM, loading SPL image, DTB image, kernel compressed image and ramfs image. The root file mounting unit 44 is used to enable SMP through the first CPU and mount the read ramfs after the second CPU completes its corresponding CPU task and enters hibernation mode, so as to complete the startup of the SMP device.

[0042] Preferably, the partitioned boot mechanism is composed of basic configuration information, partition information, and CPU task information in the configuration information. The basic configuration information includes the number of CPUs running and the memory address of the shared memory region. The partition information defines the location of the image on different storage media. The CPU task information defines the core task list of each CPU and the dependencies between tasks.

[0043] In another preferred embodiment, the task execution unit 43 includes: The first image loading unit is used to read the SPL image from the first SPI storage medium into the SRAM through the first CPU using the first SPI controller connected to the first CPU, and to run the SPL image located in the SRAM. The system initialization unit is used to initialize the SoC and DRAM through the first CPU; The second image loading unit is used to read the DTB image and ramfs image from the second SPI storage medium into SRAM and DRAM respectively through the second SPI controller connected to the second CPU. The third image loading unit is used to read the kernel compressed image from the first SPI storage medium into DRAM through the first CPU using the first SPI controller, and to run the kernel compressed image located in DRAM.

[0044] In this embodiment of the invention, for the sake of convenience and brevity, only the division of the above-described functional units and modules is used as an example. In practical applications, the above functions can be allocated to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to achieve all or part of the functions described above. Each unit and module of the device can be implemented by corresponding hardware or software units. Each unit and module can be an independent hardware or software unit, or it can be integrated into a single hardware or software unit, which is not intended to limit the invention. In addition, the specific names of each functional unit and module are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the device can be referred to the corresponding description in the foregoing method embodiments, and will not be repeated here.

[0045] Example 3: Figure 5 The structure of the SMP device provided in Embodiment 3 of the present invention is shown. For ease of explanation, only the parts related to the embodiments of the present invention are shown.

[0046] The SMP device 5 of this embodiment includes a processor 50, a memory 51, and a computer program 52 stored in the memory 51 and executable on the processor 50. When the processor 50 executes the computer program 52, it implements the steps described in the above-described SMP device startup method embodiment, for example... Figure 2 The steps S201 to S204 are shown. Alternatively, when the processor 50 executes the computer program 52, it implements the functions of each unit in the above-described device embodiments, for example... Figure 4 The function of the unit shown.

[0047] In this embodiment of the invention, when the SMP device is powered on, the first CPU of the SMP device reads the CPU scheme configuration file into the shared memory area of ​​SRAM. According to the configuration information in the CPU scheme configuration file, the first CPU enables at least one second CPU. According to the partition boot mechanism in the configuration information, the first CPU and the second CPU execute their respective CPU tasks in parallel. The CPU tasks include initializing the SoC and DRAM, loading the SPL image, DTB image, kernel compressed image, and ramfs image. After the second CPU completes its corresponding CPU task and enters hibernation mode, the first CPU enables SMP and mounts the read ramfs to complete the boot of the SMP device. Thus, through the customizable partition boot mechanism, the multi-core processor resources are fully utilized, making the boot performance before kernel operation more efficient, saving system boot time, improving the boot speed of the SMP device, and thereby improving the user experience.

[0048] When the processor 50 executes the computer program 52 in the SMP device 5 of this embodiment of the invention to implement a startup method for the SMP device, the steps implemented can be referred to the description of the foregoing method embodiment, and will not be repeated here.

[0049] Example 4: In this embodiment of the invention, a computer-readable storage medium is provided, which stores a computer program. When executed by a processor, the computer program implements the steps in the above-described embodiment of the SMP device startup method, for example... Figure 2 The steps S201 to S104 are shown. Alternatively, when the computer program is executed by the processor, it implements the functions of each unit in the above-described device embodiments, for example... Figure 4 The function of the unit shown.

[0050] In this embodiment of the invention, when the SMP device is powered on, the first CPU of the SMP device reads the CPU scheme configuration file into the shared memory area of ​​SRAM. According to the configuration information in the CPU scheme configuration file, the first CPU enables at least one second CPU. According to the partition boot mechanism in the configuration information, the first CPU and the second CPU execute their respective CPU tasks in parallel. The CPU tasks include initializing the SoC and DRAM, loading the SPL image, DTB image, kernel compressed image, and ramfs image. After the second CPU completes its corresponding CPU task and enters hibernation mode, the first CPU enables SMP and mounts the read ramfs to complete the boot of the SMP device. Thus, through the customizable partition boot mechanism, the multi-core processor resources are fully utilized, making the boot performance before kernel operation more efficient, saving system boot time, improving the boot speed of the SMP device, and thereby improving the user experience.

[0051] The computer-readable storage medium of this invention can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EEPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this invention, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0052] The above embodiments are merely illustrative of the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the scope of disclosure involved in the above embodiments is not limited to technical solutions formed by specific combinations of the above technical features, but should also cover other technical solutions formed by arbitrary combinations of the above technical features or their equivalent features without departing from the above-disclosed concept. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0053] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in sequential order. In certain circumstances, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the invention. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

Claims

1. A method of starting an SMP device, characterized by, The method comprises the following steps: reading a CPU scheme configuration file into a shared memory region in SRAM by a first CPU of the SMP device after the SMP device is powered on; enabling at least one second CPU by the first CPU according to configuration information in the CPU scheme configuration file; performing respective CPU tasks by the first CPU and the second CPU in parallel according to a partition booting mechanism in the configuration information, wherein the CPU tasks comprise initializing a SoC and a DRAM, loading an SPL image, a DTB image, a kernel compressed image and a ramfs image; after the second CPU completes its corresponding CPU task and enters a sleep mode, enabling SMP by the first CPU and mounting the completed ramfs to complete booting of the SMP device.

2. The method of claim 1, wherein, The partition booting mechanism is composed of basic configuration information, partition information and CPU task information in the configuration information, wherein the basic configuration information comprises a number of CPU running and a memory address of the shared memory region, the partition information defines locations of the images on different storage media, and the CPU task information defines a core task list of each CPU and a dependency relationship between tasks.

3. The method of claim 2, wherein, The step of performing respective CPU tasks by the first CPU and the second CPU in parallel according to a partition booting mechanism in the configuration information comprises: reading the SPL image from a first SPI storage medium into the SRAM by the first CPU through a first SPI controller connected to the first CPU, and running the SPL image in the SRAM; initializing the SoC and the DRAM by the first CPU; reading the DTB image and the ramfs image from a second SPI storage medium into the SRAM and the DRAM respectively by the second CPU through a second SPI controller connected to the second CPU; reading the kernel compressed image from the first SPI storage medium into the DRAM by the first CPU through the first SPI controller, and running the kernel compressed image in the DRAM.

4. The method of claim 3, wherein, The step of reading the SPL image from a first SPI storage medium into the SRAM by the first CPU through a first SPI controller connected to the first CPU, and running the SPL image in the SRAM comprises: when the task of the CPU task information is the SPL, acquiring offset address and length information of the SPL image in the first SPI storage medium from the partition information by the first CPU; reading the SPL image from the first SPI storage medium into the SRAM by the first CPU according to the offset address and the length information; when confirming that the reading operation of the SPL image has been completed, running the SPL image in the SRAM by the first CPU.

5. The method of claim 1, wherein, According to the partition startup mechanism in the configuration information, the step of executing respective corresponding CPU tasks by the first CPU and the second CPU in parallel further comprises: updating the execution state of the respective CPU tasks of the first CPU and the second CPU to the shared memory region in real time; according to the execution state, confirming whether the current task of the first CPU and the second CPU satisfies the execution condition.

6. A starting apparatus of an SMP device, characterized by comprising: The device comprises: a file reading unit, configured to read a CPU scheme configuration file to a shared memory region in SRAM by a first CPU of an SMP device after the SMP device is powered on; a CPU enabling unit, configured to enable at least one second CPU by the first CPU according to configuration information in the CPU scheme configuration file; a task execution unit, configured to execute respective corresponding CPU tasks by the first CPU and the second CPU in parallel according to a partition startup mechanism in the configuration information, wherein the CPU tasks include initializing SoC and DRAM, loading SPL image, DTB image, kernel compressed image and ramfs image; a root file mounting unit, configured to enable the SMP by the first CPU and mount the read ramfs after the second CPU completes its corresponding CPU task and enters a sleep mode, so as to complete the startup of the SMP device.

7. The apparatus of claim 6, wherein, The partition startup mechanism is composed of basic configuration information, partition information and CPU task information in the configuration information, wherein the basic configuration information includes the number of CPU running and the memory address of the shared memory region, the partition information defines the location of the image on different storage media, and the CPU task information defines the core task list of each CPU and the dependency relationship between tasks.

8. The apparatus of claim 7, wherein, The task execution unit comprises: a first image loading unit, configured to read the SPL image from a first SPI storage medium to the SRAM by the first CPU through a first SPI controller connected with the first CPU, and run the SPL image in the SRAM; a system initialization unit, configured to initialize the SoC and the DRAM by the first CPU; a second image loading unit, configured to read the DTB image and the ramfs image from a second SPI storage medium to the SRAM and the DRAM respectively by the second CPU through a second SPI controller connected with the second CPU; a third image loading unit, configured to read the kernel compressed image from the first SPI storage medium to the DRAM by the first CPU through the first SPI controller, and run the kernel compressed image in the DRAM.

9. An SMP device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 5.

10. A computer-readable storage medium storing a computer program, the computer program comprising instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1-9. The computer program is executed by the processor to implement the steps of the method according to any one of claims 1 to 5.

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