System on chip, storage module, system interface parameter training method and device

Abstract

The present disclosure relates to the technical field of chip design, and particularly provides a system on chip, a storage module, a system interface parameter training method and equipment. The system on chip is capable of communicating with a memory, and comprises at least one of a reference voltage adjustment module, a calibration resistance adjustment module and a delay control module. The reference voltage adjustment module is configured to perform reference voltage value training to obtain a target reference voltage value, and the system on chip and the memory communicate based on the target reference voltage value. The calibration resistance adjustment module is configured to perform calibration resistance value training to obtain a target calibration resistance value, and the system on chip and the memory communicate based on the target calibration resistance value. The delay control module is configured to perform signal delay value training to obtain a target signal delay value, and the system on chip and the memory communicate based on the target signal delay value. The present disclosure improves the data interaction reliability of the system on chip.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, and in particular to a system-on-a-chip, a memory module, a method and device for training system interface parameters. Background Technology

[0002] Memory modules composed of System on Chip (SoC) and volatile memory are fundamental components of electronic devices for data reading, writing, and instruction processing. Among them, Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM) interface is also widely used in storage modules as a common data communication interface.

[0003] In related technologies, after the storage module is powered on, it is necessary to initialize appropriate calibration resistors, reference voltages, data strobe (DQS) signal delays, and address command delays, etc., to ensure normal communication between the on-chip system and the memory based on the DDR interface.

[0004] However, the initialization schemes for module operating parameters provided in related technologies are often prone to problems such as abnormal initialization of memory modules or abnormal operation after initialization, which leads to a decrease in the operational reliability of memory modules. Summary of the Invention

[0005] This disclosure is made in view of the above-mentioned problems. This disclosure provides a system-on-a-chip, a storage module, a method and apparatus for training system interface parameters, which can improve the reliability of data interaction in a system-on-a-chip.

[0006] According to a first aspect of this disclosure, a system-on-a-chip (SoC) is provided, the SoC being able to communicate with a memory, and including at least one of a reference voltage adjustment module, a calibration resistor adjustment module, and a delay control module; wherein...

[0007] The reference voltage adjustment module is used to perform reference voltage value training to obtain a target reference voltage value, and the on-chip system and the memory communicate based on the target reference voltage value;

[0008] The calibration resistor adjustment module is used to perform calibration resistor value training to obtain a target calibration resistor value, and the on-chip system and the memory communicate based on the target calibration resistor value;

[0009] The delay control module is used to perform signal delay value training to obtain a target signal delay value, and the on-chip system and the memory communicate based on the target signal delay value.

[0010] In one embodiment, the delay control module includes at least one of a data delay submodule, an address delay submodule, and a command delay submodule; the data delay submodule is used to perform data strobe signal delay training to obtain a target data strobe signal delay value, and / or perform data signal delay training to obtain a target data signal delay value, wherein the on-chip system and the memory communicate based on the target data strobe signal delay value and / or the target data signal delay value; the address delay submodule is used to perform address signal delay training to obtain a target address signal delay value, wherein the on-chip system and the memory communicate based on the target address signal delay value; the command delay submodule is used to perform command signal delay training to obtain a target command signal delay value, wherein the on-chip system and the memory communicate based on the target command signal delay value.

[0011] According to a second aspect of this disclosure, a storage module is provided, the storage module including a system-on-chip as described in the first aspect, and a memory communicating with the system-on-chip.

[0012] According to a third aspect of this disclosure, a system interface parameter training method is provided, the method being applied to a storage module as described in the second aspect, wherein the on-chip system in the storage module includes a reference voltage regulation module, the method comprising:

[0013] Step a1: Determine the initial reference voltage value and the initial voltage correction step size;

[0014] Step b1: Instruct the on-chip system to interact with the memory based on the first reference voltage value and test data, and determine the size of the first timing window associated with the first reference voltage value, wherein the first reference voltage value is the difference between the initial reference voltage value and the initial voltage correction step size;

[0015] Step c1: Instruct the on-chip system to interact with the memory based on the second reference voltage value and test data, and determine the size of the second timing window associated with the second reference voltage value, wherein the second reference voltage value is the sum of the initial reference voltage value and the initial voltage correction step size;

[0016] Step d1: When it is determined that the size of the first timing window and the size of the second timing window are equal, the initial reference voltage value is determined as the target reference voltage value.

[0017] In one embodiment, the method further includes: when it is determined that the size of the first timing window is not equal to the size of the second timing window, repeatedly performing the following steps: updating the initial reference voltage value and the initial voltage correction step size; performing the steps as described in b1 and c1 of the third aspect based on the updated initial reference voltage value and the updated initial voltage correction step size; until the size of the first timing window is equal to the size of the second timing window. In one embodiment, updating the initial reference voltage value and the initial voltage correction step size includes: when it is determined that the size of the first timing window is larger than the size of the second timing window, updating the initial reference voltage value to the first reference voltage value and decreasing the initial voltage correction step size; when it is determined that the size of the first timing window is smaller than the size of the second timing window, updating the initial reference voltage value to the second reference voltage value and decreasing the initial voltage correction step size.

[0018] According to a fourth aspect of this disclosure, a system interface parameter training method is provided, the method being applied to a storage module as described in the second aspect, wherein the on-chip system in the storage module includes a calibration resistor adjustment module, the method comprising:

[0019] Step a2: Determine the initial calibration resistor value and the initial resistance correction step size;

[0020] Step b2: Instruct the on-chip system to interact with the memory based on the first calibration resistor value and test data, and determine the size of a third timing window associated with the first calibration resistor value, wherein the first calibration resistor value is the difference between the initial calibration resistor value and the initial resistor correction step size;

[0021] Step c2: Instruct the on-chip system to interact with the memory based on the second calibration resistor value and test data, and determine the size of the fourth timing window associated with the second calibration resistor value, wherein the second calibration resistor value is the sum of the initial calibration resistor value and the initial resistor correction step size;

[0022] Step d2: When it is determined that the size of the third timing window and the size of the fourth timing window are equal, the initial calibration resistor value is determined as the target calibration resistor value.

[0023] In one embodiment, the method further includes: when it is determined that the size of the third timing window is not equal to the size of the fourth timing window, repeating the following steps: updating the initial calibration resistor value and the initial resistance correction step size; based on the updated initial calibration resistor value and the updated initial resistance correction step size, performing the steps as described in b2 and c2 of the fourth aspect; until the size of the third timing window is equal to the size of the fourth timing window.

[0024] According to a fifth aspect of this disclosure, a system interface parameter training method is provided, the method being applied to an on-chip system of a storage module as described in the second aspect, wherein the on-chip system of the storage module includes a delay control module, the method comprising:

[0025] The boundary of the first signal delay value is determined based on the initial signal delay value and the correction step size of the first signal delay value.

[0026] Based on the first signal delay value boundary and the second signal delay value correction step size, the second signal delay value boundary is determined; wherein the second signal delay value correction step size is smaller than the first signal delay value correction step size;

[0027] Based on the first signal delay value correction step size and the second signal delay value boundary, a third signal delay value boundary is determined, wherein the third signal delay value boundary is greater than the second signal delay value boundary;

[0028] The average difference between the boundary of the second signal delay value and the boundary of the third signal delay value is determined as the target signal delay value; wherein, when the delay control module includes a data delay submodule, the signal is a data strobe signal or a data signal; when the delay control module includes an address delay submodule, the signal is an address signal; and when the delay control module includes a command delay submodule, the signal is a command signal.

[0029] In one implementation, determining the boundary of the first signal delay value based on the initial signal delay value and the first signal delay value correction step size includes: determining the sum of the initial signal delay value and the first signal delay value correction step size to obtain a first test signal delay value; instructing the on-chip system to interact with the memory to generate test data based on the first test signal delay value; if the process of the on-chip system interacting with the memory to generate test data is error-free, then repeating the following steps: determining the first test signal delay value as the updated initial signal delay value; determining the sum of the updated initial signal delay value and the first signal delay value correction step size to obtain an updated first test signal delay value; instructing the on-chip system to interact with the memory to generate test data based on the updated first test signal delay value; until the process of the on-chip system interacting with the memory to generate test data encounters an error, and then determining the updated first test signal delay value as the boundary of the first signal delay value.

[0030] In one implementation, determining the second signal delay value boundary based on the first signal delay value boundary and the second signal delay value correction step size includes: determining the difference between the first signal delay value boundary and the second signal delay value correction step size to obtain a second test signal delay value; instructing the on-chip system to interact with the memory using test data based on the second test signal delay value; if an error occurs during the interaction of test data between the on-chip system and the memory, repeating the following steps: determining the second test signal delay value as the updated first signal delay value boundary; determining the difference between the updated first signal delay value boundary and the second signal delay value correction step size to obtain an updated second test signal delay value; instructing the on-chip system to interact with the memory using test data based on the updated second test signal delay value; until no error occurs during the interaction of test data between the on-chip system and the memory, determining the updated second test signal delay value as the second signal delay value boundary.

[0031] In one implementation, determining a third signal delay value boundary based on the first signal delay value correction step size and the second signal delay value boundary includes: determining the second signal delay value boundary and the sum of the first signal delay value correction step size to obtain a third test signal delay value; instructing the on-chip system to interact with the memory using test data based on the third test signal delay value; if the process of the on-chip system interacting with the memory using test data is error-free, then repeating the following steps: determining the third test signal delay value as the updated second signal delay value boundary; determining the sum of the updated second signal delay value boundary and the first signal delay value correction step size to obtain the updated third test signal delay value; instructing the on-chip system to interact with the memory using test data based on the updated third test signal delay value; until the process of the on-chip system interacting with the memory using test data encounters an error, then determining the updated third test signal delay value as the third signal delay value boundary.

[0032] In one implementation, after determining the third signal delay value boundary based on the first signal delay value correction step size and the second signal delay value boundary, the method further includes: obtaining a fourth signal delay value boundary based on the third signal delay value boundary and the second signal delay value correction step size; and determining the fourth signal delay value boundary as the adjusted third signal delay value boundary.

[0033] In one implementation, obtaining a fourth signal delay value boundary based on the third signal delay value boundary and the second signal delay value correction step size includes: determining the difference between the third signal delay value boundary and the second signal delay value correction step size to obtain a fourth test signal delay value; instructing the on-chip system to interact with the memory using test data based on the fourth test signal delay value; if an error occurs during the interaction of the on-chip system with the memory using test data, repeating the following steps: determining the fourth test signal delay value as the updated third signal delay value boundary; determining the difference between the updated third signal delay value boundary and the second signal delay value correction step size to obtain an updated fourth test signal delay value; instructing the on-chip system to interact with the memory using test data based on the updated fourth test signal delay value; until no error occurs during the interaction of the on-chip system with the memory using test data, determining the corresponding updated fourth test signal delay value as the fourth signal delay value boundary.

[0034] According to a sixth aspect of this disclosure, an electronic device is provided, comprising a storage module as described in the second aspect, wherein a reference voltage regulation module in the system-on-chip of the storage module is configured to perform the method as described in the third aspect; and / or,

[0035] The calibration resistor adjustment module in the system-on-chip is used to perform the method described in the fourth aspect; and / or,

[0036] The delay control module in the system-on-a-chip is used to perform the method described in the fifth aspect.

[0037] The system-on-a-chip (SoC), storage module, system interface parameter training method, and device provided in this disclosure can, through at least one software module among a reference voltage adjustment module, a calibration resistor adjustment module, and a delay control module, train the SoC for relevant target reference voltage, target calibration resistor, and / or target signal delay value during initialization. This allows for training communication control parameters such as target reference voltage, target calibration resistor, and / or target signal delay value that match the current abnormal environment or special scenario, enabling communication under abnormal environments or special scenarios. On the one hand, it eliminates the need for additional hardware circuitry for the SoC to determine communication control parameters, reducing the hardware complexity of the SoC and minimizing the impact on the effective data sampling window size during data transmission, thereby improving the reliability of data interaction between the SoC and the memory. On the other hand, it enables the determination of communication control parameters adapted to the current actual usage scenario based on software modules, increasing the flexibility of communication parameter determination, preventing the impact of environmental or scenario changes on data communication stability, and further enhancing the communication reliability between the SoC and the memory under abnormal environments or special scenarios.

[0038] It should be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further illustration of the claimed technology. Attached Figure Description

[0039] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0040] Figure 1 This is a schematic diagram of the architecture of a memory module provided in related technologies.

[0041] Figure 2 This is a schematic diagram of the architecture of a system-on-a-chip according to an embodiment of this disclosure.

[0042] Figure 3 This is a schematic diagram of an architecture of a system-on-a-chip and a memory according to an embodiment of this disclosure.

[0043] Figure 4 This is a schematic diagram of the architecture of a storage module according to an embodiment of the present disclosure.

[0044] Figure 5 This is a flowchart of a method for training system interface parameters of a reference voltage regulation module according to an embodiment of the present disclosure.

[0045] Figure 6 This is another flowchart of a method for training system interface parameters of a reference voltage regulation module according to an embodiment of the present disclosure.

[0046] Figure 7 This is a flowchart of a method for training system interface parameters of a calibration resistor adjustment module according to an embodiment of the present disclosure.

[0047] Figure 8 This is another flowchart of a method for training system interface parameters of a calibration resistor adjustment module according to an embodiment of the present disclosure.

[0048] Figure 9 This is a flowchart of a method for training system interface parameters of a delay control module according to an embodiment of this disclosure.

[0049] Figure 10 This is another flowchart of a method for training system interface parameters by executing a delay control module according to an embodiment of the present disclosure.

[0050] Figure 11 This is a schematic diagram illustrating a computer program product according to an embodiment of the present disclosure.

[0051] Figure 12 This is a hardware block diagram illustrating an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this disclosure more apparent, exemplary embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments of this disclosure. It should be understood that this disclosure is not limited to the exemplary embodiments described herein.

[0053] like Figure 1 The diagram illustrates the architecture of a memory module provided in the related art. The memory module includes a system-on-a-chip (SoC) A1 and a memory (DDR SDRAM) A2, wherein the external resistance values ​​of the SoC and the DDR SDRAM are fixed. Figure 1 A 240Ω calibration resistor is connected to the ZQ Calibration pin of the SoC and DDR SDRAM to facilitate configuration of the SoC end-drive capability and on-die termination (ODT) requirements through the combination of the calibration resistor and the SoC internal resistor network.

[0054] Meanwhile, a DC-to-DC converter (DCDC) is used between the SoC and DDR SDRAM to convert one DC voltage to another to generate the core voltage (VDD) in the memory module and the DDR I / O interface power supply voltage (VDD for Output, VDDQ). Additionally, a stable low-noise reference voltage (VREF) is provided between the SoC and DDR SDRAM through a low dropout regulator (LDO); or, VREF is obtained by dividing VDDQ through a resistor divider.

[0055] During the communication between the SoC and DDR SDRAM, data interaction is achieved through the coordination of a set of signals: clock signal (CK / CLK), command signal (CMD), data signal (Data), and address signal (Address, Add).

[0056] However, in related technologies, combining Figure 1It is known that because the resistance value of the calibration resistor is fixed, in special scenarios such as multi-rank design and high and low temperature environments, the fixed resistance value of the calibration resistor may not meet the configuration requirements for signal transmission, resulting in power jitter problems in special scenarios, causing abnormal data judgment, abnormal memory module initialization, and even causing devices equipped with memory modules to crash.

[0057] Furthermore, in the process of providing a reference voltage between the SoC and DDR SDRAM through an LDO or a resistor divider, corresponding lines and devices need to be laid out on the printed circuit board (PCB). These lines and devices may increase the signal path length during the data transmission process between the SoC and DDR SDRAM, affecting the rise and fall times of the signal edges, thereby affecting the size of the effective sampling window of the data during data transmission, causing data transmission errors, and leading to abnormal operation of the memory module.

[0058] Furthermore, during the initialization of the delay values ​​of clock signals, command signals, data signals, and address signals, only the impact of the delay values ​​of these signals themselves is usually considered. This can lead to power fluctuations in the delay values ​​of the trained signals under abnormal environments such as high and low temperatures, resulting in abnormal initialization of the memory module and even causing devices equipped with memory modules to crash.

[0059] To address the aforementioned problems, embodiments of this disclosure provide a system-on-a-chip (SoC) capable of communicating with a memory, including at least one of a reference voltage adjustment module, a calibration resistor adjustment module, and a delay control module; wherein...

[0060] The reference voltage regulation module is used to perform reference voltage value training to obtain the target reference voltage value. The on-chip system and the memory communicate based on the target reference voltage value.

[0061] The calibration resistor adjustment module is used to perform calibration resistor value training to obtain the target calibration resistor value. The on-chip system and the memory communicate based on the target calibration resistor value.

[0062] The delay control module is used to perform signal delay value training to obtain the target signal delay value. The on-chip system and the memory communicate based on the target signal delay value.

[0063] like Figure 2 As shown, Figure 2 The diagram shows an architecture of a system-on-a-chip provided in an embodiment of the present disclosure, wherein the system-on-a-chip includes a reference voltage adjustment module a11, a calibration resistor adjustment module a12, and a delay control module a13.

[0064] In summary, the system-on-a-chip (SoC) provided in this disclosure can, through at least one software module among the reference voltage adjustment module, calibration resistor adjustment module, and delay control module, perform relevant target reference voltage training, target calibration resistor training, and / or target signal delay value training during the SoC initialization process. This facilitates the training of communication control parameters such as target reference voltage, target calibration resistor, and / or target signal delay value that match the current abnormal environment or special scenario under abnormal or special conditions. On the one hand, no additional hardware circuitry is required for the SoC to determine communication control parameters, which not only reduces the hardware complexity of the SoC but also reduces the impact on the effective data sampling window size during data transmission, improving the reliability of data interaction between the SoC and the memory. On the other hand, by realizing the determination of communication control parameters adapted to the current actual use scenario based on software modules, the flexibility of determining communication parameters can be improved, preventing the impact of environmental or scenario changes on the stability of data communication, and further enhancing the communication reliability between the SoC and the memory under abnormal or special conditions.

[0065] It is understood that, in the embodiments of this disclosure, when the system-on-a-chip includes a reference voltage adjustment module, a calibration resistor adjustment module, and a delay control module, the system-on-a-chip can correct or collaboratively correct the impact of abnormal environments or special scenarios on the communication process between the system-on-a-chip and the memory from three dimensions: reference voltage, calibration resistor, and signal delay value. This can further improve the communication reliability between the system-on-a-chip and the memory under abnormal environments or special scenarios.

[0066] In one optional implementation, the delay control module includes at least one of a data delay submodule, an address delay submodule, and a command delay submodule;

[0067] The data delay submodule is used to perform data strobe signal delay training to obtain the target data strobe signal delay value, and / or perform data (Data Queue, DQ) signal delay training to obtain the target data signal delay value. The on-chip system and the memory communicate based on the target data strobe signal delay value and / or the target data signal delay value.

[0068] The address delay submodule is used to perform address signal delay training to obtain the target address signal delay value. The on-chip system and the memory communicate based on the target address signal delay value.

[0069] The command delay submodule is used to perform command signal delay training to obtain the target command signal delay value. The on-chip system and the memory communicate based on the target command signal delay value.

[0070] By using at least one of the data delay submodule, address delay submodule, and command delay submodule in the delay control module, the delay values ​​of the relevant target data strobe signal, target data signal, target address signal, and / or target command signal are trained. This facilitates training on the delay conditions of data strobe signals, data signals, address signals, and / or command signals involved in the communication between the on-chip system and the memory, further reducing the impact of abnormal environments and / or special scenarios on the communication process, thereby significantly improving the communication reliability between the on-chip system and the memory under abnormal environments or special scenarios.

[0071] Optionally, in this embodiment of the disclosure, the address delay submodule and the command delay submodule can be merged into an address command delay submodule, such as... Figure 3 As shown, Figure 3 The diagram illustrates an architecture of a system-on-a-chip (SoC) and a memory according to an embodiment of this disclosure. The SoC includes a reference voltage adjustment module a11, a calibration resistor adjustment module a12, and a delay control module. The delay control module includes a data delay submodule a131 and an address command delay submodule a132. The address command delay submodule a132 is used to perform address command (CA) signal delay training to obtain a target address command signal delay value and a target clock signal delay value, so that the SoC and the memory can communicate based on the target address command signal delay value.

[0072] It is understandable that, such as Figure 3 The on-chip system shown can perform hardware initialization after power-on, and through the reference voltage adjustment module a11, calibration resistor adjustment module a12, data delay submodule a131 and address command delay submodule a132, respectively train to obtain the corresponding target reference voltage, target calibration resistor, target data strobe signal delay value, target data signal delay value and target address command signal delay value.

[0073] In this system-on-a-chip, the DDR controller a14 and the data delay submodule a131 interact with the data delay submodule a131 via data read / write (dfi_w / rdata) commands to transmit data. The data delay submodule a131 generates DQS and DQ signals corresponding to the data to be transmitted based on the target data strobe signal delay value and the target data signal delay value, and then interacts with the memory to transmit the data based on the DQS and DQ signals. At the same time, the DDR controller also needs to send read / write parameter information related to data read / write (such as read / write instructions, target address for reading / writing data in memory, etc.) to the address command delay submodule a132 via address commands (dfi_command). The address command delay submodule a132 then generates address command signals and clock signals related to the read / write parameter information based on the target address command signal delay value and the target clock signal delay value, and then transmits the read / write parameter information to the memory based on the address command signals and clock signals.

[0074] Optionally, the DDR controller a14 can send a write data (dfi_rdata) command to the data delay submodule a131 and send the data to be written to the data delay submodule a131. Then, the data delay submodule a131 generates DQS and DQ signals corresponding to the data to be written through the target data strobe signal delay value and the target data signal delay value, and sends the data to be written to the memory.

[0075] Meanwhile, the DDR controller a14 sends write data parameter information (such as the write instruction, the target address for writing data in memory, etc.) to the address command delay submodule a132 via the address command (dfi_command). The address command delay submodule a132 generates CK and CA signals based on the target address command signal delay value and the target clock signal delay value, so that the timing of CK and CA signals is completely synchronized with the memory's operating clock when they arrive at the memory. This allows the memory to write the data to be written based on the DQS and DQ signals according to the write instruction and the target address for writing data.

[0076] Similarly, the DDR controller a14 can also send a read data (dfi_wdata) command to the data delay submodule a131. After receiving the dfi_wdata command, the data delay submodule a131 prepares to receive the data returned by the memory. At the same time, the DDR controller also needs to send read data parameter information related to the read data (such as the read instruction, the target address of the data to be read in the memory, etc.) to the address command delay submodule a132 via the address command (dfi_command). The address command delay submodule a132 signal ensures that the timing of the CK signal and CA signal is synchronized with the memory's working clock when they arrive at the memory. Then, the memory performs the read operation according to the read instruction and the target address of the read data, and then returns the read data via the DQ signal and DQS signal. Among them, after receiving the read data, the data delay submodule a131 parses the DQS signal and DQ signal based on the target data strobe signal delay value and the target data signal delay value to obtain the read data, and sends the read data to the DDR controller to realize the data reading.

[0077] It is understandable that during the process of reading and writing data between the on-chip system and the memory, the reliability of communication during data interaction can be ensured based on the target reference voltage and target calibration resistor obtained through training.

[0078] This disclosure provides a storage module, which includes the above-described system-on-a-chip (SoC) and a memory communicating with the SoC. The SoC may include at least one of a reference voltage regulation module, a calibration resistor regulation module, and a delay control module.

[0079] For example, such as Figure 4 As shown, Figure 4 The diagram shows an architecture of a storage module provided in an embodiment of the present disclosure. The storage module includes a system-on-chip A1 and a memory A2. The system-on-chip A1 includes a reference voltage adjustment module a11, a calibration resistor adjustment module a12, and a delay control module a13. The data interaction scheme between the system-on-chip A1 and the memory A2 can be referred to the above embodiment, and will not be repeated here.

[0080] It is understood that in the storage module provided in this embodiment, the on-chip system A1 does not require an external calibration resistor with a fixed resistance value. Instead, the calibration resistor adjustment module a12 trains the target calibration resistor value for communication between the on-chip system A1 and the memory A2. Furthermore, the on-chip system A1 and the memory A2 do not require a reference voltage provided by an LDO or resistor divider. Instead, the reference voltage adjustment module a11 trains the target reference voltage value for communication between the on-chip system A1 and the memory A2. The calibration resistor adjustment module a12 and the reference voltage adjustment module a11 not only reduce the hardware limitations of the storage module but also... This reduces the complexity of the components and also decreases the impact of effective data on the size of the sampling window during data transmission, improving the reliability of data interaction between the on-chip system and the memory within the storage module. Simultaneously, the storage module enables multi-dimensional software modules (reference voltage adjustment module a11, calibration resistor adjustment module a12, and delay control module a13) to determine the target values ​​of communication control parameters for the current actual usage scenario. This enhances the flexibility in determining communication parameters, prevents environmental or scenario changes from affecting the stability of data communication within the storage module, and further improves the reliability of data communication within the storage module under abnormal environments or special scenarios.

[0081] Based on the aforementioned hardware, this disclosure also provides a system interface parameter training method, applied to the aforementioned storage module, where the on-chip system in the storage module includes a reference voltage regulation module, such as... Figure 5 As shown, the process of the reference voltage regulation module executing the system interface parameter training method includes:

[0082] Step a1: Determine the initial reference voltage value and the initial voltage correction step size;

[0083] Step b1: Instruct the on-chip system to interact with the memory based on the first reference voltage value and test data, and determine the size of the first timing window associated with the first reference voltage value;

[0084] The first reference voltage value is the difference between the initial reference voltage value and the initial voltage correction step size.

[0085] Step c1 instructs the on-chip system to interact with the memory based on the second reference voltage value and test data, and to determine the size of the second timing window associated with the second reference voltage value;

[0086] The second reference voltage value is the sum of the initial reference voltage value and the initial voltage correction step size.

[0087] Step d1: When it is determined that the size of the first timing window and the size of the second timing window are equal, the initial reference voltage value is determined as the target reference voltage value.

[0088] Wherein, when the difference between the size of the first time window and the size of the second time window is within a preset range, the size of the first time window and the size of the second time window can be considered equal. The preset range can be determined based on actual needs, and this embodiment does not limit it; or, when the size of the first time window and the size of the second time window are completely equal, the size of the first time window and the size of the second time window are considered equal.

[0089] In summary, the system interface parameter training method provided in this disclosure has two advantages. First, it can first determine the initial reference voltage value and the initial voltage correction step size by using preliminary interactive test data between the on-chip system and the memory, thereby improving the rationality of the determined initial reference voltage value and the initial voltage correction step size. This, in turn, facilitates the improvement of the rationality of the target reference voltage value determined based on the initial reference voltage value and the initial voltage correction step size. Second, by increasing and decreasing the two reference voltage values, it obtains the timing window determined during the data interaction between the on-chip system and the memory under the two reference voltage values. When the two timing windows are of the same size, it is determined that the on-chip system and the memory can ensure reliable data communication based on the initial reference voltage value. Thus, the initial reference voltage value is determined as the target reference voltage value, improving the rationality and reliability of the determined target reference voltage value.

[0090] The following are Figure 5 The specific implementation methods of each step in the illustrated embodiment are described in detail below:

[0091] In step a1, in one optional implementation, in response to an initialization command, the on-chip system is instructed to interact with the memory to obtain test data to determine an initial reference voltage value and an initial voltage correction step size. In another optional implementation, the initial reference voltage value and the initial voltage correction step size are configured based on experimental results.

[0092] In this embodiment, the initialization command can be detected after a cold or warm start of the storage module. In a cold start scenario, after the storage module is powered on and undergoes a hardware reset, the firmware within the system-on-a-chip generates an initialization command to instruct the reference voltage adjustment module to initialize. Alternatively, in a warm start scenario, the reference voltage adjustment module within the system-on-a-chip can initialize itself after detecting the initialization command generated by the reset firmware during operation. The initial reference voltage value is a reference value used to determine the target reference voltage, and the initial voltage correction step size is the correction magnitude value when adjusting the initial reference voltage value during the process of determining the target reference voltage based on the initial reference voltage value.

[0093] In one optional implementation, the process by which the reference voltage adjustment module, in response to an initialization command, instructs the on-chip system to interact with the memory to obtain test data to determine an initial reference voltage value and an initial voltage correction step size may include: in response to the initialization command, instructing the on-chip system to send test data to the memory based on a preset reference voltage value; and instructing the on-chip system to collect test response data sent by the memory based on a preset sampling clock; further, if the test response data is determined to be abnormal response test data, or if the on-chip system does not receive test response data sent by the memory, correcting the preset reference voltage value based on the preset voltage correction step size, and repeating the above test process based on the corrected preset reference voltage until test response data is received or the test response data is normal response test data; determining the corrected preset reference voltage as the initial reference voltage value; and determining the preset voltage correction step size as the initial voltage correction step size.

[0094] The correction of the preset reference voltage value based on the preset voltage correction step size refers to increasing or decreasing the preset reference voltage value by the preset voltage correction step size; the preset sampling clock; and the preset voltage correction step size can be determined based on actual needs, which is not limited in this embodiment; it should be noted that during the initialization process, the on-chip system can be initialized by sending fixed-pattern test data (such as 01010101) to the memory, wherein the normal response test data is the preset response data associated with the test data. Specifically, the preset response data can be determined based on actual needs, which is not limited in this embodiment.

[0095] In one optional implementation, if the test response data is still abnormal or the on-chip system still does not receive the response test data after repeating the above test process a target number of times based on the corrected preset reference voltage value, then the preset voltage correction step size needs to be updated, and the above test process is re-executed based on the updated preset voltage correction step size until the test response data is normal or the response test data is received. Then, the corrected preset reference voltage is determined as the initial reference voltage value, and the updated preset voltage correction step size is determined as the initial voltage correction step size.

[0096] The target number can be determined based on actual needs, and this embodiment does not limit it; updating the preset voltage correction step size refers to increasing or decreasing the preset voltage correction step size by a target value, which can be determined based on actual needs, and this embodiment does not limit it.

[0097] In step b1, the on-chip system is instructed to interact with the memory to obtain test data based on the first reference voltage value, and to determine the size of the first timing window associated with the first reference voltage value.

[0098] In this embodiment of the disclosure, the first reference voltage value is the difference between the initial reference voltage value and the initial voltage correction step size, wherein the timing window is the effective time interval for data returned by the on-chip system acquisition memory.

[0099] In one optional implementation, the process by which the reference voltage adjustment module instructs the on-chip system to interact with the memory based on a first reference voltage value and to determine the size of a first timing window associated with the first reference voltage value includes: the reference voltage adjustment module instructs the on-chip system to send test data to the memory based on the difference between an initial reference voltage value and an initial voltage correction step size; if the on-chip system receives test response data sent by the memory, or if it receives correct test response data corresponding to the test data sent by the memory, then the timing window formed by the first reference voltage value and the initial reference voltage value is used as the first timing window; if the on-chip system does not receive test response data sent by the memory or receives incorrect test response data sent by the memory, then the following steps are executed repeatedly, i.e., instructing the on-chip system to interact with the memory based on the updated first reference voltage value, until the on-chip system receives test response data or correct test response data from the memory, and the loop ends. Wherein, the updated first reference voltage value is the difference between the first reference voltage value before the update and the initial reference voltage correction step size.

[0100] In one implementation, during the exchange of test data between the on-chip system and the memory, one end sends test data, and the other end, upon receiving the test data, sends back test response data. For example, the on-chip system sends test data to the memory, and the memory, upon receiving the test data, sends back test response data to the on-chip system; or, the memory sends test data to the on-chip system, and the on-chip system, upon receiving the test data, sends back test response data to the memory. Thus, if one end of the on-chip system and the memory sends test data to the other and receives test response data from the other end, the exchange of test data between the on-chip system and the memory is considered successful; otherwise, the exchange of test data between the on-chip system and the memory is considered to have failed.

[0101] In another implementation, when the on-chip system (OS-C) and memory exchange test data, there is a one-to-one correspondence between the test data and the test response data. During this exchange, if one end sends test data, the other end will respond with a corresponding test response. For example, if the OS-C sends test data to the memory, the memory will respond with a corresponding test response; or, if the memory sends test data to the OS-C, the OS-C will respond with a corresponding test response. If one end sends test data to the other and receives a corresponding test response, the exchange is considered successful. If one end sends test data and receives a non-corresponding test response, or receives no response at all, the exchange is considered unsuccessful. If the test response data and the test data cannot be matched one-to-one, then the test response data is considered to be incorrect test response data, that is, the test response data is considered to be erroneous test response data.

[0102] In one optional implementation, the process by which the reference voltage adjustment module instructs the on-chip system to interact with the memory based on a first reference voltage value and to determine the size of a first timing window associated with the first reference voltage value includes: Step B1, instructing the on-chip system to send test data to the memory based on the first reference voltage value, and instructing the on-chip system to acquire the test response data sent by the memory based on a preset sampling clock; Step B2, if the test response data sent by the memory is incorrect test response data, or if the on-chip system fails to acquire the test response data sent by the memory within the preset sampling clock, the following steps are executed cyclically: Step B3, adjusting the phase of the preset sampling clock in the direction of decreasing phase of the sampling clock to obtain... The first updated sampling clock is used; then, based on the first updated sampling clock, step B1 is executed until test response data or correct test response data is obtained, and the first updated sampling clock is determined as the first timing window boundary; further, the following steps are executed cyclically: step B4, instructing the on-chip system to adjust the phase of the preset sampling clock in the direction of increasing phase of the sampling clock to obtain the second updated sampling clock; based on the second updated sampling clock, step B1 is executed until test response data or correct test response data is obtained, and the second updated sampling clock is determined as the second timing window boundary; finally, the area between the first timing window boundary and the second timing window boundary is determined as the first timing window size.

[0103] It should be noted that the adjustment range of the sampling clock phase in the embodiments of this disclosure can be determined based on actual needs, and the embodiments of this disclosure do not limit it in this regard.

[0104] In step c1, the on-chip system is instructed to interact with the memory based on the second reference voltage value to obtain test data and to determine the size of the second timing window associated with the second reference voltage value.

[0105] In this embodiment of the disclosure, the second reference voltage value is the sum of the initial reference voltage value and the initial voltage correction step size.

[0106] In one optional embodiment, the process by which the reference voltage adjustment module instructs the on-chip system to interact with the memory based on a second reference voltage value and to determine the size of a second timing window associated with the second reference voltage value includes: the reference voltage adjustment module instructs the on-chip system to send test data to the memory based on the sum of an initial reference voltage value and an initial voltage correction step size; if the on-chip system receives test response data sent by the memory, or if it receives correct test response data corresponding to the test data sent by the memory, then the timing window formed by the second reference voltage value and the initial reference voltage value is used as the second timing window; if the on-chip system does not receive test response data sent by the memory or receives incorrect test response data sent by the memory, then the following steps are executed repeatedly, i.e., instructing the on-chip system to interact with the memory based on the updated second reference voltage value, until the on-chip system receives test response data or correct test response data from the memory, and the loop ends. Wherein, the updated second reference voltage value is the sum of the second reference voltage value before the update and the initial reference voltage correction step size.

[0107] It should be noted that, in another optional embodiment, the process by which the reference voltage adjustment module instructs the on-chip system to interact with the memory based on the second reference voltage value and to determine the size of the second timing window associated with the second reference voltage value can be referred to in the above embodiment, whereby the reference voltage adjustment module instructs the on-chip system to interact with the memory based on the first reference voltage value and to determine the size of the first timing window associated with the first reference voltage value. This disclosure will not elaborate further on this aspect.

[0108] Step d1: When it is determined that the size of the first timing window and the size of the second timing window are equal, the initial reference voltage value is determined as the target reference voltage value.

[0109] In one optional implementation, when the reference voltage adjustment module determines that the size of the first timing window is not equal to the size of the second timing window, the following steps are repeated: updating the initial reference voltage value and the initial voltage correction step size; then, based on the updated initial reference voltage value and the updated initial voltage correction step size, steps b1 and c1 are performed as described above until the size of the first timing window is equal to the size of the second timing window. This allows for proactive correction of suboptimal initial reference voltage values ​​and initial voltage correction step sizes when the sizes of the first and second timing windows are not equal. This effectively avoids abnormal training of the target reference voltage value due to deviations in the setting of the initial reference voltage value and the initial voltage correction step size, ensuring reliable training of a target reference voltage value that conforms to the current scenario under various conditions such as different processes, voltage and temperature variations, and / or different memory chips. This significantly improves the reliability and training efficiency of the trained target reference voltage value.

[0110] In one optional implementation, the process of the reference voltage adjustment module updating the initial reference voltage value and the initial voltage correction step size includes: when it is determined that the size of the first timing window is larger than the size of the second timing window, updating the initial reference voltage value to the first reference voltage value and decreasing the initial voltage correction step size; wherein, updating the initial reference voltage value to the first reference voltage value means determining the first reference voltage value as the updated initial reference voltage value. When the size of the first timing window is larger than the size of the second timing window, it can be determined that the target reference voltage value is closer to the first reference voltage value associated with the first timing window, and the process of determining the first reference voltage value as the updated initial reference voltage value and decreasing the voltage correction step size is repeated. Then, the on-chip system is instructed to interact with the memory to obtain test data based on the updated initial reference voltage value until the interaction with the test data is successful, thus obtaining the target reference voltage value. This improves the accuracy of determining the target reference voltage value and, compared to manually configuring the reference voltage value through trial and error to obtain a suitable target reference voltage value, improves the efficiency of determining the target reference voltage value.

[0111] Alternatively, when the size of the first timing window is determined to be smaller than the size of the second timing window, the initial reference voltage value is updated to the second reference voltage value, and the initial voltage correction step size is reduced. Updating the initial reference voltage value to the second reference voltage value means determining the second reference voltage value as the updated initial reference voltage value. When the size of the first timing window is smaller than the second timing window, the target reference voltage value can be determined to be closer to the second reference voltage value associated with the second timing window. The process of determining the second reference voltage value as the updated initial reference voltage value and reducing the voltage correction step size is repeated, instructing the on-chip system to interact with the memory to obtain test data based on the updated initial reference voltage value, until the test data interaction is successful and the target reference voltage value is obtained. This improves the accuracy of determining the target reference voltage value and, compared to manually configuring the reference voltage value through trial and error to obtain a suitable target reference voltage value, improves the efficiency of determining the target reference voltage value.

[0112] It is understood that, in one implementation of this disclosure, reducing the initial voltage correction step size includes: reducing it by a predetermined proportion based on the initial voltage correction step size, such as reducing it by one-half or one-quarter. In another implementation, the voltage correction step size difference between the reduced initial voltage correction step size and the original initial voltage correction step size can be less than or equal to a target voltage difference. The target voltage difference can be determined based on actual needs, and this disclosure does not limit this. For example, the target voltage difference can be one-half or one-third of the initial voltage correction step size.

[0113] It should be noted that, in the embodiments of this disclosure, the numbers of steps a1, b1, c1 and d1 do not represent the training order of the system interface parameter training method. For example, steps b1 and c1 can be executed simultaneously, or steps b1 can be executed first and then steps c1, or steps c1 can be executed first and then steps b1, etc. Specifically, it can be determined based on actual needs, and the embodiments of this disclosure do not limit it in this way.

[0114] For example, such as Figure 6 As shown, Figure 6 This disclosure provides another flowchart of a method for training system interface parameters of a reference voltage regulation module, including:

[0115] S601, in response to an initialization command, instructs the on-chip system to interact with the memory to obtain test data to determine the initial reference voltage value and the initial voltage correction step size.

[0116] Specifically, the system-on-chip (SoC) and memory interact with each other based on a preset reference voltage value and a preset voltage correction step size. When the interaction is successful, the corresponding reference voltage and voltage correction step size are set as the initial reference voltage and the initial voltage correction step size. When the interaction fails, the system-on-chip updates the preset reference voltage value and the preset voltage correction step size, instructing the SoC to interact with the memory based on the updated preset reference voltage value and preset voltage correction step size, until the interaction is successful, at which point the loop ends.

[0117] S602, instructs the on-chip system to interact with the memory based on the first reference voltage value (the difference between the initial reference voltage value and the initial reference voltage correction step size) to obtain test data, and to determine the first timing window size win1 associated with the first reference voltage value;

[0118] S603 instructs the on-chip system to interact with the memory based on the second reference voltage value (the sum of the initial reference voltage value and the initial reference voltage correction step size) to obtain test data and determine the second timing window size win2 associated with the second reference voltage value;

[0119] S604, determine whether the size of the first time window win1 is equal to the size of the second time window win2;

[0120] S605, if the size of the first timing window win1 is equal to the size of the second timing window win2, then the initial reference voltage value is determined as the target reference voltage value;

[0121] S606, If the size of the first time window win1 is not equal to the size of the second time window win2, then determine whether the size of the first time window win1 is greater than the size of the second time window win2;

[0122] S607, if the first timing window size win1 is greater than the second timing window size win2, then the following process is executed repeatedly: the first reference voltage value is determined as the updated initial reference voltage value, and the initial voltage correction step size is reduced, for example, by half as the new initial voltage correction step size. Then, S602 to S603 are executed again until the updated first timing window size win1 and the updated second timing window size win2 are determined to be equal. The loop ends, and the final updated initial reference voltage value is determined as the target reference voltage value.

[0123] S608, if the first timing window size win1 is smaller than the second timing window size win2, then the following process is executed repeatedly: the second reference voltage value is determined as the updated initial reference voltage value, and the voltage correction step size is reduced, for example, by half as the new initial voltage correction step size. Then, S602 to S603 are executed again until the updated first timing window size win1 and the updated second timing window size win2 are determined to be equal. The loop ends, and the updated initial reference voltage value is determined as the target reference voltage value.

[0124] In S601-S608 above, assuming the on-chip system and memory successfully exchange test data, the corresponding initial reference voltage value is 8V and the initial reference voltage correction step size is 4; the on-chip system is instructed to exchange test data with the memory based on the first reference voltage value of 4V and the second reference voltage value of 12V respectively. Assuming both exchange test data are successful, the first timing window size win1 associated with 4V and the second timing window size win2 associated with 12V are determined. The sizes of win1 and win2 are compared. If win1 equals win2, then 8V is determined as the target reference voltage; if win1 does not equal win2... Then, the process iteratively executes the process of taking the larger of win1 and win2 as the new initial reference voltage value (i.e., one of the first reference voltage and the second reference voltage). For example, the larger window win2, corresponding to 12V, is taken as the new initial reference voltage value, and the initial voltage correction step size is reduced, for example, by half, i.e., the new initial voltage correction step size is 2. Then, based on the new initial reference voltage value such as 12V and the new initial reference voltage correction step size such as 2, steps S602-S603 are executed until win1 and win2 are equal, and the corresponding new initial reference voltage value is taken as the target reference voltage value.

[0125] This disclosure also provides a system interface parameter training method, which is applied to the aforementioned storage module. When the on-chip system in the storage module includes a calibration resistor adjustment module, such as... Figure 7 As shown, the process of the calibration resistor adjustment module executing the system interface parameter training method includes:

[0126] Step a2: Determine the initial calibration resistor value and the initial resistance correction step size;

[0127] Step b2 instructs the on-chip system to interact with the memory based on the first calibration resistor value and test data, and to determine the size of the third timing window associated with the first calibration resistor value;

[0128] The first calibration resistor value is the difference between the initial calibration resistor value and the initial resistance correction step size.

[0129] Step c2 instructs the on-chip system to interact with the memory based on the second calibration resistor value and test data, and to determine the size of the fourth timing window associated with the second calibration resistor value;

[0130] The second calibration resistor value is the sum of the initial calibration resistor value and the initial resistance correction step size;

[0131] Step d2: When it is determined that the size of the third timing window and the size of the fourth timing window are equal, the initial calibration resistor value is determined as the target calibration resistor value.

[0132] Specifically, when the difference between the size of the third time-series window and the size of the fourth time-series window is within a preset range, the size of the third time-series window and the size of the fourth time-series window can be considered equal; or, when the size of the third time-series window and the size of the fourth time-series window are completely equal, the size of the third time-series window and the size of the fourth time-series window are considered equal.

[0133] In summary, the system interface parameter training method provided in this disclosure, on the one hand, can determine the initial calibration resistor value and initial resistance correction step size corresponding to successful interaction test data between the on-chip system and the memory, thereby improving the rationality of the determined initial calibration resistor value and initial resistance correction step size, and thus improving the rationality of the target calibration resistor value determined based on the initial calibration resistor value and initial resistance correction step size; on the other hand, by increasing and decreasing the two calibration resistor values, the timing window determined during the data interaction between the on-chip system and the memory under the two calibration resistor values ​​is obtained, and when the two timing windows are of the same size, the corresponding initial calibration resistor value is determined as the target calibration resistor value, which can ensure reliable data communication and improve the rationality and reliability of the determined target calibration resistor value.

[0134] The following are Figure 7 The specific implementation methods of each step in the illustrated embodiment are described in detail below:

[0135] In step a2, in one optional implementation, in response to an initialization command, the on-chip system is instructed to interact with the memory to obtain test data to determine the initial calibration resistor value and the initial resistance correction step size. In another optional implementation, the initial calibration resistor value and the initial resistance correction step size are configured based on experimental results.

[0136] In this embodiment of the disclosure, in a cold start scenario for the storage module, after the storage module is powered on and undergoes a hardware reset, the firmware within the on-chip system generates an initialization command to instruct the calibration resistor adjustment module to perform initialization; alternatively, in a warm start scenario, the calibration resistor adjustment module can perform initialization after detecting the initialization command generated by the reset firmware during operation. The initial calibration resistor is a reference value used to determine the target calibration resistor, and the initial voltage correction step size is the correction magnitude value when adjusting the initial calibration resistor value during the process of determining the target calibration resistor based on the initial calibration resistor.

[0137] In one optional implementation, the process by which the calibration resistor adjustment module, in response to an initialization command, instructs the on-chip system to interact with the memory to obtain test data to determine the initial calibration resistor value and the initial resistor correction step size may include: in response to the initialization command, instructing the on-chip system to send test data to the memory based on a preset calibration resistor value; and instructing the on-chip system to collect the test response data sent by the memory based on a preset sampling clock; further, if the test response data is determined to be abnormal response test data, or if the on-chip system does not receive the test response data sent by the memory, correcting the preset calibration resistor value based on the preset resistor correction step size, and repeating the above test process based on the corrected preset calibration resistor value until test response data is received or the test response data is normal response test data; determining the corrected preset calibration resistor value as the initial calibration resistor value; and determining the preset resistor correction step size as the initial resistor correction step size.

[0138] In this context, correcting the preset calibration resistor value based on the preset resistor correction step size means increasing or decreasing the preset calibration resistor value by the preset resistor correction step size; the preset resistor correction step size can be determined based on actual needs, and this embodiment does not limit it.

[0139] In one optional implementation, if the test response data is still abnormal or the on-chip system still does not receive the response test data after repeating the above test process a target number of times based on the corrected preset calibration resistor value, then the preset resistor correction step size needs to be updated, and the above test process is re-executed based on the updated preset resistor correction step size until the test response data is normal or the response test data is received. Then, the corrected preset calibration resistor is determined as the initial calibration resistor value, and the updated preset resistor correction step size is determined as the initial resistor correction step size.

[0140] Updating the preset resistance correction step size refers to increasing or decreasing the preset resistance correction step size by a target value. This target value can be determined based on actual needs, such as half of the preset resistance correction step size. This disclosure does not limit this.

[0141] In step b2, the on-chip system is instructed to interact with the memory based on the first calibration resistor value and test data, and to determine the size of a third timing window associated with the first calibration resistor value.

[0142] In this embodiment of the disclosure, the first calibration resistor value is the difference between the initial calibration resistor value and the initial resistance correction step size.

[0143] In one optional implementation, the process by which the calibration resistor adjustment module instructs the on-chip system to interact with the memory based on a first calibration resistor value and to determine the size of a third timing window associated with the first calibration resistor value includes: the calibration resistor adjustment module instructs the on-chip system to send test data to the memory based on the difference between the initial calibration resistor value and the initial resistor correction step size; if the on-chip system receives test response data sent by the memory, or if it receives correct test response data corresponding to the test data sent by the memory, then the timing window formed by the first calibration resistor value and the initial calibration resistor value is used as the third timing window; if the on-chip system does not receive test response data sent by the memory or receives incorrect test response data sent by the memory, then the following steps are executed repeatedly, i.e., instructing the on-chip system to interact with the memory based on the updated first calibration resistor value, until the on-chip system receives test response data or correct test response data from the memory, and the loop ends. Wherein, the updated first calibration resistor value is the difference between the first calibration resistor value before the update and the initial resistor correction step size.

[0144] In another optional implementation, the process by which the calibration resistor adjustment module instructs the on-chip system to interact with the memory based on the first calibration resistor value and to determine the size of the third timing window associated with the first calibration resistor value includes: step B11, instructing the on-chip system to send test data to the memory based on the first calibration resistor value, and instructing the on-chip system to collect the test response data sent by the memory based on a preset sampling clock; step B21, if the test response data is incorrect or the on-chip system fails to collect the test response data sent by the memory within the preset sampling clock, the following steps are executed repeatedly: step B31, adjusting the phase of the preset sampling clock in the direction of decreasing phase of the sampling clock to obtain the third update. The sampling clock is updated; then, based on the first updated sampling clock, step B11 is executed until test response data or correct test response data is obtained, and the third updated sampling clock is determined as the third timing window boundary; further, the following steps are executed in a loop: step B41, instructing the on-chip system to adjust the phase of the preset sampling clock in the direction of increasing phase of the sampling clock to obtain the fourth updated sampling clock; based on the second updated sampling clock, step B11 is executed until test response data or correct test response data is obtained, and the fourth updated sampling clock is determined as the fourth timing window boundary; finally, the area between the third timing window boundary and the fourth timing window boundary is determined as the third timing window size.

[0145] Step c2 instructs the on-chip system to interact with the memory based on the second calibration resistor value and test data, and to determine the size of the fourth timing window associated with the second calibration resistor value.

[0146] In this embodiment of the disclosure, the second calibration resistor value is the sum of the initial calibration resistor value and the initial resistance correction step size.

[0147] In one optional embodiment, the process by which the calibration resistor adjustment module instructs the on-chip system to interact with the memory based on the second calibration resistor value and to determine the size of the fourth timing window associated with the second calibration resistor value includes: the calibration resistor adjustment module instructs the on-chip system to send test data to the memory based on the sum of the initial calibration resistor value and the initial resistance correction step size; if the on-chip system receives test response data sent by the memory, or if it receives correct test response data corresponding to the test data sent by the memory, then the timing window formed by the second calibration resistor value and the initial calibration resistor value is used as the fourth timing window; if the on-chip system does not receive test response data sent by the memory or receives incorrect test response data sent by the memory, then the following steps are executed repeatedly, i.e., instructing the on-chip system to interact with the memory based on the updated second calibration resistor value, until the on-chip system receives test response data or correct test response data from the memory, and then the loop ends. Wherein, the updated second calibration resistor value is the sum of the second calibration resistor before the update and the initial resistance correction step size.

[0148] It should be noted that, in another optional embodiment, the process by which the calibration resistor adjustment module instructs the on-chip system to interact with the memory based on the second calibration resistor value and test data, and to determine the size of the fourth timing window associated with the second calibration resistor value, can be referred to in the above embodiment, where the calibration resistor adjustment module instructs the on-chip system to interact with the memory based on the first calibration resistor value and test data, and to determine the size of the third timing window associated with the first calibration resistor value. This disclosure will not elaborate further on this aspect.

[0149] Step d2: When it is determined that the size of the third timing window and the size of the fourth timing window are equal, the initial calibration resistor value is determined as the target calibration resistor value.

[0150] In one alternative implementation, when it is determined that the size of the third time-series window is not equal to the size of the fourth time-series window, the following steps are repeated:

[0151] Update the initial calibration resistor value and the initial resistor correction step size; based on the updated initial calibration resistor value and the updated initial resistor correction step size, perform steps b2 and c2 above until the size of the third timing window is equal to the size of the fourth timing window. Even when the sizes of the third and fourth timing windows are not equal, proactive correction can be made to suboptimal initial calibration resistor values ​​and initial resistor correction step sizes. This effectively avoids abnormal target calibration resistor training caused by deviations in the setting of the initial calibration resistor value and initial resistor correction step size, ensuring reliable training of target calibration resistor values ​​that conform to the current scenario under various conditions such as different processes, voltage and temperature variations, and / or different memory chips. This significantly improves the reliability and training efficiency of the trained target calibration resistor values.

[0152] In one optional implementation, the process of the calibration resistor adjustment module updating the initial calibration resistor value and the initial resistance correction step size includes: when it is determined that the size of the third timing window is larger than the size of the fourth timing window, updating the initial calibration resistor value to the first calibration resistor value and decreasing the initial resistance correction step size; wherein, updating the initial calibration resistor value to the first calibration resistor value means determining the first calibration resistor value as the updated initial calibration resistor value. When the size of the third timing window is larger than the fourth timing window, if it is determined that the target calibration resistor value is closer to the first calibration resistor value associated with the third timing window, then the process of determining the first calibration resistor value as the updated initial calibration resistor value and decreasing the resistance correction step size is repeated, instructing the on-chip system to interact with the memory to obtain test data based on the updated initial calibration resistor value, until the interaction with the test data is successful and the target calibration resistor value is obtained. This improves the accuracy of determining the target calibration resistor value and, compared to manually configuring the calibration resistor value through trial and error to obtain a suitable target calibration resistor value, improves the efficiency of determining the target calibration resistor value.

[0153] Alternatively, when the size of the third timing window is determined to be smaller than the size of the fourth timing window, the initial calibration resistor value is updated to the second calibration resistor value, and the initial resistance correction step size is reduced. Here, updating the initial calibration resistor value to the second calibration resistor value means determining the second calibration resistor value as the updated initial calibration resistor value. If the size of the third timing window is smaller than the fourth timing window, and the target calibration resistor value is determined to be closer to the second calibration resistor value associated with the fourth timing window, then the process of determining the second calibration resistor value as the updated initial calibration resistor value and reducing the resistance correction step size is repeated. The on-chip system is instructed to interact with the memory to obtain test data based on the updated initial calibration resistor value until the test data interaction is successful, thus obtaining the target calibration resistor value. This improves the efficiency and accuracy of determining the target calibration resistor value.

[0154] It is understood that, in one implementation of this disclosure, reducing the initial resistance correction step size includes: reducing it by a predetermined proportion based on the initial resistance correction step size, such as reducing it by half or one-quarter. In another implementation, the difference between the reduced resistance correction step size and the original resistance correction step size can be less than or equal to the target calibration resistance difference. The target calibration resistance difference can be determined based on actual needs, and this disclosure does not limit this. For example, the target resistance difference can be half of the initial resistance correction step size, or one-third of the initial resistance correction step size.

[0155] It should be noted that, in the embodiments of this disclosure, the numbers of steps a2, b2, c2 and d2 do not represent the training order of the system interface parameter training method. For example, steps b2 and c2 can be executed simultaneously, or steps b2 can be executed first and then steps c2, or steps c2 can be executed first and then steps b2, etc. Specifically, it can be determined based on actual needs, and the embodiments of this disclosure do not limit it in this way.

[0156] For example, such as Figure 8 As shown, Figure 8 This disclosure provides another flowchart of a method for training system interface parameters of a calibration resistor adjustment module, including:

[0157] S801, in response to an initialization command, instructs the on-chip system to interact with the memory to obtain test data to determine the initial calibration resistor value and the initial resistor correction step size;

[0158] S802, instructs the on-chip system to interact with the memory based on the first calibration resistor value (the difference between the initial calibration resistor value and the initial resistor correction step size) and determine the third timing window size win3 associated with the first calibration resistor value;

[0159] S803 instructs the on-chip system to interact with memory test data based on the second calibration resistor value (the sum of the initial calibration resistor value and the initial resistor correction step size) and determine the fourth timing window size win4 associated with the second calibration resistor value;

[0160] S804, determine whether the size of the third time window win3 is equal to the size of the fourth time window win4;

[0161] S805, if the third timing window size win3 is equal to the fourth timing window size win4, then the initial calibration resistor is determined as the target calibration resistor value;

[0162] S806, if the size of the third time window win3 is not equal to the size of the fourth time window win4, then determine whether the size of the third time window win3 is greater than the size of the fourth time window win4;

[0163] S807, if the third timing window size win3 is greater than the fourth timing window size win4, then the following process is executed repeatedly: the first calibration resistor value is determined as the updated initial calibration resistor value, and the resistance correction step size is reduced, for example, by half, as the new resistance correction step size. Then, S802 to S803 are executed again until the updated third timing window size win3 and the updated fourth timing window size win4 are determined to be equal. The loop ends, and the updated initial calibration resistor value is determined as the target calibration resistor value.

[0164] S808, if the third timing window size win3 is less than the fourth timing window size win4, then the following process is executed repeatedly: the second calibration resistor value is determined as the updated initial calibration resistor value, and the resistance correction step size is reduced, for example, by half as the new initial resistance correction step size. Then, S802 to S803 are executed again until the updated third timing window size win3 and the updated fourth timing window size win4 are determined to be equal. The loop ends, and the updated initial calibration resistor value is determined as the target calibration resistor value.

[0165] In S801-S808 above, assuming the on-chip system successfully exchanges test data with the memory, the corresponding initial calibration resistor value is 120Ω and the initial resistance correction step size is 60. The on-chip system is instructed to exchange test data with the memory based on the first calibration resistor value of 60Ω and the second calibration resistor value of 180Ω respectively. Assuming both exchanges are successful, the third timing window size win3 associated with 60Ω and the fourth timing window size win4 associated with 180Ω are determined. The sizes of win3 and win4 are compared. If win3 equals win4, then 120Ω is determined as the target calibration resistor value; if win3 does not equal win4, then... If n4 is equal to 60Ω, then the larger of the corresponding calibration resistor values ​​between win3 and win4 is used as the new initial calibration resistor value (i.e., one of the first and second calibration resistor values). For example, the larger window value win3 (60Ω) is used as the new initial calibration resistor value, and the initial voltage correction step size is reduced, for example, by half, i.e., the new initial voltage correction step size is 30. Then, based on the new initial calibration resistor value (e.g., 60Ω) and the new initial reference voltage correction step size (e.g., 30), steps S802-S803 are executed until win3 and win4 are equal, and the corresponding new initial calibration resistor value is used as the target calibration resistor value. This disclosure also provides a system interface parameter training method, applied to the above-mentioned storage module, where the on-chip system in the storage module includes a delay control module, such as... Figure 9 As shown, the process of the delay control module executing the method includes:

[0166] S901, determine the boundary of the first signal delay value based on the initial signal delay value and the first signal delay value correction step size;

[0167] S902, based on the first signal delay value boundary and the second signal delay value correction step size, determine the second signal delay value boundary;

[0168] Wherein, the correction step size for the second signal delay value is smaller than the correction step size for the first signal delay value;

[0169] S903, based on the first signal delay value correction step size and the second signal delay value boundary, determine the third signal delay value boundary;

[0170] Among them, the boundary of the third signal delay value is greater than the boundary of the second signal delay value;

[0171] S904, the average difference between the second signal delay value boundary and the third signal delay value boundary is determined as the target signal delay value;

[0172] In the case where the delay control module includes a data delay submodule, the signal is a data strobe signal or a data signal; in the case where the delay control module includes an address delay submodule, the signal is an address signal; and in the case where the delay control module includes a command delay submodule, the signal is a command signal.

[0173] In summary, the system interface parameter training method provided in this embodiment allows the delay control module to respond to an initialization command by first coarsely adjusting the signal delay value based on an initial signal delay value and a larger first signal delay value to preliminarily determine the boundary of the first signal delay value, and then finely adjusting the signal delay value with a smaller second signal delay value to determine the boundary of the second signal delay value. Simultaneously, based on the boundary of the second signal delay value and a larger first signal delay value, a third signal delay value boundary is determined, and the average difference between the second and third signal delay value boundaries is determined as the target signal delay value. The method combines coarse and fine adjustments in determining the boundary of the second signal delay value, which not only improves the reliability of the second signal delay value boundary but also improves the reliability of the target signal delay value. Furthermore, the efficiency of determining the target signal delay value is improved because the delay value boundary can be quickly determined with a large step size.

[0174] The following are Figure 9 The specific implementation methods of each step in the illustrated embodiment are described in detail below:

[0175] In S901, in one optional implementation, the delay control module responds to the initialization command by determining the boundary of the first signal delay value based on the initial signal delay value and the first signal delay value correction step size.

[0176] In this embodiment of the disclosure, in a cold start scenario for the storage module, after the storage module is powered on and undergoes a hardware reset, the firmware within the on-chip system generates an initialization command to instruct the delay control module to perform initialization; alternatively, in a warm start scenario, the delay control module can perform initialization after detecting the initialization command generated by the reset firmware during operation. The initial signal delay value is a reference value used to determine the target signal delay value. The first signal delay value correction step size and the second signal delay value correction step size are the correction amplitude values ​​when correcting the signal delay value during the process of determining the target signal delay value based on the initial signal delay value. Specifically, these values ​​can be determined based on actual needs, and this embodiment of the disclosure does not limit them.

[0177] In one optional implementation, the delay control module, in response to an initialization command, determines the boundary of a first signal delay value based on an initial signal delay value and a first signal delay value correction step size. This process includes: determining the sum of the initial signal delay value and the first signal delay value correction step size to obtain a first test signal delay value; instructing the on-chip system to interact with the memory to exchange test data based on the first test signal delay value; if the on-chip system interacts with the memory to exchange test data without error, repeating the following steps: determining the first test signal delay value as the updated initial signal delay value; determining the sum of the updated initial signal delay value and the first signal delay value correction step size to obtain an updated first test signal delay value; instructing the on-chip system to interact with the memory to exchange test data based on the updated first test signal delay value, until an error occurs in the on-chip system interacts with the memory to exchange test data, and then determining the updated first test signal delay value as the boundary of the first signal delay value. By repeatedly using a larger first signal delay value to correct the step size, and increasing the first test signal delay value obtained from the initial signal delay value for interactive testing, a suitable first signal delay value boundary can be quickly located, that is, the left boundary of the effective signal window can be quickly determined, which can improve the efficiency of data sampling.

[0178] It should be noted that when the delay control module instructs the on-chip system to interact with the memory based on the delay value of the first test signal, it means that the on-chip system sends test data to the memory based on the delay value of the first test signal. When the on-chip system interacts with the memory without errors, it means that the on-chip system receives test response data returned by the memory after sending the test data, or receives test response data returned by the memory that corresponds one-to-one with the test data.

[0179] In one optional implementation, the process by which the delay control module determines the second signal delay value boundary based on a first signal delay value boundary and a second signal delay value correction step size includes: determining the difference between the first signal delay value boundary and the second signal delay value correction step size to obtain a second test signal delay value; instructing the on-chip system to interact with the memory using test data based on the second test signal delay value; if an error occurs during the interaction of test data between the on-chip system and the memory, repeating the following steps: determining the second test signal delay value as the updated first signal delay value boundary; determining the difference between the updated first signal delay value boundary and the second signal delay value correction step size to obtain an updated second test signal delay value; instructing the on-chip system to interact with the memory using test data based on the updated second test signal delay value until no error occurs during the interaction of test data between the on-chip system and the memory, and then determining the updated second test signal delay value as the second signal delay value boundary. By repeatedly using a smaller first signal delay value to correct the step size, the second test signal delay value obtained by reducing the first test signal delay value is used for interactive testing. If the interactive data is correct again during the repetition process, the updated second test signal delay value is determined as the final left boundary of the signal valid window. In this way, the left boundary of the window can be precisely located by backtracking, which improves the accuracy of determining the left boundary of the signal valid window.

[0180] In one optional implementation, the process by which the delay control module determines a third signal delay value boundary based on a first signal delay value correction step size and a second signal delay value boundary includes: determining the sum between the second signal delay value boundary and the first signal delay value correction step size to obtain a third test signal delay value, and instructing the on-chip system to interact with the memory to obtain test data based on the third test signal delay value; if the on-chip system interacts with the memory to obtain test data without error, then repeating the following steps: determining the third test signal delay value as the updated second signal delay value boundary; determining the sum between the updated second signal delay value boundary and the first signal delay value correction step size to obtain an updated third test signal delay value; instructing the on-chip system to interact with the memory to obtain test data based on the updated third test signal delay value, until an error occurs in the on-chip system interacts with the memory to obtain test data, and then determining the updated third test signal delay value as the third signal delay value boundary. By repeatedly using a larger first signal delay value to correct the step size, the third test signal delay value obtained by increasing the left boundary of the fine-tuned signal effective window is used for interactive testing. If an error occurs in the interactive data during the repetition process, the updated third test signal delay value is determined as the boundary of the third signal delay value. This achieves the goal of determining the boundary of the third signal delay value through a fast coarse adjustment method, and improves the efficiency of determining the right boundary of the signal effective window.

[0181] In one optional implementation, after determining the third signal delay value boundary based on the first signal delay value correction step size and the second signal delay value boundary, the delay control module can further: obtain a fourth signal delay value boundary based on the third signal delay value boundary and the second signal delay value correction step size; and determine the fourth signal delay value boundary as the adjusted third signal delay value boundary. After obtaining the right boundary of the effective signal window, the third signal delay value boundary can be finely adjusted using a smaller second signal delay value correction step size to improve the accuracy of the determined right boundary of the effective signal window.

[0182] The process of obtaining the fourth signal delay value boundary based on the third signal delay value boundary and the second signal delay value correction step size includes: determining the difference between the third signal delay value boundary and the second signal delay value correction step size to obtain the fourth test signal delay value, and instructing the on-chip system to interact with the memory to obtain test data based on the fourth test signal delay value; if it is determined that an error occurs during the interaction of test data between the on-chip system and the memory, the following steps are repeated: determining the fourth test signal delay value as the updated third signal delay value boundary; determining the difference between the updated third signal delay value boundary and the second signal delay value correction step size to obtain the updated fourth test signal delay value; instructing the on-chip system to interact with the memory to obtain test data based on the updated fourth test signal delay value until no error occurs during the interaction of test data between the on-chip system and the memory, and determining the corresponding updated fourth test signal delay value as the fourth signal delay value boundary. The interaction test is performed by repeatedly reducing the third signal delay value boundary by a smaller second signal delay value to obtain a fourth test signal delay value. If the interaction data is correct again during the repetition process, the updated fourth test signal delay value is determined as the updated third signal delay value boundary. This achieves the goal of finely adjusting the third signal delay value boundary through a backtracking fine-tuning strategy, further improving the accuracy of the right boundary of the determined effective signal window.

[0183] It is understandable that the above-mentioned delay control module instructs the on-chip system to interact with the memory based on the test signal delay value (such as the first test signal delay value / second test signal delay value / third test signal delay value / fourth signal delay value). This means instructing the on-chip system to send test data to the memory based on the test signal delay value and receive test response data from the memory, or instructing the memory to send test data to the on-chip system based on the test signal delay value and receive test response data from the on-chip system.

[0184] It should be noted that, in the embodiments of this disclosure, when the delay control module includes an address delay submodule or a command delay submodule, the address delay submodule or the command delay submodule can perform clock signal delay training to obtain the target clock signal delay value; the process of the address delay submodule or the command delay submodule performing clock signal delay training to obtain the target clock signal delay value can refer to the process of determining the target signal delay value in the above embodiments, and this disclosure does not limit it.

[0185] For example, such as Figure 10 A flowchart illustrating a method for training system interface parameters of a delay control module according to an embodiment of this disclosure is shown, including:

[0186] S101, determine the sum of the initial signal delay value and the first signal delay value correction step size, obtain the first test signal delay value, and instruct the on-chip system to interact with the memory to test data based on the first test signal delay value;

[0187] S102, determine whether there is an error in the process of the on-chip system interacting with the memory to obtain test data;

[0188] S103, if there is no error in the process of the on-chip system interacting with the memory to exchange test data, the first test signal delay value is determined as the updated initial signal delay value, and the process is repeated in S101 until there is an error in the process of the on-chip system interacting with the memory to exchange test data, and the updated first test signal delay value is determined as the boundary of the first signal delay value.

[0189] S104, if an error occurs during the process of exchanging test data between the on-chip system and the memory, the first test signal delay value is determined as the boundary of the first signal delay value;

[0190] S105, determine the difference between the boundary of the first signal delay value and the correction step size of the second signal delay value, obtain the second test signal delay value, and instruct the on-chip system to interact with the memory based on the second test signal delay value;

[0191] S106, determine whether there is an error in the process of exchanging test data between the on-chip system and the memory;

[0192] S107, if it is determined that an error occurred during the interaction of test data between the on-chip system and the memory, the second test signal delay value is determined as the boundary of the updated first signal delay value, and the process is repeated in S105 until no error is found during the interaction of test data between the on-chip system and the memory, and the updated second test signal delay value is determined as the boundary of the second signal delay value.

[0193] S108, if it is determined that there are no errors in the process of the on-chip system interacting with the memory to obtain test data, the second test signal delay value is determined as the boundary of the second signal delay value;

[0194] S109, determine the boundary of the second signal delay value and the sum of the correction steps of the first signal delay value, obtain the third test signal delay value, and instruct the on-chip system to interact with the memory to test data based on the third test signal delay value;

[0195] S1010, determines whether there is an error in the process of exchanging test data between the on-chip system and the memory;

[0196] S1011, If ​​there is no error in the process of the on-chip system interacting with the memory to exchange test data, the third test signal delay value is determined as the boundary of the updated second signal delay value, and the process is repeated in S109 until there is an error in the process of the on-chip system interacting with the memory to exchange test data, and the updated third test signal delay value is determined as the boundary of the third signal delay value.

[0197] S1012, If an error occurs during the process of exchanging test data between the on-chip system and the memory, the delay value of the third test signal is determined as the boundary of the delay value of the third signal.

[0198] S1013, determine the boundary of the third signal delay value and the difference between the correction steps of the second signal delay value, obtain the fourth test signal delay value, and instruct the on-chip system to interact with the memory test data based on the fourth test signal delay value;

[0199] S1014, determine whether there is an error in the process of exchanging test data between the on-chip system and the memory;

[0200] S1015, if it is determined that an error occurred during the interaction of test data between the on-chip system and the memory, the delay value of the fourth test signal is determined as the boundary of the updated delay value of the third signal, and the process is repeated in S1013 until it is determined that no error occurred during the interaction of test data between the on-chip system and the memory, and the updated delay value of the fourth test signal is determined as the boundary of the fourth signal delay value.

[0201] S1016, If it is determined that there are no errors in the process of the on-chip system interacting with the memory to obtain test data, the delay value of the fourth test signal is determined as the boundary of the delay value of the fourth signal;

[0202] S1017, The boundary of the fourth signal delay value is determined as the adjusted boundary of the third signal delay value;

[0203] S1018, the average difference between the adjusted third signal delay value boundary and the second signal delay value boundary is determined as the target signal delay value.

[0204] Exemplary embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing a computer program, wherein the computer program, when executed by a computer's processor, is used to cause the computer to perform a method according to embodiments of this disclosure.

[0205] like Figure 11 As shown, an exemplary embodiment of this disclosure also provides a computer program product 1100, including a computer program 1101, wherein the computer program, when executed by a computer's processor, is used to cause the computer to perform a method according to an embodiment of this disclosure.

[0206] Exemplary embodiments of this disclosure also provide an electronic device, including the storage module provided in the above embodiments, wherein a reference voltage adjustment module in the system-on-a-chip of the storage module is used to execute the above-described system interface parameter training method to determine a target reference voltage; and / or, a calibration resistor adjustment module in the system-on-a-chip is used to execute the above-described system interface parameter training method to determine a target calibration resistor; and / or, a delay control module in the system-on-a-chip is used to execute the above-described system interface parameter training method to determine a target signal delay value.

[0207] refer to Figure 12 The following description serves as a structural block diagram of the electronic device 1200 disclosed herein, which is an example of a hardware device applicable to various aspects of this disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the disclosure described and / or claimed herein.

[0208] like Figure 12 As shown, the electronic device 1200 includes a computing unit 1201, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1202 or a computer program loaded from a storage unit 1208 into a random access memory (RAM) 1203. The RAM 1203 may also store various programs and data required for the operation of the electronic device 1200. The computing unit 1201, ROM 1202, and RAM 1203 are interconnected via a bus 1204. An input / output (I / O) interface 1205 is also connected to the bus 1204.

[0209] Multiple components in electronic device 1200 are connected to I / O interface 1205, including: input unit 1206, output unit 1207, storage unit 1208, and communication unit 1209. Input unit 1206 can be any type of device capable of inputting information to electronic device 1200. Input unit 1206 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of electronic device. Output unit 1207 can be any type of device capable of presenting information and may include, but is not limited to, a display, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 1208 may include, but is not limited to, disk and optical disk. Communication unit 1209 allows electronic device 1200 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and / or chipsets, such as Bluetooth™ devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0210] The computing unit 1201 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1201 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1201 performs the various methods and processes described above. For example, in some embodiments, the methods of the exemplary embodiments of this disclosure can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 1208. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 1200 via ROM 1202 and / or communication unit 1209. In some embodiments, the computing unit 1201 can be configured to perform the methods of the exemplary embodiments of this disclosure by any other suitable means (e.g., by means of firmware).

[0211] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0212] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0213] As used in this disclosure, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, device, and / or apparatus (e.g., disk, optical disk, memory, programmable logic device (PLD)) for providing machine instructions and / or data to a programmable processor, including machine-readable media that receive machine instructions as machine-readable signals. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0214] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0215] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0216] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this disclosure are performed, in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center integrating one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD).

[0217] Although this disclosure has been described in conjunction with specific features and embodiments, it will be apparent that various modifications and combinations can be made therein without departing from the spirit and scope of this disclosure. Accordingly, this specification and drawings are merely exemplary illustrations of the disclosure as defined by the appended claims and are to be considered as covering any and all modifications, variations, combinations, or equivalents within the scope of this disclosure. It is obvious that those skilled in the art can make various alterations and modifications to this disclosure without departing from its spirit and scope. Thus, this disclosure is also intended to include any such modifications and modifications that fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. A system-on-a-chip (SoC) capable of communicating with a memory, characterized in that, It includes at least one of a reference voltage adjustment module, a calibration resistor adjustment module, and a delay control module; wherein, The reference voltage adjustment module is used to perform reference voltage value training to obtain a target reference voltage value, and the on-chip system and the memory communicate based on the target reference voltage value; The calibration resistor adjustment module is used to perform calibration resistor value training to obtain a target calibration resistor value, and the on-chip system and the memory communicate based on the target calibration resistor value; The delay control module is used to perform signal delay value training to obtain a target signal delay value, and the on-chip system and the memory communicate based on the target signal delay value; The delay control module obtains the target signal delay value through the following system interface parameter training method: The boundary of the first signal delay value is determined based on the initial signal delay value and the correction step size of the first signal delay value. Based on the first signal delay value boundary and the second signal delay value correction step size, the second signal delay value boundary is determined; wherein the second signal delay value correction step size is smaller than the first signal delay value correction step size; Based on the first signal delay value correction step size and the second signal delay value boundary, a third signal delay value boundary is determined, wherein the third signal delay value boundary is greater than the second signal delay value boundary; The average difference between the boundary of the second signal delay value and the boundary of the third signal delay value is determined as the target signal delay value; wherein, when the delay control module includes a data delay submodule, the signal is a data strobe signal or a data signal; when the delay control module includes an address delay submodule, the signal is an address signal; and when the delay control module includes a command delay submodule, the signal is a command signal.

2. The system-on-a-chip according to claim 1, characterized in that, The delay control module includes at least one of a data delay submodule, an address delay submodule, and a command delay submodule; The data delay submodule is used to perform data gating signal delay training to obtain a target data gating signal delay value, and / or perform data signal delay training to obtain a target data signal delay value. The on-chip system and the memory communicate based on the target data gating signal delay value and / or the target data signal delay value. The address delay submodule is used to perform address signal delay training to obtain a target address signal delay value, and the on-chip system and the memory communicate based on the target address signal delay value; The command delay submodule is used to perform command signal delay training to obtain a target command signal delay value, and the on-chip system and the memory communicate based on the target command signal delay value.

3. The system-on-a-chip according to claim 1, characterized in that, The reference voltage adjustment module obtains the target reference voltage value through the following system interface parameter training method: Step a1: Determine the initial reference voltage value and the initial voltage correction step size; Step b1: Instruct the on-chip system to interact with the memory based on the first reference voltage value and test data, and determine the size of the first timing window associated with the first reference voltage value, wherein the first reference voltage value is the difference between the initial reference voltage value and the initial voltage correction step size; Step c1: Instruct the on-chip system to interact with the memory based on the second reference voltage value and test data, and determine the size of the second timing window associated with the second reference voltage value, wherein the second reference voltage value is the sum of the initial reference voltage value and the initial voltage correction step size; Step d1: When it is determined that the size of the first timing window and the size of the second timing window are equal, the initial reference voltage value is determined as the target reference voltage value.

4. The system-on-a-chip according to claim 3, characterized in that, Also includes: When it is determined that the size of the first timing window is not equal to the size of the second timing window, repeat the following steps: Update the initial reference voltage value and the initial voltage correction step size; Steps b1 and c1 are performed based on the updated initial reference voltage value and the updated initial voltage correction step size; This continues until the size of the first timing window is equal to the size of the second timing window.

5. The system-on-a-chip according to claim 4, characterized in that, The updating of the initial reference voltage value and the initial voltage correction step size includes: When it is determined that the size of the first timing window is larger than the size of the second timing window, the initial reference voltage value is updated to the first reference voltage value, and the initial voltage correction step size is reduced. When it is determined that the size of the first timing window is smaller than the size of the second timing window, the initial reference voltage value is updated to the second reference voltage value, and the initial voltage correction step size is reduced.

6. The system-on-a-chip according to claim 1, characterized in that, The calibration resistor adjustment module obtains the target calibration resistor value through the following system interface parameter training method: Step a2: Determine the initial calibration resistor value and the initial resistance correction step size; Step b2: Instruct the on-chip system to interact with the memory based on the first calibration resistor value and test data, and determine the size of a third timing window associated with the first calibration resistor value, wherein the first calibration resistor value is the difference between the initial calibration resistor value and the initial resistor correction step size; Step c2: Instruct the on-chip system to interact with the memory based on the second calibration resistor value and test data, and determine the size of the fourth timing window associated with the second calibration resistor value, wherein the second calibration resistor value is the sum of the initial calibration resistor value and the initial resistor correction step size; Step d2: When it is determined that the size of the third timing window and the size of the fourth timing window are equal, the initial calibration resistor value is determined as the target calibration resistor value.

7. The system-on-a-chip according to claim 6, characterized in that, Also includes: When it is determined that the size of the third time-series window is not equal to the size of the fourth time-series window, repeat the following steps: Update the initial calibration resistor value and the initial resistance correction step size; Based on the updated initial calibration resistor value and the updated initial resistor correction step size, perform steps b2 and c2; This continues until the size of the third timing window is equal to the size of the fourth timing window.

8. The system-on-a-chip according to claim 7, characterized in that, The updating of the initial calibration resistor value and the initial resistance correction step size includes: When it is determined that the size of the third timing window is larger than the size of the fourth timing window, the initial calibration resistor value is updated to the first calibration resistor value, and the initial resistor correction step size is reduced. When it is determined that the size of the third timing window is smaller than the size of the fourth timing window, the initial calibration resistor value is updated to the second calibration resistor value, and the initial resistor correction step size is reduced.

9. The system-on-a-chip according to claim 1, characterized in that, The step of determining the boundary of the first signal delay value based on the initial signal delay value and the correction step size of the first signal delay value includes: The sum of the initial signal delay value and the correction step size of the first signal delay value is determined to obtain the first test signal delay value; The on-chip system interacts with the memory based on the delay value of the first test signal; If the process of the on-chip system interacting with the memory to exchange test data proceeds without error, then repeat the following steps: The first test signal delay value is determined as the updated initial signal delay value; The updated initial signal delay value and the sum of the first signal delay value correction step size are determined to obtain the updated first test signal delay value; The updated first test signal delay value indicates the test data for the interaction between the on-chip system and the memory; Until an error occurs during the process of the on-chip system interacting with the memory to exchange test data, the updated first test signal delay value is determined as the boundary of the first signal delay value.

10. The system-on-a-chip according to claim 1, characterized in that, Determining the second signal delay value boundary based on the first signal delay value boundary and the second signal delay value correction step size includes: The difference between the boundary of the first signal delay value and the correction step size of the second signal delay value is determined to obtain the second test signal delay value; The on-chip system interacts with the memory based on the delay value of the second test signal; If an error occurs during the process of the on-chip system interacting with the memory to exchange test data, the following steps are repeated: The second test signal delay value is determined as the updated boundary of the first signal delay value; Based on the difference between the updated first signal delay value boundary and the second signal delay value correction step size, the updated second test signal delay value is obtained; The updated second test signal delay value indicates the test data for the interaction between the on-chip system and the memory; Until no errors occur during the process of the on-chip system interacting with the memory to obtain test data, the updated second test signal delay value is determined as the boundary of the second signal delay value.

11. The system-on-a-chip according to claim 1, characterized in that, The step of determining the third signal delay value boundary based on the first signal delay value correction step size and the second signal delay value boundary includes: The boundary of the second signal delay value is determined, and the sum of the correction steps of the first signal delay value is obtained to obtain the third test signal delay value; The on-chip system interacts with the memory based on the delay value of the third test signal; If the process of the on-chip system interacting with the memory to exchange test data proceeds without error, then repeat the following steps: The third test signal delay value is determined as the updated boundary of the second signal delay value; The updated third test signal delay value is obtained by determining the sum between the updated boundary of the second signal delay value and the correction step size of the first signal delay value. The updated third test signal delay value indicates the test data for the interaction between the on-chip system and the memory. Until an error occurs during the process of the on-chip system interacting with the memory to obtain test data, the updated third test signal delay value is determined as the boundary of the third signal delay value.

12. The system-on-a-chip according to claim 1, characterized in that, After determining the third signal delay value boundary based on the first signal delay value correction step size and the second signal delay value boundary, the method further includes: Based on the third signal delay value boundary and the second signal delay value correction step size, the fourth signal delay value boundary is obtained; The boundary of the fourth signal delay value is determined as the adjusted boundary of the third signal delay value.

13. The system-on-a-chip according to claim 12, characterized in that, The step of obtaining the fourth signal delay value boundary based on the third signal delay value boundary and the second signal delay value correction step size includes: The difference between the boundary of the third signal delay value and the correction step size of the second signal delay value is determined to obtain the fourth test signal delay value; The on-chip system interacts with the memory based on the delay value of the fourth test signal; If an error occurs during the process of the on-chip system interacting with the memory to exchange test data, the following steps are repeated: The delay value of the fourth test signal is determined as the boundary of the updated delay value of the third signal; The difference between the updated boundary of the third signal delay value and the correction step size of the second signal delay value is determined to obtain the updated fourth test signal delay value; The updated fourth test signal delay value indicates the test data for the interaction between the on-chip system and the memory. Until no errors occur during the process of the on-chip system interacting with the memory to obtain test data, the corresponding updated fourth test signal delay value is determined as the boundary of the fourth signal delay value.

14. A storage module, characterized in that, The storage module includes the system-on-a-chip as described in claim 1, and a memory that communicates with the system-on-a-chip.

15. An electronic device, characterized in that, Including the storage module as described in claim 14, the reference voltage adjustment module in the system-on-chip of the storage module is used to perform reference voltage value training to obtain a target reference voltage value, and the system-on-chip communicates with the memory based on the target reference voltage value; And / or, The calibration resistor adjustment module in the system-on-a-chip is used to perform calibration resistor value training to obtain a target calibration resistor value, and the system-on-a-chip communicates with the memory based on the target calibration resistor value; and / or, The delay control module in the system-on-a-chip is used to perform signal delay value training to obtain a target signal delay value. The system-on-a-chip communicates with the memory based on the target signal delay value. The delay control module obtains the target signal delay value through the following system interface parameter training method: The boundary of the first signal delay value is determined based on the initial signal delay value and the correction step size of the first signal delay value. Based on the first signal delay value boundary and the second signal delay value correction step size, the second signal delay value boundary is determined; wherein the second signal delay value correction step size is smaller than the first signal delay value correction step size; Based on the first signal delay value correction step size and the second signal delay value boundary, a third signal delay value boundary is determined, wherein the third signal delay value boundary is greater than the second signal delay value boundary; The average difference between the boundary of the second signal delay value and the boundary of the third signal delay value is determined as the target signal delay value; wherein, when the delay control module includes a data delay submodule, the signal is a data strobe signal or a data signal; when the delay control module includes an address delay submodule, the signal is an address signal; and when the delay control module includes a command delay submodule, the signal is a command signal.

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