Programmable chip multi-module parallel dft verification method and system

Abstract

This invention relates to the field of integrated circuit testing technology, and more particularly to a method and system for parallel DFT verification of multiple modules of a programmable chip. The invention routes the I / O ports of the programmable chip to the scan signal interface of a designated module to generate a customized bit stream. A DFT simulation management file is created, merging the scan signal interfaces of all designated modules into a unified scan signal interface. Based on the DFT simulation management file, a stimulus data file and a test protocol file are generated. Customized stimuli are generated by combining the customized bit stream, and parallel scanning of multiple designated modules is achieved based on these customized stimuli, thus improving the flexibility and efficiency of DFT verification.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and in particular to a method and system for parallel DFT verification of programmable chips with multiple modules. Background Technology

[0002] Design for Testability (DFT) is a common method for detecting chip defects.

[0003] Traditional DFT scanning methods are generally determined during the design phase. Verification personnel use EDA tools to perform chain insertion and DFT simulation verification based on the scan signal interfaces reserved in the design. This approach is not flexible enough for DFT verification of programmable chips. Typically, due to the limited number of reserved scan signal interfaces, the available IO (Input / Output) resources for use as scan signal interfaces are limited, which slows down simulation efficiency. On the other hand, for the sake of scanning efficiency, traditional scan chain designs may couple multiple modules together, which increases the difficulty of subsequent problem localization.

[0004] In recent years, emerging technologies have proposed test platforms suitable for large-scale chip simulation, as well as methods to convert various raw test vectors into vectors that the platform can recognize. These methods have superior performance compared to traditional software simulation platforms and can reduce the simulation time. However, this approach cannot specify which modules are inside the programmable chip to scan, and the I / O resources available for this approach are determined at the beginning of the design.

[0005] Therefore, proposing a DFT simulation verification method suitable for programmable chips with freely specifyable simulation modules is a problem that urgently needs to be solved. Summary of the Invention

[0006] This invention provides a method and system for parallel DFT verification of multiple modules in a programmable chip. It generates customized stimuli by using a stimulus data file, a test protocol file, and a customized bit stream, and performs parallel scanning of multiple specified modules based on the customized stimuli, thereby improving the flexibility and efficiency of DFT verification.

[0007] To achieve the above objectives, the present invention provides a multi-module parallel DFT verification method for programmable chips, the method comprising:

[0008] Identify the I / O ports of the programmable chip and multiple designated modules to be scanned;

[0009] The IO port is routed to the scan signal interface of the designated module to generate a plug-in netlist, and a custom bit stream is generated based on the plug-in netlist;

[0010] Modify the scan signal interface of each specified module to a unified scan signal interface and instantiate the specified module to generate a DFT simulation control file;

[0011] Input the DFT simulation control file and the pluggable netlist into a preset DFT stimulus generation tool to generate stimulus data files and test protocol files;

[0012] Generate the top layer of the programmable chip based on the interleaved netlist;

[0013] Instantiate the test protocol file to generate the top-level test protocol;

[0014] Interconnect the top layer of the programmable chip and the top layer of the test protocol;

[0015] Based on the customized bitstream and the stimulus data file, perform parallel DFT simulations of multiple specified modules on the top layer of the programmable chip and the top layer of the test protocol to obtain the DFT verification results of the specified modules.

[0016] Optionally, determining the I / O ports of the programmable chip and the multiple designated modules to be scanned includes:

[0017] The available I / O ports in the programmable chip are determined based on pin constraints;

[0018] The specified module to be scanned is determined, and the number of scan signal interfaces of the specified module to be scanned does not exceed the number of I / O ports.

[0019] Optionally, the step of routing the IO port to the scan signal interface of the designated module to obtain a plug-in netlist, and generating a custom bitstream based on the plug-in netlist, includes:

[0020] Determine the location information of the specified module in the programmable chip;

[0021] Based on the location information, complete the wiring from the IO port to the idle interface of the designated module, and generate a wiring netlist;

[0022] The idle interface in the wiring netlist is modified to the scan signal interface reserved by the designated module and the preset scan logic is inserted to obtain the plug-in netlist;

[0023] A custom bitstream is generated based on the aforementioned interleaved netlist.

[0024] Optionally, the step of modifying the scan signal interface of each specified module to a unified scan signal interface and instantiating the specified module to generate a DFT simulation control file further includes:

[0025] Determine the value of the non-scanning signal interface of the specified module in scan mode, and generate fixed value constraints. The fixed value constraints are used to store the subsequently generated DFT simulation control file.

[0026] The cancellation circuit components are set to cancel the reserved circuit components at the scan signal interface of the specified module. The cancellation circuit components are used to store the subsequently generated DFT simulation control file.

[0027] Optionally, the step of inputting the DFT simulation control file and the pluggable netlist into a preset DFT stimulus generation tool to generate stimulus data files and test protocol files includes:

[0028] The preset DFT excitation generation tool determines the excitation information for the specified module based on the instantiated specified module, the fixed value constraint, and the cancellation circuit components, and generates an excitation data file;

[0029] The test protocol file is generated by setting the stimulus output interface and result detection interface using the preset DFT stimulus generation tool.

[0030] Optionally, the top layer of the test protocol includes an excitation output interface and a result detection interface;

[0031] The interconnection of the programmable chip top layer and the test protocol top layer includes:

[0032] The excitation output interface of the top layer of the test protocol is interconnected with the top layer of the programmable chip, and the result detection interface of the top layer of the test protocol is interconnected with the top layer of the programmable chip.

[0033] Optionally, the scan signal interface includes a scan input interface and a scan output interface;

[0034] The step of performing parallel DFT simulations of multiple specified modules on the top layer of the programmable chip and the top layer of the test protocol based on the customized bitstream and the stimulus data file, and obtaining the DFT verification results of the specified modules, includes:

[0035] The customized bitstream is input into the top layer of the programmable chip to configure the scan path and generate a scan signal.

[0036] The scanning signal controls the top layer of the test protocol to generate a stimulus data signal based on the stimulus data file.

[0037] The excitation data signal is input to the top layer of the programmable chip through the excitation output interface of the top layer of the test protocol, and then input to the scan input interface of multiple designated modules through the plug-in netlist of the top layer of the programmable chip to obtain the scan result by performing parallel scan on multiple designated modules;

[0038] The scan result is output through the scan output interface to the result detection interface at the top layer of the programmable chip via the top layer of the test protocol.

[0039] The top layer of the test protocol performs detection based on the scan results to obtain DFT verification results for multiple specified modules.

[0040] This invention also provides a programmable chip multi-module parallel DFT verification system, the system comprising:

[0041] The information confirmation module is used to determine the I / O ports of the programmable chip and the specified modules to be scanned.

[0042] The bit stream generation module is used to generate a plug-in netlist by routing the IO port to the scan signal interface of the designated module, and generate a customized bit stream based on the plug-in netlist;

[0043] A customized stimulus file generation module is used to modify the scan signal interface of each specified module to a unified scan signal interface and instantiate the specified module to generate a DFT simulation control file; the DFT simulation control file and the pluggable netlist are input into a preset DFT stimulus generation tool to generate a stimulus data file and a test protocol file;

[0044] The simulation verification module is used to generate a programmable chip top layer based on the interleaving netlist; instantiate the test protocol file to generate a test protocol top layer; interconnect the programmable chip top layer and the test protocol top layer; and perform parallel DFT simulations of multiple specified modules on the programmable chip top layer and the test protocol top layer based on the custom bit stream and the stimulus data file to obtain the DFT verification results of the specified modules.

[0045] Optionally, the top layer of the test protocol includes an excitation output interface and a result detection interface;

[0046] The simulation verification module is specifically used for:

[0047] The excitation output interface of the top layer of the test protocol is interconnected with the top layer of the programmable chip, and the result detection interface of the top layer of the test protocol is interconnected with the top layer of the programmable chip.

[0048] Optionally, the scan signal interface includes a scan input interface and a scan output interface;

[0049] The simulation verification module is specifically used for:

[0050] The customized bitstream is input into the top layer of the programmable chip to configure the scan path and generate a scan signal.

[0051] The scanning signal controls the top layer of the test protocol to generate a stimulus data signal based on the stimulus data file.

[0052] The excitation data signal is input to the top layer of the programmable chip through the excitation output interface of the top layer of the test protocol, and then input to the scan input interface of multiple designated modules through the plug-in netlist of the top layer of the programmable chip to obtain the scan result by performing parallel scan on multiple designated modules;

[0053] The scan result is output through the scan output interface to the result detection interface at the top layer of the test protocol via the top layer of the programmable chip;

[0054] The top layer of the test protocol performs detection based on the scan results to obtain DFT verification results for multiple specified modules.

[0055] This invention routes the I / O ports of a programmable chip to the scan signal interface of a specified module to generate a custom bit stream. It creates a DFT simulation management file to merge the scan signal interfaces of all specified modules into a unified scan signal interface. Based on the DFT simulation management file, it generates a stimulus data file and a test protocol file. Combined with the custom bit stream, it generates a custom stimulus. Based on the custom stimulus, it realizes parallel scanning of multiple specified modules, thereby improving the flexibility and efficiency of DFT verification. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of a DFT simulation control file provided in an embodiment of the present invention;

[0057] Figure 2 This is a schematic diagram of a simulation architecture provided for an embodiment of the present invention.

[0058] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0059] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0060] Before introducing this invention, the terms will be explained below.

[0061] FPGA chip: Field-Programmable Gate Array, is a semi-custom integrated circuit whose hardware functions can be defined by software configuration. Its core feature is that it is field-programmable. After leaving the factory, FPGA chips can be modified multiple times by users according to their needs to realize various customized functions, from simple logic control to complex signal processing.

[0062] Bitstream: A bitstream file is a binary format configuration file used to define the connection methods and logic functions of internal hardware resources in an FPGA. It is the core carrier for realizing the field-programmable characteristics of programmable chips.

[0063] EDA tools: Electronic Design Automation refers to a collection of software tools used to assist in the entire process from chip design, simulation, verification, and manufacturing. They can automate the complex wiring process inside the chip and display it through a visual interface.

[0064] A netlist file is a text file used in electronic design to describe circuit components (such as resistors, capacitors, transistors, logic gates, modules, etc.) and their interconnections. It serves as a core bridge connecting "abstract logic design" and "physical implementation / simulation verification," and is essentially a "structured description" of the circuit structure.

[0065] Base testing (ATE): Automatic Test Equipment, is a testing solution that uses automated hardware and software systems to perform batch and efficient testing on electronic components, chips, circuit boards, or complete products. Its core objective is to quickly identify "qualified / unqualified" products during the production, R&D, or maintenance stages, and to screen out devices with functional defects, substandard performance, or reliability issues, while reducing the cost and error of manual testing.

[0066] IO resources: Chip IO resources are short for "input / output resources", which are the general term for the hardware module resources that enable the chip to interact with external circuits and devices for signals and data.

[0067] Inserted chain netlist: The product after inserting the DFT scan chain into the chip's regular netlist file, adding scan logic to the netlist.

[0068] In one embodiment of the present invention, the multi-module parallel DFT verification method for programmable chips includes four stages: determining the specified module, generating a custom bit stream, generating a custom stimulus file, and DFT simulation verification.

[0069] Phase 1: Identify the specified module, including step S1:

[0070] S1 determines the I / O ports of the programmable chip and multiple designated modules to be scanned.

[0071] Specifically, step S1 may include S1.1-S1.2:

[0072] S1.1 Determine the available I / O ports in the programmable chip based on pin limitations.

[0073] S1.2 Determine the specified module to be scanned, wherein the number of scan signal interfaces of the specified module to be scanned does not exceed the number of IO ports.

[0074] It should be noted that actual requirements may include limitations such as the pin limitations of the test base and the pin limitations of the chip package. The amount of I / O resources of the programmable chip that can be used in this DFT verification process will be determined based on these pin limitations.

[0075] Phase 2, generating a custom bitstream, includes step S2:

[0076] S2 routes the IO port to the scan signal interface of the designated module to generate a plug-in netlist, and generates a custom bit stream based on the plug-in netlist.

[0077] Specifically, step S2 may include S2.1-S2.4:

[0078] S2.1 Determine the location information of the designated module in the programmable chip;

[0079] S2.2 Based on the location information, complete the wiring from the IO port to the idle interface of the designated module, and generate a wiring netlist;

[0080] S2.3 Modify the idle interface in the wiring netlist to the scan signal interface reserved by the designated module and insert the preset scan logic to obtain the plug-in netlist;

[0081] S2.4 Generate a custom bitstream based on the pluggable netlist.

[0082] It should be noted that the actual location of a specified module within a programmable chip can be determined using EDA tools. Since the scan signal interfaces of modules within a programmable chip are usually reserved interfaces and not normally visible, EDA tools typically cannot directly route from I / O ports to the scan interfaces. Therefore, EDA tools can be used to route each I / O port to an unused interface of the specified module based on its location. Ideally, the routing lengths from the I / O ports to each module should be approximately the same during this process, generating a routing netlist. Then, the routing netlist is modified, changing the routing interface on the specified module from an unused interface to a reserved scan signal interface and inserting preset scan logic, resulting in a linking netlist. Scan signals typically include Scanin, Scanen, Scanmode, Scanclk, and Scanout. A custom bitstream is generated by inputting the linking netlist into a script.

[0083] Phase 3: Generate a customized incentive file, including steps S3.1-S3.2:

[0084] S3.1 Modify the scanning signal interface of each specified module to a unified scanning signal interface and instantiate the specified module to generate a DFT simulation control file;

[0085] S3.2 Input the DFT simulation control file and the pluggable netlist into a preset DFT stimulus generation tool to generate stimulus data file and test protocol file.

[0086] Optionally, the following may be included before step S3.1:

[0087] Determine the value of the non-scanning signal interface of the specified module in scan mode, and generate fixed value constraints. The fixed value constraints are used to store the subsequently generated DFT simulation control file.

[0088] The cancellation circuit components are set to cancel the reserved circuit components at the scan signal interface of the specified module. The cancellation circuit components are used to store the subsequently generated DFT simulation control file.

[0089] It should be noted that determining the values ​​of the non-scanning pins of a specified module in scan mode, setting fixed value constraints for the module based on these values, preventing changes in such pin signals from affecting scan coverage, determining whether the designer has reserved circuit components such as inverters at the scan signal interface of the specified module, and setting custom circuit components to offset the influence of reserved circuit components on the scan signal.

[0090] Furthermore, the preset DFT stimulus generation tool determines the stimulus information for the specified module based on the instantiated specified module, the fixed value constraint, and the cancellation circuit components, and generates a stimulus data file; the preset DFT stimulus generation tool sets the stimulus output interface and the result detection interface, and generates a test protocol file.

[0091] like Figure 1 As shown, Figure 1 This is a schematic diagram of a DFT simulation control file provided by the present invention. The DFT simulation control file merges the scan signal interfaces of all specified modules into a unified scan signal interface, instantiates all specified modules within the DFT simulation control file, and places the fixed value constraints and set cancellation circuit components within the DFT simulation control file.

[0092] Phase 4, DFT simulation verification, includes steps S4.1-S4.4:

[0093] S4.1 Generate the top layer of the programmable chip based on the interleaving netlist;

[0094] S4.2 Instantiate the test protocol file to generate the top-level test protocol;

[0095] S4.3 Interconnect the top layer of the programmable chip and the top layer of the test protocol;

[0096] S4.4 Perform parallel DFT simulations of multiple specified modules on the top layer of the programmable chip and the top layer of the test protocol based on the customized bit stream and the stimulus data file, and obtain the DFT verification results of the specified modules.

[0097] Furthermore, the scan signal interface includes a scan input interface and a scan output interface; the test protocol top layer includes an excitation output interface and a result detection interface. The excitation output interface of the test protocol top layer is interconnected with the programmable chip top layer, and the result detection interface of the test protocol top layer is interconnected with the programmable chip top layer.

[0098] To more clearly illustrate the simulation architecture of this invention, accompanying drawings are provided, such as... Figure 2 As shown, Figure 2 This invention provides a schematic diagram of a simulation architecture. The simulation top layer includes a programmable chip top layer and a test protocol top layer. Step S4.4 specifically includes S4.4.1-S4.4.5:

[0099] S4.4.1 Input the customized bit stream into the top layer of the programmable chip, configure the scan path of the programmable chip and generate a scan signal;

[0100] S4.4.2 The scanning signal controls the top layer of the test protocol to generate an excitation data signal based on the excitation data file;

[0101] The excitation data signal in S4.4.3 is input to the top layer of the programmable chip through the excitation output interface of the top layer of the test protocol, and then input to the scan input interface of multiple designated modules through the plug-in netlist of the top layer of the programmable chip to obtain the scan result by performing parallel scan on multiple designated modules;

[0102] The scanning result described in S4.4.4 is output to the result detection interface at the top layer of the test protocol via the scanning output interface through the programmable chip.

[0103] The top-level test protocol described in S4.4.5 performs detection based on the scan results to obtain DFT verification results for multiple specified modules.

[0104] It should be noted that during simulation, the custom bit stream is input to the top layer of the programmable chip to complete the internal scan path configuration of the programmable chip. Then, the scan signal controls the designated module to perform the scan mode and sends the test stimulus. The scan result is automatically detected by the internal detection mechanism of the test protocol top layer.

[0105] The excitation data signal output from the top layer of the test protocol is directly input to the scan input interface corresponding to the specified module in the plug-in netlist through the top layer of the programmable chip. After the scan of the specified module is completed, the scan result is output through the scan output interface to the structure detection interface of the top layer of the test protocol for detection.

[0106] This invention routes the I / O ports of a programmable chip to the scan signal interface of a specified module to generate a custom bit stream. It creates a DFT simulation management file to merge the scan signal interfaces of all specified modules into a unified scan signal interface. Based on the DFT simulation management file, it generates a stimulus data file and a test protocol file. Combined with the custom bit stream, it generates a custom stimulus. Based on the custom stimulus, it realizes parallel scanning of multiple specified modules, thereby improving the flexibility and efficiency of DFT verification.

[0107] In another embodiment of the present invention, a programmable chip multi-module parallel DFT verification system is also provided, the system comprising:

[0108] The information confirmation module is used to determine the I / O ports of the programmable chip and the specified modules to be scanned.

[0109] The bit stream generation module is used to generate a plug-in netlist by routing the IO port to the scan signal interface of the designated module, and generate a customized bit stream based on the plug-in netlist;

[0110] A customized stimulus file generation module is used to modify the scan signal interface of each specified module to a unified scan signal interface and instantiate the specified module to generate a DFT simulation control file; the DFT simulation control file and the pluggable netlist are input into a preset DFT stimulus generation tool to generate a stimulus data file and a test protocol file;

[0111] The simulation verification module is used to generate a programmable chip top layer based on the interleaving netlist; instantiate the test protocol file to generate a test protocol top layer; interconnect the programmable chip top layer and the test protocol top layer; and perform parallel DFT simulations of multiple specified modules on the programmable chip top layer and the test protocol top layer based on the custom bit stream and the stimulus data file to obtain the DFT verification results of the specified modules.

[0112] Optionally, the top layer of the test protocol includes an excitation output interface and a result detection interface;

[0113] The simulation verification module is specifically used for:

[0114] The excitation output interface of the top layer of the test protocol is interconnected with the top layer of the programmable chip, and the result detection interface of the top layer of the test protocol is interconnected with the top layer of the programmable chip.

[0115] Optionally, the scan signal interface includes a scan input interface and a scan output interface;

[0116] The simulation verification module is specifically used for:

[0117] The customized bitstream is input into the top layer of the programmable chip to configure the scan path and generate a scan signal.

[0118] The scanning signal controls the top layer of the test protocol to generate a stimulus data signal based on the stimulus data file.

[0119] The excitation data signal is input to the top layer of the programmable chip through the excitation output interface of the top layer of the test protocol, and then input to the scan input interface of multiple designated modules through the plug-in netlist of the top layer of the programmable chip to obtain the scan result by performing parallel scan on multiple designated modules;

[0120] The scan result is output through the scan output interface to the result detection interface at the top layer of the test protocol via the top layer of the programmable chip;

[0121] The top layer of the test protocol performs detection based on the scan results to obtain DFT verification results for multiple specified modules.

[0122] In the programmable chip multi-module parallel DFT verification system described in this embodiment of the invention, each module adopts the same technical means as the programmable chip multi-module parallel DFT verification method and can produce the same technical effect, which will not be repeated here.

[0123] In the embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and actual implementations may have other classification methods.

[0124] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0125] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0126] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for parallel DFT verification of a programmable chip using multiple modules, characterized in that, The methods include: Identify the I / O ports of the programmable chip and multiple designated modules to be scanned; The process of routing the I / O ports to the scan signal interface of the designated module to generate a plug-in netlist, and generating a custom bitstream based on the plug-in netlist, includes: determining the location information of the designated module in the programmable chip; completing the routing from the I / O ports to the idle interfaces of the designated module based on the location information, generating a routing netlist; modifying the idle interfaces in the routing netlist to the scan signal interfaces reserved by the designated module and inserting preset scan logic to obtain the plug-in netlist; and generating a custom bitstream based on the plug-in netlist. Modify the scan signal interface of each specified module to a unified scan signal interface and instantiate the specified module to generate a DFT simulation control file; Input the DFT simulation control file and the pluggable netlist into a preset DFT stimulus generation tool to generate stimulus data files and test protocol files; Generate the top layer of the programmable chip based on the interleaved netlist; Instantiate the test protocol file to generate the top-level test protocol; Interconnect the top layer of the programmable chip and the top layer of the test protocol; Based on the customized bitstream and the stimulus data file, perform parallel DFT simulations of multiple specified modules on the top layer of the programmable chip and the top layer of the test protocol to obtain the DFT verification results of the specified modules.

2. The programmable chip multi-module parallel DFT verification method as described in claim 1, characterized in that, The process of determining the I / O ports of the programmable chip and multiple designated modules to be scanned includes: The available I / O ports in the programmable chip are determined based on pin constraints; The specified module to be scanned is determined, and the number of scan signal interfaces of the specified module to be scanned does not exceed the number of I / O ports.

3. The programmable chip multi-module parallel DFT verification method as described in claim 1, characterized in that, The step of modifying the scan signal interface of each specified module to a unified scan signal interface and instantiating the specified module to generate a DFT simulation control file also includes: Determine the value of the non-scanning signal interface of the specified module in scan mode, and generate fixed value constraints. The fixed value constraints are used to store the subsequently generated DFT simulation control file. The cancellation circuit components are set to cancel the reserved circuit components at the scan signal interface of the specified module. The cancellation circuit components are used to store the subsequently generated DFT simulation control file.

4. The programmable chip multi-module parallel DFT verification method as described in claim 3, characterized in that, The step of inputting the DFT simulation control file and the pluggable netlist into a preset DFT stimulus generation tool to generate stimulus data files and test protocol files includes: The preset DFT excitation generation tool determines the excitation information for the specified module based on the instantiated specified module, the fixed value constraint, and the cancellation circuit components, and generates an excitation data file; The test protocol file is generated by setting the stimulus output interface and result detection interface using the preset DFT stimulus generation tool.

5. The multi-module parallel DFT verification method for programmable chips as described in claim 1, characterized in that, The top-level test protocol includes an incentive output interface and a result detection interface; The interconnection of the programmable chip top layer and the test protocol top layer includes: The excitation output interface of the top layer of the test protocol is interconnected with the top layer of the programmable chip, and the result detection interface of the top layer of the test protocol is interconnected with the top layer of the programmable chip.

6. The programmable chip multi-module parallel DFT verification method as described in claim 4, characterized in that, The scan signal interface includes a scan input interface and a scan output interface; The step of performing parallel DFT simulations of multiple specified modules on the top layer of the programmable chip and the top layer of the test protocol based on the customized bitstream and the stimulus data file, and obtaining the DFT verification results of the specified modules, includes: The customized bitstream is input into the top layer of the programmable chip to configure the scan path and generate a scan signal. The scanning signal controls the top layer of the test protocol to generate a stimulus data signal based on the stimulus data file. The excitation data signal is input to the top layer of the programmable chip through the excitation output interface of the top layer of the test protocol, and then input to the scan input interface of multiple designated modules through the plug-in netlist of the top layer of the programmable chip to obtain the scan result by performing parallel scan on multiple designated modules; The scan result is output through the scan output interface to the result detection interface at the top layer of the test protocol via the top layer of the programmable chip; The top layer of the test protocol performs detection based on the scan results to obtain DFT verification results for multiple specified modules.

7. A programmable chip multi-module parallel DFT verification system, characterized in that, The system includes: The information confirmation module is used to determine the I / O ports of the programmable chip and the specified modules to be scanned. The bitstream generation module is used to generate a linking netlist by routing the I / O ports to the scan signal interface of the designated module, and generate a customized bitstream based on the linking netlist. This includes: determining the location information of the designated module in the programmable chip; completing the routing from the I / O ports to the idle interfaces of the designated module based on the location information, generating a routing netlist; modifying the idle interfaces in the routing netlist to the scan signal interfaces reserved by the designated module and inserting preset scan logic to obtain the linking netlist; and generating a customized bitstream based on the linking netlist. A customized stimulus file generation module is used to modify the scan signal interface of each specified module to a unified scan signal interface and instantiate the specified module to generate a DFT simulation control file; the DFT simulation control file and the pluggable netlist are input into a preset DFT stimulus generation tool to generate a stimulus data file and a test protocol file; The simulation verification module is used to generate a programmable chip top layer based on the interleaving netlist; instantiate the test protocol file to generate a test protocol top layer; interconnect the programmable chip top layer and the test protocol top layer; and perform parallel DFT simulations of multiple specified modules on the programmable chip top layer and the test protocol top layer based on the custom bit stream and the stimulus data file to obtain the DFT verification results of the specified modules.

8. The programmable chip multi-module parallel DFT verification system as described in claim 7, characterized in that, The top-level test protocol includes an incentive output interface and a result detection interface; The simulation verification module is specifically used for: The excitation output interface of the top layer of the test protocol is interconnected with the top layer of the programmable chip, and the result detection interface of the top layer of the test protocol is interconnected with the top layer of the programmable chip.

9. The programmable chip multi-module parallel DFT verification system as described in claim 7, characterized in that, The scan signal interface includes a scan input interface and a scan output interface; The simulation verification module is specifically used for: The customized bitstream is input into the top layer of the programmable chip to configure the scan path and generate a scan signal. The scanning signal controls the top layer of the test protocol to generate a stimulus data signal based on the stimulus data file. The excitation data signal is input to the top layer of the programmable chip through the excitation output interface of the top layer of the test protocol, and then input to the scan input interface of multiple designated modules through the plug-in netlist of the top layer of the programmable chip to obtain the scan result by performing parallel scan on multiple designated modules; The scan result is output through the scan output interface to the result detection interface at the top layer of the test protocol via the top layer of the programmable chip; The top layer of the test protocol performs detection based on the scan results to obtain DFT verification results for multiple specified modules.

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