Chip placement methods, devices, equipment, and media based on reinforcement learning networks

Abstract

This application provides a chip placement method, apparatus, device, and medium based on reinforcement learning networks. The method determines placement evaluation data for the current placement scheme. For the current placement scheme, a boundary intersection algorithm is used to solve a comprehensive evaluation model to obtain a compromise solution for the placement evaluation. Based on the difference between the placement evaluation data and reference placement evaluation data, the reinforcement learning network is guided to determine unplaced target cells and their corresponding placement strategies according to the circuit netlist characteristics. Then, the target cells are added to the current placement scheme according to the placement strategies until all cells are placed. Embodiments of this application can achieve a balance between multiple mutually constrained placement evaluation metrics (such as area, latency, and power consumption) during the chip placement process.

Description

Technical Field

[0001] This application relates to the field of chip layout, and more specifically, to a chip layout method, apparatus, device, and storage medium based on reinforcement learning networks. Background Technology

[0002] Chip placement is a crucial step in integrated circuit design. It refers to the process of arranging the various circuit units (such as logic units, memory units, input / output ports, clock circuits, etc.) of a chip in the chip's physical space.

[0003] The goal of chip placement is to optimize performance, power consumption, area, and other design constraints while meeting the chip's functional requirements, in order to achieve the best chip design results. In other words, a chip not only needs to fulfill functional requirements but also needs to achieve a balance in terms of area, performance, power consumption, and manufacturability. This is a key issue in integrated circuit design and manufacturing. Summary of the Invention

[0004] In view of this, this application provides a chip layout method, apparatus, device and storage medium based on reinforcement learning networks, so as to at least solve the problems existing in the related technologies.

[0005] Specifically, this application is implemented through the following technical solution:

[0006] This application provides a chip layout method based on reinforcement learning networks, including:

[0007] Obtain the circuit netlist of the target chip, the circuit netlist including laid-out cells and unlaid-out cells;

[0008] The circuit netlist is subjected to feature extraction to obtain circuit netlist features; the circuit netlist features include the position features of the laid-out cells;

[0009] The current layout scheme is determined based on the positional characteristics of the already laid-out units, and the layout evaluation data of the current layout scheme is determined.

[0010] The boundary intersection algorithm is used to solve the comprehensive evaluation model to obtain the layout evaluation compromise solution; wherein, the comprehensive evaluation model is used to characterize the constraint relationship between the comprehensive evaluation index and each layout evaluation index, and the layout evaluation compromise solution includes the reference layout evaluation data of the current layout scheme;

[0011] Based on the difference between the layout evaluation data and the reference layout evaluation data, the reinforcement learning network is guided to determine the unplaced target cells and their corresponding placement strategies according to the circuit netlist features.

[0012] According to the layout strategy, the target cell is added to the current layout scheme, and the step of determining the layout evaluation data of the current layout scheme is returned until all cells are laid out to obtain the target layout scheme, and the target chip is physically laid out based on the target layout scheme.

[0013] In some implementations, the step of using the boundary intersection algorithm to solve the comprehensive evaluation model to obtain a compromise solution for the layout evaluation includes:

[0014] Obtain the layout constraints and the boundary values ​​corresponding to each of the layout evaluation indicators;

[0015] Based on each of the aforementioned layout evaluation indicators, a target space is constructed; the target space is used to characterize the correlation between the various layout evaluation indicators.

[0016] In the target space, based on the layout constraints and various boundary values, the comprehensive evaluation model is solved to obtain the layout evaluation compromise solution.

[0017] In some implementations, the step of solving the comprehensive evaluation model in the target space based on the layout constraints and various boundary values ​​to obtain the layout evaluation compromise solution includes:

[0018] In the target space, based on the layout constraints and various boundary values, the comprehensive evaluation model is solved to obtain a compromise solution;

[0019] Based on the compromise solution, the layout constraints and the model coefficients of the comprehensive evaluation model are adjusted respectively, and the process of solving the comprehensive evaluation model in the target space is returned until the preset iteration requirements are met, resulting in multiple compromise solutions.

[0020] The layout evaluation compromise solution is determined from the plurality of compromise solutions.

[0021] In some implementations, the layout constraints include at least one of physical constraints, electrical constraints, and design and manufacturing constraints.

[0022] In some implementations, the circuit netlist features are extracted using a feature extraction network, wherein the feature extraction network is obtained by self-supervised training of an initial feature extraction network, which includes a feature extraction module, an encoder, and a decoder; the feature extraction network is trained in the following manner:

[0023] Obtain a circuit netlist sample and an initial layout canvas corresponding to the circuit netlist sample; the initial layout canvas includes the already laid-out sample cells in the circuit netlist sample.

[0024] The circuit netlist sample is input into the feature extraction module to obtain the circuit netlist sample features;

[0025] The initial layout canvas is partially covered to obtain a covered layout canvas;

[0026] The encoder encodes the masking layout canvas to obtain encoded features, and the circuit netlist sample features are fused with the encoded features to obtain fused features.

[0027] The fused features are decoded by the decoder to obtain the restored layout canvas;

[0028] Based on the restored layout canvas and the initial layout canvas, the initial feature extraction network is trained under self-supervised conditions to obtain the feature extraction network.

[0029] In some implementations, the step of performing self-supervised training on the initial feature extraction network based on the restored layout canvas and the initial layout canvas to obtain the feature extraction network includes:

[0030] The first loss is determined based on the pixel difference between the restored layout canvas and the initial layout canvas;

[0031] The restored layout canvas is matched with the cells in the initial layout canvas to obtain multiple cell pairs. The cross-union ratio of each cell pair is determined, and the second loss is determined based on the cross-union ratio of each cell pair.

[0032] Based on the first loss and the second loss, a target loss is determined, and the network parameters of the initial feature extraction network are adjusted based on the target loss until the preset training conditions are met, thus obtaining the feature extraction network.

[0033] In some implementations, the circuit netlist sample features include sample cell features of each sample cell; the feature fusion of the circuit netlist sample features and the coding features to obtain fused features includes:

[0034] Filter the target sample cell features corresponding to the masked sample cells from the circuit netlist sample features;

[0035] The target sample unit features are subjected to dimensionality transformation to obtain target sample unit features with target dimensions; the target dimension is the same as the dimension of the encoded features.

[0036] The target sample unit features with the target dimension are fused with the encoded features to obtain the fused features.

[0037] This application also provides a chip placement apparatus based on a reinforcement learning network, comprising:

[0038] The netlist acquisition module is used to acquire the circuit netlist of the target chip, wherein the circuit netlist includes laid-out cells and unlaid-out cells;

[0039] The feature extraction module is used to extract features from the circuit netlist using a feature extraction network to obtain circuit netlist features; the circuit netlist features include the position features of the placed cells;

[0040] The data determination module is used to determine the current layout scheme based on the positional characteristics of the already laid-out units, and to determine the layout evaluation data of the current layout scheme;

[0041] The model solving module is used to solve the comprehensive evaluation model using the boundary intersection algorithm to obtain the layout evaluation compromise solution; wherein, the comprehensive evaluation model is used to characterize the constraint relationship between the comprehensive evaluation index and each layout evaluation index, and the layout evaluation compromise solution includes the reference layout evaluation data of the current layout scheme;

[0042] The cell determination module is used to guide the reinforcement learning network to determine the unplaced target cells and their corresponding placement strategies based on the differences between the placement evaluation data and the reference placement evaluation data, according to the circuit netlist features.

[0043] The entity placement module is used to add the target unit to the current placement scheme according to the placement strategy, return to the step of executing the placement evaluation data of the current placement scheme, until all units are placed to obtain the target placement scheme, and perform entity placement on the target chip based on the target placement scheme.

[0044] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the chip layout method based on reinforcement learning network described in any of the foregoing embodiments.

[0045] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the chip layout method based on reinforcement learning network described in any of the foregoing embodiments.

[0046] This application also provides a computer program product, including a computer program that, when run by a processor, performs the steps of any of the possible reinforcement learning network-based chip layout methods described above.

[0047] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0048] In this embodiment, for the current layout scheme, the boundary intersection algorithm is used to solve the comprehensive evaluation model to obtain the layout evaluation compromise solution. The layout evaluation compromise solution includes the reference layout evaluation data of the current layout scheme. Thus, the reinforcement learning network can be guided to lay out the target unit based on the difference between the layout evaluation data and the reference layout evaluation data. Since the comprehensive evaluation model represents the constraint relationship between the comprehensive evaluation index and each layout evaluation index, the layout evaluation compromise solution obtained in this way can achieve a balance between multiple layout evaluation indexes (such as area, latency, power consumption, etc.), avoiding the overall performance loss caused by optimizing a single index.

[0049] Secondly, the step-by-step layout method in this application (determining one target unit and updating the layout scheme each time) combined with dynamic evaluation feedback can correct deviations in a timely manner during the layout process, avoiding the cost of large-scale adjustments later.

[0050] Furthermore, the reinforcement learning network obtains reward values ​​by comparing the placement evaluation data with the compromise solution of the placement evaluation, realizing a closed-loop learning mechanism of "evaluation-feedback-optimization". As the placement process progresses, the network can continuously optimize the placement strategy to adapt to different circuit structures (such as differences in complexity and cell type), improving the versatility and intelligence of the placement.

[0051] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0052] Figure 1 This is a flowchart illustrating a chip layout method based on a reinforcement learning network, as shown in an exemplary embodiment of this application.

[0053] Figure 2 This is a flowchart illustrating another chip layout method based on reinforcement learning networks, as shown in an exemplary embodiment of this application;

[0054] Figure 3 This is a flowchart illustrating the training process of a feature extraction network according to an exemplary embodiment of this application;

[0055] Figure 4 This is a flowchart illustrating the training process of a feature extraction network according to an exemplary embodiment of this application;

[0056] Figure 5 This is a schematic diagram of the structure of a chip layout device based on a reinforcement learning network, as illustrated in an exemplary embodiment of this application.

[0057] Figure 6 This is a schematic diagram of another chip layout device based on a reinforcement learning network, as illustrated in an exemplary embodiment of this application.

[0058] Figure 7 This is a hardware structure diagram of an electronic device illustrated in an exemplary embodiment of this application. Detailed Implementation

[0059] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0060] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0061] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0062] Chip placement is a crucial step in integrated circuit design. It refers to the process of arranging the various circuit units (such as logic units, memory units, input / output ports, clock circuits, etc.) of a chip in the chip's physical space.

[0063] The goal of chip placement is to optimize performance, power consumption, area, and other design constraints (such as bus length and process technology) while meeting the chip's functional requirements, in order to achieve the best chip design results. In other words, a chip not only needs to fulfill its functional requirements but also needs to achieve a balance in terms of area, performance, power consumption, and manufacturability. This is a key issue in integrated circuit design and manufacturing.

[0064] Based on the above research, this disclosure provides a chip placement method based on reinforcement learning networks. The method first obtains the circuit netlist of the target chip, which includes placed cells and unplaced cells. Next, feature extraction is performed on the circuit netlist to obtain circuit netlist features, including the positional features of the placed cells. Then, based on the positional features of the placed cells, a current placement scheme is determined, and the placement evaluation data of the current placement scheme is determined. A boundary intersection algorithm is used to solve the comprehensive evaluation model to obtain a compromise solution for the placement evaluation. The comprehensive evaluation model is used to characterize the constraint relationship between the comprehensive evaluation index and each placement evaluation index. The compromise solution for the placement evaluation includes reference placement evaluation data for the current placement scheme. Then, based on the difference between the placement evaluation data and the reference placement evaluation data, the reinforcement learning network is guided to determine the unplaced target cells and their corresponding placement strategies according to the circuit netlist features. Finally, the target cells are added to the current placement scheme according to the placement strategy, and the step of determining the placement evaluation data of the current placement scheme is returned until all cells are placed to obtain the target placement scheme. Finally, the target chip is physically placed based on the target placement scheme.

[0065] In this embodiment, for the current layout scheme, the boundary intersection algorithm is used to solve the comprehensive evaluation model to obtain the layout evaluation compromise solution. The layout evaluation compromise solution includes the reference layout evaluation data of the current layout scheme. Thus, the reinforcement learning network can be guided to place the target unit according to the difference between the layout evaluation data and the reference layout evaluation data. Since the comprehensive evaluation model represents the constraint relationship between the comprehensive evaluation index and each layout evaluation index, the layout evaluation compromise solution obtained in this way can achieve a balance between multiple layout evaluation indexes (such as area, latency, power consumption, etc.) and avoid the overall performance loss caused by optimizing a single index.

[0066] Secondly, the step-by-step layout method in this application (determining one target unit and updating the layout scheme each time) combined with dynamic evaluation feedback can correct deviations in a timely manner during the layout process, avoiding the cost of large-scale adjustments later.

[0067] Furthermore, the reinforcement learning network obtains reward values ​​by comparing the placement evaluation data with the compromise solution of the placement evaluation, realizing a closed-loop learning mechanism of "evaluation-feedback-optimization". As the placement process progresses, the network can continuously optimize the placement strategy to adapt to different circuit structures (such as differences in complexity and cell type), improving the versatility and intelligence of the placement.

[0068] To facilitate understanding of this embodiment, a detailed description of the chip placement method based on reinforcement learning networks disclosed in this disclosure is provided first. The execution entity of the chip placement method based on reinforcement learning networks provided in this disclosure is generally an electronic device. This electronic device can be a server, which can be an independent physical server, a server cluster composed of multiple physical servers, or a distributed system. It can also be a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud storage, big data, and artificial intelligence platforms. In other embodiments, the electronic device can also be a terminal device, which can be a mobile device, terminal, handheld device, computing device, etc.

[0069] In other embodiments, the method can also be applied to an implementation environment consisting of electronic devices and servers. Furthermore, this reinforcement learning network-based chip placement method can also be implemented by the processor calling computer-readable instructions stored in memory.

[0070] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0071] Please participate in the attached... Figure 1 The above is a flowchart illustrating a chip layout method based on a reinforcement learning network, as shown in an exemplary embodiment of this application. Figure 1 As shown, the chip layout method based on reinforcement learning networks in this embodiment may include the following steps S101~S106:

[0072] S101: Obtain the circuit netlist of the target chip, the circuit netlist including laid-out cells and unlaid-out cells.

[0073] A circuit netlist is a text file or data structure that describes the various components (or units) in an electronic circuit and their connections. It is a core piece of fundamental data in the chip design process. It is essentially the "blueprint" of the circuit, clearly recording the circuit's constituent units, the attributes of each unit, and the electrical connections between them.

[0074] In chip design, the main contents of a circuit netlist typically include: Component / cell information: such as the model, number, or attribute parameters of transistors, resistors, capacitors, logic gates, macrocells, etc.; Connection relationships: using nodes (Net) to identify the connections between pins of each cell, clarifying the transmission path of signals from one cell to another; Port information: the definition of the circuit's input / output ports, used for interaction with external circuits or systems.

[0075] There are various formats for circuit netlists, such as SPICE (mostly used for analog circuits), Verilog netlists (mostly used for digital circuits), and EDIF. During the chip placement and routing phase, the physical location and connections of each cell are determined, ultimately transforming the logic design into a physical entity layout.

[0076] Among them, a laid-out cell refers to a cell with a fixed placement position in the target chip, such as an input / output interface, while an unlaid-out cell refers to a cell that needs to be laid out.

[0077] In some implementations, a circuit netlist may include multiple subnetlists, each subnetlist including multiple cells. For example, a circuit netlist may be represented as N1: A, B; N2: B, C, D; N3: A, D, where N1, N2, and N3 represent subnetlists, A, B, C, and D represent cells, A and B indicate that there is a connection between cell A and cell B, and B, C, and D indicate that there is a connection between cell B, cell C, and cell D.

[0078] S102: Perform feature extraction on the circuit netlist to obtain circuit netlist features; the circuit netlist features include the position features of the laid-out cells.

[0079] In this embodiment, the circuit netlist features are extracted using a feature extraction network, which may include various graph neural networks, such as graph convolutional neural networks, graph attention networks, and graph perceptron hybrid networks. The feature extraction network is obtained through self-supervised training of an initial feature extraction network; the training process of the feature extraction network is described later.

[0080] By using a feature extraction network, the complex cell information in the circuit netlist can be mapped to a lower dimension to obtain circuit netlist features. These features include cell features, connection relationship features between cells, and position features of the laid-out cells. Cell features can include cell size features, cell pin layout features, and cell electrical features.

[0081] S103: Determine the current layout scheme based on the positional characteristics of the already laid-out units, and determine the layout evaluation data of the current layout scheme.

[0082] Here, since the already laid-out units are units with fixed layout positions, the current layout scheme can be determined based on the positional characteristics of the already laid-out units, that is, the already laid-out units are laid out.

[0083] In this embodiment, after determining the current layout scheme, layout evaluation data for the current layout scheme can be determined based on a preset evaluation algorithm. The layout evaluation metrics include data corresponding to multiple layout evaluation metrics. For example, if the layout evaluation metrics include area, bus length, and power consumption, then the layout evaluation data can include area metrics, bus length metrics, and power consumption metrics.

[0084] The following preset evaluation algorithms for bus length, layout density, and congestion level may include evaluation algorithms for bus length, layout density, and congestion level.

[0085] Regarding bus length evaluation algorithms, it should be understood that bus length directly impacts signal delay and clock frequency. Excessive bus length increases parasitic reactance and capacitance, leading to higher signal delay. Longer bus lengths often introduce greater clock skew in clock networks and reduce the maximum clock frequency. Furthermore, excessive bus length also results in higher circuit power consumption and leakage current, negatively affecting semiconductor device performance. In addition, bus length also impacts signal integrity, fabrication difficulty, fabrication cost, and thermal management. Therefore, bus length is used as a metric in evaluation algorithms.

[0086] There are many methods for calculating bus length, such as the half-period bus length model, the Steiner tree length model, the square bus length model, and the smooth bus length model. Taking the half-period bus length as an example, for any circuit netlist, the line length is the sum of the range of the x-coordinate and the range of the y-coordinate of the components in the netlist. To avoid the bus length being zero, please refer to formula (1) for its expression:

[0087] (1)

[0088] Where x is the x-coordinate of the component and y is the y-coordinate of the component.

[0089] Regarding layout density, it should be understood that layout density directly affects the difficulty of routing, whether chips overlap, and whether chip area is wasted. Therefore, layout density needs to be controlled within an appropriate range. It should not be too high, which would affect routing, nor too low, which would waste chip area.

[0090] Methods for evaluating layout density include grid-based evaluation, diffusion model-based evaluation, and electrostatic model-based evaluation. A common grid-based evaluation method divides the chip into equal-sized grids and calculates the proportion of the component area in the entire chip.

[0091] Regarding congestion levels, it should be understood that congestion level measures whether the capacity of the cabling is sufficient for all netlists in the same area. Congestion level has a significant impact on cabling difficulty, timing violations, and DRC errors. Severe congestion can lead to cabling failures. Congestion levels must be considered in advance during the layout process to avoid later cabling failures. Commonly used models include global routing estimation methods, probabilistic models, and RUDY. Here, we take the global routing estimation method as an example. After the initial layout is completed, a global routing algorithm is executed once, and the congestion level is determined by comparing the cabling cost in the fast routing result with the cabling capacity target.

[0092] S104: The boundary intersection algorithm is used to solve the comprehensive evaluation model to obtain the layout evaluation compromise solution; wherein, the comprehensive evaluation model is used to characterize the constraint relationship between the comprehensive evaluation index and each layout evaluation index, and the layout evaluation compromise solution includes the reference layout evaluation data of the current layout scheme.

[0093] The comprehensive evaluation model is used to characterize the constraint relationship between the comprehensive evaluation index and each layout evaluation index. Each layout evaluation index can include any number of indicators such as power consumption, performance, area, bus length, congestion level, signal integrity, and thermal management.

[0094] Please refer to formula (1), which is the expression for the comprehensive evaluation model:

[0095] (1)

[0096] in, As a comprehensive evaluation indicator, These are the model coefficients corresponding to the layout evaluation indicators. To lay out the evaluation index function, i This indicates the layout evaluation indicators.

[0097] In some implementations, when using the boundary intersection algorithm to solve the comprehensive evaluation model based on the layout evaluation data to obtain a compromise solution for the layout evaluation, the following steps (A) to (C) may be included:

[0098] (A) Obtain the layout constraints and the boundary values ​​corresponding to each of the layout evaluation indicators.

[0099] The layout constraints include at least one of physical constraints, electrical constraints, and design process constraints.

[0100] Physical constraints can refer to constraints on physical space, geometric dimensions, or structural characteristics. For example, physical constraints can include cell spacing constraints, region constraints, and density constraints. For instance, cell spacing constraints can mean that two adjacent cells (such as logic gates) must maintain a minimum distance (such as 2μm) to prevent physical overlap or interference. Region constraints can mean that specific functional units need to be placed in a designated area. For example, the power management module needs to be placed on the edge of the chip near the power pins to facilitate power distribution. Density constraints can mean that the cell layout density in a certain area of ​​the chip cannot exceed a threshold (such as a maximum of 100 cells per square millimeter) to avoid wiring difficulties or heat dissipation problems.

[0101] Electrical constraints refer to constraints on the electrical characteristics of a circuit, ensuring that the layout meets electrical performance requirements such as signal transmission, power consumption, and timing. These constraints can include timing constraints, signal interference constraints, and load constraints. For example, a timing constraint might mean that the delay of a critical path (such as the path from the CPU's adder to the register) must be less than a specified value (e.g., 2ns), requiring layout optimization to shorten the physical distance and reduce transmission delay. A signal interference constraint might mean that the routing areas of high-speed signals (such as clock signals) and sensitive signals (such as analog signals) must maintain a minimum distance (e.g., 5μm) to avoid electromagnetic interference (EMI). A load constraint might mean that the number of load units connected to a certain drive unit (such as a buffer) cannot exceed a maximum limit (e.g., a maximum of 8 units), preventing waveform distortion caused by insufficient signal driving capability.

[0102] Design process constraints refer to the chip manufacturing process level and flow constraints to ensure that the chip layout conforms to the process specifications. These constraints can include minimum linewidth constraints, minimum via size, orientation constraints, and density uniformity constraints. For example, a minimum linewidth constraint can include ensuring that the width of the pin connections or internal metal lines of a cell is not less than the minimum allowed by the process (e.g., the minimum linewidth is 7nm in a 7nm process). A density uniformity constraint can include ensuring that the cell distribution on the chip surface maintains a certain uniformity to avoid overly dense or sparse areas in certain regions.

[0103] In this context, the boundary values ​​corresponding to each layout evaluation metric refer to the reasonable range or threshold set for each layout evaluation metric (such as area, latency, power consumption, etc.) in chip layout design. These boundary values ​​are quantitative standards for judging whether the layout scheme is feasible and meets the design requirements. Boundary values ​​can include "lower limit" (minimum value) and / or "upper limit" (maximum value). Some layout evaluation metrics only require unidirectional constraints (such as area usually only having an upper limit, and latency only having an upper limit).

[0104] (B) Based on each of the layout evaluation indicators, a target space is constructed; the target space is used to characterize the correlation between the various layout evaluation indicators.

[0105] Here, each point in the target space represents a layout scheme, and the coordinate value of each point is composed of the evaluation data of the corresponding layout scheme on various evaluation indicators (such as area 5mm², latency 1.2ns, power consumption 80mW). In this way, the correlation between multiple layout evaluation indicators can be determined.

[0106] As mentioned above, the layout evaluation data includes the indicator data corresponding to multiple layout evaluation indicators. Therefore, the target space can be constructed based on the indicator data corresponding to multiple layout evaluation indicators.

[0107] Optionally, it can be determined based on the indicator data corresponding to multiple layout evaluation indicators.

[0108] (C) In the target space, based on the layout constraints and each boundary value, the comprehensive evaluation model is solved to obtain the layout evaluation compromise solution.

[0109] Here, since the target space represents the correlation between various layout evaluation indicators, and the layout constraints and the boundary values ​​of each layout evaluation indicator limit the solution range, the compromise solution of layout evaluation can be obtained by solving the comprehensive evaluation model under the above conditions.

[0110] Optionally, when solving the comprehensive evaluation model in the target space based on the layout constraints and various boundary values ​​to obtain the layout evaluation compromise solution, it can be determined through the following steps (1) to (3):

[0111] (1) In the target space, based on the layout constraints and each boundary value, the comprehensive evaluation model is solved to obtain a compromise solution.

[0112] (2) Based on the compromise solution, adjust the layout constraints and the model coefficients of the comprehensive evaluation model, and return to the step of solving the comprehensive evaluation model in the target space until the preset iteration requirements are met, and obtain multiple compromise solutions.

[0113] (3) Determine the layout evaluation compromise solution from the plurality of compromise solutions.

[0114] It is understandable that, theoretically, only one compromise solution can be obtained when solving the comprehensive evaluation model. However, since the layout constraints and model coefficients of the comprehensive evaluation model in this application are all manually set values, the layout constraints and model coefficients of the comprehensive evaluation model can be adjusted according to the compromise solution. Specifically, as mentioned above, the layout constraints include at least one of physical constraints, electrical constraints, and design process constraints. Therefore, the adjustment of multiple layout constraints can refer to the adjustment of at least one of the above three constraints. In addition, according to formula (1), each layout evaluation index corresponds to a model coefficient. Therefore, the model coefficients of each layout evaluation index can be adjusted respectively. In this way, the steps of solving the comprehensive evaluation model in the target space based on the layout constraints and each boundary value can be returned to obtain the compromise solution. The iteration is completed until the preset iteration requirements are met, and multiple compromise solutions are obtained.

[0115] Among them, achieving the preset iteration requirements may include reaching a preset number of iterations or the compromise solution meeting the preset requirements.

[0116] Optionally, after obtaining multiple compromise solutions, the indicator data of each layout evaluation index in each compromise solution can be evaluated separately. For example, for each compromise solution, the corresponding comprehensive evaluation index value can be determined, and the layout evaluation compromise solution can be determined from multiple compromise solutions based on the comprehensive evaluation index value.

[0117] Thus, by iteratively calculating the previous compromise solution, the accuracy of the layout evaluation compromise solution can be improved.

[0118] Optionally, when adjusting the layout constraints and the model coefficients of the comprehensive evaluation model according to the compromise solution, the adjustment can be made based on the differences between the various index data in the reference layout evaluation data included in the compromise solution.

[0119] For example, if the comprehensive evaluation model is a model for two evaluation indicators, delay and bus length, and its model coefficient is 1:2, then a compromise solution with a delay of 1.5 and a bus length of 2.4 is obtained. At this point, the delay can be considered to be small, and the weight of the delay can be increased to make the delay larger. In this case, the model coefficient can be adjusted to 1:1, and the next iteration can be carried out based on the coefficient of 1:1.

[0120] S105: Based on the difference between the layout evaluation data and the reference layout evaluation data, guide the reinforcement learning network to determine the unplaced target cells and their corresponding layout strategies according to the circuit netlist features.

[0121] Here, after obtaining the compromise solution for the layout evaluation of the current layout scheme, the reinforcement learning network can be guided to determine the unplaced target cells and their corresponding layout strategies based on the differences between the layout evaluation data and the reference layout evaluation data, according to the characteristics of the circuit netlist.

[0122] Specifically, the reward value of the reinforcement learning network can be determined based on the difference between the layout evaluation data and the reference layout evaluation data, and the reward value can guide the reinforcement learning network to determine the target unit machine layout strategy.

[0123] Here, it can be understood that the difference between the layout evaluation data and the reference layout evaluation data can be used to characterize the merits of the current layout scheme. In this way, the reward value is determined, and combined with the circuit netlist features (used to provide a reference for the global layout), the reinforcement learning network can be guided to determine the unlaid target cells and the corresponding layout strategies. Here, the layout strategies can include the placement position and orientation of the target cells.

[0124] S106: Add the target cell to the current layout scheme according to the layout strategy, return to the step of determining the layout evaluation data of the current layout scheme, until all cells are laid out to obtain the target layout scheme, and perform physical layout of the target chip based on the target layout scheme.

[0125] It is understandable that once a reinforcement learning network determines the target unit and its corresponding layout strategy, it can add the target unit to the current layout scheme according to the layout strategy to generate a new current layout scheme.

[0126] Furthermore, after the current layout scheme is updated, the process can return to the step of determining the layout evaluation data of the current layout scheme. In this way, a target cell and its corresponding layout strategy can be determined in each iteration. The target cell is added to the current layout scheme each time until all cells are placed, and the target layout scheme is obtained.

[0127] Finally, after determining the target layout scheme, the target chip can be physically laid out according to the target layout scheme. That is, each physical unit is laid out according to the target layout scheme to obtain the target chip. Here, the target chip is the physical chip. In this way, a balanced design of the target chip in various evaluation indicators can be achieved, which is conducive to improving the chip performance.

[0128] Optionally, the target chip type may include, but is not limited to, digital chips, analog chips, mixed-signal chips, etc.

[0129] The following is combined with Figure 2 The complete process of the chip layout generation method described above will be explained.

[0130] Figure 2A flowchart illustrating another chip layout generation method provided for an exemplary embodiment of this application. (See flowchart for example.) Figure 2 As shown, the method includes steps S201 to S212:

[0131] S201: Obtain the circuit netlist of the target chip, and extract features from the circuit netlist to obtain circuit netlist features. The circuit netlist features include the cell features of each cell, the connection relationship features between each cell, and the position features of the laid-out cells.

[0132] S202: Determine the current layout scheme based on the location characteristics of the already laid-out units.

[0133] S203: Determine whether all units have been laid out. If yes, proceed to step S212; otherwise, proceed to step S204.

[0134] S204: Determine the layout evaluation data for the current layout scheme;

[0135] S205: Obtain the layout constraints and the boundary values ​​corresponding to each layout evaluation index, and construct the target space.

[0136] S206: In the target space, based on the layout constraints and various boundary values, the comprehensive evaluation model is solved to obtain a compromise solution.

[0137] S207: Determine whether the preset iteration requirements have been met. If yes, proceed to step S209; otherwise, proceed to step S208.

[0138] S208: Adjust the model coefficients of the layout constraints and the comprehensive evaluation model according to the compromise solution, and return to the execution step S206.

[0139] S209: Obtain multiple compromise solutions and determine the layout evaluation compromise solution from among the multiple compromise solutions. The layout evaluation compromise solution includes reference layout evaluation data for the current layout scheme.

[0140] S210: Based on the difference between the layout evaluation data and the reference layout evaluation data, determine the reward value of the reinforcement learning network, and guide the reinforcement learning network to determine the unplaced target cells and their corresponding placement strategies based on the circuit netlist characteristics.

[0141] S211: Add the target cell to the current layout scheme according to the layout strategy, and execute step S203.

[0142] S212: Obtain the target layout scheme and perform physical layout of the target chip based on the target layout scheme.

[0143] The following is combined with Figure 3 and Figure 4The training process of the feature extraction network in this application is described in detail. Figure 3 A flowchart illustrating the training process of a feature extraction network provided in an exemplary embodiment of this application. Figure 4 A flowchart illustrating the training process of a feature extraction network provided for an exemplary embodiment of this application.

[0144] In this embodiment, the feature extraction network is obtained by self-supervised training of an initial feature extraction network. The initial feature extraction network includes a feature extraction module, an encoder, and a decoder. The feature extraction module can use a preset neural network to implement the feature extraction function. The preset neural network can be a graph convolutional neural network, a graph attention network, or a graph perceptron hybrid network, etc., which is not limited here.

[0145] like Figure 3 As shown, the training process of the feature extraction network includes S301~S306:

[0146] S301: Obtain a circuit netlist sample and an initial layout canvas corresponding to the circuit netlist sample; the initial layout canvas includes at least some sample cells from the circuit netlist sample.

[0147] The circuit netlist sample here can include multiple sample cells and the connection relationships between the sample cells.

[0148] The initial layout canvas can refer to an image based on the layout of at least some of the sample cells among a plurality of sample cells. For example, a circuit netlist sample may include 100 cells, while the initial layout canvas may include 50 cells.

[0149] Optionally, when generating the initial layout canvas, an empty canvas can be constructed first, and each sample cell and its connection relationship can be drawn in the empty canvas according to the size and position of each sample cell indicated in the circuit netlist sample, so as to obtain the initial layout canvas.

[0150] S302: Input the circuit netlist sample into the feature extraction module to obtain the circuit netlist sample features.

[0151] The feature extraction module can be a graph convolutional neural network, a graph attention network, or a graph perceptron hybrid network, etc., and there are no restrictions here.

[0152] Here, the circuit netlist sample is input into the feature extraction module to obtain the circuit netlist sample features. The circuit netlist sample features contain similar content to the circuit netlist features in the previous embodiments, and will not be described in detail here.

[0153] like Figure 4As shown, the circuit netlist sample 10 can be input into the feature extraction module 20 to obtain the circuit netlist sample feature 30, which includes the unit feature 31 and the connection relationship feature 32 of each unit.

[0154] S303: Partially cover the initial layout canvas to obtain a covered layout canvas.

[0155] Specifically, the initial layout canvas can be divided into multiple grids of the same size. According to the preset grid ratio, the target grid can be selected from the multiple grids for masking to obtain the masked layout canvas.

[0156] It can be understood that the masking in this step is pixel-level masking (i.e., all-zero masking), such as... Figure 4 As shown, 40 is the initial layout canvas and 50 is the masking layout canvas.

[0157] Optionally, if the size of the initial layout canvas is not divisible by the side length of the grid, blank areas are filled at the edges. Alternatively, if the size of the initial layout canvas is larger than a first preset size or smaller than a second preset size, the initial layout canvas can be scaled up by a certain ratio before grid division to obtain a pre-processed canvas, and then partially covered to obtain a covered layout canvas.

[0158] S304: The encoder encodes the masking layout canvas to obtain encoded features, and the circuit netlist sample features are fused with the encoded features to obtain fused features.

[0159] For further details, please continue to see Figure 4 The masking layout canvas 50 can be input into the encoder to obtain the encoded features corresponding to the masking layout canvas. That is, the masking layout canvas is used as the initial feature extraction network label.

[0160] Simultaneously, the circuit netlist sample features and the encoded features are fused to obtain fused features. In this way, the features extracted by the network and the visual features obtained by encoding can be fused together.

[0161] S305: The fusion feature is decoded by the decoder to obtain the restored layout canvas.

[0162] Furthermore, by decoding the fused features through a decoder, the restored layout canvas 60 can be obtained. Here, the restored layout canvas can be understood as the prediction data.

[0163] S306: Based on the restored layout canvas and the initial layout canvas, the initial feature extraction network is trained under self-supervised conditions to obtain the feature extraction network.

[0164] In this way, after obtaining the restored layout canvas, the initial feature extraction network can be self-supervised and trained based on the restored layout canvas and the initial layout canvas to obtain the feature extraction network.

[0165] Here, self-supervised training of the initial feature extraction network can refer to adjusting the network parameters of the feature extraction module, encoder, and decoder respectively, and obtaining the feature extraction network based on the adjusted feature extraction module, encoder, and decoder.

[0166] Optionally, the feature extraction module with adjusted parameters can also be used as the feature extraction network.

[0167] In some implementations, when performing self-supervised training on the initial feature extraction network based on the restored layout canvas and the initial layout canvas to obtain the feature extraction network, the following steps (I) to (III) may be included:

[0168] (I) Determine the first loss based on the pixel difference between the restored layout canvas and the initial layout canvas.

[0169] Here, the pixel mean square error can be determined based on the pixels of the restored layout canvas and the initial layout canvas, and the pixel mean square error can be used as the first loss.

[0170] (II) Match the cells in the restored layout canvas with the cells in the initial layout canvas to obtain multiple cell pairs, determine the cross-union ratio of each cell pair, and determine the second loss based on the cross-union ratio of each cell pair.

[0171] The Intersection over Union (IoU) quantifies the degree of overlap between the restored layout canvas and the initial layout canvas.

[0172] (III) Based on the first loss and the second loss, determine the target loss, and adjust the network parameters of the initial feature extraction network based on the target loss until the preset training conditions are met, thereby obtaining the feature extraction network.

[0173] After determining the first loss and the second loss, the target loss can be determined based on the first loss and the second loss. Here, the target loss can be obtained by weighted summation of the first loss and the second loss. Then, the network parameters of the initial feature extraction network (such as feature extraction module, encoder, decoder) are adjusted according to the target loss until the preset number of iterations is reached or the target loss meets the preset loss requirements (such as the target loss being less than the preset loss), thus obtaining the feature extraction network.

[0174] Corresponding to the aforementioned embodiments of the chip placement method based on reinforcement learning networks, this application also provides a hardware accelerator, which includes a processor unit, a computing unit, a policy inference unit, a storage unit, and a scheduling unit. The processor unit receives the training results of the neural network model and combines them with the reinforcement learning network to generate a comprehensive evaluation model. The computing unit includes a parallel computing unit, which includes a tensor computation core for parallel cost function calculation and gradient update of multiple compromise solutions. The parallel computing unit also includes a matrix multiplication array and a sparse computation module to support efficient computation of sparse graph convolution and attention mechanisms. The policy inference unit executes forward inference and value functions of the policy network during the reinforcement learning process to generate placement policies. The storage unit stores the intermediate training states of the network, placement schemes, and circuit netlist features extracted by the feature extraction network. The scheduling unit allocates tasks and schedules data flows between the parallel computing unit and the storage unit during the placement optimization iteration process.

[0175] In some implementations, the storage unit includes an on-chip high-bandwidth memory for storing the netlist structure and layout state information of the compromise solution. The processor unit can programmably configure weights to support weighted optimization among line length, congestion, latency, and power consumption.

[0176] The aforementioned hardware accelerators can be deployed independently or in conjunction with CPUs, GPUs, and FPGAs, providing a scalable platform.

[0177] Corresponding to the aforementioned embodiments of the chip placement method based on reinforcement learning networks, this application also provides embodiments of a chip placement apparatus based on reinforcement learning networks.

[0178] Please refer to Figure 5 This is a schematic diagram illustrating the structure of a chip placement device based on a reinforcement learning network, as shown in an exemplary embodiment of this application. Figure 5 As shown, the chip placement apparatus 500 based on reinforcement learning networks includes:

[0179] The netlist acquisition module 510 is used to acquire the circuit netlist of the target chip, wherein the circuit netlist includes laid-out cells and unlaid-out cells;

[0180] Feature extraction module 520 is used to extract features from the circuit netlist to obtain circuit netlist features; the circuit netlist features include the position features of the laid-out cells;

[0181] The data determination module 530 is used to determine the current layout scheme based on the positional characteristics of the already laid-out units, and to determine the layout evaluation data of the current layout scheme;

[0182] The model solving module 540 is used to solve the comprehensive evaluation model using the boundary intersection algorithm to obtain the layout evaluation compromise solution; wherein, the comprehensive evaluation model is used to characterize the constraint relationship between the comprehensive evaluation index and each layout evaluation index, and the layout evaluation compromise solution includes the reference layout evaluation data of the current layout scheme;

[0183] The cell determination module 550 is used to guide the reinforcement learning network to determine the unplaced target cells and their corresponding placement strategies based on the circuit netlist features, according to the difference between the placement evaluation data and the reference placement evaluation data.

[0184] The entity placement module 560 is used to add the target unit to the current placement scheme according to the placement strategy, return to the step of executing the placement evaluation data of the current placement scheme, until all units are placed to obtain the target placement scheme, and perform entity placement on the target chip based on the target placement scheme.

[0185] In some implementations, the model solving module 540 is specifically used for:

[0186] Obtain the layout constraints and the boundary values ​​corresponding to each of the layout evaluation indicators;

[0187] Based on each of the aforementioned layout evaluation indicators, a target space is constructed; the target space is used to characterize the correlation between the various layout evaluation indicators.

[0188] In the target space, based on the layout constraints and various boundary values, the comprehensive evaluation model is solved to obtain the layout evaluation compromise solution.

[0189] In some implementations, the model solving module 540 is specifically used for:

[0190] In the target space, based on the layout constraints and various boundary values, the comprehensive evaluation model is solved to obtain a compromise solution;

[0191] Based on the compromise solution, the layout constraints and the model coefficients of the comprehensive evaluation model are adjusted respectively, and the process of solving the comprehensive evaluation model in the target space is returned until the preset iteration requirements are met, resulting in multiple compromise solutions.

[0192] The layout evaluation compromise solution is determined from the plurality of compromise solutions.

[0193] In some implementations, the layout constraints include at least one of physical constraints, electrical constraints, and design and manufacturing constraints.

[0194] Please see Figure 6This is a schematic diagram of another chip placement apparatus based on a reinforcement learning network, provided as an exemplary embodiment of this application. Figure 6 As shown, the chip placement device 500 based on reinforcement learning networks further includes a network training module 570. The circuit netlist features are obtained by extracting the circuit netlist features through a feature extraction network. The feature extraction network is obtained by self-supervised training of an initial feature extraction network, which includes a feature extraction module, an encoder, and a decoder. The network training module 570 is used for:

[0195] Obtain a circuit netlist sample and an initial layout canvas corresponding to the circuit netlist sample; the initial layout canvas includes the already laid-out sample cells in the circuit netlist sample.

[0196] The circuit netlist sample is input into the feature extraction module to obtain the circuit netlist sample features;

[0197] The initial layout canvas is partially covered to obtain a covered layout canvas;

[0198] The encoder encodes the masking layout canvas to obtain encoded features, and the circuit netlist sample features are fused with the encoded features to obtain fused features.

[0199] The fused features are decoded by the decoder to obtain the restored layout canvas;

[0200] Based on the restored layout canvas and the initial layout canvas, the initial feature extraction network is trained under self-supervised conditions to obtain the feature extraction network.

[0201] In some implementations, the network training module 570 is specifically used for:

[0202] The first loss is determined based on the pixel difference between the restored layout canvas and the initial layout canvas;

[0203] The restored layout canvas is matched with the cells in the initial layout canvas to obtain multiple cell pairs. The cross-union ratio of each cell pair is determined, and the second loss is determined based on the cross-union ratio of each cell pair.

[0204] Based on the first loss and the second loss, a target loss is determined, and the network parameters of the initial feature extraction network are adjusted based on the target loss until the preset training conditions are met, thus obtaining the feature extraction network.

[0205] In some implementations, the circuit netlist sample features include the sample cell features of each sample cell; the network training module 570 is specifically used for:

[0206] Filter the target sample cell features corresponding to the masked sample cells from the circuit netlist sample features;

[0207] The target sample unit features are subjected to dimensionality transformation to obtain target sample unit features with target dimensions; the target dimension is the same as the dimension of the encoded features.

[0208] The target sample unit features with the target dimension are fused with the encoded features to obtain the fused features.

[0209] The specific implementation process of the functions and roles of each unit in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0210] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0211] Corresponding to the chip layout method based on reinforcement learning networks described above, embodiments of this disclosure also provide an electronic device, such as... Figure 7 The diagram shown is a structural schematic of an electronic device provided in an embodiment of this disclosure, including:

[0212] Electronic device 700 includes a processor 710, an internal bus 720, memory 730, a network interface 740, and non-volatile memory 750, and may also include other hardware required for its functions. One or more embodiments of this specification can be implemented in software, for example, the processor 710 reads the corresponding computer program from the non-volatile memory 750 into the memory 730 and then runs it. Of course, besides software implementation, one or more embodiments of this specification do not exclude other implementation methods, such as logic devices or a combination of hardware and software, etc. That is to say, the execution entity of the following processing flow is not limited to individual logic units, but can also be hardware or logic devices.

[0213] The memory 730, also known as internal memory, is used to temporarily store the computational data in the processor 710, as well as the data exchanged with non-volatile memory 750 such as hard disk. The processor 710 exchanges data with the non-volatile memory 750 through the memory 730.

[0214] In this embodiment, memory 730 is specifically used to store application code that executes the solution of this application, and its execution is controlled by processor 710. That is, when the electronic device is running, processor 710 communicates with network interface 740, memory 730 and non-volatile memory 750 through internal bus 720, so that processor 710 executes the application code stored in memory 730 and non-volatile memory 750, thereby executing the chip layout method based on reinforcement learning network described in the above method embodiment.

[0215] Processor 710 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor.

[0216] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 700. In other embodiments of this application, the electronic device 700 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0217] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the chip placement method based on a reinforcement learning network described in the above-described method embodiments. The storage medium can be either volatile or non-volatile computer-readable storage.

[0218] This disclosure also provides a computer program product carrying program code. The program code includes instructions that can be used to execute the steps of the chip layout method based on reinforcement learning network in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0219] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0220] The embodiments of the subject matter and functional operation described in this specification can be implemented in the following ways: digital electronic circuits, tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this specification and their structural equivalents, or combinations thereof. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier for execution by a data processing apparatus or for controlling the operation of a data processing apparatus. Alternatively or additionally, the program instructions may be encoded on artificially generated propagation signals, such as machine-generated electrical, optical, or electromagnetic signals, which are generated to encode information and transmit it to a suitable receiving device for execution by the data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or combinations thereof.

[0221] The processing and logic flow described in this specification can be executed by one or more programmable computers that execute one or more computer programs to perform corresponding functions by operating on input data and generating output. The processing and logic flow can also be executed by dedicated logic circuitry—such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits), and the device can also be implemented as dedicated logic circuitry.

[0222] Suitable computers for executing computer programs include, for example, general-purpose and / or special-purpose microprocessors, or any other type of central processing unit. Typically, the central processing unit receives instructions and data from read-only memory and / or random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices for storing data, such as disks, magneto-optical disks, or optical disks, or the computer will be operatively coupled to such mass storage devices to receive data from or transfer data to them, or both. However, a computer is not required to have such devices. Furthermore, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, to name a few.

[0223] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, such as semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks. Processors and memory may be supplemented by or incorporated into dedicated logic circuitry.

[0224] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of the claims, but rather are primarily intended to describe features of specific embodiments of a particular invention. Certain features described in the various embodiments herein may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented separately in various embodiments or in any suitable sub-combination. Furthermore, while features may function in certain combinations as described above and even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in some cases, and a claimed combination may refer to a sub-combination or a variation thereof.

[0225] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or requiring all illustrated operations to be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0226] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings are not necessarily shown in a specific order or sequence to achieve the desired result. In some implementations, multitasking and parallel processing may be advantageous.

[0227] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A chip placement method based on reinforcement learning networks, characterized in that, include: Obtain the circuit netlist of the target chip; the circuit netlist includes laid-out cells and unlaid-out cells; The circuit netlist is subjected to feature extraction to obtain circuit netlist features; the circuit netlist features include the position features of the laid-out cells; The current layout scheme is determined based on the positional characteristics of the already laid-out units, and the layout evaluation data of the current layout scheme is determined. The boundary intersection algorithm is used to solve the comprehensive evaluation model to obtain the layout evaluation compromise solution; the comprehensive evaluation model is used to characterize the constraint relationship between the comprehensive evaluation index and each layout evaluation index, and the layout evaluation compromise solution includes the reference layout evaluation data of the current layout scheme; Based on the difference between the layout evaluation data and the reference layout evaluation data, the reinforcement learning network is guided to determine the unplaced target cells and their corresponding placement strategies according to the circuit netlist features. According to the layout strategy, the target cell is added to the current layout scheme, and the step of determining the layout evaluation data of the current layout scheme is returned until all cells are laid out to obtain the target layout scheme. Then, the target chip is physically laid out based on the target layout scheme. The step of using the boundary intersection algorithm to solve the comprehensive evaluation model to obtain the layout evaluation compromise solution includes: obtaining the layout constraints and the boundary values ​​corresponding to each of the layout evaluation indicators; constructing a target space based on each of the layout evaluation indicators; the target space is used to characterize the correlation between the various layout evaluation indicators; and solving the comprehensive evaluation model in the target space based on the layout constraints and each boundary value to obtain the layout evaluation compromise solution.

2. The method according to claim 1, characterized in that, In the target space, based on the layout constraints and various boundary values, the comprehensive evaluation model is solved to obtain the layout evaluation compromise solution, including: In the target space, based on the layout constraints and various boundary values, the comprehensive evaluation model is solved to obtain a compromise solution; Based on the compromise solution, the layout constraints and the model coefficients of the comprehensive evaluation model are adjusted respectively, and the process of solving the comprehensive evaluation model in the target space is returned until the preset iteration requirements are met, resulting in multiple compromise solutions. The layout evaluation compromise solution is determined from the plurality of compromise solutions.

3. The method according to claim 2, characterized in that, The layout constraints include at least one of physical constraints, electrical constraints, and design and process constraints.

4. The method according to claim 1, characterized in that, The circuit netlist features are obtained by extracting features from the circuit netlist using a feature extraction network. The feature extraction network is obtained through self-supervised training of an initial feature extraction network, which includes a feature extraction module, an encoder, and a decoder. The feature extraction network is trained in the following manner: Obtain a circuit netlist sample and an initial layout canvas corresponding to the circuit netlist sample; the initial layout canvas includes the already laid-out sample cells in the circuit netlist sample. The circuit netlist sample is input into the feature extraction module to obtain the circuit netlist sample features; The initial layout canvas is partially covered to obtain a covered layout canvas; The encoder encodes the masking layout canvas to obtain encoded features, and the circuit netlist sample features are fused with the encoded features to obtain fused features. The decoder decodes the fused features to obtain the restored layout canvas; Based on the restored layout canvas and the initial layout canvas, the initial feature extraction network is trained under self-supervised conditions to obtain the feature extraction network.

5. The method according to claim 4, characterized in that, The step of performing self-supervised training on the initial feature extraction network based on the restored layout canvas and the initial layout canvas to obtain the feature extraction network includes: The first loss is determined based on the pixel difference between the restored layout canvas and the initial layout canvas; The restored layout canvas is matched with the cells in the initial layout canvas to obtain multiple cell pairs. The cross-union ratio of each cell pair is determined, and the second loss is determined based on the cross-union ratio of each cell pair. Based on the first loss and the second loss, a target loss is determined, and the network parameters of the initial feature extraction network are adjusted based on the target loss until the preset training conditions are met, thus obtaining the feature extraction network.

6. The method according to claim 5, characterized in that, The circuit netlist sample features include the sample unit features of each sample unit; the feature fusion of the circuit netlist sample features and the coding features to obtain fused features includes: Filter the target sample cell features corresponding to the masked sample cells from the circuit netlist sample features; The target sample unit features are subjected to dimensionality transformation to obtain target sample unit features with target dimensions; the target dimension is the same as the dimension of the encoded features. The target sample unit features with the target dimension are fused with the encoded features to obtain the fused features.

7. A chip placement device based on a reinforcement learning network, characterized in that, include: The netlist acquisition module is used to acquire the circuit netlist of the target chip, wherein the circuit netlist includes laid-out cells and unlaid-out cells; The feature extraction module is used to extract features from the circuit netlist to obtain circuit netlist features; the circuit netlist features include the position features of the placed cells; The data determination module is used to determine the current layout scheme based on the positional characteristics of the already laid-out units, and to determine the layout evaluation data of the current layout scheme; The model solving module is used to solve the comprehensive evaluation model using the boundary intersection algorithm to obtain the layout evaluation compromise solution; wherein, the comprehensive evaluation model is used to characterize the constraint relationship between the comprehensive evaluation index and each layout evaluation index, and the layout evaluation compromise solution includes the reference layout evaluation data of the current layout scheme; The cell determination module is used to guide the reinforcement learning network to determine the unplaced target cells and their corresponding placement strategies based on the differences between the placement evaluation data and the reference placement evaluation data, according to the circuit netlist features. The entity placement module is used to add the target unit to the current placement scheme according to the placement strategy, return to the step of executing the placement evaluation data of the current placement scheme, until all units are placed to obtain the target placement scheme, and perform entity placement on the target chip based on the target placement scheme; The model solving module is specifically used to: obtain the layout constraints and the boundary values ​​corresponding to each of the layout evaluation indicators; construct a target space based on each of the layout evaluation indicators; the target space is used to characterize the correlation between the various layout evaluation indicators; and solve the comprehensive evaluation model in the target space based on the layout constraints and each boundary value to obtain the layout evaluation compromise solution.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the chip layout method based on reinforcement learning network as described in any one of claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the chip layout method based on reinforcement learning network as described in any one of claims 1-6.

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