Ultrasonic fingerprint readout circuit and ultrasonic fingerprint chip

Abstract

The present disclosure provides an ultrasonic fingerprint readout circuit and an ultrasonic fingerprint chip, and relates to the technical field of semiconductors. The ultrasonic fingerprint readout circuit comprises: a piezoelectric transducer configured to convert a return wave into a return wave voltage, the piezoelectric transducer comprising a pixel plate; a pixel integration module comprising a first switch assembly and a pixel integration operational amplifier, the first switch assembly being configured to reset the pixel plate by the pixel integration operational amplifier after the piezoelectric transducer sends an ultrasonic wave; a bidirectional integration module comprising a second switch assembly and a gain differential operational amplifier, the gain differential operational amplifier being configured to perform bidirectional integration based on a return wave integration voltage; and a sampling and quantization module configured to perform sampling and quantization processing on positive-phase differential signals and inverted-phase differential signals before and after bidirectional integration, so as to generate a target signal. According to the technical scheme of the present disclosure, the pixel integration operational amplifier can have dual functions of resetting the pixel plate and outputting the return wave integration voltage.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an ultrasonic fingerprint reading circuit and an ultrasonic fingerprint chip. Background Technology

[0002] An ultrasonic fingerprint chip uses a piezoelectric transducer to emit ultrasonic waves, receives the echoes reflected by the ridges of the finger and converts them into electrical signals, and then processes the electrical signals to identify the fingerprint. The ultrasonic fingerprint chip includes multiple readout circuits. The readout circuits require two reference voltages when working, one for resetting the pixel plate and the other for the internal operational amplifier. However, since the two reference voltages are configured separately and both contribute noise, the performance of the ultrasonic fingerprint readout results needs to be optimized.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide an ultrasonic fingerprint reading circuit and an ultrasonic fingerprint chip, which at least to some extent overcome the problem that the performance of ultrasonic fingerprint reading results needs to be optimized in related technologies.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, an ultrasonic fingerprint reading circuit is provided, comprising: a piezoelectric transducer configured to receive the echo of an emitted ultrasonic wave and convert the echo into an echo voltage, the piezoelectric transducer including a pixel plate; and a pixel integration module connected to the piezoelectric transducer, including a first switching assembly and a pixel integration operational amplifier, the first switching assembly being configured to reset the pixel plate after the piezoelectric transducer emits the ultrasonic wave, and to connect an output opposite to the echo voltage after receiving the echo voltage. The system comprises: an echo integration voltage; a bidirectional integration module connected to the pixel integration module, including a second switching component and a gain differential operational amplifier, wherein the gain differential operational amplifier is used to output a positive-phase differential signal and an anti-phase differential signal, and the second switching component is used to configure the gain differential operational amplifier to perform bidirectional integration based on the echo integration voltage; and a sampling and quantization module connected to the bidirectional integration module, used to sample and quantize the positive-phase differential signal and the anti-phase differential signal before and after bidirectional integration to generate a target signal, wherein the target signal is used to generate or simulate an image containing fingerprint features.

[0007] In one embodiment of this disclosure, during a first time period, the piezoelectric transducer emits the ultrasonic wave, the pixel electrode enters a high-voltage isolation state, and the pixel integrating operational amplifier enters a reset state; during a second time period, the pixel electrode is released from the high-voltage isolation, and the pixel integrating operational amplifier remains in the reset state; during a third time period, the pixel integrating operational amplifier configures the pixel electrode to the reset state; and during a fourth time period, the pixel integrating operational amplifier switches to a continuous integration state.

[0008] In one embodiment of this disclosure, the first switch assembly includes: a first switch, one end of which is connected to the pixel electrode plate and the other end of which is grounded; a second switch disposed between the pixel electrode plate and the pixel integration operational amplifier; and a third switch disposed in parallel with the pixel integration operational amplifier. During a first time period, the first switch and the third switch are closed, and the second switch is open. During a second time period, the first switch is switched to open. During a third time period, the second switch is switched to closed. During a fourth time period, the third switch is switched to open.

[0009] In one embodiment of this disclosure, the pixel integrating operational amplifier includes a first operational amplifier and a first integrating capacitor. The first operational amplifier includes a first input terminal, a second input terminal, and a first output terminal. One end of the second switch is connected to one end of the first switch, and the other end of the second switch is connected to the first input terminal. The second input terminal is used to connect to a first reference voltage. One end of the first integrating capacitor is connected to the other end of the second switch, and the other end of the first integrating capacitor is connected to the first output terminal. The third switch is connected in parallel with the first integrating capacitor.

[0010] In one embodiment of this disclosure, during the first time period, the piezoelectric transducer receives a high-voltage pulse signal, the first input terminal is disconnected from the pixel plate, the first output terminal is short-circuited to the first input terminal, the first integrating capacitor is short-circuited, the first operational amplifier enters a reset mode, and the first integrating capacitor enters a discharge-cleared state; during the second time period, the piezoelectric transducer stops receiving the high-voltage pulse signal, and the first input terminal is in a state awaiting calibration; during the third time period, the pixel plate is connected to the first input terminal, and the voltage of the pixel plate is clamped to the first reference voltage to complete the reset; during the fourth time period, the echo voltage is connected to the first input terminal, and the first operational amplifier and the first integrating capacitor convert the echo voltage into the echo integrated voltage connected to the first output terminal based on negative feedback.

[0011] In one embodiment of this disclosure, the fourth time period sequentially includes a first sub-time period, a second sub-time period, a third sub-time period, and a fourth sub-time period. During the first and second time periods, the gain differential operational amplifier enters an initial reset state. During the third and first sub-time periods, the gain differential operational amplifier switches to a calibration reset state. During the second sub-time period, the gain differential operational amplifier switches to a ready state before bidirectional integration. During the third sub-time period, the gain differential operational amplifier switches to a differential amplification operating state. During the fourth sub-time period, the gain differential operational amplifier switches to a signal lock state.

[0012] In one embodiment of this disclosure, the gain differential operational amplifier includes a second operational amplifier, a first gain capacitor, and a second gain capacitor. The second operational amplifier includes a third input terminal, a fourth input terminal, a second output terminal, and a third output terminal. The second output terminal outputs the inverted differential signal, and the third output terminal outputs the non-inverted differential signal. The first gain capacitor is disposed between the third input terminal and the second output terminal, and the second gain capacitor is disposed between the fourth input terminal and the third output terminal.

[0013] In one embodiment of this disclosure, the second switching assembly includes a first group of switches, a second group of switches, and a third group of switches. The first group of switches includes a fourth and a fifth switch, and the second group of switches includes a sixth and a seventh switch. The fourth and sixth switches are disposed between the pixel integration operational amplifier and the third input terminal, and the fifth and seventh switches are disposed between the pixel integration operational amplifier and the fourth input terminal. The third group of switches includes an eighth and a ninth switch. The eighth switch is connected in parallel with the first gain capacitor, and the ninth switch is connected in parallel with the second gain capacitor. During the first time period and the second time period, the first group of switches and the second group of switches are open, and the third group of switches is closed. During the third time period and the first sub-time period, the first group of switches and the second group of switches are switched to closed. During the second sub-time period, the first group of switches, the second group of switches, and the third group of switches are switched to open. During the third sub-time period, the first group of switches and the second group of switches are alternately opened and closed. During the fourth sub-time period, the first group of switches and the second group of switches are switched to open.

[0014] In one embodiment of this disclosure, the fourth switch, the fifth switch, the sixth switch, and the seventh switch have a common terminal. The bidirectional integration module further includes: a second integration capacitor disposed between the pixel integration amplifier and the common terminal; and a third integration capacitor, one end of which is connected to the common terminal, and the other end of which is connected to a digital-to-analog conversion calibration voltage.

[0015] In one embodiment of this disclosure, during the first and second time periods, the second integrating capacitor, the third integrating capacitor, the first gain capacitor, and the second gain capacitor are short-circuited, and the second operational amplifier is short-circuited to enter an initial reset state; during the third and first sub-time periods, the second operational amplifier clamps the second integrating capacitor and the third integrating capacitor to a second reference voltage; during the second sub-time period, the second operational amplifier is unshort-circuited; during the third sub-time period, the second integrating capacitor and the third integrating capacitor perform bidirectional alternating integration, the first gain capacitor adjusts the amplified inverting differential signal output by the second operational amplifier based on negative feedback, and the second gain capacitor adjusts the amplified positive differential signal output by the second operational amplifier based on negative feedback; during the fourth sub-time period, the second integrating capacitor and the third integrating capacitor stop integrating, and the second operational amplifier switches to the signal-locked state.

[0016] In one embodiment of this disclosure, the sampling and quantization module includes: a sampling unit connected to the gain differential operational amplifier, configured to acquire a first positive-phase differential signal and a first negative-phase differential signal at a first time moment, and to acquire a second positive-phase differential signal and a second negative-phase differential signal at a second time moment, to determine a first difference between the second positive-phase differential signal and the second negative-phase differential signal, and a second difference between the first positive-phase differential signal and the first negative-phase differential signal, and to determine a voltage difference based on the first difference and the second difference; and a quantization unit connected to the sampling unit, configured to convert the voltage difference into the target signal, wherein the first time moment is a time moment in the first sub-time period or the second sub-time period, and the second time moment is a time moment in the fourth sub-time period.

[0017] In one embodiment of this disclosure, the sampling unit includes: a capacitor-to-digital converter, including a binary weighted capacitor array, including a first capacitor subarray and a second capacitor subarray, wherein the first capacitor subarray is used to store the first inverted differential signal and multiple components of the second positive differential signal, and the second capacitor subarray is used to store the first positive differential signal and multiple components of the second inverted differential signal to output the voltage difference, wherein the multiple components correspond to the weights of the binary weighted capacitors and are used to match the number of binary bits of the target signal.

[0018] In one embodiment of this disclosure, the quantization unit includes: a comparator, including a first comparison terminal, a second comparison terminal, and a fourth output terminal, wherein the first comparison terminal is connected to the voltage difference, the second comparison terminal is connected to a second reference voltage, and the fourth output terminal outputs a comparison level; and a successive approximation register, used to determine the binary target signal sequentially from the most significant bit to the least significant bit based on the comparison level.

[0019] In one embodiment of this disclosure, the piezoelectric transducer further includes: a piezoelectric electrode plate, and a piezoelectric layer disposed between the piezoelectric electrode plate and the pixel electrode plate.

[0020] According to another aspect of this disclosure, an ultrasonic fingerprint chip is provided, comprising: the ultrasonic fingerprint reading circuit provided in the above embodiments.

[0021] The voltage conversion scheme provided in the embodiments of this disclosure connects the pixel integration module to the piezoelectric transducer. Through the switching control of the first switching component, the pixel integration operational amplifier can directly reuse a single reference voltage to reset the pixel plate. This configures the pixel integration operational amplifier to have the dual functions of resetting the pixel plate and outputting the echo integration voltage. Compared with the dual reference voltage configuration, this reduces noise sources. In addition, the bidirectional integration module performs bidirectional integration based on the echo integration voltage, amplifying the amplitudes of the positive and negative differential signals. The sampling and quantization module samples and quantizes the differential signals before and after bidirectional integration. By calculating the difference between the two samples, the inherent noise of the circuit is further canceled. Since the voltage amplitude obtained based on the sampled positive and negative differential signals is twice that in the unidirectional integration mode, the signal-to-noise ratio and detection sensitivity of the echo voltage signal can be effectively improved. This improves the extraction accuracy of the effective electrical signal of the fingerprint echo and the accuracy of fingerprint feature recognition.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] Figure 1 A circuit diagram of an ultrasonic fingerprint reading circuit in the related art is shown;

[0025] Figure 2 Show Figure 1 A schematic diagram of the working timing of an ultrasonic fingerprint reading circuit;

[0026] Figure 3 A schematic diagram of an ultrasonic fingerprint reading circuit according to an embodiment of the present disclosure is shown.

[0027] Figure 4 The diagram shows a piezoelectric transducer and a pixel integration module in the ultrasonic fingerprint reading circuit of this embodiment.

[0028] Figure 5 The diagram shows a bidirectional integration module and a sampling and quantization circuit in the ultrasonic fingerprint reading circuit of this embodiment.

[0029] Figure 6 This diagram illustrates the timing sequence of an ultrasonic fingerprint reading circuit according to an embodiment of the present disclosure.

[0030] Figure 7 The diagram shows a circuit diagram of a sampling unit and a quantization unit in an embodiment of this disclosure. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0032] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0033] An ultrasonic fingerprint chip is a semiconductor chip that uses a piezoelectric transducer to receive ultrasonic echoes and convert them into electrical signals. These signals are then processed by a readout circuit to identify fingerprint ridge features, achieving high-precision biometric identification. In related technologies, an ultrasonic fingerprint chip typically contains many detection units, each integrating a piezoelectric sensing capacitor. ,like Figure 1The ultrasonic fingerprint reading circuit shown may include a piezoelectric sensing capacitor 102, a pixel circuit 104, a programmable gain amplifier (PGA) 106, and an analog-to-digital converter (ADC) 108. The piezoelectric sensing capacitor 102 includes an upper electrode 1022, a lower electrode (i.e., the top metal electrode of the detection unit) 1024, and a piezoelectric layer 1026 between the upper electrode 1022 and the lower electrode 1024. The top metal electrode of the detection unit is used to receive the ultrasonic echo voltage. When a finger is pressed on the surface of the ultrasonic fingerprint chip, a driving voltage applied to the upper electrode 1022 drives the piezoelectric layer 1026 to generate an ultrasonic wave emission signal. When the echo signal of the ultrasonic wave reaches the piezoelectric layer 1026, the voltage on the lower electrode 1024 changes and is detected by the readout circuit, i.e., the echo voltage is detected. By judging the echo voltage The amplitude is used to determine whether it is a valley or a ridge, thus completing the fingerprint recognition operation. Additionally... The parasitic capacitance in pixel circuit 104 It is the reset voltage of pixel circuit 104. It is the reference voltage of the first operational amplifier pxl_op. and The relationship can be: = =1 / 2 power supply voltage.

[0034] Figure 2 It shows Figure 1 The ultrasonic fingerprint reading circuit shown has one possible operating timing, such as... Figure 2 As shown, when the high-voltage coding circuit of the ultrasonic fingerprint chip ( Figure 1 When working (not shown), that is, during the t0 period, S1 is pulled high, which pulls PXL low. After the coding is completed, the t1 period begins, S1 is set low, S4 is pulled high, and pxl_op is reset. Then, the t2 period begins, S2 is pulled high, and PXL is also reset to Vref1. At this point, both pxl_op and PXL have completed their resets. Then S4 is pulled low, and the pxl_op reset ends.

[0035] At some point during time period t3, the PGA samples px_out for the first time to obtain vs1. Then, during time period t4, S2 is pulled low and S3 is pulled high. The PIXEL circuit integrates V1 for the first time, from the peak to the trough. After integration, S3 is pulled low and S2 is pulled high, PXL is reset. After the reset, S2 is pulled low and S3 is pulled high, and the PIXEL circuit integrates V1 for the second time, from the peak to the trough. This integration process is repeated multiple times (e.g., ...). Figure 2As shown in the figure (integration 5 times), we can see that time period t4 is the integration time of the PIXEL circuit. After the 5 integrations are completed, time period t5 begins. S3 is pulled low and S2 is pulled high. At some point in time period t5, the PGA samples px_out for the second time to obtain vs2. The output of the PGA is gain. (vs2-vs1), where gain is the known gain of the PGA, can be determined by quantizing the output of the PGA using the ADC. This allows us to judge the fingerprint status above the detection unit.

[0036] In traditional ultrasonic fingerprint reading circuits, the following fixed processing methods are adopted to address the three core requirements of pixel plate reset, integral amplification reference, and operational amplifier offset compensation:

[0037] A separate reset voltage needs to be set for pixel circuit 104. To ensure the first operational amplifier pxl_op completes its reset and enters a ready state for receiving ultrasonic echoes, thus guaranteeing initial stability for subsequent signal acquisition, a separate reference voltage needs to be configured for it. To ensure the accuracy of the echo voltage integration process, due to the inherent input offset voltage in pxl_op. Furthermore, pxl_op must be chopped to reduce the impact of misalignment on the signal.

[0038] However, on the one hand, due to and Each of these factors introduces noise, which is then superimposed in the circuit, directly reducing the chip's signal-to-noise ratio. Furthermore, the ultrasonic fingerprint echo signal itself has a relatively small amplitude, and this noise superposition further weakens the discernibility of the effective signal. On the other hand... To meet the requirement of rapid pixel plate reset, strong driving capability and high bandwidth are required. These requirements will increase the complexity of the readout circuit design. In addition, the introduction of chopper circuit will further increase the circuit complexity of pxl_op.

[0039] like Figure 3 As shown, an ultrasonic fingerprint reading circuit according to an embodiment of the present disclosure includes: a piezoelectric transducer 302, a pixel integration module 304, a bidirectional integration module 306, and a sampling and quantization module 308.

[0040] The piezoelectric transducer 302 is configured to receive the echo of the emitted ultrasonic wave and convert the echo into an echo voltage.

[0041] In some embodiments, such as Figure 4 As shown, the piezoelectric transducer 302 includes a piezoelectric sensing capacitor. piezoelectric sensing capacitor It includes a pixel electrode plate 3022, a piezoelectric electrode plate 3024, and a piezoelectric layer 3026 disposed between the piezoelectric electrode plate and the pixel electrode plate.

[0042] Among them, the piezoelectric electrode plate refers to the electrode plate covering the piezoelectric layer.

[0043] In some embodiments, the piezoelectric layer may be a piezoelectric material layer such as PVDF (Polyvinylidene Fluoride) or PZT (Lead Zirconate Titanate).

[0044] Those skilled in the art will understand that electrodes are required on both sides of the piezoelectric layer for applying high voltage to drive the piezoelectric layer to emit ultrasonic waves and for conducting echo voltage when receiving echoes. One electrode can be designed as a metal electrode, such as a thin metal layer that covers the entire piezoelectric layer, which can be called the first electrode, i.e., the piezoelectric electrode in this disclosure. The piezoelectric electrode can be an Ag layer. The other electrode can be designed as a discrete metal electrode, such as using the top metal layer of a chip, which can be called the second electrode, i.e., the pixel electrode in this disclosure. When ultrasonic waves need to be emitted, the second electrode is grounded and the first electrode is connected to the driving voltage. When ultrasonic waves need to be received, the second electrode is connected to the subsequent readout circuit.

[0045] In some embodiments, the piezoelectric transducer 302 may also be a symmetrical structure with a double piezoelectric layer combined with an intermediate electrode.

[0046] In some embodiments, when the ultrasonic waves emitted by the fingerprint recognition chip come into contact with the fingerprint, the difference in the ridge and valley structure leads to different reflection energy and penetration depth of the echo. The fingerprint ridge reflects ultrasonic waves with strong energy, while the valley reflects them with weak energy. This difference causes the piezoelectric layer to generate corresponding mechanical vibrations. The piezoelectric transducer converts the mechanical vibrations into an echo voltage that matches the echo energy through the piezoelectric effect, thereby realizing the sensing conversion from acoustic signals to electrical signals.

[0047] The pixel integration module 304 is connected to the piezoelectric transducer and includes a first switching assembly and a pixel integration operational amplifier. The first switching assembly is used to configure the pixel integration operational amplifier to reset the pixel plate after the piezoelectric transducer sends ultrasonic waves, and to configure the pixel integration operational amplifier to output an echo integration voltage that is opposite to the echo voltage after receiving the echo voltage.

[0048] The first switch assembly can be a regular switch assembly or a transmission gate switch.

[0049] The bidirectional integration module 306 is connected to the pixel integration module 304 and includes a second switching component and a gain differential operational amplifier. The gain differential operational amplifier is used to output positive-phase differential signals and negative-phase differential signals. The second switching component is used to configure the gain differential operational amplifier to perform bidirectional integration based on the echo integration voltage.

[0050] The second switching component can be a discrete switching component or a multi-channel analog switch.

[0051] In some embodiments, the bidirectional integration module is specifically a programmable gain amplifier (PGA) with bidirectional integration function. The gain differential operational amplifier forms a fully differential amplification structure. Its input terminal is connected to the output terminal of the pixel integration module through a second switching component. The second switching component controls the gain differential operational amplifier to perform bidirectional integration operation based on the echo integration voltage by switching the integration path: within one integration period, the positive half-cycle (peak to trough) of the echo integration voltage can be integrated first, and then the negative half-cycle (trough to peak) can be integrated, or bidirectional integration can be performed in the reverse order.

[0052] In addition, the positive-phase differential signal and the negative-phase differential signal include the signal when it is in the reference voltage state before bidirectional integration, and the signal after the gain differential operational amplifier completes bidirectional integration. As the bidirectional integration process is executed, the amplitude of the positive-phase differential signal and the negative-phase differential signal that are being integrated in both directions is amplified cumulatively with the number of integrations. The amplitude of the positive-phase differential signal and the negative-phase differential signal is amplified cumulatively with multiple bidirectional integration processes, and its amplitude is twice that of the unidirectional integration mode, thereby effectively improving the signal-to-noise ratio and detection sensitivity of the echo voltage signal.

[0053] The sampling and quantization module 308 is connected to the bidirectional integration module 306 and is used to sample and quantize the positive-phase differential signal and the anti-phase differential signal before and after bidirectional integration to generate a target signal. The target signal is used to generate or simulate an image containing fingerprint features.

[0054] The sampling unit can be a sample-and-hold circuit for a capacitor-based digital-to-analog converter (CDAC) or a pipelined ADC (Analog-to-Digital Converter).

[0055] In some embodiments, the sampling and quantization module 308 can be Figure 5 The ADC shown.

[0056] The target signal is a digital signal obtained by the sampling and quantization module after processing the differential signal before and after bidirectional integration. It is used to carry the echo amplitude difference corresponding to the fingerprint ridges and valleys, and can be directly used to generate or restore an image containing fingerprint texture features.

[0057] In some embodiments, the sampling and quantization module is connected to the output of the bidirectional integration module to sample the positive-phase differential signal and the negative-phase differential signal at different time points. The quantization process is performed on the sampling results at the two time points, which can cancel the inherent noise of the circuit and obtain a pure voltage difference that only reflects the echo voltage. The voltage difference is converted into a target signal in digital form. After the target signals corresponding to multiple pixels are arranged in an array, an image containing the concave and convex features of fingerprint texture can be generated or simulated.

[0058] In this embodiment, the pixel integration module is connected to the piezoelectric transducer. Through the switching control of the first switching component, the pixel integration operational amplifier can directly reuse a single reference voltage to reset the pixel plate. This configures the pixel integration operational amplifier to have the dual functions of resetting the pixel plate and outputting the echo integration voltage. Compared with the dual reference voltage configuration, this reduces noise sources. In addition, the bidirectional integration module performs bidirectional integration based on the echo integration voltage, amplifying the amplitudes of the positive and negative differential signals. The sampling and quantization module samples and quantizes the differential signals before and after bidirectional integration. By calculating the difference between the two samples, the inherent noise of the circuit is further canceled out. Since the voltage amplitude obtained based on the sampled positive and negative differential signals is twice that in the unidirectional integration mode, the signal-to-noise ratio and detection sensitivity of the echo voltage signal can be effectively improved. This improves the extraction accuracy of the effective electrical signal of the fingerprint echo and the accuracy of fingerprint feature recognition.

[0059] like Figure 6 As shown, in one embodiment of this disclosure, during the first time period T0, the piezoelectric transducer emits ultrasonic waves, the pixel electrode plate enters a high-voltage isolation state, and the pixel integrating operational amplifier enters a reset state.

[0060] In some embodiments, different states of the first switching component correspond to different on / off combinations.

[0061] In some implementations, the first phase adapts to the ultrasonic emission requirements, and the high-voltage emission and circuit pre-reset are achieved in parallel through a switch combination.

[0062] In the second time period T1, the pixel plate of the first switching component is released from the high voltage isolation, and the pixel integration amplifier remains in the reset state.

[0063] In some embodiments, the second time period adapts to the transition requirements between transmission and reception, and the high-voltage isolation is released by switching adjustment to prepare for receiving the echo.

[0064] In the third time period T2, the first switching component configures the pixel plate to the reset state by the pixel integration operational amplifier.

[0065] In some embodiments, the third time period adapts to the calibration requirements of the pixel electrode plate, and the electrode plate is reset by a switch combination to eliminate residual noise.

[0066] In the fourth time period, the first switching component switches the pixel integration amplifier to continuous integration mode.

[0067] In some embodiments, the fourth time period adapts to the needs of echo signal processing by switching on and off to start the integration mode and complete the signal conversion of the echo voltage.

[0068] In this embodiment, the first switching component adapts to the on / off combination states of the ultrasonic fingerprint recognition transmission, transition, calibration, and processing flow, enabling coordinated and orderly operation of components different from ultrasonic fingerprint recognition. Specifically, in the first period, the ultrasonic high-voltage transmission, pixel plate isolation protection, and pixel integration amplifier pre-reset are completed in parallel through the switching combination. In the second period, the transition to the echo reception ready state is adjusted through the switch. In the third period, the pixel plate is reset through the switch configuration. In the fourth period, the echo voltage continuous integration conversion is started through the switch switching. This ensures the circuit safety during the high-voltage transmission stage and the continuity of reception preparation after transmission. Furthermore, the integration processing improves the purity and amplitude of the echo signal, thereby enhancing the detection sensitivity and recognition accuracy of the ultrasonic fingerprint reading circuit.

[0069] like Figure 4 As shown, in one embodiment of this disclosure, the first switch assembly includes: a first switch S1, one end of which is connected to the pixel plate and the other end of which is grounded; a second switch S2, which is disposed between the pixel plate and the pixel integration operational amplifier; and a third switch S3, which is disposed in parallel with the pixel integration operational amplifier.

[0070] In the first time period, the first switch S1 and the third switch S3 are closed, and the second switch S2 is open. In the second time period, the first switch S1 is switched to open. In the third time period, the second switch S2 is switched to closed. In the fourth time period, the third switch S3 is switched to open.

[0071] In some embodiments, during the first time period, the first switch S1 and the third switch S3 are closed, and the second switch S2 is open. At this time, the pixel plate is grounded through the first switch S1 and enters high-voltage isolation. The second operational amplifier pga_op enters the reset state due to the parallel connection of the third switch S3, adapting to the ultrasonic transmission requirements. During the second time period, the first switch S1 is open, the third switch S3 remains closed, and the second switch S2 remains open. The pixel plate is released from the ground isolation, and the pixel integration amplifier remains reset, completing the transition from transmission to reception. During the third time period, the second switch S2 is closed, the first switch S1 is open, and the third switch S3 remains closed. The pixel plate is connected to the pixel integration amplifier through the second switch S2. The pixel integration amplifier clamps the pixel plate voltage to the reference voltage Vref2 through negative feedback, realizing the reset of the pixel plate. During the fourth time period, the third switch S3 is open, the second switch S2 remains closed, and the first switch S1 is open. The pixel integration amplifier exits the reset state and the piezoelectric sensing capacitor is connected through the integration capacitor. The converted echo voltage is continuously integrated to output the echo integrated voltage px_out, which is adapted to the echo signal processing requirements.

[0072] In this embodiment, by controlling the on / off state of the first switch S1, the second switch S2, and the third switch S3, the high-voltage isolation protection of the pixel plate is achieved by grounding the first switch S1 during the ultrasonic emission stage. The third switch S3 is used to complete the reset calibration in parallel with the operational amplifier. Combined with the on / off switching of the second switch S2, the plate reset and integration mode are seamlessly connected. While simplifying the structure of the switching components, the residual charge and noise of the pixel plate are effectively eliminated, ensuring the purity and amplitude stability of the echo integration voltage, and ultimately improving the detection accuracy of the ultrasonic fingerprint signal and the reliability of the circuit operation.

[0073] like Figure 4 As shown, in one embodiment of this disclosure, the pixel integration operational amplifier includes a first operational amplifier pxl_op and a first integration capacitor. The first operational amplifier pxl_op includes a first input terminal, a second input terminal, and a first output terminal. One end of the second switch S2 is connected to one end of the first switch S1, and the other end of the second switch S2 is connected to the first input terminal. The second input terminal is used to connect a first reference voltage. The first integrating capacitor... One end of the first integrating capacitor is connected to the other end of the second switch S2. The other end is connected to the first output terminal, and the third switch S3 is connected to the first integrating capacitor. Parallel configuration.

[0074] Among them, one of the first input terminal and the second input terminal is an inverting input terminal, and the other is a positive input terminal.

[0075] In some embodiments, when the third switch S3 is closed, the first integrating capacitor When short-circuited, during the first to third time periods, the first operational amplifier pxl_op operates in voltage follower mode. Through a negative feedback mechanism, the voltage at the first input terminal is clamped to the first reference voltage at the second input terminal. Combined with the opening and closing of the first switch S1 and the second switch S2, high-voltage isolation, release, and reset of the pixel plate can be achieved. That is, the pixel plate voltage is clamped to the first reference voltage along with the first input terminal. When the third switch S3 is opened, corresponding to the fourth time period, the first integrating capacitor... In the access circuit, the first operational amplifier pxl_op switches to integrator mode, and the piezoelectric transducer... The converted echo voltage is input to the first input terminal via the second switch S2. The first operational amplifier pxl_op, through negative feedback, activates the first integrating capacitor. The charge is continuously accumulated, converting the echo voltage into a continuously amplified echo integral voltage and outputting it from the first output terminal.

[0076] In this embodiment, through the first operational amplifier pxl_op and the first integrating capacitor The parallel connection with the third switch S3 utilizes the on / off state of the third switch S3 to achieve voltage following, i.e., reset and integration, i.e., signal processing mode switching. This ensures the reliability of pixel plate reset based on the first reference voltage and negative feedback, and also leverages the first integrating capacitor. The integration function amplifies the weak signal of the echo voltage, while simplifying the circuit structure of the pixel integration module and reducing the noise introduction of independent reset devices.

[0077] In one embodiment of this disclosure, during a first time period, the piezoelectric transducer receives a high-voltage pulse signal, the first input terminal is disconnected from the pixel electrode, the first output terminal is short-circuited to the first input terminal, and the first integrating capacitor... When shorted, the first operational amplifier pxl_op enters reset mode, and the first integrating capacitor... The system enters a discharge reset state; in the second phase, the piezoelectric transducer stops receiving high-voltage pulse signals, and the first input terminal is in a state awaiting calibration; in the third phase, the pixel plate is connected to the first input terminal, and the voltage of the pixel plate is clamped to the first reference voltage to complete the reset; in the fourth phase, the echo voltage is connected to the first input terminal, the first operational amplifier pxl_op, and the first integrating capacitor. The echo voltage is converted into the echo integral voltage connected to the first output terminal based on negative feedback.

[0078] like Figure 6As shown, in some embodiments, during the first time period, when the high-voltage coding circuit outputs a high-voltage pulse signal to the piezoelectric transducer, the first switch S1 closes to ground the pixel electrode plate. The piezoelectric electrode plate receives the high-voltage pulse, and the piezoelectric layer undergoes the inverse piezoelectric effect under the action of the high-voltage electric field, generating mechanical vibration and emitting ultrasonic waves outward.

[0079] In some embodiments, during the second time period, the high-voltage pulse stops, the first switch S1 opens to disconnect the pixel plate from the ground isolation, the third switch S3 remains closed, the second switch S2 opens, the first operational amplifier pxl_op remains reset, and the first input terminal is in a state to be calibrated.

[0080] In some embodiments, during the third time period, the second switch S2 is closed to connect the pixel electrode plate to the first input terminal of the first operational amplifier pxl_op. The second input terminal of the first operational amplifier pxl_op is connected to the first reference voltage. The voltage of the first input terminal (and the pixel electrode plate) is clamped to the reference voltage through negative feedback, thereby completing the electrode plate reset.

[0081] In some embodiments, during the fourth time period, the third switch S3 is open, and the first integrating capacitor... A piezoelectric transducer is connected between the first input and output terminals of the first operational amplifier pxl_op. The fingerprint echo is converted into an echo voltage and input to the first input terminal via the second switch S2. The first operational amplifier pxl_op, based on negative feedback, activates the first integrating capacitor. Accumulated charge converts the echo voltage into an amplified echo integral voltage, which is then output from the output terminal.

[0082] In this embodiment, the first switching component, the first operational amplifier pxl_op, and the first integrating capacitor are combined. The function is to achieve both the isolation and protection of the ultrasonic emission of the piezoelectric transducer and the pixel plate during the high-voltage emission stage, and to complete the plate reset through negative feedback to eliminate residual noise. Simultaneously, it utilizes the first integrating capacitor... The integration function amplifies weak echo signals, which simplifies device configuration and helps improve the purity and amplitude stability of the echo integrated voltage.

[0083] like Figure 6 As shown, in one embodiment of this disclosure, the fourth time period sequentially includes the first sub-time period T3, the second sub-time period T4, the third sub-time period T5, and the fourth sub-time period T6.

[0084] In the first and second time periods, the gain differential op-amp enters the initial reset state; in the third time period and the first sub-time period, the gain differential op-amp switches to the calibration reset state; in the second sub-time period, the gain differential op-amp switches to the ready state before bidirectional integration; in the third sub-time period, the gain differential op-amp switches to the state of performing bidirectional integration; in the fourth sub-time period, the gain differential op-amp switches to the signal lock state.

[0085] like Figure 5 As shown, in one embodiment of this disclosure, the gain differential operational amplifier includes a second operational amplifier pga_op and a first gain capacitor. Second gain capacitor The second operational amplifier pga_op includes a third input terminal, a fourth input terminal, a second output terminal, and a third output terminal. The second output terminal outputs an inverted differential signal, and the third output terminal outputs a non-inverting differential signal. The first gain capacitor... The second gain capacitor is located between the third input terminal and the second output terminal. It is positioned between the fourth input and the third output.

[0086] In one embodiment of this disclosure, the second switching assembly includes a first set of switches, a second set of switches, and a third set of switches.

[0087] like Figure 5 As shown, the first set of switches includes a fourth switch S4 and a fifth switch S5; the second set of switches includes a sixth switch S6 and a seventh switch S7; the fourth and sixth switches are located between the pixel integration operational amplifier and the third input terminal, and the fifth and seventh switches are located between the pixel integration operational amplifier and the fourth input terminal; the third set of switches includes an eighth switch S8 and a ninth switch S9; the eighth switch is connected to the first gain capacitor. Parallel connection, ninth switch and second gain capacitor in parallel.

[0088] Specifically, during the first and second time periods, the first and second sets of switches are open, and the third set of switches is closed. During the third time period and the first sub-time period, the first and second sets of switches are switched to closed. During the second sub-time period, the first, second, and third sets of switches are switched to open. During the third sub-time period, the first and second sets of switches are switched to open and closed alternately. During the fourth sub-time period, the first and second sets of switches are switched to open.

[0089] In some embodiments, the switching of the second switching component is to adapt to the bidirectional integration module, namely the reset calibration, bidirectional integration and signal holding of the PGA circuit.

[0090] like Figure 6As shown, during the first time period T0 and the second time period T1, the fourth switch S4, the fifth switch S5, the sixth switch S6, and the seventh switch S7 are open to isolate the pixel integration module output, and the eighth switch S8 and the ninth switch S9 are closed to allow the first gain capacitor to... Second gain capacitor Shorting the circuit puts the second operational amplifier pga_op of the bidirectional integration module into reset mode, discharging the first gain capacitor Cf1 and the second gain capacitor to zero, preparing for subsequent integration. During the third time period T2 and the first sub-time period T3, switches S4, S5, S6, and S7 are closed, connecting the echo integration voltage output from the pixel integration module to the third and fourth input terminals of the second operational amplifier pga_op. Simultaneously, switches S8 and S9 remain closed, completing the signal path establishment and reference calibration before integration. During the second sub-time period T4, all switches are opened, allowing the integration module to... The gain capacitor maintains the current charge state, enabling signal temporary storage. During the third sub-period T5, the fourth switch S4 and the fifth switch S5 are synchronously and the sixth switch S6 and the seventh switch S7 are synchronously and alternately opened and closed, switching the input path of the echo integration voltage. This controls the second operational amplifier pga_op to integrate the positive or negative half-cycle of the echo integration voltage, i.e., to perform bidirectional integration, and to amplify the peak-to-peak value of the signal using a differential structure. During the fourth sub-period T6, the fourth switch S4, the fifth switch S5, the sixth switch S6, and the seventh switch S7 are disconnected, isolating the input signal and maintaining the integrated signal state, providing a stable input for the sampling and quantization module.

[0091] In this embodiment, the group on / off control of the second switching component not only realizes the reset calibration and signal path switching of the bidirectional integration module, but also completes the peak-to-peak bidirectional integration of the echo integration voltage based on the alternating on / off logic, doubling the signal amplitude. At the same time, the signal is temporarily stored by disconnecting the switch. While simplifying the circuit control, it suppresses the accumulation of offset voltage, thereby improving the signal-to-noise ratio and detection sensitivity. Ultimately, it enhances the processing accuracy of the ultrasonic fingerprint echo signal and the circuit's anti-interference capability. While simplifying the switching control logic, it can amplify the effective amplitude of the echo signal and reduce signal crosstalk between modules, enabling subsequent large ADC sampling to more accurately capture the weak signal differences corresponding to the fingerprint ridges.

[0092] like Figure 5 As shown, in one embodiment of this disclosure, the fourth, fifth, sixth, and seventh switches have a common terminal. The bidirectional integration module further includes: a second integrating capacitor C1, disposed between the pixel integrating operational amplifier and the common terminal; and a third integrating capacitor C2, one end of which is connected to the common terminal, and the other end of which is connected to the digital-to-analog conversion calibration voltage. .

[0093] In some embodiments, the second integrating capacitor C1 is used to transmit the echo integration voltage output by the pixel integrating module, while the third integrating capacitor C2 is used to introduce... Combined with the on / off control of the switch, before bidirectional integration, The charge balance of the second integrating capacitor C1 and the third integrating capacitor C2 is calibrated to cancel the inherent offset voltage of the circuit. When the switches are switched on and off alternately, the echo integration voltage transmitted by the second integrating capacitor C1 and the calibration voltage of the third integrating capacitor C2 work together to enable the bidirectional integrating module to maintain the stability of the reference voltage while amplifying the echo signal.

[0094] In one embodiment of this disclosure, during the first and second time periods, the second integrating capacitor C1, the third integrating capacitor C2, the first gain capacitor Cf1, and the second gain capacitor Cf2 are short-circuited, and the second operational amplifier pga_op is short-circuited to enter an initial reset state. During the third time period and the first sub-time period, the second operational amplifier pga_op clamps the second integrating capacitor C1 and the third integrating capacitor C2 to the second reference voltage. During the second sub-time period, the second operational amplifier pga_op is un-short-circuited. During the third sub-time period, the second integrating capacitor C1 and the third integrating capacitor C2 perform bidirectional alternating integration, the first gain capacitor Cf1 adjusts the amplified inverted differential signal output by the second operational amplifier pga_op based on negative feedback, and the second gain capacitor Cf2 adjusts the amplified positive differential signal output by the second operational amplifier pga_op based on negative feedback. During the fourth sub-time period, the second integrating capacitor C1 and the third integrating capacitor C2 stop integrating, and the second operational amplifier pga_op switches to a signal-locked state.

[0095] In some embodiments, during the first and second time periods, the second integrating capacitor C1, the third integrating capacitor C2, the first gain capacitor Cf1, and the second gain capacitor Cf2 are shorted by a switch, and the second operational amplifier pga_op is shorted simultaneously to bring it into an initial reset state, completing capacitor discharge and zeroing and operational amplifier reference reset, eliminating residual charge and offset from the previous period. During the third time period and the first sub-time period, the short circuit of the second operational amplifier pga_op is released, and its negative feedback is used to clamp the second integrating capacitor C1 and the third integrating capacitor C2 to the second reference voltage to complete capacitor voltage calibration. During the second sub-time period, the short circuit of the second operational amplifier pga_op is completely released, bringing it into the integration mode. During the third sub-time period, the second integrating capacitor C1 and the third integrating capacitor C2 alternately integrate the echo signal, and the first gain capacitor Cf1 and the second gain capacitor Cf2 amplify the inverted and positive differential signals respectively through negative feedback, realizing bidirectional amplification of the peak-to-peak value of the echo signal. During the fourth sub-time period, the second integrating capacitor C1 and the third integrating capacitor C2 stop integrating, and the second operational amplifier pga_op locks the current output signal to provide a stable differential signal for subsequent sampling.

[0096] In this embodiment, by performing a phased reset, calibration, integration, and latching, the residual interference from the capacitor and operational amplifier is completely eliminated in the initial stage, and the signal reference is unified by clamping the reference voltage. At the same time, the effective amplitude of the echo signal is amplified by relying on bidirectional alternating integration and negative feedback amplification of the gain capacitor, thereby enabling the output of a stable differential signal with sufficient amplitude.

[0097] In one embodiment of this disclosure, the sampling and quantization module includes a sampling unit 702 and a quantization unit 704.

[0098] The sampling unit is connected to the gain differential operational amplifier and is used to acquire a first positive-phase differential signal and a first negative-phase differential signal at a first time, and to acquire a second positive-phase differential signal and a second negative-phase differential signal at a second time, so as to determine a first difference between the second positive-phase differential signal and the second negative-phase differential signal, and a second difference between the first positive-phase differential signal and the first negative-phase differential signal, and to determine the voltage difference based on the first difference and the second difference.

[0099] The quantization unit is connected to the sampling unit and is used to convert the voltage difference into a target signal. The first time is the time in the first sub-time period or the second sub-time period, and the second time is the time in the fourth sub-time period.

[0100] In some embodiments, in conjunction with the timing of the bidirectional integration module, the sampling unit acquires the first positive-phase differential signal and the first negative-phase differential signal output by the gain differential operational amplifier at the first moment, corresponding to the initial reference signal. At the second moment, it acquires the second positive-phase differential signal and the second negative-phase differential signal after integration and amplification, corresponding to the valid echo signal. Then, it calculates the first difference between the second positive-phase differential signal and the second negative-phase differential signal, i.e., the signal difference after integration, and the second difference between the first positive-phase differential signal and the first negative-phase differential signal, i.e., the initial reference difference. The difference between the two is obtained by subtracting the two, which only reflects the amplitude of the echo signal. The quantization unit converts the voltage difference into a digital signal to complete the digitization of the echo signal.

[0101] In this embodiment, the sampling unit cancels out common-mode interference and reference offset of the circuit through dual-time differential sampling and extracts the effective change of the echo signal. The quantization unit converts the analog voltage difference into a digital signal, providing a more accurate and interference-resistant digital input for subsequent fingerprint recognition, which in turn helps to improve the distinguishability of the fingerprint signal.

[0102] like Figure 7As shown, in one embodiment of this disclosure, the sampling unit 702 includes: a capacitor-to-digital converter (CDAC) including a binary weighted capacitor array, including a first capacitor subarray and a second capacitor subarray. The first capacitor subarray includes upper rows of C0 to Cn for storing a first inverted differential signal Von1 and multiple components Vop2 of a second positive differential signal. The second capacitor subarray and the first capacitor subarray include lower rows of C0 to Cn for storing the first positive differential signal Vop1 and multiple components Von2 of the second inverted differential signal, to output a voltage difference. The multiple components correspond to the weights of the binary weighted capacitors, used to match the number of binary bits of the target signal.

[0103] In some embodiments, such as Figure 7 As shown, the upper row of capacitors is the first capacitor subarray, and the lower row of capacitors is the second capacitor subarray, both of which are binary weighted structures. The capacitance values ​​satisfy the following:

[0104] (1)

[0105] (2)

[0106] The first subarray first stores the first inverted differential signal, i.e., the initial reference, and then superimposes and stores the binary component of the second positive differential signal, corresponding to the integrated positive signal. The second subarray first stores the first positive differential signal, i.e., the initial reference, and then superimposes and stores the binary component of the second inverted differential signal, corresponding to the integrated inverted signal. Based on the principle of capacitor charge conservation, the voltage difference at the output of the capacitor-to-digital converter (CDAC) corresponds to the effective signal difference between the first and second differences, and the capacitor weight matches the number of binary bits of the target signal, thus realizing the quantization-level storage of the signal.

[0107] In this embodiment, the echo signal is sampled and stored using a binary weighted capacitor array. At the same time, the common-mode interference of the initial reference is canceled by a dual capacitor subarray. While ensuring that the sampling accuracy matches the number of bits of the digital signal, this approach simplifies the circuit structure of the sampling unit and improves the stability and anti-interference capability of the signal storage.

[0108] In one embodiment of this disclosure, the quantization unit 704 includes: a comparator, including a first comparison terminal, a second comparison terminal, and a fourth output terminal, wherein the first comparison terminal is connected to a voltage difference, the second comparison terminal is connected to a second reference voltage, and the fourth output terminal outputs a comparison level; and a successive approximation register, used to determine the binary target signal sequentially from the most significant bit to the least significant bit based on the comparison level.

[0109] In some embodiments, the quantization unit adopts a successive approximation SAR architecture, that is, the first comparison terminal of the comparator is connected to the voltage difference output by the CDAC, and the second comparison terminal is connected to the second reference voltage. By comparing the high level and low level of the output, the successive approximation register SAR starts from the most significant bit of the digital signal and adjusts the weight of each binary bit in sequence based on the comparison level to match the weight of the CDAC capacitor. After each bit is adjusted, the comparator judges the magnitude of the voltage difference and the current weight voltage until all bits are determined, so that a binary digital signal corresponding to the echo signal can be output.

[0110] In this embodiment, the digital conversion of the echo voltage difference is realized based on the successive approximation quantization of the comparator and the SAR register. This not only ensures that the resolution of the digital signal matches the sampling accuracy of the CDAC, but also improves the quantization efficiency by determining each bit from the high bit to the low bit, so that the final output digital signal can accurately reflect the amplitude difference of the fingerprint echo.

[0111] An ultrasonic fingerprint chip according to an embodiment of the present disclosure includes: the ultrasonic fingerprint reading circuit described in any of the above embodiments.

[0112] In some embodiments, the ultrasonic fingerprint chip includes a pixel array, including multiple piezoelectric transducers, and may further include a high-voltage pulse generation module for generating high-voltage pulse signals, a timing control module for outputting switching timing, and providing a first reference voltage, a second reference voltage, and a digital-to-analog conversion calibration voltage. Reference voltage modules, etc.

[0113] In this embodiment, based on the configuration of multi-state switch control, bidirectional integral amplification, dual-time differential sampling, and successive approximation quantization of the recognition circuit, the timing coordination of the switching components ensures high-voltage isolation and circuit pre-reset of the pixel plate during the ultrasonic transmission stage. During the reception stage, residual noise is eliminated through calibration. The bidirectional integral module amplifies the peak-to-peak value of the echo signal and suppresses offset interference. Dual-time differential sampling and CDAC weighted storage further cancel common-mode noise. Finally, through successive approximation quantization, a high-resolution digital signal is output, which can more accurately distinguish the differences in ultrasonic echo amplitude corresponding to fingerprint ridges, thereby improving the accuracy and anti-interference ability of fingerprint recognition.

[0114] In this disclosure, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0115] In the description of this disclosure, it should be understood that the terms "upper," "lower," "left," "right," "front," "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0116] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0117] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure. Other embodiments of this disclosure will be readily apparent to those skilled in the art upon consideration of the specification and practice of the solutions disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An ultrasonic fingerprint reading circuit, characterized in that, include: A piezoelectric transducer is configured to receive the echo of an emitted ultrasonic wave and convert the echo into an echo voltage, the piezoelectric transducer including pixel plates; A pixel integration module, connected to the piezoelectric transducer, includes a first switching assembly and a pixel integration operational amplifier. The first switching assembly is used to configure the pixel integration operational amplifier to reset the pixel plate after the piezoelectric transducer sends the ultrasonic wave, and to configure the pixel integration operational amplifier to output an echo integration voltage that is opposite to the echo voltage after receiving the echo voltage. A bidirectional integration module, connected to the pixel integration module, includes a second switching component and a gain differential operational amplifier. The gain differential operational amplifier is used to output positive-phase differential signals and negative-phase differential signals. The second switching component is used to configure the gain differential operational amplifier to perform bidirectional integration based on the echo integration voltage. The sampling and quantization module, connected to the bidirectional integration module, is used to sample and quantize the positive-phase differential signal and the anti-phase differential signal before and after bidirectional integration to generate a target signal, which is used to generate or simulate an image containing fingerprint features.

2. The ultrasonic fingerprint reading circuit according to claim 1, characterized in that, In the first time period, the piezoelectric transducer emits the ultrasonic wave, the pixel electrode plate enters a high-voltage isolation state, and the pixel integral operational amplifier enters a reset state. In the second time period, the pixel electrode is released from the high-voltage isolation, and the pixel integral operational amplifier remains in the reset state. During the third time period, the pixel integration amplifier configures the pixel plate to a reset state. During the fourth time period, the pixel integration amplifier of the first switching component switches to continuous integration mode.

3. The ultrasonic fingerprint reading circuit according to claim 2, characterized in that, The first switching component includes: A first switch, one end of which is connected to the pixel electrode plate, and the other end of which is grounded; The second switch is disposed between the pixel electrode and the pixel integration operational amplifier; The third switch is connected in parallel with the pixel integration amplifier. Specifically, during the first time period, the first switch and the third switch are closed, and the second switch is open; during the second time period, the first switch is switched to open; during the third time period, the second switch is switched to closed; and during the fourth time period, the third switch is switched to open.

4. The ultrasonic fingerprint reading circuit according to claim 3, characterized in that, The pixel integrating operational amplifier includes a first operational amplifier and a first integrating capacitor. The first operational amplifier includes a first input terminal, a second input terminal, and a first output terminal. One end of the second switch is connected to one end of the first switch, and the other end of the second switch is connected to the first input terminal. The second input terminal is used to connect to a first reference voltage. One end of the first integrating capacitor is connected to the other end of the second switch, and the other end of the first integrating capacitor is connected to the first output terminal. The third switch is connected in parallel with the first integrating capacitor.

5. The ultrasonic fingerprint reading circuit according to claim 4, characterized in that, During the first time period, the piezoelectric transducer receives a high-voltage pulse signal, the first input terminal is disconnected from the pixel plate, the first output terminal is short-circuited to the first input terminal, the first integrating capacitor is short-circuited, the first operational amplifier enters a reset mode, and the first integrating capacitor enters a discharge clear state. During the second time period, the piezoelectric transducer stops receiving the high-voltage pulse signal, and the first input terminal is in a state of waiting for calibration. During the third time period, the pixel plate is connected to the first input terminal, and the voltage of the pixel plate is clamped to the first reference voltage to complete the reset. During the fourth time period, the echo voltage is connected to the first input terminal, and the first operational amplifier and the first integrating capacitor convert the echo voltage into the echo integrated voltage connected to the first output terminal based on negative feedback.

6. The ultrasonic fingerprint reading circuit according to claim 2, characterized in that, The fourth time period includes, in sequence, the first sub-time period, the second sub-time period, the third sub-time period, and the fourth sub-time period. During the first and second time periods, the gain differential operational amplifier enters an initial reset state. During the third time period and the first sub-time period, the second switching component switches the gain differential operational amplifier to a calibration reset state; During the second sub-period, the second switching component switches the gain differential operational amplifier to the ready state before bidirectional integration; During the third sub-period, the second switching component switches the gain differential operational amplifier to a state of performing bidirectional integration; During the fourth sub-period, the second switching component switches the gain differential operational amplifier to a signal-locked state.

7. The ultrasonic fingerprint reading circuit according to claim 6, characterized in that, The gain differential operational amplifier includes a second operational amplifier, a first gain capacitor, and a second gain capacitor. The second operational amplifier includes a third input terminal, a fourth input terminal, a second output terminal, and a third output terminal. The second output terminal outputs the inverted differential signal, and the third output terminal outputs the non-inverted differential signal. The first gain capacitor is disposed between the third input terminal and the second output terminal, and the second gain capacitor is disposed between the fourth input terminal and the third output terminal.

8. The ultrasonic fingerprint reading circuit according to claim 7, characterized in that, The second switch assembly includes a first set of switches, a second set of switches, and a third set of switches. The first set of switches includes a fourth switch and a fifth switch, and the second set of switches includes a sixth switch and a seventh switch. The fourth switch and the sixth switch are disposed between the pixel integration operational amplifier and the third input terminal, and the fifth switch and the seventh switch are disposed between the pixel integration operational amplifier and the fourth input terminal. The third set of switches includes an eighth switch and a ninth switch. The eighth switch is connected in parallel with the first gain capacitor, and the ninth switch is connected in parallel with the second gain capacitor. Specifically, during the first and second time periods, the first and second sets of switches are open, and the third set of switches is closed. During the third and first sub-time periods, the first and second sets of switches are switched to closed. During the second sub-time period, the first, second, and third sets of switches are switched to open. During the third sub-time period, the first and second sets of switches are alternately opened and closed. During the fourth sub-time period, the first and second sets of switches are switched to open.

9. The ultrasonic fingerprint reading circuit according to claim 8, characterized in that, The fourth switch, the fifth switch, the sixth switch, and the seventh switch have a common terminal, and the bidirectional integration module further includes: The second integrating capacitor is disposed between the pixel integrating operational amplifier and the common terminal; The third integrating capacitor has one end connected to the common terminal and the other end connected to the digital-to-analog conversion calibration voltage.

10. The ultrasonic fingerprint reading circuit according to claim 9, characterized in that, During the first and second time periods, the second integrating capacitor, the third integrating capacitor, the first gain capacitor and the second gain capacitor are shorted, and the second operational amplifier is shorted to enter the initial reset state. During the third time period and the first sub-time period, the second operational amplifier clamps the second integrating capacitor and the third integrating capacitor to the second reference voltage; During the second sub-period, the second operational amplifier is unshort-circuited; During the third sub-period, the second integrating capacitor and the third integrating capacitor perform bidirectional alternating integration, the first gain capacitor adjusts the amplified inverted differential signal output by the second operational amplifier based on negative feedback, and the second gain capacitor adjusts the amplified positive differential signal output by the second operational amplifier based on negative feedback. During the fourth sub-period, the second integrating capacitor and the third integrating capacitor stop integrating, and the second operational amplifier switches to the signal-locked state.

11. The ultrasonic fingerprint reading circuit according to claim 6, characterized in that, The sampling and quantization module includes: A sampling unit, connected to the gain differential operational amplifier, is used to acquire a first positive-phase differential signal and a first negative-phase differential signal at a first time, and to acquire a second positive-phase differential signal and a second negative-phase differential signal at a second time, so as to determine a first difference between the second positive-phase differential signal and the second negative-phase differential signal, and a second difference between the first positive-phase differential signal and the first negative-phase differential signal, and to determine the voltage difference based on the first difference and the second difference; A quantization unit, connected to the sampling unit, is used to convert the voltage difference into the target signal, wherein the first time moment is a time moment in the first sub-time period or the second sub-time period, and the second time moment is a time moment in the fourth sub-time period.

12. The ultrasonic fingerprint reading circuit according to claim 11, characterized in that, The sampling unit includes: A capacitor-to-digital converter includes a binary weighted capacitor array, which comprises a first capacitor subarray and a second capacitor subarray. The first capacitor subarray stores a first inverting differential signal and multiple components of a second positive differential signal. The second capacitor subarray stores the first positive differential signal and multiple components of the second inverting differential signal to output the voltage difference. The multiple components correspond to the weights of the binary weighted capacitors and are used to match the number of binary bits of the target signal.

13. The ultrasonic fingerprint reading circuit according to claim 12, characterized in that, The quantization unit includes: The comparator includes a first comparison terminal, a second comparison terminal, and a fourth output terminal. The first comparison terminal is connected to the voltage difference, the second comparison terminal is connected to a second reference voltage, and the fourth output terminal outputs a comparison level. A successive approximation register is used to determine the binary target signal sequentially from the most significant bit to the least significant bit based on the comparison level.

14. The ultrasonic fingerprint reading circuit according to claim 1, characterized in that, The piezoelectric transducer also includes: A piezoelectric electrode plate and a piezoelectric layer disposed between the piezoelectric electrode plate and the pixel electrode plate.

15. An ultrasonic fingerprint chip, characterized in that, include: The ultrasonic fingerprint reading circuit as described in any one of claims 1 to 14.

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