A differential power amplifier and radio frequency chip

Abstract

The application belongs to the technical field of communication, and particularly relates to a differential power amplifier and a radio frequency chip. The differential power amplifier comprises a first transformer, an input matching circuit, an amplification circuit, a second transformer, a first linear bias circuit and a second linear bias circuit. The first transformer is used for differentiating a radio frequency signal into a first input signal and a second input signal and outputting the first input signal and the second input signal to the input matching circuit respectively. The first linear bias circuit is used for providing a bias voltage for a first input end of the amplification circuit. The second linear bias circuit is used for providing a bias voltage for a second input end of the amplification circuit. Compared with the prior art, the differential power amplifier provided by the application has a simple circuit structure and can self-adaptively compensate for unbalanced components in the circuit without other additional circuit structures, so that the balance of the differential power amplifier circuit is optimized, and the performance of the differential power amplifier is optimized.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a differential power amplifier and a radio frequency chip. Background Technology

[0002] In the field of communication technology, gallium arsenide heterojunction bipolar transistors (GaAs HBTs) have been widely researched and applied in microwave power amplifiers due to their excellent high power density and high linearity, especially in core components of radio frequency communication such as mobile phone power amplifiers, where they have become one of the mainstream core devices. However, gallium arsenide HBTs have inherent structural defects; the parasitic capacitance between their base and emitter significantly degrades the device's linear performance. This problem has become one of the key bottlenecks restricting the performance improvement of GaAs HBT power amplifiers.

[0003] To improve the linear performance of GaAs HBT power amplifiers, active linear bias circuits are commonly used in differential power amplifier design for performance optimization. The core design logic of this active linear bias circuit lies in achieving stable control of the power transistor's quiescent operating point by appropriately setting the capacitance value of capacitor Cb within the circuit. When the input RF signal power increases, some RF signal leaks into the bias circuit. After rectification by the linear bias circuit, this leads to a decrease in the DC voltage drop across the base-emitter junction. Simultaneously, the voltage drop across the base-emitter junction of the first and second power transistors in the amplifier circuit during the increase in input power can be compensated for by this voltage drop reduction effect, thereby stabilizing the power amplifier's quiescent operating point and ultimately achieving the goal of optimizing the power amplifier's linear performance.

[0004] However, in the above-mentioned active linear bias circuit, the capacitance value of capacitor Cb has a decisive influence on the overall performance of the power amplifier. If the capacitance value of capacitor Cb is larger, it means that more RF power leaks into the bias circuit, the voltage compensation effect of the linear bias circuit on the first and second power transistors is more significant, and the linear performance optimization effect is better. But at the same time, a larger capacitance value of Cb will have a negative impact on key performance indicators such as the saturation power and energy conversion efficiency of the power amplifier, forming an inherent contradiction between "linear performance optimization" and "saturation power and efficiency guarantee".

[0005] Furthermore, in the design practice of high-power power amplifiers, the differential architecture has become the mainstream architecture choice for achieving high-power amplification due to its advantages such as good anti-interference capability and ease of power combining. However, in the actual circuit fabrication and operation, the circuit balance of differential power amplifiers often deviates significantly from the ideal design state. Especially in high-frequency operating scenarios, the balance defects of the differential architecture are further highlighted by the combined effects of various factors such as circuit parasitic parameters, differences in device consistency, and wiring asymmetry. This severely limits the core performance indicators of the power amplifier, such as gain flatness, linearity, and efficiency, becoming another important technical challenge restricting the performance breakthrough of high-power GaAs HBT differential power amplifiers.

[0006] Therefore, there is an urgent need for a new differential power amplifier and RF chip to solve the above-mentioned technical problems. Summary of the Invention

[0007] This invention provides a differential power amplifier and an RF chip, aiming to optimize the balance of the differential power amplifier circuit and improve the performance of the differential power amplifier.

[0008] In a first aspect, the present invention provides a differential power amplifier, the differential power amplifier comprising a first transformer, an input matching circuit, an amplification circuit, a second transformer, a first linear bias circuit, and a second linear bias circuit;

[0009] The first end of the primary coil of the first transformer is used to receive radio frequency signals, the second end of the primary coil of the first transformer is grounded, the first end of the secondary coil of the first transformer is connected to the first input terminal of the input matching circuit, and the second end of the secondary coil of the first transformer is connected to the second input terminal of the input matching circuit; the first transformer is used to differentially divide the radio frequency signal into a first input signal and a second input signal and output them to the first input terminal and the second input terminal of the input matching circuit, respectively.

[0010] The first output terminal of the input matching circuit is connected to the first input terminal of the amplifier circuit, and the second output terminal of the input matching circuit is connected to the second input terminal of the amplifier circuit.

[0011] The first output terminal of the amplifier circuit is connected to the first terminal of the primary coil of the second transformer, and the second output terminal of the amplifier circuit is connected to the second terminal of the primary coil of the second transformer.

[0012] The first terminal of the secondary coil of the second transformer is used for output signal, and the second terminal of the secondary coil of the second transformer is grounded; the second transformer is used to combine and output the first input signal and the second input signal after being amplified by the amplifier circuit.

[0013] The first terminal of the first linear bias circuit is connected to the power supply voltage, the second terminal of the first linear bias circuit is connected to the first input terminal of the amplifier circuit, the third terminal of the first linear bias circuit is connected to the first terminal of the second linear bias circuit, and the fourth terminal of the first linear bias circuit is connected to the second terminal of the second linear bias circuit; the first linear bias circuit is used to provide a bias voltage to the first input terminal of the amplifier circuit.

[0014] The third terminal of the second linear bias circuit is connected to the power supply voltage, and the fourth terminal of the second linear bias circuit is connected to the second input terminal of the amplifier circuit; the second linear bias circuit is used to provide a bias voltage to the second input terminal of the amplifier circuit.

[0015] Preferably, the first linear bias circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, a first resistor, and a second resistor;

[0016] The first end of the first resistor serves as the first end of the first linear bias circuit. The second end of the first resistor is connected to the collector of the second transistor, the gate of the first transistor, and the first end of the first capacitor. The second end of the first capacitor serves as the third end of the first linear bias circuit. The gate of the second transistor is connected to the collector of the second transistor. The emitter of the second transistor is connected to the gate and the collector of the third transistor. The emitter of the third transistor is grounded. The collector of the first transistor is connected to the first end of the first resistor. The emitter of the first transistor serves as the fourth end of the first linear bias circuit. The first end of the second resistor is connected to the emitter of the first transistor. The second end of the second resistor serves as the second end of the first linear bias circuit.

[0017] Preferably, the second linear bias circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a third resistor, a fourth resistor, and a second capacitor;

[0018] The first end of the third resistor serves as the third end of the second linear bias circuit. The second end of the third resistor is connected to the gate of the fourth transistor, the collector of the fifth transistor, and the first end of the second capacitor. The second end of the second capacitor serves as the first end of the second linear bias circuit. The gate of the fifth transistor is connected to the collector of the fifth transistor. The emitter of the fifth transistor is connected to the collector of the sixth transistor and the gate of the sixth transistor. The emitter of the sixth transistor is grounded. The collector of the fourth transistor is connected to the first end of the third resistor. The emitter of the fourth transistor serves as the second end of the second linear bias circuit. The first end of the fourth resistor is connected to the emitter of the fourth transistor. The second end of the fourth resistor serves as the fourth end of the second linear bias circuit.

[0019] Preferably, the input matching circuit includes a third capacitor and a fourth capacitor; the first terminal of the third capacitor serves as the first input terminal of the input matching circuit, the second terminal of the third capacitor serves as the first output terminal of the input matching circuit, the first terminal of the fourth capacitor serves as the second input terminal of the input matching circuit, and the second terminal of the fourth capacitor serves as the second output terminal of the input matching circuit.

[0020] Preferably, the amplification circuit includes a first transistor and a second transistor; the input terminal of the first transistor serves as the first input terminal of the amplification circuit, the output terminal of the first transistor serves as the first output terminal of the amplification circuit, and the ground terminal of the first transistor is grounded; the input terminal of the second transistor serves as the second input terminal of the amplification circuit, the output terminal of the second transistor serves as the second output terminal of the amplification circuit, and the ground terminal of the second transistor is grounded.

[0021] Preferably, the first transistor and the second transistor are MOSFETs or bipolar transistors.

[0022] Secondly, the present invention also provides a radio frequency chip, the radio frequency chip comprising a differential power amplifier as described in any of the above embodiments.

[0023] Compared with existing technologies, the differential power amplifier proposed in this invention includes a first transformer, an input matching circuit, an amplification circuit, a second transformer, a first linear bias circuit, and a second linear bias circuit. The first transformer is used to differentially divide the radio frequency signal into a first input signal and a second input signal, which are then output to the input matching circuit respectively. The first linear bias circuit provides a bias voltage to the first input terminal of the amplification circuit. The second linear bias circuit provides a bias voltage to the second input terminal of the amplification circuit. The differential power amplifier proposed in this invention has a simple circuit structure and can adaptively compensate for unbalanced components in the circuit without the need for other additional circuit structures, optimizing the balance of the differential power amplifier circuit and thus optimizing the performance of the differential power amplifier. Attached Figure Description

[0024] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0025] Figure 1 This is a circuit diagram of a differential power amplifier provided in an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0027] Example 1

[0028] Please refer to Figure 1 The present invention provides a differential power amplifier 100, which includes a first transformer T1, an input matching circuit 1, an amplification circuit 2, a second transformer T2, a first linear bias circuit 3, and a second linear bias circuit 4.

[0029] The first end of the primary coil of the first transformer T1 is used to receive radio frequency signals, the second end of the primary coil of the first transformer T1 is grounded, the first end of the secondary coil of the first transformer T1 is connected to the first input terminal of the input matching circuit 1, and the second end of the secondary coil of the first transformer T1 is connected to the second input terminal of the input matching circuit 1; the first transformer T1 is used to differentially divide the radio frequency signal into a first input signal and a second input signal and output them to the first input terminal and the second input terminal of the input matching circuit 1, respectively.

[0030] The first output terminal of the input matching circuit 1 is connected to the first input terminal of the amplifier circuit 2, and the second output terminal of the input matching circuit 1 is connected to the second input terminal of the amplifier circuit 2.

[0031] The first output terminal of the amplifier circuit 2 is connected to the first terminal of the primary coil of the second transformer T2, and the second output terminal of the amplifier circuit 2 is connected to the second terminal of the primary coil of the second transformer T2.

[0032] The first end of the secondary coil of the second transformer T2 is used for output signal, and the second end of the secondary coil of the second transformer T2 is grounded; the second transformer T2 is used to combine and output the first input signal and the second input signal after being amplified by the amplifier circuit 2.

[0033] The first terminal of the first linear bias circuit 3 is connected to the power supply voltage Vb, the second terminal of the first linear bias circuit 3 is connected to the first input terminal of the amplifier circuit 2, the third terminal of the first linear bias circuit 3 is connected to the first terminal of the second linear bias circuit 4, and the fourth terminal of the first linear bias circuit 3 is connected to the second terminal of the second linear bias circuit 4; the first linear bias circuit 3 is used to provide a bias voltage to the first input terminal of the amplifier circuit 2.

[0034] The third terminal of the second linear bias circuit 4 is connected to the power supply voltage Vb, and the fourth terminal of the second linear bias circuit 4 is connected to the second input terminal of the amplifier circuit 2; the second linear bias circuit 4 is used to provide a bias voltage to the second input terminal of the amplifier circuit 2.

[0035] In this embodiment of the invention, the first linear bias circuit 3 includes a first transistor HBT1, a second transistor D1, a third transistor D2, a first capacitor C1, a first resistor, and a second resistor; wherein, the first capacitor C1 is a bypass capacitor.

[0036] The first end of the first resistor serves as the first end of the first linear bias circuit 3. The second end of the first resistor is connected to the collector of the second transistor D1, the gate of the first transistor HBT1, and the first end of the first capacitor C1. The second end of the first capacitor C1 serves as the third end of the first linear bias circuit 3. The gate of the second transistor D1 is connected to the collector of the second transistor D1. The emitter of the second transistor D1 is connected to the gate and the collector of the third transistor D2. The emitter of the third transistor D2 is grounded. The collector of the first transistor HBT1 is connected to the first end of the first resistor. The emitter of the first transistor HBT1 serves as the fourth end of the first linear bias circuit 3. The first end of the second resistor is connected to the emitter of the first transistor HBT1. The second end of the second resistor serves as the second end of the first linear bias circuit 3.

[0037] In this embodiment of the invention, the second linear bias circuit 4 includes a fourth transistor HBT2, a fifth transistor D3, a sixth transistor D4, a third resistor, a fourth resistor, and a second capacitor C2; wherein, the second capacitor C2 is a bypass capacitor.

[0038] The first end of the third resistor serves as the third end of the second linear bias circuit 4. The second end of the third resistor is connected to the gate of the fourth transistor HBT2, the collector of the fifth transistor D3, and the first end of the second capacitor C2. The second end of the second capacitor C2 serves as the first end of the second linear bias circuit 4. The gate of the fifth transistor D3 is connected to the collector of the fifth transistor D3. The emitter of the fifth transistor D3 is connected to the collector and the gate of the sixth transistor D4. The emitter of the sixth transistor D4 is grounded. The collector of the fourth transistor HBT2 is connected to the first end of the third resistor. The emitter of the fourth transistor HBT2 serves as the second end of the second linear bias circuit 4. The first end of the fourth resistor is connected to the emitter of the fourth transistor HBT2. The second end of the fourth resistor serves as the fourth end of the second linear bias circuit 4.

[0039] In this embodiment of the invention, the input matching circuit 1 includes a third capacitor C3 and a fourth capacitor C4; the first end of the third capacitor C3 serves as the first input terminal of the input matching circuit 1, the second end of the third capacitor C3 serves as the first output terminal of the input matching circuit 1, the first end of the fourth capacitor C4 serves as the second input terminal of the input matching circuit 1, and the second end of the fourth capacitor C4 serves as the second output terminal of the input matching circuit 1.

[0040] In this embodiment of the invention, the amplifier circuit 2 includes a first transistor HBTp and a second transistor HBTn; the input terminal of the first transistor HBTp serves as the first input terminal of the amplifier circuit 2, the output terminal of the first transistor HBTp serves as the first output terminal of the amplifier circuit 2, and the ground terminal of the first transistor HBTp is grounded; the input terminal of the second transistor HBTn serves as the second input terminal of the amplifier circuit 2, the output terminal of the second transistor HBTn serves as the second output terminal of the amplifier circuit 2, and the ground terminal of the second transistor HBTn is grounded.

[0041] In this embodiment of the invention, the first transistor HBTp and the second transistor HBTn are MOS transistors or bipolar transistors.

[0042] Specifically, during the operation of the differential power amplifier 100, when the input RF signal power increases, some RF signal leaks into the first linear bias circuit 3 and the second linear bias circuit 4. The base-emitter junction DC voltage drop after rectification by the first transistor HBT1 and the fourth transistor HBT2 decreases, thus compensating for the reduction in base-emitter junction voltage during the increase in input power by the first transistor HBTp and the second transistor HBTn. This stabilizes the quiescent operating point of the differential power amplifier 100, thereby optimizing its linear performance. Simultaneously, since the first capacitor C1 and the second capacitor C2 are not directly grounded but connected to the other side of the linear bias circuit, if an imbalance occurs during the increase in input power, such as VB > VD, the circuit exhibits the following relationship:

[0043] ;

[0044] ;

[0045] According to the above formula, we can obtain:

[0046] ;

[0047] ;

[0048] Wherein, VA, VB, VC, and VD respectively represent as follows: Figure 1 The voltage values ​​at nodes A, B, C, and D in the circuit diagram shown are represented by Cb. + Cb represents the capacitance value of the first capacitor C1. - This indicates the capacitance value of the second capacitor, C2. represents an imaginary number, Represents the angular frequency, and Cb(VA+VD) represents the capacitance between nodes A and D. This represents the capacitance between nodes B and C.

[0049] Therefore, when VB > VD, we have C <Cb + <Cb - Therefore, the current of the first transistor HBTp is greater than the current of the second transistor HBTn. To maintain the current balance between the first transistor HBTp and the second transistor HBTn, it is necessary to suppress the decreasing trend of the base-emitter junction voltage of the first transistor HBT1 as the input power increases, i.e., Cb needs to be... + <Cb - Therefore, when the differential power amplifier 100 is unbalanced, the circuit structure of the differential power amplifier 100 of this application can effectively suppress the unbalanced components and achieve the balance of the differential power amplifier without the need for additional redundant circuit structures.

[0050] Compared with existing technologies, the differential power amplifier proposed in this invention includes a first transformer, an input matching circuit, an amplification circuit, a second transformer, a first linear bias circuit, and a second linear bias circuit. The first transformer is used to differentially divide the radio frequency signal into a first input signal and a second input signal, which are then output to the input matching circuit respectively. The first linear bias circuit provides a bias voltage to the first input terminal of the amplification circuit. The second linear bias circuit provides a bias voltage to the second input terminal of the amplification circuit. The differential power amplifier proposed in this invention has a simple circuit structure and can adaptively compensate for unbalanced components in the circuit without the need for other additional circuit structures, optimizing the balance of the differential power amplifier circuit and thus optimizing the performance of the differential power amplifier.

[0051] Example 2

[0052] This invention also provides a radio frequency (RF) chip, which includes the differential power amplifier 100 as described in the above embodiments and can achieve the same technical effects. Please refer to the description in the above embodiments, which will not be repeated here.

[0053] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0054] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A differential power amplifier, characterized in that, The differential power amplifier includes a first transformer, an input matching circuit, an amplification circuit, a second transformer, a first linear bias circuit, and a second linear bias circuit. The first transformer is used to receive radio frequency signals and differentially divide the radio frequency signals into a first input signal and a second input signal, and output them to the first input terminal and the second input terminal of the input matching circuit, respectively. The first output terminal of the input matching circuit is connected to the first input terminal of the amplifier circuit, and the second output terminal of the input matching circuit is connected to the second input terminal of the amplifier circuit. The second transformer is used to combine and output the first input signal and the second input signal after being amplified by the amplifier circuit; The first terminal of the first linear bias circuit is connected to the power supply voltage, the second terminal of the first linear bias circuit is connected to the first input terminal of the amplifier circuit, the third terminal of the first linear bias circuit is connected to the first terminal of the second linear bias circuit, and the fourth terminal of the first linear bias circuit is connected to the second terminal of the second linear bias circuit; the first linear bias circuit is used to provide a bias voltage to the first input terminal of the amplifier circuit. The third terminal of the second linear bias circuit is connected to the power supply voltage, and the fourth terminal of the second linear bias circuit is connected to the second input terminal of the amplifier circuit; the second linear bias circuit is used to provide a bias voltage to the second input terminal of the amplifier circuit. The first linear bias circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, a first resistor, and a second resistor; The first end of the first resistor serves as the first end of the first linear bias circuit. The second end of the first resistor is connected to the collector of the second transistor, the base of the first transistor, and the first end of the first capacitor. The second end of the first capacitor serves as the third end of the first linear bias circuit. The base of the second transistor is connected to the collector of the second transistor. The emitter of the second transistor is connected to the base and the collector of the third transistor. The emitter of the third transistor is grounded. The collector of the first transistor is connected to the first end of the first resistor. The emitter of the first transistor serves as the fourth end of the first linear bias circuit. The first end of the second resistor is connected to the emitter of the first transistor. The second end of the second resistor serves as the second end of the first linear bias circuit. The second linear bias circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a third resistor, a fourth resistor, and a second capacitor; The first end of the third resistor serves as the third end of the second linear bias circuit. The second end of the third resistor is connected to the base of the fourth transistor, the collector of the fifth transistor, and the first end of the second capacitor. The second end of the second capacitor serves as the second end of the second linear bias circuit. The base of the fifth transistor is connected to the collector of the fifth transistor. The emitter of the fifth transistor is connected to the collector of the sixth transistor and the base of the sixth transistor. The emitter of the sixth transistor is grounded. The collector of the fourth transistor is connected to the first end of the third resistor. The emitter of the fourth transistor serves as the first end of the second linear bias circuit. The first end of the fourth resistor is connected to the emitter of the fourth transistor. The second end of the fourth resistor serves as the fourth end of the second linear bias circuit.

2. The differential power amplifier as described in claim 1, characterized in that, The input matching circuit includes a third capacitor and a fourth capacitor; the first end of the third capacitor serves as the first input terminal of the input matching circuit, the second end of the third capacitor serves as the first output terminal of the input matching circuit, the first end of the fourth capacitor serves as the second input terminal of the input matching circuit, and the second end of the fourth capacitor serves as the second output terminal of the input matching circuit.

3. The differential power amplifier as described in claim 1, characterized in that, The amplifier circuit includes a first transistor and a second transistor; the input terminal of the first transistor serves as the first input terminal of the amplifier circuit, the output terminal of the first transistor serves as the first output terminal of the amplifier circuit, and the ground terminal of the first transistor is grounded; the input terminal of the second transistor serves as the second input terminal of the amplifier circuit, the output terminal of the second transistor serves as the second output terminal of the amplifier circuit, and the ground terminal of the second transistor is grounded.

4. The differential power amplifier as described in claim 3, characterized in that, The first transistor and the second transistor are MOSFETs or bipolar transistors.

5. A radio frequency chip, characterized in that, The radio frequency chip includes a differential power amplifier as described in any one of claims 1-4.

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