Analog voltage output method, microcontroller unit and storage medium of dual digital-to-analog converter

Abstract

This application belongs to the field of digital-to-analog converter (DAC) technology, and relates to an analog voltage output method, microcontroller unit, and storage medium for a dual DAC. By employing a preset equivalent digital conversion strategy, the target voltage is decomposed into digital codes from two low-resolution DACs, achieving high-resolution mapping at the digital level. In the calibration process, the system periodically samples the actual sampled voltage and calculates the target error. Combining adjustment calculation strategies and channel selection strategies, the DACs are dynamically adjusted, achieving closed-loop error correction and coarse and fine adjustment division of labor for each cycle. Through continuous iteration, the actual sampled voltage can accurately approximate the target value, and the preset accuracy has been verified. This achieves equivalent high-precision output without requiring a high-resolution DAC, reducing system cost, improving flexibility, and overcoming the nonlinear errors of low-resolution DACs, meeting the high-precision analog output requirements of industrial automation, test and measurement, and precision instruments.

Description

Technical Field

[0001] This application belongs to the field of digital-to-analog converter technology, specifically relating to an analog voltage output method, microcontroller unit, and storage medium of a dual digital-to-analog converter. Background Technology

[0002] In fields such as industrial automation control, test and measurement, precision instruments, and audio processing, high-precision analog voltage signals are often required. The accuracy of the analog voltage output directly affects the measurement accuracy and control performance of the system. Therefore, digital-to-analog converters (DACs), as key components for realizing analog signal output, are widely used in these scenarios.

[0003] In existing technologies, achieving high-precision analog voltage output typically relies on high-resolution DAC chips, such as 16-bit or higher resolution DAC devices. These DACs employ complex internal structure design and precision manufacturing processes to ensure high linearity and output accuracy. However, due to their higher design and manufacturing costs, high-resolution DAC chips are generally significantly more expensive than low- or medium-resolution DAC devices, and there are limitations in terms of device selection, delivery time, power consumption, and packaging.

[0004] In developing this application, the inventors discovered that the prior art suffers from at least the following problems: Firstly, directly using a high-resolution DAC chip significantly increases system cost; secondly, once a DAC device is selected, its resolution and performance characteristics are essentially fixed at the hardware level, limiting the system's flexibility in different application scenarios. Furthermore, in situations where application conditions are limited, suitable high-resolution DAC devices are not readily available, thus restricting the freedom of system design to some extent. Therefore, how to achieve high-precision analog voltage output while controlling system cost has become a pressing problem in the relevant technical field. Summary of the Invention

[0005] To address the aforementioned issues, this application provides an analog voltage output method, microcontroller unit, and storage medium for a dual digital-to-analog converter, thereby effectively improving the accuracy of analog voltage output without relying on high-resolution digital-to-analog converter devices. This reduces system costs and increases application flexibility while ensuring output accuracy.

[0006] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a method for analog voltage output of a dual digital-to-analog converter (DDAC), applied to a DDAC synthesis system. The DDAC synthesis system includes a first DDAC and a second DDAC. The method includes: converting a preset target voltage according to a preset equivalent digital quantity conversion strategy to obtain a first digital code of the first DDAC and a second digital code of the second DDAC; performing a calibration process according to the target voltage until a preset condition is met; wherein the calibration process includes: acquiring the actual sampled voltage in the current cycle, and obtaining the target error of the current cycle according to the target voltage and the actual sampled voltage; when the target error meets a first preset range, performing an adjustment process; wherein the adjustment process includes: obtaining the target adjustment amount of the current cycle according to a preset adjustment amount calculation strategy and the target error; determining the target DDAC from the first DDAC and the second DDAC according to the target error and a preset channel selection strategy; obtaining the target digital code of the target DDAC and the predicted sampled voltage of the next cycle according to the first digital code, the second digital code, and the target adjustment amount; and verifying the actual sampled voltage when the calibration process ends to obtain the target output result.

[0007] In some embodiments, a preset target voltage is converted according to a preset equivalent digital conversion strategy to obtain a first digital code of a first digital-to-analog converter and a second digital code of a second digital-to-analog converter. This includes: calculating the target voltage according to a preset compensation coefficient to obtain a target mapped voltage; performing equivalent numerical conversion on the target mapped voltage to obtain an equivalent digital code; and decomposing the equivalent digital code to obtain the first digital code and the second digital code.

[0008] In some embodiments, decomposing the equivalent digital code to obtain a first digital code and a second digital code includes: judging the equivalent digital code; if the equivalent digital code is not greater than a preset overload threshold, performing remainder and integer division calculations on the equivalent digital code according to a preset proportional coefficient to obtain the first digital code and the second digital code; if the equivalent digital code is greater than the preset overload threshold, obtaining the maximum constraint value of the digital code of the second digital-to-analog converter, and using the maximum constraint value of the digital code as the second digital code; and obtaining the first digital code based on the equivalent digital code and the preset overload threshold.

[0009] In some embodiments, the target adjustment amount for the current period is obtained according to a preset adjustment amount calculation strategy and the target error, including: obtaining the target error of the previous period and the integral cumulative term of the current period; obtaining the target proportional term value based on the proportional term coefficient and the target error of the current period; obtaining the target integral term value based on the integral term coefficient and the integral cumulative term; obtaining the target differential term value based on the differential term coefficient, the target error of the current period and the target error of the previous period; and obtaining the target adjustment amount based on the target proportional term value, the target integral term value and the target differential term value.

[0010] In some embodiments, determining a target digital-to-analog converter (DAC) from a first DAC and a second DAC based on a target error and a preset channel selection strategy includes: judging the target error; when the target error meets a second preset range, using the first DAC as the target DAC; when the target error does not meet the second preset range, using the second DAC as the target DAC.

[0011] In some embodiments, obtaining a target digital code for a target digital-to-analog converter (DAC) and a predicted sampling voltage for the next cycle based on a first digital code, a second digital code, and a target adjustment amount includes: acquiring a first adjustment sensitivity of a first DAC and a second adjustment sensitivity of a second DAC; when the target DAC is a first DAC, obtaining a target digital code based on the first digital code and the target adjustment amount; performing boundary detection processing on the target digital code to obtain the target digital code; obtaining a first voltage change based on the first adjustment sensitivity and the target adjustment amount; obtaining a predicted sampling voltage for the next cycle based on the first voltage change and the actual sampling voltage; when the target DAC is a second DAC, obtaining a target digital code based on the second digital code and the target adjustment amount; performing boundary detection processing on the target digital code to obtain the target digital code; obtaining a second voltage change based on the second adjustment sensitivity and the target adjustment amount; and obtaining a predicted sampling voltage for the next cycle based on the second voltage change and the actual sampling voltage.

[0012] In some embodiments, boundary detection processing is performed on the target digital code to obtain the target digital code, including: obtaining the maximum constraint value of the digital code of the target digital-to-analog converter corresponding to the target digital code; judging the target digital code; when the target digital code meets a third preset range, the target digital code is not updated; when the target digital code does not meet the third preset range and the target digital code is less than zero, the target digital code is set to zero; when the target digital code does not meet the third preset range and the target digital code is greater than the maximum constraint value of the digital code, the maximum constraint value of the digital code is set as the target digital code; when the target digital code meets a fourth preset range, the digital-to-analog converter switching adjustment process is executed.

[0013] In some embodiments, when the target digital code meets a fourth preset range, a digital-to-analog converter (DAC) switching and adjustment process is executed, including: when the target digital code meets the fourth preset range, judging the target error; if the target error is positive, switching the target DAC to obtain the switched target DAC, and adjusting the target digital code corresponding to the target DAC upwards; if the target error is negative, switching the target DAC to obtain the switched target DAC, and adjusting the target digital code corresponding to the target DAC downwards; after the upward or downward adjustment process is completed, clearing the integral accumulation term to zero.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of this application is: to provide a microcontroller unit, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the above-mentioned method.

[0015] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of this application is: to provide a non-volatile computer-readable storage medium that stores computer-executable instructions, which, when executed by a microcontroller unit, cause the microcontroller unit to execute the above-mentioned method.

[0016] Unlike related technologies, this application provides an analog voltage output method, microcontroller unit, and storage medium for a dual digital-to-analog converter. Through a preset equivalent digital conversion strategy, the target voltage is decomposed into digital codes from two lower-resolution DACs, achieving high-resolution mapping at the digital level. Subsequently, in the calibration process, the actual sampled voltage is periodically sampled and the target error is calculated. Combined with a preset adjustment calculation strategy and channel selection strategy, dynamic adjustment of the two DACs is achieved. This process ensures closed-loop correction of the target error in each control cycle, and through the division of labor between coarse and fine adjustments, output accuracy is optimized simultaneously at both the digital and analog levels. Through continuous iterative closed-loop adjustment, the actual sampled voltage can accurately approximate the target voltage, and the preset accuracy is confirmed in the output verification stage, thus achieving equivalent high-precision output without relying on high-resolution DAC devices. Based on this, this application combines low-resolution DACs, dynamic closed-loop calibration, and intelligent channel selection, which not only significantly reduces device costs but also improves system adaptability and flexibility. At the same time, it can overcome the inherent nonlinear error of low-resolution DACs, meet the high-precision analog output requirements in fields such as industrial automation control, test and measurement, and precision instruments, and ensure that the output accuracy reaches or even approaches the level of traditional high-resolution DAC solutions. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 This is a schematic diagram of the structure of a dual digital-to-analog converter synthesis system provided in an embodiment of this application;

[0019] Figure 2 This is a flowchart of an analog voltage output method for a dual digital-to-analog converter provided in an embodiment of this application;

[0020] Figure 3 This is a flowchart of a calibration process provided in an embodiment of this application;

[0021] Figure 4 This is a flowchart of an adjustment process provided in an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of the hardware structure of a microcontroller provided in an embodiment of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application. It should be noted that, unless otherwise specified, the various features in the embodiments of this application can be combined with each other, and all are within the protection scope of this application.

[0024] When an element is described as "connected" to another element, it can be directly connected to the other element, or there may be one or more intervening elements between them.

[0025] The terms "first," "second," "third," "fourth," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," "third," "fourth," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0026] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application.

[0027] Please see Figure 1 , Figure 1 This is a schematic diagram of a dual digital-to-analog converter synthesis system provided in an embodiment of this application. Figure 1 As shown, the dual digital-to-analog converter (DAC) synthesis system 100 includes: a microcontroller unit 10, a first DAC 20, a second DAC 30, a resistor network 40, an operational amplifier 50, and a subsequent amplifier circuit 60. The resistor network 40 includes a first resistor 41 and a second resistor 42. The microcontroller unit 10 is connected to the first DAC 20 and the second DAC 30. The first DAC 20 is also connected to the operational amplifier 50 via the first resistor 41, and the second DAC 30 is also connected to the operational amplifier 50 via the second resistor 42. The operational amplifier 50 is also connected to the subsequent amplifier circuit 60.

[0028] The microcontroller unit 10 is the control core of the dual digital-to-analog converter synthesis system 100. It can be a general-purpose microcontroller (MCU) or an embedded processing unit with computing and control capabilities. In this embodiment, the microcontroller unit 10 receives the digital instruction corresponding to the target voltage, decomposes it into a first digital code of the first digital-to-analog converter 20 and a second digital code of the second digital-to-analog converter 30, and writes the digital code into the corresponding digital-to-analog converter through the built-in DMA (Direct Memory Access) or IO interface. It can be understood that when the first digital-to-analog converter 20 and the second digital-to-analog converter 30 are DAC modules integrated inside the MCU, the decomposed first and second digital codes are transmitted to the first digital-to-analog converter 20 and the second digital-to-analog converter 30 inside the MCU through the built-in DMA, and then the analog voltage is output through the 0 port in the IO interface on the MCU. When the first digital-to-analog converter 20 and the second digital-to-analog converter 30 are independent DAC chips (such as...), ... Figure 1 As shown in the diagram, the MCU transmits the first digital code and the second digital code to the first digital-to-analog converter 20 and the second digital-to-analog converter 30 respectively via I2C and other communication interfaces through its O port. Then, the DAC chip outputs an analog voltage. In addition, the microcontroller unit 10 is also used to execute calibration and adjustment procedures to dynamically adjust the system output voltage to ensure the accuracy and stability of the analog voltage output.

[0029] The first digital-to-analog converter 20 is a digital-to-analog converter in the dual digital-to-analog converter synthesis system 100. It can be a low-resolution digital-to-analog converter, such as a 12-bit voltage output DAC with a reference voltage source of 3.3V. This digital-to-analog converter is used to convert digital signals into corresponding analog voltage signals. In this embodiment, the first digital-to-analog converter 20 receives a first digital code from the microcontroller unit 10 and outputs a corresponding analog voltage signal according to the first digital code. This analog voltage signal is sent to the input terminal of the operational amplifier 50 via the first resistor 41.

[0030] The second digital-to-analog converter 30 is also a digital-to-analog converter in the dual digital-to-analog converter synthesis system 100. Its structure and resolution can be the same as the first digital-to-analog converter 20, for example, both being 12-bit digital-to-analog converters. In this embodiment, the second digital-to-analog converter 30 receives a second digital code from the microcontroller unit 10 and outputs a corresponding analog voltage signal according to the second digital code. This analog voltage signal is connected to the operational amplifier 50 through the second resistor 42.

[0031] The resistor network 40 consists of a first resistor 41 and a second resistor 42, which can be high-precision, low-temperature-coefficient resistors. In this embodiment, the first resistor 41 and the second resistor 42 are connected to the first digital-to-analog converter 20 and the second digital-to-analog converter 30, respectively, and their resistance ratio is set according to a preset weighting relationship, preferably 15:1. It should be noted that the resistance ratio of the first resistor 41 (R1) and the second resistor 42 (R2) provided in this embodiment is not limited to 15:1, and can be any ratio of R1 = (N-1)×R2 (where N is the number of bits of the DAC, and the DAC here specifically refers to the DAC chip corresponding to the high-precision digital-to-analog converter to be simulated by the dual digital-to-analog converter synthesis system 100). Through this resistor network, analog voltage signals with different weights are superimposed at the input of the operational amplifier 50, thereby achieving weighted synthesis in the analog domain, providing a basis for the system to obtain an equivalent high-resolution output.

[0032] Operational amplifier 50 is the analog signal buffering and amplification unit in the dual digital-to-analog converter synthesis system 100. It typically employs a precision operational amplifier device with high input impedance and low output impedance. Operational amplifier 50 can be configured as a voltage follower or a non-inverting amplifier circuit to achieve isolation and buffering of the input signal. In this embodiment, operational amplifier 50 is used to buffer the analog signal superimposed by resistor network 40, preventing the load or subsequent circuits from affecting the weighting ratio, while providing stable output drive capability to ensure the accuracy and stability of the synthesized voltage.

[0033] The post-amplifier circuit 60 is an analog signal conditioning circuit located at the output of the operational amplifier 50, which can be selectively configured according to actual application requirements. This circuit is typically used for amplitude amplification, level matching, or output interface adaptation of analog voltage signals. In this embodiment, the post-amplifier circuit 60 is used to amplify the synthesized voltage output from the operational amplifier 50 to the required final output range to meet the requirements of different application scenarios for output voltage amplitude and driving capability; when the output voltage range of the operational amplifier 50 already meets the usage requirements, the post-amplifier circuit 60 can also be omitted.

[0034] It should be noted that, taking the dual digital-to-analog converter synthesis system 100, where both the first digital-to-analog converter 20 and the second digital-to-analog converter 30 are 12-bit digital-to-analog converters (DACs), as an example, their digital codes range from 0 to 4095, and their output voltages are linearly correlated with their respective digital codes. When the output voltage of the first digital-to-analog converter 20... The output voltage of the second digital-to-analog converter 30 is connected to the summing node of the operational amplifier via R1. When connected to the same summing node via R2, based on Kirchhoff's current law and the virtual open circuit characteristic of the operational amplifier, a current balance equation can be written at the summing node, thus obtaining the superposition relationship of the output voltage with respect to the two input voltages. The circuit superposition principle formula is as follows:

[0035] (1);

[0036] When the resistance ratio of R1 to R2 satisfies the condition R1 = 15R2, formula (1) can be further simplified to formula (2):

[0037] (2);

[0038] Therefore, it can be seen that the output voltage of the second digital-to-analog converter 30 has a larger weight in the synthesis result, while the output voltage of the first digital-to-analog converter 20 has a smaller weight. The two are weighted and superimposed in the analog domain with a fixed ratio.

[0039] Since the output voltage of each 12-bit digital-to-analog converter can be expressed as:

[0040] (3);

[0041] (4);

[0042] Wherein, DAC1 is the first digital code of the first digital-to-analog converter 20, and DAC2 is the second digital code of the second digital-to-analog converter 30. The reference voltage for the digital-to-analog converter, for example, It is 3300mV.

[0043] Therefore, by substituting formulas (3) and (4) into formula (2), we can... The equivalent digital code and the output voltage are uniformly represented as a linear mapping relationship, i.e., formula (5):

[0044] (5);

[0045] The maximum value of the equivalent digital code (15DAC2+DAC1) is... .

[0046] From the above formula (5), it can be seen that the voltage represented by the least significant bit (LSB) of this system is:

[0047] ;

[0048] The LSB of an ideal 16-bit DAC is:

[0049] ;

[0050] By comparison, the two are almost identical in numerical value and are difficult to distinguish in engineering applications.

[0051] It is understandable that by weighting the outputs of two 12-bit analog-to-digital converters in the analog domain with a fixed ratio, and using an equivalent digital code (15DAC2 + DAC1) as the equivalent control quantity in the digital domain, this system can achieve voltage subdivision capability equivalent to an ideal 16-bit analog-to-digital converter in terms of output voltage resolution. Therefore, based on the circuit structure, mathematical mapping relationship, and the derivation of the minimum voltage resolution, it can be proven that this system, in principle, utilizes two 12-bit analog-to-digital converters to achieve analog voltage output accuracy equivalent to that of a 16-bit analog-to-digital converter.

[0052] The implementation process of the analog voltage output method of the dual digital-to-analog converter provided in this application will be described in detail below with reference to specific embodiments.

[0053] Please see Figure 2 , Figure 2 This is a flowchart illustrating an analog voltage output method for a dual-digital-to-analog converter (DADC) according to an embodiment of this application. This method is applied to the microcontroller unit 10 of the aforementioned DADC synthesis system 100. For example... Figure 2 As shown, the method includes steps S11-S13:

[0054] S11: According to the preset equivalent digital conversion strategy, the preset target voltage is converted to obtain the first digital code of the first digital-to-analog converter and the second digital code of the second digital-to-analog converter.

[0055] In this system, the goal of the software algorithm is not simply to map the target voltage to the digital code of two 12-bit DACs, but rather to reproduce the output behavior of an ideal 16-bit digital-to-analog converter at the system level. For an ideal 16-bit DAC, its output voltage and digital code satisfy a linear relationship:

[0056] (6);

[0057] The digital code D of the 16-bit DAC has a value range of 0 to 65535, corresponding to a complete 16-bit quantization space.

[0058] However, this system is actually composed of two 12-bit DACs. The maximum value of the combined digital quantity formed by weighting them in the analog domain is 65520, not 65535. This means that the maximum digital range that the system can physically cover is slightly smaller than the full range of an ideal 16-bit DAC.

[0059] If in software processing directly If the ideal 16-bit DAC is mapped to digital code D and used indiscriminately as a system control variable, the actual maximum output voltage that the system can achieve will be lower than the theoretically expected value when approaching full-scale output. This results in full-scale compression and overall proportional error. This error does not originate from the nonlinearity of the DAC itself, but rather from the proportional mismatch introduced by the inherent difference between the system's joint quantization range (65520) and the ideal quantization range (65535).

[0060] To eliminate this proportional mismatch and ensure that the actual output voltage of the system remains consistent with the output characteristics of an ideal 16-bit DAC throughout the entire range, it is necessary to pre-compensate the equivalent digital quantity at the software level.

[0061] By transforming the above formula (5), we can obtain formula (7):

[0062] (7);

[0063] The equivalent digital code K is the aforementioned 15DAC2+DAC1.

[0064] To make the output of this system equal We can obtain:

[0065] (8);

[0066] Simplifying, we get formula (9):

[0067] (9);

[0068] Understandably, by introducing compensation coefficients 65520 / 65535, the ideal 16-bit digital code D is scaled so that its mapped equivalent digital code K falls precisely within the equivalent digital range that the system can actually cover. In this way, when the system output reaches its maximum equivalent digital code, the corresponding analog voltage can still accurately match the output voltage of the ideal 16-bit DAC at full scale, thus avoiding the accumulation of proportional deviations across the entire range.

[0069] Further, simplifying the compensation coefficients 65520 / 65535 yields the simplified compensation coefficients 4368 / 4369, denoted as... This coefficient mathematically accurately describes the proportional relationship between the actual quantization space of the system and the ideal 16-bit quantization space. By multiplying the target voltage by this compensation coefficient in the software algorithm, forward compensation for the inherent range difference of the system is achieved, ensuring that the output voltage synthesized by the two 12-bit DACs maintains consistency with the ideal 16-bit DAC in terms of overall proportion, endpoint consistency, and resolution. Therefore, introducing a compensation coefficient is a necessary means to ensure that this system can still achieve equivalent 16-bit output accuracy and correct voltage mapping even without a complete 16-bit physical quantization space.

[0070] Specifically, according to a preset equivalent digital conversion strategy, a preset target voltage is converted to obtain a first digital code of the first digital-to-analog converter and a second digital code of the second digital-to-analog converter. This includes: calculating the target voltage according to a preset compensation coefficient to obtain a target mapped voltage; performing equivalent numerical conversion on the target mapped voltage to obtain an equivalent digital code; and decomposing the equivalent digital code to obtain the first digital code and the second digital code.

[0071] The process of decomposing the equivalent digital code to obtain a first digital code and a second digital code includes: judging the equivalent digital code; if the equivalent digital code is not greater than a preset overload threshold, performing remainder and integer division calculations on the equivalent digital code according to a preset proportional coefficient to obtain the first digital code and the second digital code; if the equivalent digital code is greater than the preset overload threshold, obtaining the maximum constraint value of the digital code of the second digital-to-analog converter, and using the maximum constraint value of the digital code as the second digital code; and obtaining the first digital code based on the equivalent digital code and the preset overload threshold.

[0072] Regarding the output voltage of this system after operational amplifier 50 and before subsequent amplifier circuit 60 (i.e., the preset target voltage), multiplied by a compensation coefficient Obtain the target mapped voltage This is a mathematical compensation that maps the target voltage to the actual output range of the system, and its calculation formula is as follows:

[0073] (10);

[0074] Understandably, the maximum theoretical voltage produced by the dual digital-to-analog converter synthesis system 100 is slightly lower than the maximum value of an ideal 16-bit DAC. To compensate, the target voltage is first slightly reduced proportionally (4368 / 4369 ≈ 0.99977). This compensation factor... This precisely describes the relationship between this system (maximum output of 65,520 digital units) and an ideal 16-bit system (65,535 units). This step ensures that the voltage is exactly 3.3V when the system output reaches its maximum value.

[0075] Subsequently, based on formulas (7) and (10), the formula for calculating the equivalent digital code K can be obtained:

[0076] (11);

[0077] The round() function rounds the integer value to the nearest integer.

[0078] When K ≤ 61425 (preset overload threshold), DAC2 = K / 15, DAC1 = K%15 (remainder). Here, 15 (preset scaling factor) is obtained based on the resistance ratio of R1 and R2 mentioned above. Since the maximum range of digital codes output by a single 12-bit DAC (maximum digital code constraint value) is 4095, we know that 61425 = 15. 4095 represents the maximum value that the second digital-to-analog converter can contribute under unloaded (unsaturated) conditions. It's understandable that if K ≤ 61425, it means that both DACs can operate within their normal range and can be calculated within that range.

[0079] When K > 61425, it means that even if the second digital-to-analog converter is turned up to its maximum (4095), it is not enough, and it needs to enter the saturation range for calculation, allowing the first digital-to-analog converter to help fill the remaining part. At this time, DAC2 = 4095, DAC1 = K - 61425.

[0080] By employing a pre-defined equivalent digital-to-digital conversion strategy, the target voltage is precisely mapped to the digital codes of two lower-resolution DACs, thereby reproducing the output characteristics of an ideal 16-bit DAC at the system level. In this process, a compensation coefficient is introduced. (4368 / 4369) effectively solves the problem of full-scale proportional deviation caused by the actual quantization range (65520) being slightly lower than the ideal 16-bit quantization range (65535), ensuring that the output voltage remains consistent with the theoretical target across the entire range. Through the integer division and remainder decomposition strategy of the equivalent digital code, and the limiting processing for overload conditions, the output weights of DAC1 and DAC2 can be reasonably allocated, achieving a division of labor between fine-tuning and coarse-tuning. This allows the two 12-bit DACs to accurately approximate the target 16-bit output after combination. This approach not only ensures the linearity and endpoint consistency of the full-range output but also eliminates the proportional error caused by hardware range differences, providing a reliable digital foundation for subsequent closed-loop calibration and dynamic adjustment. Thus, high-precision, low-cost, and stable analog voltage output is achieved without relying on high-resolution DAC devices.

[0081] S12: Perform the calibration process according to the target voltage until the preset conditions are met.

[0082] Please see Figure 3 , Figure 3 This is a flowchart of a calibration process provided in an embodiment of this application. For example... Figure 3 As shown, the calibration process includes steps S121-S122:

[0083] S121: In the current cycle, acquire the actual sampled voltage, and based on the target voltage and the actual sampled voltage, obtain the target error for the current cycle.

[0084] Within each control cycle, the system first acquires the current actual sampled voltage through a high-precision analog-to-digital converter (ADC). The voltage is an analog signal processed by operational amplifier 50 and subsequent amplifier circuit 60. During this process, the value measured by the ADC may deviate from the actual physical voltage due to factors such as range error, DAC gain error, resistor network deviation, and operational amplifier bias. Therefore, directly performing closed-loop control based on the sampled voltage will lead to the accumulation of output error.

[0085] To address this issue, the system undergoes an initial calibration before first use. This is achieved by measuring the actual output voltage using a high-precision 8.5-digit digital multimeter. The voltage value is then transmitted to the microcontroller unit 10 (MCU) via serial port. The MCU will then measure the voltage value. The voltage obtained by its ADC sampling Perform ratio calculations to obtain the calibration coefficient. The data is then stored in EEPROM. During subsequent operation, the system collects... By multiplying by this calibration factor To obtain accurate actual sampling voltage Understandably, the significance of initial calibration lies in eliminating the gain deviation of the ADC and DAC themselves, as well as the operational amplifier bias and resistor network errors, so that the closed-loop control is based on the accurate perception of the real physical voltage, thereby ensuring the accuracy of subsequent dynamic adjustment and the high-precision output capability of the system.

[0086] In each control cycle t, the MCU determines the target voltage. With actual sampling voltage The difference between them is used to calculate the target error for the current period:

[0087] (12);

[0088] The system control cycle is typically set to 1 millisecond, and this time parameter is determined based on a comprehensive optimization of the system response characteristics and processor capabilities.

[0089] Understandably, this target error will serve as the basis for closed-loop regulation, used for subsequent adjustment calculations and channel selection. Through periodic sampling, error calculation, and closed-loop correction, the system can continuously correct its output during dynamic operation, ensuring that the combined output voltage of the first digital-to-analog converter and the second digital-to-analog converter gradually approaches the target value in each control cycle, significantly improving the system's analog output accuracy and linearity.

[0090] S122: When the target error meets the first preset range, execute the adjustment process.

[0091] Please see Figure 4 , Figure 4 This is a flowchart of an adjustment process provided in an embodiment of this application. For example... Figure 4 As shown, the adjustment process includes steps S1221-S1223:

[0092] S1221: Based on the preset adjustment calculation strategy and target error, obtain the target adjustment amount for the current cycle.

[0093] The process of obtaining the target adjustment amount for the current period based on the preset adjustment amount calculation strategy and target error includes: obtaining the target error of the previous period and the integral cumulative term of the current period; obtaining the target proportional term value based on the proportional term coefficient and the target error of the current period; obtaining the target integral term value based on the integral term coefficient and the integral cumulative term; obtaining the target differential term value based on the differential term coefficient, the target error of the current period and the target error of the previous period; and obtaining the target adjustment amount based on the target proportional term value, the target integral term value and the target differential term value.

[0094] Dead zone detection is performed on the target error. The dead zone threshold is ±0.1mV. The detection logic is as follows:

[0095] When the target error meets the first preset range (|e(t)|>0.1mV), it is determined that the target error has exceeded the allowable dead zone range, and the system will immediately start the subsequent adjustment process.

[0096] When the target error does not meet the first preset range, i.e., |e(t)|≤0.1mV (i.e., the preset condition of the calibration process), the system is determined to have entered the steady-state dead zone. At this point, the calibration process is terminated. This mechanism aims to completely eliminate the micro-oscillations at the steady-state point caused by measurement noise or minor circuit disturbances, thereby improving system energy efficiency and extending actuator lifespan.

[0097] When the adjustment process begins, the system starts calculating the target adjustment amount required for the current cycle. The calculation formula is:

[0098] (13);

[0099] To ensure the smoothness of the adjustment process, the target adjustment amount is limited using the clip function. This limit value (±5 LSB) is determined based on a combination of DAC adjustment resolution and system inertia characteristics, and is not specified here. The target adjustment amount calculation process is divided into target proportional term value. Calculate the value of the target integral term. Calculation and target differential value The calculation consists of three parts. The formula is as follows:

[0100] (14);

[0101] (15);

[0102] (16);

[0103] in, This is the proportionality coefficient. The coefficient of the integral term, The coefficients of the differential term, The target error for the current period, This represents the target error from the previous period. This is the cumulative term for integration.

[0104] In the calculation of the target integral term value, the integral term is used to eliminate steady-state error, and its update rule is as follows:

[0105] (17);

[0106] To prevent integral saturation, Apply strict amplitude limits:

[0107] (18);

[0108] Here, clip(x, a, b) is a clipping function that ensures that the variable x is constrained within the interval [a, b]. It should be noted that [-50, +50] can be adaptively set according to the actual situation and is not limited here.

[0109] A sophisticated target adjustment calculation strategy enables high-precision dynamic closed-loop control of the output voltage of a dual digital-to-analog converter (DAC). Specifically, the system first calculates the target proportional term P(t), target integral term I(t), and target derivative term D(t) based on the target error e(t) of the current cycle, the error e(t-1) of the previous cycle, and the integral accumulation term I_accum(t). The target proportional term rapidly responds to error changes, providing immediate correction of output deviations; the target integral term eliminates steady-state errors by accumulating historical errors, ensuring long-term output accuracy; and the target derivative term provides predictive compensation for the rate of error change, improving system response speed and suppressing overshoot. During the target adjustment generation process, a dead-zone judgment mechanism is introduced. When the target error is not greater than the dead-zone threshold, the adjustment operation of the current cycle is terminated, thus avoiding ineffective adjustments caused by measurement noise or minor circuit disturbances, reducing system energy consumption, and extending the lifespan of DAC and amplifier components. Furthermore, to ensure the smoothness and safety of the adjustment process, the target adjustment... (t) A limiting process (±5 LSB) is employed to prevent excessive adjustment within a single cycle from causing system oscillation or overshoot. Simultaneously, the integral accumulation term I_accum(t) is also limited (±50) to avoid long-term error accumulation caused by integral saturation. Based on this, through the organic combination of proportional-integral-derivative term calculation, dead-zone judgment, and limiting processing, fine closed-loop regulation of the output voltage is achieved. This ensures a balance between dynamic response speed, steady-state accuracy, and hardware safety, thereby significantly improving the system's output accuracy, reliability, and stability, meeting the requirements of high-precision analog control scenarios.

[0110] S1222: Determine the target digital-to-analog converter from the first digital-to-analog converter and the second digital-to-analog converter based on the target error and the preset channel selection strategy.

[0111] The process of determining the target digital-to-analog converter (DAC) from the first DAC and the second DAC based on the target error and a preset channel selection strategy includes: judging the target error; when the target error meets a second preset range, using the first DAC as the target DAC; and when the target error does not meet the second preset range, using the second DAC as the target DAC.

[0112] In each control cycle, the system first calculates the target error e(t) based on step S121, provided that the error exceeds the steady-state dead zone, i.e., |e(t)|>0.1 mV. This ensures that the adjustment action is initiated only when necessary, avoiding ineffective adjustment caused by measurement noise or minor disturbances. Under this condition, the system further compares the target error with a preset channel selection threshold (e.g., 3 mV) to distinguish between adjustment requirements for small and large errors.

[0113] If the target error of the current cycle meets the second preset range (0.1 mV < |e(t)| < 3 mV), the system will select the first digital-to-analog converter (DAC) as the target DAC and keep the second DAC as a non-adjustable channel. The first DAC has a smaller weight in the system's superimposed output, and its adjustment step is small (i.e., the first adjustment sensitivity is about 0.050 mV / LSB), which is suitable for fine-tuning the output, thereby achieving high-precision steady-state locking and avoiding overshoot or steady-state oscillation. Conversely, when the target error does not meet the second preset range, i.e., |e(t)| ≥ 3 mV, the system will select the second DAC as the target DAC, and the first DAC will temporarily stop adjusting. The second DAC has a dominant weight in the synthesized output, and its adjustment step is larger (i.e., the second adjustment sensitivity is about 0.755 mV / LSB), which can quickly reduce large deviations and achieve the function of quickly approaching the target voltage. The selection result is directly used for the target digital code calculation in the subsequent step S1223, so that the subsequent adjustment amount only acts on the selected DAC, thereby giving full play to the advantages of the two DACs in the two stages of "coarse adjustment and fast approach" and "fine adjustment and high-precision locking".

[0114] Through an intelligent channel selection strategy, the system output adjustment achieves both precision and efficiency. When the actual sampled voltage deviates from the target voltage and exceeds the dead zone threshold (|e(t)|>0.1 mV), the appropriate adjustment channel is automatically selected based on the error magnitude: when the error magnitude is small (0.1 mV<|e(t)|<3 mV), a low-weight first digital-to-analog converter is selected for fine-tuning, resulting in a small adjustment step and high-precision locking of the target voltage, avoiding steady-state oscillations caused by excessive DAC step size; while when the error magnitude is large (|e(t)|≥3 mV), a high-weight second digital-to-analog converter is selected for rapid adjustment, with a larger step size, which can quickly reduce the deviation and achieve rapid approach to the target voltage. This dynamic division of labor of "coarse adjustment + fine adjustment" not only significantly improves the system's response speed and steady-state accuracy, but also naturally utilizes the weight difference advantage of the dual DAC hardware to achieve efficient, smooth, and controllable output adjustment, while effectively preventing uneven adjustment or oscillations caused by the limitations of a single DAC hardware characteristic, thereby improving the overall output stability and reliability while ensuring dynamic performance.

[0115] S1223: Based on the first digital code, the second digital code, and the target adjustment amount, obtain the target digital code of the target digital-to-analog converter and the predicted sampling voltage for the next cycle.

[0116] The process of obtaining the target digital code of the target digital-to-analog converter (DAC) and the actual sampling voltage for the next cycle based on the first digital code, the second digital code, and the target adjustment amount includes: acquiring the first adjustment sensitivity of the first DAC and the second adjustment sensitivity of the second DAC; when the target DAC is the first DAC, obtaining the target digital code based on the first digital code and the target adjustment amount; performing boundary detection processing on the target digital code to obtain the target digital code; obtaining the first voltage change based on the first adjustment sensitivity and the target adjustment amount; obtaining the predicted sampling voltage for the next cycle based on the first voltage change and the actual sampling voltage; when the target DAC is the second DAC, obtaining the target digital code based on the second digital code and the target adjustment amount; performing boundary detection processing on the target digital code to obtain the target digital code; obtaining the second voltage change based on the second adjustment sensitivity and the target adjustment amount; and obtaining the predicted sampling voltage for the next cycle based on the second voltage change and the actual sampling voltage.

[0117] The process of performing boundary detection on the target digital code to obtain the target digital code includes: obtaining the maximum constraint value of the digital code of the target digital-to-analog converter corresponding to the target digital code; judging the target digital code; when the target digital code meets the third preset range, not updating the target digital code; when the target digital code does not meet the third preset range and the target digital code is less than zero, setting the target digital code to zero; when the target digital code does not meet the third preset range and the target digital code is greater than the maximum constraint value of the digital code, setting the maximum constraint value of the digital code as the target digital code; and when the target digital code meets the fourth preset range, executing the digital-to-analog converter switching adjustment process.

[0118] Specifically, when the target digital code meets the fourth preset range, a digital-to-analog converter (DAC) switching and adjustment process is executed, including: when the target digital code meets the fourth preset range, judging the target error; if the target error is positive, switching the target DAC to obtain the switched target DAC, and adjusting the target digital code corresponding to the target DAC upwards; if the target error is negative, switching the target DAC to obtain the switched target DAC, and adjusting the target digital code corresponding to the target DAC downwards; after the upward or downward adjustment process is completed, the integral accumulation term is cleared to zero.

[0119] First, the system acquires the first digital code DAC1 of the first digital-to-analog converter and the second digital code DAC2 of the second digital-to-analog converter in the current control cycle, as well as the target adjustment amount Δ(t), and processes it according to the target digital-to-analog converter (first digital-to-analog converter or second digital-to-analog converter) determined in S1222 above. To achieve high-precision output, each DAC has a different adjustment sensitivity: the first digital-to-analog converter corresponds to a low-weight, fine-tuning mode, and its first adjustment sensitivity is approximately 0.050 mV / LSB; the second digital-to-analog converter corresponds to a high-weight, coarse-tuning mode, and its second adjustment sensitivity is approximately 0.755 mV / LSB.

[0120] When the target digital-to-analog converter is the first digital-to-analog converter, the system combines the DAC1 of the current first digital-to-analog converter with the target adjustment amount to calculate the target digital code. The calculation formula is as follows:

[0121] (19);

[0122] Here, X is 1 or 2, corresponding to DAC1 or DAC2 respectively. It can be understood that after determining the target digital-to-analog converter, the corresponding target digital code is updated through the target adjustment amount.

[0123] Subsequently, the system performs boundary detection to ensure that the target digital code is within a legal range. Understandably, the target digital code must be between [0, 4095] (the third preset range). If the target digital code itself is within the range of [0, 4095], its original value remains unchanged. If the target digital code is less than 0, it is set to zero; if the target digital code is greater than 4095, it is set to the maximum constraint value of the target digital-to-analog converter (DAC), 4095 (when it is a 12-bit DAC). This boundary detection logic ensures that the algorithm will not produce illegal outputs under computational anomalies or environmental interference, thereby protecting hardware security.

[0124] After completing boundary detection, the system, in conjunction with the first adjustment sensitivity of the first digital-to-analog converter, maps the target adjustment amount to a first voltage change ΔV1, and compares it with the actual sampled voltage. By superimposing the samples, the predicted sampling voltage for the next control cycle is obtained. This calculation provides a reference voltage for the next cycle of closed-loop control, enabling the controller to accurately assess errors and make continuous adjustments.

[0125] When the target digital-to-analog converter (DAC) is the second DAC, the processing flow is similar to that of the first DAC: the system first calculates the target digital code based on the digital code (DAC2) of the second DAC and the target adjustment amount, executes the same boundary detection logic (ensuring that the digital code is within the range of [0, 4095]), then converts Δ(t) into the second voltage change amount ΔV2 based on the second adjustment sensitivity, and superimposes it with the current actual sampling voltage to obtain the predicted sampling voltage for the next cycle. .

[0126] Furthermore, when the target digital code meets the fourth preset range, the digital-to-analog converter (DAC) switching adjustment process is executed. It is understood that when the target digital code still reaches an extreme value after boundary detection (i.e., the DAC reaches its upper or lower limit), and the target error still exceeds the dead-zone threshold (i.e., the fourth preset range), the system will automatically switch the adjustment channel. For example, when the first DAC has reached its lower limit and the target error is negative (meaning the output voltage needs to be further reduced), the system will switch to the second DAC for downward adjustment. Subsequently, during fine-tuning in the fine-tuning mode after downward adjustment, the integral accumulation term I_accum(t) needs to be cleared. It is understood that in this embodiment, the coarse-tuning mode is when the second DAC is used as the target DAC for target digital-to-analog converter adjustment; the fine-tuning mode is when the first DAC is used as the target DAC for target digital-to-analog converter adjustment. This switching process ensures that the system can continue to effectively adjust the output under any boundary conditions, preventing adjustment stagnation or oscillation.

[0127] By precisely updating and protecting the target digital code of the target digital-to-analog converter (DAC), the core guarantee function of high-precision closed-loop output control is achieved. First, based on the calculated target adjustment amount and adjustment sensitivity, the target adjustment amount is accurately mapped to the DAC's digital code. Combined with the current actual sampled voltage, the predicted sampled voltage for the next cycle is calculated, providing a reliable reference for closed-loop control and enabling the system to continuously and accurately approach the target voltage. This process ensures that the target error is corrected in a timely manner within each control cycle, improving the system's dynamic response capability and steady-state accuracy. Second, through strict boundary detection, the DAC's digital code is limited to the effective range [0, 4095], and the adjustment mode is automatically switched when the boundary is reached, avoiding illegal outputs caused by algorithm anomalies or hardware interference, ensuring hardware safety and system stability. Finally, this step fully leverages the advantages of the dual-DAC architecture, using the high-weight DAC for rapid coarse adjustment and the low-weight DAC for fine fine adjustment, naturally dividing the adjustment process into two stages: "rapid approach" and "precise locking," achieving high-resolution, low-oscillation, and high-efficiency analog voltage output. Based on this, step S1223 not only ensures the safety and reliability of the system output, but also significantly improves the dynamic adjustment performance and steady-state locking accuracy, enabling the system to achieve high-precision output equivalent to a 16-bit DAC in complex working environments.

[0128] S13: When the calibration process is completed, the actual sampled voltage is verified to obtain the target output result.

[0129] After completing the entire closed-loop calibration iteration, the system first acquires the final DAC output value for the current cycle, including the digital codes of the first digital-to-analog converter and the second digital-to-analog converter (DAC1 and DAC2). For example, the adjusted final value of DAC2 is 2907 (initial value 2911, reduced by 4 LSBs), while the final value of DAC1 remains at 10. The system determines the output state of each DAC by reading the final digital codes in the DAC registers, providing basic data for subsequent output verification.

[0130] Subsequently, the final actual sampling voltage is sampled using high-precision measuring instruments. For example, the measured final actual sampling voltage... The value is 2199.95 mV. To obtain the final actual output voltage of the system... Furthermore, the gain G of the subsequent amplifier circuit must be considered (e.g., G is 1.5). The system multiplies the final actual sampled voltage by the gain of the subsequent amplifier stage to obtain the final output voltage:

[0131] ;

[0132] Finally, the system compares the final actual output voltage with the ideal final output voltage (2200mV × 1.5 = 3300mV) obtained after the target voltage is amplified by the gain G of the subsequent amplifier circuit, and calculates the target output result (absolute error and relative error). The absolute error is +0.075 mV, and the relative error is 0.0023%. This verification process quantifies the accuracy of the closed-loop regulation, confirming that after multi-cycle iterative adaptive closed-loop calibration, the system's error is controlled at the microvolt level under high-precision measurement conditions, thus verifying the effectiveness of the dual-DAC combination and intelligent regulation strategy.

[0133] By reading the final digital code and combining it with the actual sampled voltage measured by a high-precision measuring instrument, the system can quantify the contribution of each DAC to the total output. Simultaneously, considering the gain of the subsequent amplifier circuit, it achieves accurate calculation and confirmation of the final actual output voltage. Based on this, the system further calculates the absolute and relative errors, thereby verifying the accuracy and stability of the closed-loop calibration strategy across the entire range. This process not only confirms that the final actual output voltage maintains a high degree of consistency with the theoretical target within the microvolt range, but also demonstrates the synergistic effect of functional modules such as closed-loop iterative adjustment, boundary protection, and intelligent channel selection. This ensures that the system achieves an equivalent 16-bit high-precision output without relying on a high-resolution DAC, providing a reliable high-precision analog signal output guarantee for applications such as industrial automation, test and measurement, and precision instruments.

[0134] The implementation process of the analog voltage output method of the dual digital-to-analog converter provided in this application embodiment will be described below with reference to a specific example.

[0135] For example, the initial system parameters are set as follows: ideal final output voltage of the system. The voltage is 3300mV; the gain G of the subsequent amplifier circuit is 1.5; therefore, the target voltage (the target voltage before amplification) is... =3300mV / 1.5 =2200mV; Both the first and second digital-to-analog converters are 12-bit DACs (corresponding to code value range 0 to 4095), and their reference voltage... All values ​​are 3300mV; the resistance ratio of the first resistor to the second resistor is 15:1; the control cycle is set to 1 millisecond; the dead zone threshold is set to ±0.1mV; the channel selection threshold is set to 3mV; the proportional coefficient Kp is 0.8; the integral coefficient Ki is 0.1; the derivative coefficient Kd is 0.05; the integral term limit range is [-50, +50]; the single target adjustment limit is ±5 LSB.

[0136] First, according to the preset equivalent digital conversion strategy, the preset target voltage is converted to obtain the first digital code of the first digital-to-analog converter and the second digital code of the second digital-to-analog converter. It can be understood that, according to formulas (10) and (11), K=43660 can be obtained.

[0137] Since K=43660≤61425, calculate: DAC2 = 43660 / 15 = 2911, DAC1 = 43660 % 15 =10.

[0138] When the control cycle is the first cycle (t=1), the actual sampled voltage is obtained. The value is 2203mV; the target error is calculated as: e(1) = 2200mV - 2203mV = -3mV; at this time, |e(1)| = 3mV > 0.1mV, the target error exceeds the dead zone threshold, and the adjustment process is started.

[0139] Subsequently, the target adjustment amount is calculated. Among them, the integral cumulative term I_accum(0) = 0, the target error of the previous cycle e(0) = 0; P(t) = Kp × e(1) = 0.8 × (-3) = -2.4; I_accum(1) = I_accum(0) + e(1) = 0 + (-3) = -3; the integral term limit check is performed: -3 is within the range of [-50, +50], and is judged to be valid; I(1) = 0.1 × (-3) = -0.3; D(1) = 0.05 × [(-3) - 0] = -0.15; (1) = clip((-2.4+(-0.3)+(-0.15)),-5,+5) = clip(-2.85, -5, +5) = -2.85, rounded to -3 LSB.

[0140] At this point, |e(1)| = 3 mV. According to the preset channel selection strategy, it can be known that: when |e(t)| ≥ 3 mV, the large error mode is selected, and DAC2 (coarse adjustment mode) is adjusted; when |e(t)| < 3 mV, the small error mode is selected, and DAC1 (fine adjustment mode) is adjusted. In this period, |e(1)| = 3 mV, satisfying the condition |e| ≥ 3 mV, DAC2 is adjusted. Calculate the new DAC2 code value: = 2911 + (-3) = 2908. Boundary check: 2908 is in the range [0, 4095], valid; Update DAC output: Set DAC2 = 2908, DAC1 remains at 10.

[0141] Finally, the system response prediction is as follows: DAC2 adjustment amount: -3 LSB, DAC2 adjustment sensitivity: 0.755 mV / LSB; theoretical change in output voltage (second voltage change): ΔV = -3 × 0.755 ≈ -2.265 mV; predicted new voltage: 2203mV - 2.265 mV ≈ 2200.735 mV (predicted sampling voltage for the next cycle).

[0142] When the control cycle is the second cycle (t=2), the actual sampled voltage is obtained. = 2200.7 mV; Calculate the target error: e(2) = 2200mV - 2200.7 mV = -0.7 mV; At this time, |e(2)| = 0.7mV > 0.1mV, the target error exceeds the dead zone threshold, and the adjustment process is started.

[0143] Subsequently, the target adjustment amount is calculated. Among them, the cumulative term of the previous cycle I_accum(1) = -3, the error of the previous cycle e(1) = -3; P(t) = 0.8 × (-0.7) = -0.56; I_accum(2) = I_accum(1) + e(2) = -3 + (-0.7) = -3.7; the limit check of the integral term is performed: -3.7 is within the range of [-50, +50], and is deemed valid; I(2) = 0.1 × (-3.7) = -0.37; D(2) = 0.05 × [(-0.7) - (-3)] = 0.05 × 2.3 = 0.115; (2) = clip(-0.815, -5, +5) = -0.815, rounded to -1 LSB.

[0144] At this point, |e(2)| = 0.7 mV. According to the preset channel selection strategy, it can be known that: when |e(t)| ≥ 3 mV, the large error mode is selected, and DAC2 (coarse adjustment mode) is adjusted; when |e(t)| < 3 mV, the small error mode is selected, and DAC1 (fine adjustment mode) is adjusted. Therefore, DAC1 is selected for adjustment. Calculate the new DAC1 code value: = 10 + (-1) = 9. Boundary check: 9 is in the range [0, 4095], valid; Update DAC output: Set DAC1 = 9, DAC2 remains at 2908.

[0145] Finally, the system response prediction is as follows: DAC1 adjustment amount: -1 LSB, DAC1 adjustment sensitivity: 0.050 mV / LSB; theoretical output voltage change (first voltage change): ΔV = -1 × 0.050 ≈ -0.050 mV; predicted new voltage: 2200.7 mV - 0.050 mV ≈ 2200.65 mV (predicted sampling voltage for the next cycle).

[0146] When the control cycle is the 3rd cycle (t=3), the actual sampled voltage is obtained. The target value is 2200.65 mV; the target error is calculated as: e(3) = 2200mV - 2200.65 mV = -0.65mV; at this time, |e(3)| = 0.65mV > 0.1mV, the target error exceeds the dead zone threshold, and the adjustment process is started.

[0147] Subsequently, the target adjustment amount is calculated. Among them, the cumulative term of the previous cycle I_accum(2) = -3.7, the error of the previous cycle e(2) = -0.7; P(t) = 0.8 × (-0.65) = -0.52; I_accum(3) = I_accum(2) + e(3) = -3.7 + (-0.65) = -4.35; the limit check of the integral term is performed: -4.35 is within the range of [-50, +50], and is judged to be valid; I(3) = 0.1 × (-4.35) = -0.435; D(3) = 0.05 × [(-0.65) - (-0.7)] = 0.05 × 0.05 = 0.0025; (3) = clip(-0.9525, -5, +5) = -0.9525, rounded down to -1 LSB.

[0148] At this point, |e(3)| = 0.65 mV. When |e(t)| < 3 mV, select the small error mode and adjust DAC1. Calculate the new DAC1 code value: = 9 + (-1) = 8. Boundary check: 8 is within the range [0, 4095], valid; Update DAC output: Set DAC1 = 8, DAC2 remains at 2908.

[0149] Finally, the system response prediction is as follows: DAC1 adjustment amount: -1 LSB, DAC1 adjustment sensitivity: 0.050 mV / LSB; theoretical output voltage change (first voltage change): ΔV = -1 × 0.050 ≈ -0.050 mV; predicted new voltage: 2200.65 mV - 0.050 mV ≈ 2200.60 mV (predicted sampling voltage for the next cycle).

[0150] By continuing to adjust using the same method, the error will decrease by approximately 0.05 mV each time.

[0151] 4th cycle: The target error is -0.60 mV. Adjust DAC1 to 7. The predicted sampling voltage is 2200.55 mV. The actual sampling voltage is 2200.55 mV. e(4) = 2200 - 2200.55 = -0.55 mV. |e(4)| = 0.55 mV>0.1 mV. The target error still exceeds the dead zone threshold. Continue to adjust.

[0152] Cycle 5: Target error is -0.55 mV, adjust DAC1 to DAC6, predicted sampling voltage 2200.50 mV...;

[0153] Cycle 6: Target error is -0.50 mV, adjust DAC1 to DAC5, predicted sampling voltage 2200.45 mV...;

[0154] 7th cycle: Target error is -0.45 mV, adjust DAC1 to 4, predicted sampling voltage 2200.40 mV...;

[0155] Cycle 8: Target error is -0.40 mV, adjust DAC1 to 3, predicted sampling voltage 2200.35 mV...;

[0156] 9th cycle: Target error is -0.35 mV, adjust DAC1 to DAC2, predicted sampling voltage 2200.30 mV...;

[0157] Cycle 10: Target error is -0.35 mV, adjust DAC1 to 1, predicted sampling voltage 2200.25 mV...;

[0158] Cycle 11: The target error is -0.35 mV. Adjust DAC1 to 0. The predicted voltage is 2200.20 mV. e(11) = 2200 - 2200.20 = -0.20 mV. |e(11)| = 0.20 mV > 0.1 mV. The target error still exceeds the dead zone threshold and needs to be adjusted further.

[0159] At this point, DAC1 has been adjusted to 0 and cannot be reduced further, but it has not reached the dead zone (0.1mV). In this case, e(11) is negative, indicating that the output voltage is greater than the target voltage, and the output needs to be adjusted downward. That is, in the new cycle (12th cycle), DAC2 is reduced by one level. Calculate the new DAC2 code value: = 2908 + (-1) = 2907, predict the new voltage 2200.20 mV - 0.755 mV ≈ 2199.45 mV.

[0160] Cycle 13: Acquire actual sampling voltage The value is 2199.45 mV; the target error is calculated as: e(13) = 2200mV - 2199.45mV = 0.55mV; at this time, |e(13)| = 0.55mV > 0.1mV, the target error exceeds the dead zone threshold, and the adjustment process is started.

[0161] Subsequently, the target adjustment amount is calculated. Among them, the cumulative term of the previous cycle I_accum(12) = -7.95, the error of the previous cycle e(12) = -0.2; P(t) = 0.8 × (0.55) = 0.44; I_accum(13) = 0 (it should be noted that the cumulative term of the integral is cleared here, and the integral is recalculated. It can be understood that the fine adjustment has reached 0, and at this time, the fine adjustment needs to start the integration again); the limit check of the integral term is performed: 0 is within the range of [-50, +50], which is considered valid; I(13) = 0.1 × 0 = 0; D(13) = 0.05 × [(0.55) - (-0.2)] = 0.05 × 0.05 = 0.0375; (13) = clip(0.4775, -5, +5) = 0.4775, rounded to 1 LSB.

[0162] At this point, |e(13)| = 0.55 mV. According to the preset channel selection strategy, when |e(t)| < 3 mV, the small error mode is selected, and DAC1 is adjusted. Calculate the new DAC1 code value: = 0 + (1) = 1. Boundary check: 1 is in the range [0,4095], which is valid; Update DAC output: Set DAC1 = 1, and keep DAC2 at 2907.

[0163] Finally, the system response prediction is as follows: DAC1 regulation amount: 1 LSB, DAC1 regulation sensitivity: 0.050 mV / LSB; theoretical change in output voltage (first voltage change): ΔV = 1 × 0.050 ≈ 0.050 mV; predicted new voltage: 2199.45mV + 0.050 mV ≈ 2199.5 mV (predicted sampling voltage for the next cycle).

[0164] After multiple iterative adjustments, the final adjustment result was DAC2 at 2907 (initially 2911, reduced by 4 LSBs) and DAC1 at 10 (initially 10). Subsequently, the final actual sampling voltage was sampled using a high-precision measuring instrument. For example, the measured final actual sampling voltage... The voltage is 2199.95 mV. To obtain the final actual output voltage of the system, the gain G of the subsequent amplifier circuit (e.g., G = 1.5) also needs to be considered. The system multiplies the final actual sampled voltage by the gain of the subsequent amplifier, resulting in a final actual output voltage of 3299.925 mV. Finally, the system compares the final actual output voltage with the system's ideal final output voltage. The absolute error and relative error were calculated by comparing the value to (3300mV). The absolute error was +0.075 mV, and the relative error was 0.0023%. After multiple cycles of adaptive closed-loop calibration, the error was controlled at the microvolt level under high-precision measurement conditions, thus verifying the effectiveness of the dual DAC combination and intelligent adjustment strategy.

[0165] It should be noted that the actual sampled voltage of the current cycle in the above examples looks the same as the predicted sampled voltage calculated at the end of the previous cycle. This is to facilitate the description of the implementation process of this method. In practical applications, the actual sampled voltage is the real voltage sampled back by the internal ADC. Based on the actual sampled voltage, the target error is obtained and then effectively adjusted.

[0166] It should be noted that the first digital-to-analog converter (DAC) and the second DAC provided in the embodiments of this application can be DACs of different resolutions (e.g., a 12-bit DAC and a 10-bit DAC), and are not limited to both being 12-bit DACs. It is understood that the method provided in the embodiments of this application can be naturally derived from the method for combining DACs of different resolutions. Furthermore, a more complex R-2R ladder network or other voltage divider network can be used to replace the two resistors in this embodiment to achieve different weighting or higher accuracy. The first DAC and the second DAC can be voltage-output DACs or current-output DACs (requiring an IV conversion circuit), as long as their outputs can be proportionally superimposed. The operational amplifier can also be replaced with an instrumentation amplifier or other amplifier circuits with high input impedance to meet specific common-mode rejection or differential input requirements.

[0167] This application provides a method for analog voltage output using a dual digital-to-analog converter (DAC). By mapping the target voltage to an equivalent high-resolution digital quantity in the digital domain and employing a collaborative output method using two low-resolution DACs, combined with precise weighted superposition, voltage sampling calibration, and adaptive closed-loop control, an equivalent 16-bit or even higher precision analog voltage output is achieved without relying on high-resolution DAC devices. This method fully utilizes software algorithms to allocate, calibrate, and dynamically correct the output voltage, enabling the two low-cost DACs to exhibit quantization characteristics and output accuracy close to those of a high-resolution DAC at the system level. This significantly reduces the system BOM cost and improves the cost-effectiveness of the solution. Simultaneously, this method uses software as the core control mechanism, allowing for flexible adaptation to DACs and resistor networks with different accuracy levels, temperature characteristics, and device aging states by adjusting calibration parameters, control strategies, and error compensation models. This significantly enhances the system's adaptability and scalability. By introducing software calibration and closed-loop adjustment mechanisms, this method effectively compensates for the differential and integral nonlinear errors of the DAC itself, resistor ratio deviations, and operational amplifier bias errors, overcoming the inherent error problems that are difficult to eliminate or extremely costly to correct in traditional pure hardware solutions. Based on this, the system's dependence on the absolute accuracy of individual components is significantly reduced, and the overall reliability and stability are improved. At the same time, the optimization of output accuracy and the expansion of functions can be completed through software upgrades without replacing hardware, which reduces maintenance costs and improves the economics of long-term use. It can effectively meet the application needs of high-precision analog voltage output in fields such as industrial automation control, test and measurement and precision instruments.

[0168] This application also provides a microcontroller unit 10 (MCU). Please refer to [link to relevant documentation]. Figure 5The diagram illustrates a hardware structure of a microcontroller 10 capable of executing the methods described in the embodiments above. The microcontroller 10 includes: at least one processor 11; and a memory 12 communicatively connected to the at least one processor 11. Figure 5 Taking a processor 11 as an example, the memory 12 stores instructions executable by at least one processor 11. These instructions, when executed by the at least one processor 11, enable the at least one processor 11 to perform the analog voltage output method of the dual digital-to-analog converter described in the above embodiment. The processor 11 and the memory 12 can be connected via a bus or other means. Figure 5 Taking the example of a connection between China and Israel via a bus.

[0169] The memory 12, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the analog voltage output method of the dual digital-to-analog converter in the embodiments of this application. The processor 11 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 12, thereby implementing the analog voltage output method of the dual digital-to-analog converter in the above embodiments.

[0170] The memory 12 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computing device. Furthermore, the memory 12 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 12 may optionally include memory remotely located relative to the processor 11, and these remote memories may be connected to the computing device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0171] One or more modules are stored in memory 12 and, when executed by one or more processors 11, perform the analog voltage output method of the dual digital-to-analog converter described above.

[0172] The above-described product can execute the method provided in the embodiments of this application, and has the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be found in the analog voltage output method of the dual digital-to-analog converter in the embodiments of this application.

[0173] This application provides a non-volatile computer-readable storage medium storing computer-executable instructions that are executed by one or more processors to enable at least one processor to perform the analog voltage output method of the dual digital-to-analog converter described above. For example, the non-volatile computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), magnetic tape, floppy disk, or optical data storage device, etc.

[0174] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for analog voltage output from a dual digital-to-analog converter (DADC), applied to a DADC synthesis system, the DADC synthesis system comprising a first digital-to-analog converter (DADC) and a second DADC, characterized in that, The method includes: According to the preset equivalent digital conversion strategy, the preset target voltage is converted to obtain the first digital code of the first digital-to-analog converter and the second digital code of the second digital-to-analog converter. Based on the target voltage, a calibration procedure is performed until preset conditions are met; wherein, the calibration procedure includes: In the current period, the actual sampled voltage is obtained, and the target error of the current period is obtained based on the target voltage and the actual sampled voltage. When the target error meets a first preset range, an adjustment process is executed; wherein, the adjustment process includes: obtaining the target adjustment amount for the current period based on a preset adjustment amount calculation strategy and the target error; determining a target digital-to-analog converter from the first digital-to-analog converter and the second digital-to-analog converter based on the target error and a preset channel selection strategy; and obtaining the target digital code of the target digital-to-analog converter and the predicted sampling voltage for the next period based on the first digital code, the second digital code, and the target adjustment amount. When the calibration process is completed, the actual sampled voltage is verified to obtain the target output result; The step of converting a preset target voltage according to a preset equivalent digital conversion strategy to obtain a first digital code of a first digital-to-analog converter and a second digital code of a second digital-to-analog converter includes: calculating the target voltage according to a preset compensation coefficient to obtain a target mapped voltage; performing equivalent numerical conversion on the target mapped voltage to obtain an equivalent digital code; and decomposing the equivalent digital code to obtain the first digital code and the second digital code. The step of obtaining the target adjustment amount for the current period based on the preset adjustment amount calculation strategy and the target error includes: obtaining the target error of the previous period and the integral cumulative term of the current period; obtaining the target proportional term value based on the proportional term coefficient and the target error of the current period; obtaining the target integral term value based on the integral term coefficient and the integral cumulative term; obtaining the target differential term value based on the differential term coefficient, the target error of the current period and the target error of the previous period; and obtaining the target adjustment amount based on the target proportional term value, the target integral term value and the target differential term value.

2. The analog voltage output method of the dual digital-to-analog converter according to claim 1, characterized in that, The process of decomposing the equivalent digital code to obtain the first digital code and the second digital code includes: The equivalent digital code is judged; If the equivalent digital code is not greater than the preset overload threshold, the equivalent digital code is subjected to remainder and integer division calculations according to the preset proportional coefficient to obtain the first digital code and the second digital code. If the equivalent digital code is greater than the preset overload threshold, obtain the maximum constraint value of the digital code of the second digital-to-analog converter, and use the maximum constraint value of the digital code as the second digital code; The first digital code is obtained based on the equivalent digital code and the preset overload threshold.

3. The analog voltage output method of the dual digital-to-analog converter according to claim 1, characterized in that, The step of determining the target digital-to-analog converter from the first digital-to-analog converter and the second digital-to-analog converter based on the target error and a preset channel selection strategy includes: The target error is judged; When the target error meets the second preset range, the first digital-to-analog converter is used as the target digital-to-analog converter; When the target error does not meet the second preset range, the second digital-to-analog converter is used as the target digital-to-analog converter.

4. The analog voltage output method of the dual digital-to-analog converter according to claim 3, characterized in that, The step of obtaining the target digital code of the target digital-to-analog converter and the predicted sampling voltage for the next cycle based on the first digital code, the second digital code, and the target adjustment amount includes: Obtain the first adjustment sensitivity of the first digital-to-analog converter and the second adjustment sensitivity of the second digital-to-analog converter; When the target digital-to-analog converter is the first digital-to-analog converter, the target digital code is obtained according to the first digital code and the target adjustment amount; The target digital code is obtained by performing boundary detection processing on the target digital code; The first voltage change is obtained based on the first adjustment sensitivity and the target adjustment amount; Based on the first voltage change and the actual sampled voltage, the predicted sampled voltage for the next cycle is obtained; When the target digital-to-analog converter is the second digital-to-analog converter, the target digital code is obtained according to the second digital code and the target adjustment amount; The target digital code is obtained by performing the boundary detection process on the target digital code; The second voltage change is obtained based on the second adjustment sensitivity and the target adjustment amount; The predicted sampling voltage for the next cycle is obtained based on the second voltage change and the actual sampling voltage.

5. The analog voltage output method of the dual digital-to-analog converter according to claim 4, characterized in that, The step of performing boundary detection processing on the target digital code to obtain the target digital code includes: Obtain the maximum constraint value of the digital code of the target digital-to-analog converter corresponding to the target digital code; The target digital code is judged; When the target numeric code meets the third preset range, the target numeric code is not updated; When the target numeric code does not meet the third preset range and the target numeric code is less than zero, the target numeric code is set to zero; When the target numeric code does not meet the third preset range and the target numeric code is greater than the maximum constraint value of the numeric code, the maximum constraint value of the numeric code is set as the target numeric code; When the target digital code meets the fourth preset range, the digital-to-analog converter switching and adjustment process is executed.

6. The analog voltage output method of the dual digital-to-analog converter according to claim 5, characterized in that, When the target digital code meets the fourth preset range, the digital-to-analog converter switching adjustment process is executed, including: When the target digital code meets the fourth preset range, the target error is judged; If the target error is positive, the target digital-to-analog converter is switched to obtain the switched target digital-to-analog converter, and the target digital code corresponding to the target digital-to-analog converter is adjusted upward. If the target error is negative, the target digital-to-analog converter is switched to obtain the switched target digital-to-analog converter, and the target digital code corresponding to the target digital-to-analog converter is adjusted downward. After the upward adjustment process or the downward adjustment process is completed, the integral accumulation term is cleared to zero.

7. A microcontroller unit, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1-6.

8. A non-volatile computer-readable storage medium, characterized in that, The non-volatile computer-readable storage medium stores computer-executable instructions that, when executed by a microcontroller unit, cause the microcontroller unit to perform the method described in any one of claims 1-6.

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