Encoder and bit rate control circuit and bit rate control method thereof
By classifying the coded blocks through frequency domain conversion and quantization classification circuits and dynamically adjusting the quantization parameters, the contradiction between artifacts and coding efficiency in video coding is resolved, achieving a balance between video quality and coding efficiency.
Patent Information
- Application Number
- CN202511508082.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-21
- Publication Date
- 2026-01-30
AI Technical Summary
In video coding, when the video compression ratio is large, artifacts (such as blockiness and ringing) often occur, which leads to a decrease in video quality after decoding. At the same time, reducing the quantization step size to improve artifacts will result in a decrease in coding efficiency and an increase in bit rate.
The coded blocks are classified through frequency domain conversion, quantization, and statistical classification circuits. The quantization parameters are dynamically adjusted to reduce artifacts and optimize compression efficiency. The frequency domain conversion circuit performs frequency domain conversion on the pixel values, the quantization circuit performs quantization operations, the statistical and classification circuit statistically analyzes the distribution of non-zero coefficients, and the quantization parameters are adjusted through a selection circuit.
Achieving a balance between reducing artifacts and compression efficiency, improving video quality and optimizing coding efficiency, while avoiding artifacts and maintaining a reasonable bit rate.
Smart Images
Figure CN121442104A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of image encoder technology, specifically to an encoder and its bit rate control circuit and bit rate control method. Background Technology
[0002] In video encoding, artifacts often appear when the video compression ratio is high, significantly degrading the subjective experience of the decoded video. Common artifacts include blocking artifacts and ringing artifacts. Generally, blocking and ringing artifacts can be mitigated by reducing the quantization step size. However, reducing the overall bit rate quantization step size leads to decreased compression efficiency and increased bit rate, which is detrimental to bit rate storage and transmission. Summary of the Invention
[0003] In view of the shortcomings of the prior art, one object of this application is to provide an encoder and its bit rate control circuit and bit rate control method to improve the shortcomings of the prior art.
[0004] One embodiment of this application provides an encoder, comprising: a storage circuit, an encoding circuit, and a bit rate control circuit. The storage circuit stores an encoding block containing a plurality of pixel values. The encoding circuit is coupled to the storage circuit and encodes the encoding block according to a target quantization parameter to generate a bit rate. The bit rate control circuit is coupled to the storage circuit and the encoding circuit, and includes: a frequency domain conversion circuit, a quantization circuit, a statistics and classification circuit, and a selection circuit. The frequency domain conversion circuit is coupled to the storage circuit and performs a frequency domain conversion on the plurality of pixel values to generate frequency domain data. The quantization circuit is coupled to the frequency domain conversion circuit and performs a quantization operation on the frequency domain data based on a current quantization parameter to generate quantized data. The statistics and classification circuit is coupled to the quantization circuit and classifies the encoding block based on the distribution of non-zero coefficients in the quantized data to generate a category. The selection circuit is coupled to the statistics and classification circuit and the quantization circuit and changes the current quantization parameter based on the category, or outputs the current quantization parameter as the target quantization parameter.
[0005] Another embodiment of this application provides a bit rate control circuit applied to an encoder. The encoder includes a storage circuit for storing a code block. The code block includes a plurality of pixel values. The encoder encodes the code block according to a target quantization parameter. The bit rate control circuit includes: a frequency domain conversion circuit, a quantization circuit, a statistics and classification circuit, and a selection circuit. The frequency domain conversion circuit is used to perform a frequency domain conversion on the plurality of pixel values to generate frequency domain data. The quantization circuit is coupled to the frequency domain conversion circuit and is used to perform a quantization operation on the frequency domain data based on a current quantization parameter to generate quantized data. The statistics and classification circuit is coupled to the quantization circuit and is used to classify the code block based on the distribution of non-zero coefficients in the quantized data to generate a category. The selection circuit is coupled to the statistics and classification circuit and the quantization circuit and is used to change the current quantization parameter based on the category, or output the current quantization parameter as the target quantization parameter.
[0006] Another embodiment of this application provides a bit rate control method applied to an encoder. The encoder includes a storage circuit for storing a code block. The code block includes a plurality of pixel values. The encoder encodes the code block according to a target quantization parameter. The bit rate control method includes: performing a frequency domain transformation on the plurality of pixel values to generate frequency domain data; performing a quantization operation on the frequency domain data based on a current quantization parameter to generate quantized data; classifying the code block based on the distribution of non-zero coefficients in the quantized data to generate a category; and changing the current quantization parameter based on the category, or outputting the current quantization parameter as the target quantization parameter.
[0007] The technical means embodied in the embodiments of this application can improve at least one of the shortcomings of the prior art bit rate control method. Therefore, this application can achieve a balance between reducing artifacts and compression efficiency compared to the prior art.
[0008] The features, implementation, and effects of this application are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0010] Figure 1 This is a functional block diagram of an embodiment of the encoder bit rate control method of this application; Figure 2 This is a schematic diagram of an embodiment of a bit rate control method for a coding block according to this application; Figure 3 This is a flowchart of an embodiment of the bit rate control method of this application; Figure 4 A classification table showing an embodiment of the bit rate control method of this application; Figure 5 This is a functional block diagram of another embodiment of the bit rate control method of the bit rate control circuit of this application; Figure 6 It corresponds to Figure 5 Detailed circuit diagrams and operational schematics; and Figure 7 This is a functional block diagram of another embodiment of the bit rate control method of the bit rate control circuit of this application.
[0011] Explanation of icon numbers: 100: Encoder; 110: Storage circuit; 120, 500, 700: Bit rate control circuit; 122: Frequency domain conversion circuit; 124,510: Quantization circuit; 126,520: Statistical and Classification Circuits; 128,530: Selection circuit; 130: Encoding circuit; CU: Encoding block; DR: Bit Rate; QP: Current quantization parameter; QPa: Lower limit of quantization parameter; QPb: Upper limit of quantization parameter; QPi: Initial value of quantization parameter; QPt: Target quantization parameter; th1, th2, th3: Threshold values; Tp: Category; X: Pixel value; Y: Frequency domain data; Yq: Quantitative data; 210: Low-frequency region; 220: High-frequency region; S310, S320, S330, S340, S350, S360, S370, S380, S390: Steps; 511, 512, 513, 514, 515, 516, 517: Sub-quantization circuits; 521, 522, 523, 524, 525, 526, 527: Sub-statistics and classification circuits; 710: Memory; 720: Computational circuits. Detailed Implementation
[0012] The terminology used in the following description of bit rate control methods is based on the conventional terminology used in this technical field. If this specification provides explanations or definitions for certain terms, the interpretation of those terms in terms of bit rate control methods shall be based on the explanations or definitions provided in this specification.
[0013] The bit rate control method disclosed in this application includes an encoder, its bit rate control circuit, and the bit rate control method. Since some components of the bit rate control method included in the encoder and bit rate control circuit of this application may be known components individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the bit rate control method of this invention. Furthermore, some or all of the processes of the bit rate control method of this application can be in the form of software and / or firmware bit rate control methods, and can be executed by the bit rate control circuit of this application or its equivalent device. Without affecting the full disclosure and implementability of the bit rate control method of this invention, the following description of the bit rate control method of this invention will focus on the steps rather than the hardware.
[0014] In the following descriptions, H.264 refers to MPEG-4 Part 10, Advanced Video Coding (MPEG-4 AVC); H.265 refers to High Efficiency Video Coding (HEVC); H.266 refers to Versatile Video Coding (VVC); and AV1 (AOMedia Video 1) refers to a video coding format developed by the Alliance for Open Media (AOMedia).
[0015] Figure 1 This is a functional block diagram of an embodiment of the bit rate control method of encoder 100 of this application. Encoder 100 includes a storage circuit 110, a bit rate control circuit 120 and an encoding circuit 130 that are coupled to each other.
[0016] Storage circuit 110 is used to store at least one coding unit (CU), each CU containing multiple pixel values X (e.g., pixel luminance data and / or chrominance data). A frame contains multiple coding units (CUs). Storage circuit 110 may be volatile memory, such as static random access memory (SRAM).
[0017] Encoding circuit 130 encodes the coding block CU based on the target quantization parameter QPt generated by bit rate control circuit 120 to produce bit rate DR. Encoder 100 can be applied to various encoding protocols (including but not limited to H.264, H.265, H.266, and AV1). The encoding operation of encoding circuit 130 is well known to those skilled in the art and will not be described in detail here.
[0018] Bit rate control circuit 120 is coupled to storage circuit 110 and encoding circuit 130, and is used to generate target quantization parameter QPt for pixel value X based on initial quantization parameter QPi. In some embodiments, the initial quantization parameter QP can be the current quantization parameter QPc. Bit rate control circuit 120 includes frequency domain conversion circuit 122, quantization circuit 124, statistics and classification circuit 126, and selection circuit 128 that are coupled to each other.
[0019] Frequency domain transformation circuit 122 is coupled to storage circuit 110 and is used to perform frequency domain transformation on pixel value X based on equation (1) to generate frequency domain data Y. In equation (1), the symbol "D" is the transformation matrix specified by the protocol. For example, for the H.265 protocol, the transformation matrix D is the discrete cosine transformation matrix. The operational details of frequency domain transformation circuit 122 are well known to those skilled in the art and will not be described further.
[0020] Y=DX(1) The quantization circuit 124 is coupled to the frequency domain conversion circuit 122 and is used to quantize the frequency domain data Y based on equations (2) and (3) to generate quantized data Yq.
[0021] (2) (3) "floor()" is the floor function. 」 is the quantization step size, which has a one-to-one correspondence with the current quantization parameter QP, and can be obtained through a look-up table function (「LUT()」) (Equation (2)). The look-up table function is related to the coding protocol, which is well-known to those with ordinary knowledge in this technical field, so it will not be elaborated here. 「f」 is a hyperparameter used to control the degree of quantization rounding. For example, represents that the rounding threshold is 1 / 2 (i.e., rounding), represents that the rounding threshold is 2 / 3.
[0022] The statistics and classification circuit 126 is coupled to the quantization circuit 124 and is used to classify the coding block CU based on the quantized data Yq to generate the category Tp of the coding block CU. More specifically, the statistics and classification circuit 126 counts the number of non-zero coefficients (Nac) in the high-frequency region and the number of non-zero coefficients (Ndc) in the low-frequency region of the quantized data Yq, and then compares the value Nac and / or the value Ndc with the threshold value th1, the threshold value th2, and / or the threshold value th3 (th1 < th2 < th3). In some embodiments, the threshold values th1 to th3 can be determined based on experience.
[0023] Figure 2 is a schematic diagram of an embodiment of the bit rate control method for a coding block CU in this application. The coding block CU (M1 * N1 pixels) includes a low-frequency region 210 (M② * N② pixels in the upper left corner of the bit rate control method) and a high-frequency region 220 (the remaining M1 * N1 - M② * N② pixels of the bit rate control method) (M1 > M②, and N1 > N②). The value Ndc refers to the number of non-zero coefficients in the quantized data Yq corresponding to the low-frequency region 210, and the value Nac refers to the number of non-zero coefficients in the quantized data Yq corresponding to the high-frequency region 220. In some embodiments, M1 is equal to N1 (for example, both are 32 or 16), and M② is equal to N② (for example, both are 4, 2, or 1). In other embodiments, M1 may not be equal to N1, and M② may not be equal to N②.
[0024] The selection circuit 128 is coupled to the statistics and classification circuit 126 and is used to change the current quantization parameter QP based on the category Tp of the coding block CU, or output the current quantization parameter QP as the target quantization parameter QPt based on the category Tp. The following is in coordination with Figure 3 to illustrate the operation details of the quantization circuit 124, the statistics and classification circuit 126, and the selection circuit 128.
[0025] Figure 3 is a flowchart of an embodiment of the bit rate control method of the bit rate control method in this application. Figure 3 The process includes the following steps.
[0026] Step S310: The quantization circuit 124 reads the initial value QPi of the quantization parameter from the buffer (not shown) as the current quantization parameter QP. The generation of the initial value QPi is well known to those skilled in the art and will not be described further.
[0027] Step S320: Frequency domain conversion circuit 122 performs frequency domain conversion on the coded block CU to generate frequency domain data Y. More specifically, frequency domain conversion circuit 122 performs frequency domain conversion on a complex number of pixels of the coded block CU based on equation (1).
[0028] Step S330: Quantization circuit 124 performs quantization operation on frequency domain data Y based on the current quantization parameter QP to generate quantized data Yq. More specifically, quantization circuit 124 performs quantization operation on frequency domain data Y based on equations (2) and (3).
[0029] Step S340: The statistical and classification circuit 126 calculates the distribution of non-zero coefficients in the quantized data Yq and classifies the coding block CU based on this distribution to generate category Tp. The distribution of non-zero coefficients refers to the values Nac and Ndc. More specifically, the statistical and classification circuit 126 is based on... Figure 4 The classification table is used to classify the coded blocks (CUs). For example... Figure 4 As shown, when the value Ndc is less than the threshold th1 and the value Nac equals 0, the coded block CU is classified as category 1 (Tp = 1, block effect region). When the value Nac is greater than 0 and less than the threshold th2, the coded block CU is classified as category 2 (Tp = 2, ringing effect region). When the sum of the values Ndc and Nac is greater than or equal to the threshold th3, the coded block CU is classified as category 3 (Tp = 3, region with obvious artifacts). When the coded block CU does not belong to category 1, 2, or 3, the coded block CU is classified as category 4 (Tp = 4, region with generally no artifacts).
[0030] Step S350: The selection circuit 128 determines whether the category Tp is equal to 1 or 2, and whether the current quantization parameter QP is within the adjustable range (i.e., the current quantization parameter QP is greater than the lower limit of the quantization parameter QPa). If yes, proceed to step S360; otherwise, proceed to step S370.
[0031] Step S360: Select circuit 128 reduces the current quantization parameter QP (for example, by subtracting the step value Z from the current quantization parameter QP (i.e., QP = QP - Z)), and then executes step S330 again. That is, this step reduces artifacts (including but not limited to block artifacts and ringing artifacts) and reduces the compression efficiency of the coded block CU by reducing the current quantization parameter QP (equivalent to reducing the quantization step size of the code).
[0032] Step S370: Select circuit 128 determines whether category Tp is equal to 3 and whether the current quantization parameter QP is within the adjustable range (i.e., the current quantization parameter QP is less than the upper limit of the quantization parameter QPb). If yes, proceed to step S380; otherwise, proceed to step S390.
[0033] Step S380: Select circuit 128 increases the current quantization parameter QP (for example, by adding a step value Z to the current quantization parameter QP (i.e., QP = QP + Z)), and then executes step S330 again. In other words, this step improves the compression efficiency of the coded block CU by increasing the current quantization parameter QP (equivalent to increasing the quantization step size of the code). Since the coded block CU is a region with virtually no artifacts, the improvement in compression efficiency has almost no impact on the user's subjective experience.
[0034] Steps S350 to S380 above involve the selection circuit 128 changing (i.e., decreasing or increasing) the current quantization parameter QP based on the category Tp of the coding block CU.
[0035] Step S390: The selection circuit 128 outputs the current quantization parameter QP as the target quantization parameter QPt based on the category Tp of the coding block CU. More specifically, when the category Tp is equal to 4, or when the category Tp is category 1, 2 or 3 and the current quantization parameter QP can no longer be adjusted (reaching the boundary) (i.e., the results of steps S350 and S370 are both negative), the selection circuit 128 outputs the current quantization parameter QP as the target quantization parameter QPt.
[0036] In summary, this application classifies coded blocks (CUs) based on their quantization data Yq, and determines a better target quantization parameter QPt for each CU based on its category Tp. Therefore, this application achieves a balance between artifact reduction and compression efficiency.
[0037] Figure 5 This is a functional block diagram of another embodiment of the bit rate control method of the bit rate control circuit of this application. The bit rate control circuit 500 includes a frequency domain conversion circuit 122, a quantization circuit 510, a statistics and classification circuit 520, and a selection circuit 530 that are coupled to each other.
[0038] Figure 6 It corresponds to Figure 5 The detailed circuit diagram and operation schematic are shown. The quantization circuit 510 includes multiple sub-quantization circuits 511 to 517, while the statistics and classification circuit 520 includes multiple sub-statistics and classification circuits 521 to 527. Figure 6 The multiple judgment conditions (represented by diamonds) in the code correspond to the operation of the selection circuit 530.
[0039] Multiple sub-quantization circuits 511-517 execute step S330 in parallel; that is, each sub-quantization circuit essentially performs quantization operations simultaneously using its own quantization parameters. The quantization parameter used by each sub-quantization circuit is the sum of the initial quantization parameter value QPi and a step value Z multiplied by N (N is an integer). More specifically, the quantization parameter used by sub-quantization circuit 514 is the initial quantization parameter value QPi plus 0 times the step value Z (i.e., QPi); the quantization parameter used by sub-quantization circuit 513 is the initial quantization parameter value QPi plus a negative 1 times the step value Z (i.e., QPi-Z); the quantization parameter used by sub-quantization circuit 515 is the initial quantization parameter value QPi plus a positive 1 times the step value Z (i.e., QPi+Z); and so on, until the boundary is reached (i.e., the lower limit of the quantization parameter QPa and the upper limit of the quantization parameter QPb). In other words, the sub-quantization circuits 511 to 517 perform quantization operations on the frequency domain data Y simultaneously based on the quantization parameters QPa+Z, QPi-2Z, QPi-Z, QPi, QPi+Z, QPi+2Z and QPb-Z, respectively, and generate the corresponding quantized data Yq.
[0040] Multiple sub-statistical and classification circuits 521-527 are respectively coupled to corresponding sub-quantization circuits 511-517, and the steps S340 are executed in parallel to generate a category Tp respectively.
[0041] The selection circuit 530 selects the corresponding quantization parameter as the target quantization parameter QPt based on whether category Tp is category 1, 2, or 3.
[0042] For example, when the category Tp generated by the sub-statistical and classification circuit 523 (522 or 521) is neither category 1 nor category 2, the selection circuit 530 determines that the target quantization parameter QPt is equal to the quantization parameter QPi-Z (QPi-2Z or QPa+Z) used by the corresponding bit rate control method sub-quantization circuit 513 (512 or 511).
[0043] For another example, when the category Tp generated by the sub-statistical and classification circuit 525 (526 or 527) is not category 3, the selection circuit 530 determines that the target quantization parameter QPt is equal to the quantization parameter QPi+Z (QPi+2Z or QPb-Z) used by the corresponding bit rate control method sub-quantization circuit 515 (516 or 517).
[0044] For another example, when the category Tp generated by the sub-statistics and classification circuit 524 is not category 1, 2, or 3, the selection circuit 530 determines that the target quantization parameter QPt is equal to the quantization parameter QPi used by the corresponding bit rate control method sub-quantization circuit 514.
[0045] When the category Tp generated by the sub-statistical and classification circuit 521 is still category 1 or 2, the selection circuit 530 uses the lower limit of the quantization parameter QPa as the target quantization parameter QPt. When the category Tp generated by the sub-statistical and classification circuit 527 is still category 3, the selection circuit 530 uses the upper limit of the quantization parameter QPb as the target quantization parameter QPt.
[0046] Compared to Figure 2 Bit rate control circuit 120, Figure 5 The bit rate control circuit 500 uses multiple circuits for parallel processing. Figure 3 This is part of the process, so the bit rate control circuit 500 can generate the target quantization parameter QPt faster.
[0047] In some embodiments, QPa = QPi - 4, QPb = QPi + 4, and Z = 1.
[0048] In other embodiments, Z = 2.
[0049] Figure 7 This is a functional block diagram of another embodiment of the bit rate control method of the bit rate control circuit of this application. The bit rate control circuit 700 includes a memory 710 (e.g., SRAM) and a computing circuit 720 coupled to each other. The memory 710 stores a plurality of program codes and / or program instructions. The computing circuit 720 executes these program codes and / or program instructions to complete... Figure 3 The process.
[0050] Although the foregoing embodiments use block effects and ringing effects as examples, this is not intended to limit the bit rate control method of this application. Those skilled in the art can appropriately apply this application to other types of artifacts based on the bit rate control method disclosed in this application.
[0051] Although the embodiments of this application are described above, these embodiments are not intended to limit this application. Those skilled in the art can make changes to the technical features of this application based on the express or implied content of this application. All such changes may fall within the scope of patent protection sought by this application. In other words, the scope of patent protection of this application shall be determined by the scope of the patent application as defined in this specification.
Claims
1. An encoder, characterized by The bit rate control circuit comprises: a storage circuit for storing an encoding block, the encoding block comprising a plurality of pixel values; an encoding circuit coupled to the storage circuit for encoding the encoding block according to a target quantization parameter to generate a bit rate; and a bit rate control circuit coupled to the storage circuit and the encoding circuit, and comprising: a frequency domain conversion circuit coupled to the storage circuit for frequency domain conversion of the plurality of pixel values to generate a frequency domain data; a quantization circuit coupled to the frequency domain conversion circuit for performing a quantization operation on the frequency domain data based on a current quantization parameter to generate a quantization data; a statistics and classification circuit coupled to the quantization circuit for classifying the encoding block based on the quantization data to generate a class; a selection circuit coupled to the statistics and classification circuit and the quantization circuit for changing the current quantization parameter based on the class, or outputting the current quantization parameter as the target quantization parameter. The selection circuit decreases the current quantization parameter when the class is a first class or a second class, and increases the current quantization parameter when the class is a third class. The encoding block comprises a low frequency region and a high frequency region; the number of non-zero coefficients of the quantization data in the low frequency region is a first value; the number of non-zero coefficients of the quantization data in the high frequency region is a second value; the class is the first class when the first value is less than a threshold value and the second value is equal to 0.
2. The encoder of claim 1, wherein, The class is the second class when the second value is greater than 0 and less than a second threshold value.
3. The encoder of claim 2, wherein, The class is the third class when the sum of the first value and the second value is greater than or equal to a third threshold value; the second threshold value is less than the third threshold value.
4. The encoder of claim 3, wherein, The quantization circuit comprises a plurality of sub-quantization circuits; the statistics and classification circuit comprises a plurality of sub-statistics and classification circuits; the plurality of sub-quantization circuits simultaneously perform the quantization operation using a sum of a quantization parameter initial value and N times of a step value to generate a plurality of quantization data, N being an integer; and the plurality of sub-statistics and classification circuits respectively classify the encoding block based on the plurality of quantization data.
5. The encoder of claim 4, wherein, The statistics and classification circuit classifies the encoding block based on the distribution of non-zero coefficients in the quantization data.
6. The encoder of claim 1, wherein, The bit rate control circuit is applied to an encoder, the encoder comprising a storage circuit for storing an encoding block, the encoding block comprising a plurality of pixel values, the encoder encoding the encoding block according to a target quantization parameter, the bit rate control circuit comprising:
7. The encoder of claim 1, wherein, a frequency domain conversion circuit for frequency domain conversion of the plurality of pixel values to generate a frequency domain data; 8. A bit rate control circuit, characterized by, a quantization circuit coupled to the frequency domain conversion circuit for performing a quantization operation on the frequency domain data based on a current quantization parameter to generate a quantization data; a statistics and classification circuit coupled to the quantization circuit for classifying the encoding block based on the quantization data to generate a class; a selection circuit coupled to the statistics and classification circuit and the quantization circuit for changing the current quantization parameter based on the class, or outputting the current quantization parameter as the target quantization parameter. 9. The bit rate control circuit of claim 8, wherein, The selection circuit decreases the current quantization parameter when the category is a first category or a second category, and increases the current quantization parameter when the category is a third category.
10. The bit rate control circuit of claim 9, wherein, The coding block includes a low frequency region and a high frequency region; the number of non-zero coefficients of the quantization data in the low frequency region is a first value; the number of non-zero coefficients of the quantization data in the high frequency region is a second value; and the category is the first category when the first value is less than a threshold value and the second value is equal to 0.
11. The bit rate control circuit of claim 9, wherein, The coding block includes a low frequency region and a high frequency region; the number of non-zero coefficients of the quantization data in the low frequency region is a first value; the number of non-zero coefficients of the quantization data in the high frequency region is a second value; and the category is the second category when the second value is greater than 0 and less than a second threshold value.
12. The bit rate control circuit of claim 11, wherein, The coding block includes a low frequency region and a high frequency region; the number of non-zero coefficients of the quantization data in the low frequency region is a first value; the number of non-zero coefficients of the quantization data in the high frequency region is a second value; and the category is the third category when the sum of the first value and the second value is greater than or equal to a third threshold value; and the second threshold value is less than the third threshold value.
13. The bit rate control circuit of claim 8, wherein, The quantization circuit includes a plurality of sub-quantization circuits; the statistics and category circuit includes a plurality of sub-statistics and category circuits; the plurality of sub-quantization circuits simultaneously use the sum of a quantization parameter initial value and N times of a step value to perform the quantization operation to generate a plurality of quantization data, N being an integer; and the plurality of sub-statistics and category circuits respectively classify the coding block based on the plurality of quantization data.
14. The bit rate control circuit of claim 8, wherein, The statistics and category circuit classifies the coding block based on the distribution of non-zero coefficients in the quantization data.
15. A bit rate control method characterized by, The bit rate control method is applied to an encoder, the encoder includes a storage circuit for storing a coding block, the coding block including a plurality of pixel values, the encoder encodes the coding block according to a target quantization parameter, the bit rate control method includes: performing frequency domain conversion on the plurality of pixel values to generate a frequency domain data; performing a quantization operation on the frequency domain data based on a current quantization parameter to generate a quantization data; classifying the coding block based on the quantization data to generate a category; and changing the current quantization parameter based on the category, or outputting the current quantization parameter as the target quantization parameter.
16. The bit rate control method of claim 15, wherein, The current quantization parameter is decreased when the category is a first category or a second category, and the current quantization parameter is increased when the category is a third category.
17. The bit rate control method of claim 15, wherein, The statistics and category circuit classifies the coding block based on the distribution of non-zero coefficients in the quantization data.