A gallium nitride transistor based on a type ii heterojunction gate structure

Abstract

The application relates to the technical field of semiconductor devices, and more particularly to a gallium nitride transistor based on a type II heterojunction gate structure, which comprises a substrate layer, a buffer layer, a channel layer and a barrier layer which are sequentially stacked from bottom to top, a drain, a source and a gate structure are arranged on the barrier layer, the source and the drain are arranged on the two sides of the gate structure respectively, the sidewalls of the source and the drain, the sidewall of the gate structure and the exposed surface of the barrier layer are all covered with a passivation layer; the gate structure comprises a p-type gallium nitride layer, an n-type heterojunction material layer and a gate metal layer which are sequentially stacked from bottom to top, the n-type heterojunction material layer and the p-type gallium nitride layer form a type II heterojunction P-N junction, and the gate metal layer forms an ohmic contact with the n-type heterojunction material layer. The application utilizes the staggered band structure of the type II heterojunction to realize gate self-protection, does not need to rely on an external protection circuit, significantly simplifies system design, and reduces cost and layout area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and more particularly to a gallium nitride transistor based on a type II heterojunction gate structure. BACKGROUND

[0002] Gallium nitride high electron mobility transistors have become the core devices for next-generation high-efficiency power conversion and radio frequency applications due to their high electron mobility, high breakdown field, and excellent high-frequency characteristics. Among them, p-type gallium nitride gate high electron mobility transistors have become the mainstream technology route for current commercial applications due to their relatively mature process and ability to achieve normally-off operation.

[0003] However, the gate voltage withstand capability of this conventional structure is limited, and in actual circuit applications, it is easy to exceed its critical withstand voltage due to voltage surges or switching noise, resulting in irreversible breakdown failure of the gate dielectric. In order to improve system reliability, additional voltage clamping or protection circuits are usually designed in the external circuit, which not only increases the complexity and layout area of the circuit, but also increases the overall system cost, limiting its application in compact high-integration scenarios. SUMMARY

[0004] The purpose of the present application is to overcome the shortcomings of the prior art that require the design of additional protection circuits, and to provide a gallium nitride transistor based on a type II heterojunction gate structure, which realizes overvoltage protection of the gate without relying on external protection circuits, reducing cost and layout area.

[0005] To solve the above technical problems, the technical scheme adopted by the present application is:

[0006] A gallium nitride transistor based on a type II heterojunction gate structure is provided, which comprises a substrate layer, a buffer layer, a channel layer, and a barrier layer stacked in order from bottom to top, a drain, a source, and a gate structure are provided on the barrier layer, the source and the drain are respectively provided on both sides of the gate structure, the sidewalls of the source and the drain, the sidewalls of the gate structure, and the exposed surface of the barrier layer are all covered with a passivation layer.

[0007] The gate structure comprises a p-type gallium nitride layer, an n-type heterojunction material layer, and a gate metal layer stacked in order from bottom to top, the gate metal layer forms an ohmic contact with the n-type heterojunction material layer, the n-type heterojunction material layer and the p-type gallium nitride layer form a type II heterojunction P-N junction, when the voltage applied to the gate structure reaches the threshold voltage, band-to-band tunneling occurs at the interface between the n-type heterojunction material layer and the p-type gallium nitride layer, and the resistance value of the type II heterojunction P-N junction decreases.

[0008] The gallium nitride transistor based on the type II heterojunction gate structure of the application controls the on-off of the two-dimensional electron gas in the channel layer below the barrier layer by applying voltage to the gate metal layer, through the ohmic contact of the gate metal layer with the n-type heterojunction material layer, and regulating the energy band state of the type II hetero P-N junction composed of the n-type heterojunction material layer and the p-type gallium nitride layer, so as to realize the switching of the device. When the gate voltage reaches a critical value, the type II hetero P-N junction interface occurs band-to-band tunneling due to the unique energy band arrangement, resulting in a sharp drop in the junction resistance, thereby automatically clamping the gate voltage in a safe range, realizing the self-protection of the gate structure. The passivation layer covering the source side wall, the drain side wall, the gate structure side wall and the exposed surface of the barrier layer ensures the long-term stability of the device. The application utilizes the unique staggered energy band structure of the type II heterojunction to realize the self-protection of the gate, and designs a significant valence band step at the interface. When the gate voltage exceeds the safe working range, the energy band structure can trigger an efficient band-to-band tunneling effect, causing the heterojunction resistance to drop sharply, thereby automatically clamping the gate voltage in a safe range, and at the same time, without relying on external protection circuit, significantly simplifying the system design, reducing the cost and layout area.

[0009] Further, the energy band structure of the type II hetero P-N junction is staggered, and the conduction band bottom energy level of the n-type heterojunction material layer is lower than the valence band top energy level of the p-type gallium nitride layer. The staggered energy band arrangement makes the conduction band bottom energy level of the n-type heterojunction material layer lower than the valence band top energy level of the p-type gallium nitride layer, thereby forming a significant valence band step and conduction band step at the interface. This energy band structure not only provides a physical basis for band-to-band tunneling, but also effectively blocks the injection of high-energy carriers through the built-in energy band barrier, thereby improving the gate reliability and long-term stability of the device.

[0010] Further, a valence band step ΔEv and a conduction band step ΔEc are formed at the interface between the n-type heterojunction material layer and the p-type gallium nitride layer, the valence band step ΔEv is 0.5 V~1.5 V, and the conduction band step ΔEc is 0.2 V~0.8 V. Limiting the valence band step ΔEv to the range of 0.5 V~1.5 V and the conduction band step ΔEc to the range of 0.2 V~0.8 V can not only ensure that the band-to-band tunneling is triggered effectively when the gate voltage exceeds the safe threshold, realizing voltage self-clamping, but also avoid that the large band step affects the normal switching characteristics of the device, thereby balancing the protection performance and electrical performance.

[0011] Further, the n-type heterojunction material layer remains in an incomplete depletion state within the working voltage range of the gallium nitride transistor. Making the n-type heterojunction material layer remain in an incomplete depletion state within the working voltage range can ensure that the gate has good control ability and low contact resistance, while maintaining a reasonable distribution of the internal electric field of the heterojunction, providing necessary carrier supply and transport channels for band-to-band tunneling, and ensuring reliable triggering of the self-clamping function.

[0012] Further, the n-type heterojunction material layer is selected from a combination of one or more of zinc oxide, indium zinc oxide, and indium gallium zinc oxide.

[0013] Further, the doping element of the p-type gallium nitride layer is magnesium, and the doping element of the n-type heterojunction material layer is one of aluminum, gallium, or indium. The p-type gallium nitride layer is doped with magnesium to achieve stable hole conduction, and the n-type heterojunction material layer is doped with aluminum, gallium, or indium to adjust the carrier concentration and energy band position thereof. The two together optimize the energy band alignment and tunneling characteristics of the heterojunction, thereby ensuring the normally-off characteristics and self-protection function of the device from a material system.

[0014] Further, the n-type heterojunction material layer is prepared by a low-temperature deposition process. The n-type heterojunction material layer prepared by a low-temperature deposition process can effectively suppress the passivation effect of hydrogen atoms on dopants during high-temperature processes, avoid compensation effects caused by impurity diffusion, thereby greatly improving the stability of the threshold voltage and process repeatability, simplifying the manufacturing process, and reducing the budget.

[0015] Further, ohmic contacts are formed between the source and the barrier layer, and ohmic contacts are formed between the drain and the barrier layer. The source and the drain form low-resistance ohmic contacts with the barrier layer, respectively, thereby ensuring efficient carrier injection and extraction between the two-dimensional electron gas in the channel and the external circuit, reducing the on-resistance and power consumption of the device, and improving the overall output current capacity and switching speed.

[0016] Further, the source, the drain, and the gate metal layer are made of one or more of a combination of titanium, aluminum, gold, nickel, tungsten, and titanium nitride. The source, the drain, and the gate metal are made of high-conductivity metals such as titanium, aluminum, gold, nickel, or a composite structure thereof, which not only ensures good ohmic contact characteristics and thermal stability of each electrode, but also enhances the anti-electromigration capability and long-term working reliability of the device, making it suitable for high-power and high-frequency application scenarios.

[0017] Further, the barrier layer is made of aluminum nitride or aluminum gallium nitride, and the passivation layer is made of silicon nitride or silicon oxide. The barrier layer is made of aluminum nitride or aluminum gallium nitride, which can provide sufficient band offset and polarization charge to form a high-density two-dimensional electron gas channel. The passivation layer is made of silicon nitride or silicon oxide, which can effectively suppress surface states, reduce current collapse, and protect the device from external environmental influences, thereby improving the output performance and reliability of the device.

[0018] Compared with the prior art, the present application has the following advantages:

[0019] 1. The staggered band structure of the II-type heterojunction is used to realize the gate self-protection, and a significant valence band step is designed at the interface. When the gate voltage exceeds the safe working range, the band structure can trigger an efficient band-to-band tunneling effect, so that the heterojunction resistance sharply decreases, thereby automatically clamping the gate voltage in the safe range, without relying on external protection circuit, significantly simplifying the system design, and reducing the cost and layout area.

[0020] 2. The dynamic reliability and threshold voltage stability of the device are significantly improved. The valence band step and the conduction band step formed at the interface constitute a high energy barrier, effectively inhibiting the injection of high-energy hot carriers to the gate interface, reducing the bombardment of the interface state and the generation of charge traps.

[0021] 3. There is no active interdiffusion and compensation effect between the n-type heterojunction material layer and the magnesium element in the p-type gallium nitride layer, solving the magnesium memory effect and the threshold voltage drift problem caused thereby, and ensuring the consistency and reliability of the electrical parameters of the device from the manufacturing process level. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 FIG. 1 is a structural schematic diagram of a gallium nitride transistor based on a II-type heterojunction gate structure;

[0023] Figure 2 FIG. 2 is a band diagram of a II-type heterojunction gate region;

[0024] Figure 3 FIG. 3 is a band diagram of a traditional P-N junction.

[0025] In the drawings: 1, substrate layer; 2, buffer layer; 3, channel layer; 4, barrier layer; 5, drain; 6, source; 7, passivation layer; 8, p-type gallium nitride layer; 9, n-type heterojunction material layer; 10, gate metal layer; 11, n-type gallium nitride layer. DETAILED DESCRIPTION

[0026] The application will be further described below in conjunction with specific embodiments. Among them, the drawings are only used for exemplary description, and the representation is only a schematic diagram, not a physical diagram, and cannot be understood as a limitation on the patent; in order to better illustrate the embodiments of the application, some components of the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art, it is understandable that some known structures and their descriptions in the drawings may be omitted.

[0027] The same or similar reference numerals in the drawings of the embodiments of the present application correspond to the same or similar components; in the description of the present application, it is understood that if the orientations or positional relationships indicated by the terms "upper", "lower", "left", "right" and the like are based on the orientations or positional relationships shown in the drawings, they are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore the terms describing the positional relationship in the drawings are only used for exemplary illustration, and cannot be understood as a limitation of the present patent, for those skilled in the art, the specific meanings of the above terms can be understood according to the specific circumstances.

[0028] Embodiment one

[0029] The present embodiment is a first embodiment of a gallium nitride transistor based on a type II heterojunction gate structure, as shown in Figure 1 The substrate layer 1, the buffer layer 2, the channel layer 3 and the barrier layer 4 are sequentially stacked from bottom to top, and the drain 5 and the source 6 are arranged on the barrier layer 4, and the gate structure is arranged between the drain 5 and the source 6, and the sidewalls of the source 6 and the drain 5, the sidewalls of the gate structure and the exposed surface of the barrier layer 4 are covered with the passivation layer 7.

[0030] The gate structure includes a p-type gallium nitride layer 8, an n-type heterojunction material layer 9 and a gate metal layer 10, which are sequentially stacked from bottom to top, the gate metal layer 10 forms an ohmic contact with the n-type heterojunction material layer 9, and the n-type heterojunction material layer 9 and the p-type gallium nitride layer 8 form a type II hetero P-N junction, when the voltage applied to the gate structure reaches the threshold voltage, the band-to-band tunneling occurs at the interface between the n-type heterojunction material layer 9 and the p-type gallium nitride layer 8, and the resistance value of the type II hetero P-N junction decreases.

[0031] In this embodiment, the gallium nitride transistor based on a type II heterojunction gate structure controls the switching of the device by applying a voltage to the gate metal layer 10, which, through its ohmic contact with the n-type heterojunction material layer 9, modulates the band state of the type II hetero PN junction formed by this layer and the p-type gallium nitride layer 8. This controls the on / off state of the two-dimensional electron gas in the channel layer 3 below the barrier layer 4. When the gate voltage reaches a critical value, band-to-band tunneling occurs at the type II hetero PN junction interface due to its unique band arrangement, causing a sharp drop in junction resistance. This automatically clamps the gate voltage within a safe range, achieving self-protection of the gate structure. The passivation layer 7, which fully covers the sidewalls of the source 6, drain 5, gate structure, and the exposed surface of the barrier layer 4, ensures the long-term stability of the device. This invention utilizes the unique interleaved band structure of a type II heterojunction to achieve gate self-protection. A significant valence band step is designed at the interface. When the gate voltage exceeds the safe operating range, this band structure can trigger an efficient band-to-band tunneling effect, causing the heterojunction resistance to drop sharply, thereby automatically clamping the gate voltage within the safe range. At the same time, it does not require external protection circuitry, which significantly simplifies system design and reduces cost and layout area.

[0032] In this embodiment, the type II heterojunction has an interleaved band structure, with the conduction band bottom level of the n-type heterojunction material layer 9 lower than the valence band top level of the p-type gallium nitride layer 8. This interleaved band arrangement results in a significant valence band and conduction band order at the interface, as the conduction band bottom level of the n-type heterojunction material layer 9 is lower than the valence band top level of the p-type gallium nitride layer 8. This band structure not only provides a physical basis for band-to-band tunneling but also effectively blocks the injection of high-energy carriers through a built-in band barrier, thereby improving the gate reliability and long-term stability of the device.

[0033] In this embodiment, a valence band step ΔEv and a conduction band step ΔEc are formed at the interface between the n-type heterojunction material layer 9 and the p-type gallium nitride layer 8. The valence band step ΔEv is 0.5 V to 1.5 V, and the conduction band step ΔEc is 0.2 V to 0.8 V. By limiting the valence band step ΔEv to the range of 0.5 V to 1.5 V and the conduction band step ΔEc to the range of 0.2 V to 0.8 V, it is possible to effectively trigger band tunneling and achieve voltage self-clamping when the gate voltage exceeds the safety threshold, while avoiding the impact of excessively large band steps on the normal switching characteristics of the device, thus achieving a balance between protection performance and electrical performance.

[0034] like Figure 2 , Figure 3 As shown, where E FThe difference between the conduction band energy level of the n-type heterojunction material layer 9 and the p-type gallium nitride layer 8 is ΔEc, and the difference between the valence band energy level of the n-type heterojunction material layer 9 and the p-type gallium nitride layer 8 is ΔEv. Compared with the traditional P-N junction, the II-type hetero P-N junction of the embodiment has a steep increase of the conduction band energy level Ec and the valence band energy level Ev at the interface between the n-type heterojunction material layer 9 and the p-type gallium nitride layer 8, that is, a conduction band step ΔEc and a valence band step ΔEv are formed. The high energy barrier created by the energy band structure can effectively block the injection of high-energy hot holes and hot electrons, significantly reduce the bombardment on the gate interface, thereby inhibiting the generation of interface states and charge trapping effect. At the same time, the valence band step can effectively inhibit the hole depletion phenomenon in the p-type gallium nitride layer 8 when a high voltage is applied to the drain 5, maintain the stability of the hole concentration, and ensure the stability of the threshold voltage under dynamic working conditions. The two aspects work together to significantly improve the time-dependent gate breakdown resistance and long-term reliability of the device.

[0035] Embodiment two

[0036] The embodiment is a second embodiment of a gallium nitride transistor based on a II-type heterojunction gate structure. The embodiment is similar to the first embodiment, except that the n-type heterojunction material layer 9 remains in an incomplete depletion state within the working voltage range of the gallium nitride transistor. Maintaining the n-type heterojunction material layer 9 in an incomplete depletion state within the working voltage range ensures that the gate has good control ability and low contact resistance, while maintaining a reasonable distribution of the internal electric field of the heterojunction, providing necessary current supply and transport channels for band-to-band tunneling, and ensuring reliable triggering of the self-clamping function.

[0037] The n-type heterojunction material layer 9 is selected from one or a combination of zinc oxide, indium zinc oxide, and indium gallium zinc oxide. Selecting oxide materials such as zinc oxide, indium zinc oxide, or indium gallium zinc oxide as the n-type heterojunction layer can form a good II-type band matching with the p-type gallium nitride layer 8.

[0038] The doping element of the p-type gallium nitride layer 8 is magnesium, and the doping element of the n-type heterojunction material layer 9 is one of aluminum, gallium, or indium. The p-type gallium nitride layer 8 uses magnesium doping to achieve stable hole conduction, and the n-type heterojunction material layer uses aluminum, gallium, or indium doping to adjust its carrier concentration and energy band position. The two together optimize the band alignment and tunneling characteristics of the heterojunction, ensuring the realization of the device's always-off characteristic and self-protection function from the material system.

[0039] The n-type heterojunction material layer 9 in the embodiment is prepared by a low-temperature deposition process. Preparing the n-type heterojunction material layer 9 by a low-temperature deposition process can effectively inhibit the passivation effect of hydrogen atoms on dopants during high-temperature processes, avoid compensation effects caused by impurity diffusion, and thus significantly improve the stability of the threshold voltage and the process repeatability, simplify the manufacturing process, and reduce the budget.

[0040] Embodiment three

[0041] The embodiment is a third embodiment of a gallium nitride transistor based on a type II heterojunction gate structure, which is similar to the first embodiment, except that an ohmic contact is formed between the source 6 and the barrier layer 4, and an ohmic contact is formed between the drain 5 and the barrier layer 4. The source 6 and the drain 5 form low-resistance ohmic contacts with the barrier layer 4, respectively, ensuring efficient carrier injection and extraction between the two-dimensional electron gas in the channel and the external circuit, reducing the on-resistance and power consumption of the device, and improving the overall output current capability and switching speed.

[0042] The material of the source 6, the drain 5 and the gate metal layer 10 in the embodiment is a combination of one or more of titanium, aluminum, gold, nickel, tungsten, titanium nitride. The source 6, the drain 5 and the gate metal are made of high-conductivity metals such as titanium, aluminum, gold, nickel, etc. or their composite structures, which not only ensure good ohmic contact characteristics and thermal stability of each electrode, but also enhance the anti-electromigration capability and long-term working reliability of the device, suitable for high-power and high-frequency application scenarios.

[0043] The material of the barrier layer 4 in the embodiment is aluminum nitride or aluminum gallium nitride, and the material of the passivation layer 7 is silicon nitride or silicon oxide. The barrier layer 4 uses aluminum nitride or aluminum gallium nitride material, which can provide sufficient band offset and polarization charge to form a high-density two-dimensional electron gas channel; the passivation layer 7 is made of silicon nitride or silicon oxide, which can effectively suppress surface states, reduce current collapse, and protect the device from external environment, thereby improving the output performance and reliability of the device.

[0044] In the specific content of the above specific embodiments, any technically feasible combination of technical features can be combined, and in order to make the description concise, not all possible combinations of the above technical features are described, but as long as the combination of technical features does not exist contradictory, it should be considered as the scope of the present disclosure.

[0045] Obviously, the above embodiments of the present application are only examples for clearly illustrating the present application, and are not intended to limit the embodiments of the present application. Based on the above description, those skilled in the art can make other different forms of changes or modifications. Here, it is not necessary and impossible to exhaust all the embodiments. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the claims of the present application.

Claims

1. A gallium nitride transistor based on a type II heterojunction gate structure, characterized in that, The structure includes a substrate layer (1), a buffer layer (2), a channel layer (3), and a barrier layer (4) stacked sequentially from bottom to top. A drain (5), a source (6), and a gate structure are disposed on the barrier layer (4). The source (6) and drain (5) are respectively disposed on both sides of the gate structure. The sidewalls of the source (6), the drain (5), the gate structure, and the exposed surface of the barrier layer (4) are all covered with a passivation layer (7). The gate structure includes a p-type gallium nitride layer (8), an n-type heterojunction material layer (9), and a gate metal layer (10) stacked sequentially from bottom to top. The gate metal layer (10) and the n-type heterojunction material layer (9) form an ohmic contact. The n-type heterojunction material layer (9) and the p-type gallium nitride layer (8) constitute a type II heterojunction. In an N-junction, when the voltage applied to the gate structure reaches a threshold voltage, band tunneling occurs at the interface between the n-type heterojunction material layer (9) and the p-type gallium nitride layer (8). The resistance of the N-junction decreases; the type II heterojunction P The band structure of the N-junction is interleaved, and the conduction band bottom level of the n-type heterojunction material layer (9) is lower than the valence band top level of the p-type gallium nitride layer (8); the n-type heterojunction material layer (9) remains in a partially depleted state within the operating voltage range of the gallium nitride transistor.

2. The gallium nitride transistor based on a type II heterojunction gate structure according to claim 1, characterized in that, At the interface between the n-type heterojunction material layer (9) and the p-type gallium nitride layer (8), a valence band level ΔEv and a conduction band level ΔEc are formed, wherein the valence band level ΔEv is 0.5 V to 1.5 V and the conduction band level ΔEc is 0.2 V to 0.8 V.

3. The gallium nitride transistor based on a type II heterojunction gate structure according to claim 1, characterized in that, The n-type heterojunction material layer (9) is selected from one or more of zinc oxide, indium zinc oxide, and indium gallium zinc oxide.

4. The gallium nitride transistor based on a type II heterojunction gate structure according to claim 1, characterized in that, The doping element of the p-type gallium nitride layer (8) is magnesium, and the doping element of the n-type heterojunction material layer (9) is one of aluminum, gallium or indium.

5. The gallium nitride transistor based on a type II heterojunction gate structure according to any one of claims 1 to 4, characterized in that, The n-type heterojunction material layer (9) is prepared by a low-temperature deposition process.

6. The gallium nitride transistor based on a type II heterojunction gate structure according to any one of claims 1 to 4, characterized in that, An ohmic contact is formed between the source electrode (6) and the barrier layer (4), and an ohmic contact is formed between the drain electrode (5) and the barrier layer (4).

7. The gallium nitride transistor based on a type II heterojunction gate structure according to any one of claims 1 to 4, characterized in that, The source electrode (6), the drain electrode (5), and the gate metal layer (10) are made of one or more of titanium, aluminum, gold, nickel, tungsten, and titanium nitride.

8. The gallium nitride transistor based on a type II heterojunction gate structure according to any one of claims 1 to 4, characterized in that, The barrier layer (4) is made of aluminum nitride or aluminum gallium nitride, and the passivation layer (7) is made of silicon nitride or silicon oxide.

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