Multi-material interposer stack substrate and semiconductor package structure

Abstract

The application discloses a multi-material interposer stacked substrate and a semiconductor packaging structure. The multi-material interposer stacked substrate splits a traditional single substrate into independent glass sub-substrate and silicon carbide sub-substrate, stacks through metal bonding and fills a filling material to form a multi-material integrated interposer substrate. In this way, the sub-substrate can be processed in parallel, the multi-layer stacking process is simplified, the alignment deviation and lamination defect risk are reduced, the manufacturing yield is significantly improved, and the processing time is shortened. The silicon carbide sub-substrate can integrate power devices, and the glass sub-substrate can integrate passive devices, which meets different functional requirements. The silicon carbide sub-substrate can effectively disperse heat sources and reduce thermal resistance, thereby improving the heat dissipation efficiency and operation stability of the whole module and simplifying the heat dissipation system of the whole module. The AI chip high-density integration and high-thermal management requirements are met. The sub-substrate is independently detected and screened, local defects of the traditional integral substrate do not cause the whole piece to fail, and the cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of advanced semiconductor packaging, and in particular to a multi-material interposer stacked substrate and a semiconductor packaging structure. Background Technology

[0002] With the surge in computing power demands from AI and high-performance computing chips, traditional organic substrates, due to their poor thermal stability, high signal transmission loss, and low interconnect density, can no longer meet the requirements of advanced packaging. While glass substrates possess higher mechanical strength, dimensional stability, and excellent electrical properties, enabling them to suppress chip warping under high thermal loads, reduce thermal stress reliability issues, and lower signal transmission loss, potentially enhancing the computing power of AI chips, current glass substrate technology still faces numerous challenges: through-glass via (TGV) processes are difficult, multilayer board processes are complex, multilayer wiring yields are low, processing costs are high, and the supply chain and long-term reliability data are incomplete. In particular, high-density chip integration technology for large-size glass substrates is still immature.

[0003] While the industry has explored this area before—for example, in 2010, the Tummala team at Georgia Tech verified the feasibility of a process route involving laser ablation of TGV vias, electroplating metallization filling, and surface semi-additive metal wiring; subsequently, LPKF used laser-induced wet etching to prepare TGVs; Corning developed large-size glass substrates; Renesas Electronics achieved high-speed signal transmission between GPUs and HBMs; and in 2023, Intel released a prototype product of a high-performance chip integrated on a glass substrate with a 6-layer RDL, a TGV pitch of 75 μm, and an aspect ratio close to 20:1—glass packaging substrates, such as 24-layer multilayer boards, still face significant challenges in terms of stacking alignment, dielectric uniformity, interlayer interconnect precision control, and heat dissipation due to their extremely high lamination complexity. Any tiny interlayer alignment deviation or lamination defect can lead to signal integrity issues or internal short circuits. In addition, the difficulty of via formation and electroplating processes increases exponentially, resulting in a significantly lower overall manufacturing yield than conventional multilayer boards. Therefore, technical solutions and routes need further improvement.

[0004] The information disclosed in this background section was already known to the inventors prior to the implementation of this application or was acquired during the implementation of this disclosure. Therefore, it may contain information that does not form prior art known to the public. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides a multi-material interposer stacked substrate and semiconductor packaging structure. By decomposing a single-layer substrate into independent sub-substrates of different materials, modularizing the sub-substrates design and parallel processing, and then stacking multiple sub-substrates, the invention solves the problems of complex multi-layer processes and low yields in existing single-layer substrates. It achieves complementary material advantages, simplifies the process, optimizes heat dissipation and electrical performance, and meets the advanced packaging requirements of AI and high-performance computing chips.

[0006] According to one or more embodiments, a multi-material interposer stack substrate is provided, comprising:

[0007] At least one glass sub-substrate and at least one silicon carbide sub-substrate are disposed along the stacking direction, wherein both the glass sub-substrate and the silicon carbide sub-substrate comprise:

[0008] The core board has a through hole, which is filled with a conductive material to form a conductive through hole;

[0009] Two redistribution structures are formed on opposite sides of the core board, corresponding to each other, and are electrically interconnected through the conductive vias; each redistribution structure has at least two redistribution layers;

[0010] A metal bonding layer is disposed on the side of each redistribution structure opposite to the core board and is electrically connected to the redistribution structure;

[0011] The core plate of the glass sub-substrate is made of glass, and the core plate of the silicon carbide sub-substrate is made of silicon carbide.

[0012] Along the stacking direction, any two adjacent sub-substrates are stacked and bonded through the metal bonding layer, and the bonding gap between the two adjacent sub-substrates is filled with filler material to form the multi-material interposer stacked substrate; wherein, the type combination of the two adjacent sub-substrates is selected from one of the following: (a) a silicon carbide sub-substrate and a glass sub-substrate; (b) two glass sub-substrates; (c) two silicon carbide sub-substrates; and at least one of the type combinations of the two adjacent sub-substrates is (a).

[0013] The multi-material interposer stacked substrate of the present invention splits the traditional single-material substrate into independent glass sub-substrates and silicon carbide sub-substrates, which are then stacked by metal bonding and filled with filler material to form a multi-material integrated interposer substrate. This allows for parallel processing of sub-substrates, simplifies multi-layer stacking processes, reduces alignment errors and lamination defects, significantly improves manufacturing yield, and shortens processing time. High-density integration is achieved through multi-layer sub-substrate stacking. The silicon carbide sub-substrates can integrate power devices, while the glass sub-substrates can integrate passive devices, catering to different functional requirements. Furthermore, the silicon carbide sub-substrates effectively disperse heat sources and reduce thermal resistance, thereby improving the overall module's heat dissipation efficiency and operational stability, and simplifying the overall module's heat dissipation system. Filling adjacent sub-substrates with a high thermal conductivity material eliminates air gaps at the bonding interface, improving heat dissipation efficiency and structural reliability, meeting the high-density integration and high thermal management requirements of AI chips. Independent testing and screening of sub-substrates avoids the failure of the entire substrate due to local defects in traditional monolithic substrates, reducing costs.

[0014] In addition, the multi-material interposer stacked substrate proposed according to the present invention may also have the following additional technical features:

[0015] Optionally, the top sub-substrate of the multi-material interposer stacked substrate is the silicon carbide sub-substrate.

[0016] Optionally, the redistribution structure of the glass sub-substrate integrates a passive device layer, which includes a capacitor, an inductor, or a resistor. The passive device layer is included in at least one redistribution layer of the redistribution structure or between two adjacent redistribution layers and is electrically connected to the redistribution layer.

[0017] Optionally, power devices are integrated in the core board or redistribution structure of the silicon carbide sub-substrate, and the power devices are electrically connected to the redistribution structure.

[0018] Furthermore, the redistribution layer includes a dielectric layer, a metal wiring layer, and a plurality of vias; the vias are electrically connected to the metal wiring layers of two adjacent redistribution layers, the passive device layer is included in the dielectric layer, and the passive device is electrically connected to the metal wiring layer and the vias.

[0019] Optionally, the metal bonding layer consists of a plurality of protrusions spaced apart on the side of the redistribution structure opposite to the core board.

[0020] Furthermore, the bumps on one of the redistribution structures of the sub-substrate are solder balls or gold balls, and the bumps on the other redistribution structure are copper pillars.

[0021] Optionally, the core plates of at least two of the glass sub-substrates may be made of different glass materials. The glass materials are selected from borosilicate glass, aluminosilicate glass, quartz glass, or soda-lime glass, etc. Thus, based on the thermo-mechanical-electrical simulation of the overall structure, glass core plates with different properties (such as different coefficients of thermal expansion and dielectric constants) can be selected to adapt to the glass sub-substrates, further optimizing overall stress, warpage, and transmission loss.

[0022] Optionally, in at least two of the redistribution structures of the glass sub-substrates, the dielectric layer of the redistribution layer is made of different materials.

[0023] Optionally, the dielectric layer of the redistribution layer in the redistribution structure of the glass sub-substrate is made of a different material than the dielectric layer of the redistribution layer in the redistribution structure of the silicon carbide sub-substrate.

[0024] Optionally, the filler material includes LCM material, LMUF material, CUF material, thermally conductive adhesive, prepreg, or NCF film.

[0025] According to another aspect of one or more embodiments, a method for fabricating a multi-material interposer stacked substrate is provided, comprising the following steps:

[0026] Provide at least one glass core board with conductive through holes and at least one silicon carbide core board;

[0027] A rewiring structure is provided on each of the opposite sides of each of the core boards; each of the rewiring structures has at least two redistribution layers;

[0028] A metal bonding layer is provided on the side of each redistribution structure away from the core board, and the wafer is cut to form multiple sub-substrates, wherein the glass wafer is cut to form a glass sub-substrate, and the silicon carbide wafer is cut to form a silicon carbide sub-substrate.

[0029] The plurality of sub-substrates are sequentially stacked and bonded along the stacking direction using the metal bonding layer, and the bonding gap between two adjacent sub-substrates is filled with filler material.

[0030] According to the present invention, a method for fabricating a multi-material interposer stacked substrate, by separately fabricating glass sub-substrates and silicon carbide sub-substrates and then stacking and bonding them, has the following advantages: the sub-substrate fabrication process is independently controllable; the glass sub-substrate adopts the mature laser-induced wet etching (TGV) process, and the silicon carbide sub-substrate combines deep reactive ion etching and high-temperature annealing graphene layer processes, ensuring the stable performance of each sub-substrate; the sub-substrates can be processed in parallel, significantly shortening the overall process flow time; after cutting, each individual sub-substrate is independently inspected, and qualified products are selected for stacking, avoiding the scrapping of the entire board due to local defects in traditional monolithic substrates, and significantly improving the yield; the design of integrating passive devices on the glass sub-substrate and power devices on the silicon carbide sub-substrate achieves functional modularity, without occupying additional substrate surface space; during stacking, the selection and order of sub-substrates are optimized based on thermo-mechanical-electrical simulation, and with the help of high thermal conductivity filler materials, the interlayer thermal stress is effectively relieved, the thermal resistance is reduced, and the heat dissipation efficiency is improved; the bump structure bonding can compensate for the flatness error between substrates through plastic deformation, improving the bonding accuracy and reliability, and significantly reducing the process difficulty and cost compared to the one-time processing of traditional multilayer single-material substrates.

[0031] In addition, the method for fabricating a multi-material interposer stacked substrate according to the present invention may also have the following additional technical features:

[0032] Optionally, stacking and bonding the plurality of sub-substrates using the metal bonding layer includes stacking and bonding two adjacent glass sub-substrates using the metal bonding layer, and stacking and bonding adjacent glass sub-substrates and silicon carbide sub-substrates through the metal bonding layer using the metal bonding layer; the top sub-substrate of the multi-material interposer stacked substrate is the silicon carbide sub-substrate.

[0033] Optionally, a redistribution structure is provided on each of the opposite sides of each of the core boards; each of the redistribution structures has at least two redistribution layers including:

[0034] A redistribution structure is provided on each of the opposite sides of the glass core board, and a passive device layer is provided in at least one of the redistribution structures; each redistribution structure has at least two redistribution layers; the passive device layer is provided in at least one redistribution layer of the redistribution structure or between two adjacent redistribution layers.

[0035] Furthermore, the redistribution structure includes providing a dielectric layer, a metal wiring layer, and a plurality of vias, and the provision of a passive device layer includes providing the passive device layer within the dielectric layer.

[0036] Furthermore, the passive device layer consists of multiple passive devices arranged in a spaced array on the same horizontal plane, and each passive device is connected to the metal wiring layer and the multiple vias.

[0037] Optionally, power devices are integrated in the core board or redistribution structure of the silicon carbide sub-substrate, and the power devices are electrically connected to the redistribution structure of the silicon carbide sub-substrate.

[0038] Optionally, the metal bonding layer includes a plurality of spaced bumps electrically connected to the redistribution structure on the side of the redistribution structure opposite to the core board.

[0039] Optionally, providing a glass core board with conductive vias includes providing glass core boards of at least two different glass materials, and forming the conductive vias on each of the glass core boards;

[0040] Furthermore, each glass core board having the conductive via is provided with the redistribution structure and the metal bonding layer, and each wafer is cut to form at least two types of glass sub-substrates;

[0041] The at least two types of glass sub-substrates and the silicon carbide sub-substrates are stacked and bonded using the metal bonding layer.

[0042] According to another aspect of one or more embodiments, a semiconductor packaging structure is provided, including the multi-material interposer stacked substrate described above, or the multi-material interposer stacked substrate prepared by the above manufacturing method.

[0043] A semiconductor chip is flip-chip mounted on the multi-material interposer stacked substrate and electrically connected to the metal bonding layer of the uppermost sub-substrate; and

[0044] Bottom filler adhesive is used to fill the space between the semiconductor chip and the uppermost sub-substrate.

[0045] Optionally, the semiconductor chip includes a high-bandwidth memory (HBM) and a graphics processing unit (GPU) chip, both of which are flip-chip mounted on the uppermost sub-substrate; the side of the multi-material interposer stacked substrate facing away from the semiconductor chip is connected to the PCB board to achieve electrical interconnection with external circuits.

[0046] Furthermore, the uppermost sub-substrate is a silicon carbide sub-substrate.

[0047] By adopting the above solution, the present invention has the following advantages:

[0048] 1. Improved manufacturing efficiency: Separating sub-substrates for parallel processing simplifies multi-layer stacking processes, reduces alignment deviations and lamination defects, significantly improves yield and shortens processing time; independent inspection and screening of sub-substrates avoids local defects leading to whole-wafer failure and reduces costs.

[0049] 2. Functional and Heat Dissipation Optimization: Passive devices are integrated on the glass sub-substrate, and power devices are integrated on the silicon carbide sub-substrate, achieving functional modularity without occupying additional surface space. The silicon carbide sub-substrate effectively disperses heat sources and reduces thermal resistance, while high thermal conductivity material is filled between adjacent sub-substrates to eliminate interfacial air gaps, further improving heat dissipation efficiency and structural reliability. Overall, it achieves high density, high performance, low cost, and high reliability through multi-material integration, making it suitable for high-heat, high-integration scenarios such as AI chips. Attached Figure Description

[0050] Figure 1 This is a cross-sectional schematic diagram of a multi-material interposer stacked substrate according to an embodiment of the present invention;

[0051] Figure 2 This is a schematic flowchart illustrating the fabrication method of a multi-material interposer stacked substrate according to an embodiment of the present invention.

[0052] Figures 3-20 This is a cross-sectional schematic diagram of the substrate for each step of the fabrication method of the multi-material interposer stacked substrate according to an embodiment of the present invention.

[0053] Figure 21 This is a cross-sectional schematic diagram of the semiconductor packaging structure according to an embodiment of the present invention;

[0054] Figure 22 The diagrams show an embodiment of the present invention and a conventional multilayer board structure, wherein (a) is an embodiment of the present invention, and (b) is a conventional multilayer board;

[0055] Figure 23 The images show warpage contour plots of embodiments of the present invention and conventional multilayer boards, wherein (a) is an embodiment of the present invention, and (b) is a conventional multilayer board;

[0056] Figure 24 The following are the heat dissipation simulation results of the embodiments of the present invention and the conventional multilayer board, wherein (a) is the embodiment of the present invention and (b) is the conventional multilayer board.

[0057] Label Explanation:

[0058] Multi-material interlayer stacked substrate 1;

[0059] Glass sub-substrate 10, glass core plate 110, first side 110a, second side 110b, first conductive via 111, glass-based redistribution structure 120, first glass-based redistribution structure 120a, first redistribution layer 121a, first dielectric layer 1211a, first metal wiring layer 1212a, first via 1213a, second glass-based redistribution structure 120b, second redistribution layer 121b, second dielectric layer 1211b, second metal wiring layer 1212b, second via 1213b, glass-based metal bonding layer 130, first glass-based metal bonding layer 130a, second glass-based metal bonding layer 130b, passive device layer 140;

[0060] Silicon carbide sub-substrate 20, silicon carbide core board 210, third side 210a, fourth side 210b, second conductive via 211, silicon carbide-based redistribution structure 220, first silicon carbide-based redistribution structure 220a, third redistribution layer 221a, third dielectric layer 2211a, third metal wiring layer 2212a, third via 2213a, second silicon carbide-based redistribution structure 220b, fourth redistribution layer 221b, fourth dielectric layer 2211b, fourth metal wiring layer 2212b, fourth via 2213b, silicon carbide-based metal bonding layer 230, first silicon carbide-based metal bonding layer 230a, second silicon carbide-based metal bonding layer 230b;

[0061] 30g of filler material;

[0062] High-bandwidth memory HBM 2;

[0063] Graphics processing unit (GPU) chip 3. Detailed Implementation

[0064] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0065] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art.

[0066] It should be noted that, in this paper, the direction parallel to the main surface of the core board can be referred to as the horizontal direction (X direction), and the direction perpendicular to both the horizontal direction (X direction) and the main surface of the core board can be referred to as the vertical direction (Z direction).

[0067] This application is based on the inventor's considerations as follows: Glass packaging substrates, such as 24-layer substrates, face significant challenges in stacking alignment, dielectric uniformity, interlayer interconnect precision control, and heat dissipation due to their extremely high lamination complexity. Any minute interlayer alignment deviation or lamination defect can lead to signal integrity issues or inner layer short circuits. Furthermore, the difficulty of via forming and electroplating processes increases exponentially, resulting in a significantly lower overall manufacturing yield compared to conventional multilayer boards. In addition, a single substrate material cannot simultaneously meet the multi-dimensional requirements of advanced packaging for heat dissipation, electrical performance, and integration. For example, while glass substrates have excellent electrical properties, their heat dissipation performance lags behind silicon carbide, while silicon carbide substrates are less flexible than glass substrates in integrating passive devices. Therefore, achieving complementary advantages among different substrate materials and solving the process challenges and performance bottlenecks of multilayer boards has become crucial for promoting the development of advanced semiconductor packaging.

[0068] Therefore, according to one or more embodiments of the multi-material interposer stacked substrate, the traditional single-material substrate is split into independent sub-substrates of different materials, namely, independent glass sub-substrates 10 and silicon carbide sub-substrates 20. Each sub-substrate includes a substrate with conductive material-filled vias, redistribution structures on both sides, and a metal bonding layer structure. By stacking and bonding the metal bonding layer structure and filling it with high thermal conductivity material, a multi-material interposer substrate integrating different functions is formed. In this way, the sub-substrates can be processed in parallel, simplifying the multi-layer stacking process, reducing the risk of alignment deviation and lamination defects, significantly improving manufacturing yield and shortening processing time. High-density integration is achieved through multi-layer sub-substrate stacking. The silicon carbide sub-substrates 20 can integrate power devices, and the glass sub-substrates 10 can integrate passive devices, taking into account different functional requirements. Furthermore, the silicon carbide sub-substrates 20 can effectively disperse heat sources and reduce thermal resistance, thereby improving the heat dissipation efficiency and operational stability of the entire module and simplifying the heat dissipation system of the entire module. Filling the gaps between adjacent sub-substrates with high thermal conductivity material eliminates air gaps at the bonding interface, improves heat dissipation efficiency and structural reliability, and meets the high-density integration and high thermal management requirements of AI chips. Independent testing and screening of sub-substrates avoids the failure of the entire substrate due to local defects in traditional monolithic substrates, thus reducing costs.

[0069] Figure 1 A multi-material interposer stack substrate is shown according to one or more embodiments.

[0070] refer to Figure 1 The multi-material interposer stacked substrate 1 includes at least one glass sub-substrate 10 and at least one silicon carbide sub-substrate 20 disposed along the stacking direction. Both the glass sub-substrate 10 and the silicon carbide sub-substrate 20 include: a core plate having through-holes filled with conductive material to form conductive vias; two redistribution structures formed correspondingly on opposite sides of the core plate and electrically interconnected through the conductive vias; each redistribution structure having at least two redistribution layers; and a metal bonding layer disposed on the side of each redistribution structure away from the core plate and electrically connected to the redistribution structure; the glass sub-substrate... The core board of 10 is made of glass, and the core board of silicon carbide sub-substrate 20 is made of silicon carbide. Along the stacking direction, any two adjacent sub-substrates are stacked and bonded by a metal bonding layer, and the bonding gap between the two adjacent sub-substrates is filled with a filler material to form a multi-material interlayer stacked substrate 1. The type combination of the two adjacent sub-substrates is selected from one of the following: (a) one silicon carbide sub-substrate 20 and one glass sub-substrate 10; (b) two glass sub-substrates 10; (c) two silicon carbide sub-substrates 20; and at least one type combination of the two adjacent sub-substrates is (a).

[0071] In other words, the multi-material interposer stacked substrate 1 is formed by stacking and bonding at least one glass sub-substrate 10 and at least one silicon carbide sub-substrate 20 through metal bonding layers of adjacent sub-substrates; in the multi-material interposer stacked substrate 1, two adjacent sub-substrates include glass sub-substrate 10 and silicon carbide sub-substrate 20, and glass sub-substrate 10 and glass sub-substrate 10, and / or include silicon carbide sub-substrate 20 and silicon carbide sub-substrate 20, thus splitting the single-layer substrate into independent glass and silicon carbide sub-substrates, stacking them through metal bonding and filling with filler material to form a multi-material integrated interposer substrate.

[0072] Specifically, please refer to Figures 3-20 Each glass sub-substrate 10 includes a glass core 110, two glass-based redistribution structures 120, and a glass-based metal bonding layer 130.

[0073] The glass core board 110 has a through-hole 111; that is, the glass core board 110 has a through-hole 111 that vertically penetrates the glass core board 110. Using glass as the core board offers superior power integrity performance, allowing for improved power distribution network design and signal integration, especially in relatively high frequency ranges. Furthermore, glass enables larger panel-level packaging, making parallel processing of each glass sub-substrate 10 possible, thus reducing processing time and manufacturing costs.

[0074] A first conductive via 111 may be provided between two glass-based redistribution structures 120, providing an electrical connection path between the two glass-based redistribution structures 120. There may be one or more first conductive vias 111, each containing a conductive material, which may be copper, aluminum, silver, gold, molybdenum, titanium, or a combination thereof. The first conductive via 111 may have an upper surface and a lower surface spaced apart from each other in a vertical direction. The upper surface of the first conductive via 111 may be coplanar with a first side 110a of the glass core plate 110, and the lower surface of the first conductive via 111 may be coplanar with a second side 110b of the glass core plate 110. The upper surface of the first conductive via 111 may be connected to the glass-based redistribution structure 120a of the first side 110a, and the lower surface of the first conductive via 111 may be connected to the glass-based redistribution structure 120b of the second side 110b.

[0075] Additionally, each first conductive via 111 can have any suitable shape, including, for example, a cylindrical shape. In one or more other embodiments, each first conductive via 111 can have a vertically symmetrical tapered shape.

[0076] Two glass-based redistribution structures 120 are formed one-to-one on opposite sides of the glass core plate 110 (i.e., the first side 110a and the second side 110b) and are electrically interconnected through a first conductive via 111; each glass-based redistribution structure 120 has at least two redistribution layers (e.g., 121a or 121b). The redistribution structure on the first side 110a of the glass core plate 110 can be defined as the first glass-based redistribution structure 120a; the redistribution structure on the second side 110b of the glass core plate 110 can be defined as the second glass-based redistribution structure 120b.

[0077] The first glass-based redistribution structure 120a includes at least two first redistribution layers 121a. Each first redistribution layer 121a may include a first dielectric layer 1211a, a first metal wiring layer 1212a, and a plurality of first vias 1213a; each first via 1213a electrically connects the first metal wiring layer 1212a of two adjacent first redistribution layers 121a, and the first metal wiring layer 1212a and the first via 1213a may be included in or surrounded in the first dielectric layer 1211a.

[0078] The first dielectric layer 1211a may be stacked in the vertical direction. The first dielectric layer 1211a may include an insulating material, such as a photosensitive imaging dielectric resin prepared by combining an epoxy resin and a photoinitiator, and may further include photosensitive polyimide and / or inorganic fillers, but is not limited thereto. The first metal wiring layer 1212a and the first via 1213a may be provided as conductive patterns, and the conductive patterns may be positioned within the first dielectric layer 1211a. The first metal wiring layer 1212a may be provided to extend horizontally within the first dielectric layer 1211a. The first via 1213a may penetrate one or more of the first dielectric layers 1211a in the vertical direction, thereby contacting and electrically connecting with some wiring patterns in the first metal wiring layer 1212a. The metal linewidth or spacing of the first metal wiring layer 1212a is ≥2 μm, and the metal thickness is ≥2 μm. According to some specific embodiments, the first via 1213a may have any suitable shape, including, for example, a tapered or cylindrical shape. The first metal wiring layer 1212a and the first via 1213a are made of conductive metals, such as copper, aluminum, titanium, tantalum, molybdenum and their alloys, but not limited to these.

[0079] The second glass-based redistribution structure 120b includes at least two layers of second redistribution layers 121b. Each layer of the second redistribution layer 121b may include a second dielectric layer 1211b, a second metal wiring layer 1212b, and a plurality of second vias 1213b; each second via 1213b electrically connects to the second metal wiring layers 1212b of two adjacent second redistribution layers 121b, and the second metal wiring layers 1212b and the second vias 1213b may be included in or surrounded within the second dielectric layer 1211b. The second dielectric layers 1211b may be stacked in the vertical direction. The second dielectric layer 1211b may include an insulating material, such as a photosensitive imaging dielectric resin prepared by combining epoxy resin and a photoinitiator, and may further include photosensitive polyimide and / or inorganic fillers, but is not limited thereto. The second metal wiring layer 1212b and the second via 1213b may be provided as conductive patterns, and the conductive patterns may be positioned within the second dielectric layer 1211b. The second metal wiring layer 1212b may be provided to extend horizontally within the second dielectric layer 1211b. The second via 1213b may penetrate one or more of the second dielectric layers 1211b in a vertical direction, thereby contacting and electrically connecting with some wiring patterns in the second metal wiring layer 1212b. The metal linewidth or spacing of the second metal wiring layer 1212b is ≥2 μm, and the metal thickness is ≥2 μm. According to some specific embodiments, the second via 1213b may have any suitable shape, including, for example, a tapered or cylindrical shape. The second metal wiring layer 1212b and the second via 1213b are made of conductive metals, such as copper, aluminum, titanium, tantalum, molybdenum, and their alloys, but are not limited thereto.

[0080] A glass-based metal bonding layer 130 is disposed on the side of each glass-based redistribution structure 120 facing away from the glass core plate 110 and is electrically connected to the glass-based redistribution structure 120. Two adjacent glass sub-substrates 10 are stacked and bonded through the glass-based metal bonding layer 130. That is, a metal bonding layer is disposed on the lower surface (the side facing away from the glass core plate 110) of the first glass-based redistribution structure 120a, which can be defined as the first glass-based metal bonding layer 130a; a metal bonding layer is also disposed on the upper surface (the side facing away from the glass core plate 110) of the second glass-based redistribution structure 120b, which can be defined as the second glass-based metal bonding layer 130b. In this way, the stacking of multiple glass sub-substrates 10 can be achieved by bonding two vertically opposite first glass-based metal bonding layers 130a and second glass-based metal bonding layers 130b. In one or more embodiments, the glass-based metal bonding layer 130 consists of a plurality of protrusions spaced apart on the side of the glass-based redistribution structure 120 away from the glass core 110.

[0081] Specifically, the bumps, as a concrete implementation of the glass-based metal bonding layer 130, can adopt spherical or columnar structures. Spherical bumps include, but are not limited to, reflowable solderable materials such as solder balls and gold balls; columnar bumps are preferably copper column structures, and their height can be precisely controlled through electroplating. The spacing of the bump array must meet the alignment accuracy requirements when adjacent glass sub-substrates 10 are stacked. The electrical connection between the bumps and the redistribution structure is achieved by fabricating a bump under-metal (UBM) layer on the outermost metal wiring layer of the redistribution structure, followed by forming the bump structure through ball placement or electroplating.

[0082] Thus, the staggered arrangement of bumps effectively releases the thermal stress generated during stacking, avoiding interface delamination caused by differences in thermal expansion coefficients. Secondly, the bump structure can compensate for flatness errors between substrates through plastic deformation during bonding, improving bonding yield. In addition, the air gaps formed by the bump array facilitate the full filling of the filler material 30, thereby improving the overall heat dissipation performance. Compared to traditional monolithic substrates that require the processing of multiple redistribution layers in a single step, this embodiment utilizes the bonding of the glass-based metal bonding layer 130 to significantly reduce the process difficulty of multi-layer stacking while ensuring electrical interconnect reliability.

[0083] In one or more specific embodiments, the bumps on one of the glass substrate rewiring structures 120 of the glass sub-substrate 10 are solder balls or gold balls, and the bumps on the other glass substrate rewiring structure 120 are copper pillars. For example, the bumps on the first glass substrate rewiring structure 120a are copper pillars, and the bumps on the second glass substrate rewiring structure 120b are solder balls or gold balls.

[0084] Specifically, when solder balls or gold balls are used as bump materials, their low melting points allow for interconnection of the glass-based metal bonding layer 130 during bonding via hot pressing or reflow soldering. When copper pillars are used as bump materials, their high mechanical strength and excellent conductivity enable them to withstand mechanical stress during stacking and ensure high-quality electrical signal transmission. The combination of these two bump materials allows for differentiated bonding: solder balls or gold balls provide good wettability and interfacial bonding, while copper pillars provide structural support and current carrying capacity. As a preferred embodiment, the diameter of the solder balls can be controlled between 50-200 μm, the diameter of the gold balls between 50-100 μm, and the height of the copper pillars between 50-150 μm, with a diameter matching that of the solder / gold balls.

[0085] The thickness of the glass sub-substrate 10 thus formed can be ≥150 μm. The thickness of the glass sub-substrate 10 is set to 150 μm or more primarily based on the following considerations: In multilayer interposer stacked structures, excessively thin sub-substrates are insufficient in terms of mechanical strength, thermal stability, and processing yield. Insufficient thickness may cause warping or cracking of the substrate during high-temperature bonding, affecting stacking accuracy and reliability.

[0086] According to one or more embodiments, the glass sub-substrate 10 has a passive device layer 140 integrated in its redistribution structure. The passive device layer 140 is included in at least one redistribution layer (e.g., 121a or 121b) of the glass-based redistribution structure 120 or between two adjacent redistribution layers (e.g., 121a or 121b), and is electrically connected to the redistribution layer (e.g., 121a or 121b).

[0087] For details, please refer to Figure 11 At least one glass-based redistribution structure 120 has a passive device layer 140, which is included in at least one redistribution layer (e.g., 121a or 121b) of the glass-based redistribution structure 120 or between two adjacent redistribution layers (e.g., 121a or 121b), and is electrically connected to the redistribution layer (e.g., 121a or 121b). More specifically, the passive device layer 140 may be included in at least one first redistribution layer 121a or between two adjacent first redistribution layers 121a, and is electrically connected to the first redistribution layer 121a; for example... Figure 11 In this embodiment, the passive device layer 140 is included in the innermost first redistribution layer 121a of the first glass substrate redistribution structure 120. In one or more other embodiments, the passive device layer 140 may also be included in the first redistribution layer 121a of other layers in the first glass substrate redistribution structure 120, or between two adjacent first redistribution layers 121a.

[0088] Preferably, the passive device layer 140 is included in the first dielectric layer 1211a, and the passive device is electrically connected to the first metal wiring layer 1212a and the first via 1213a.

[0089] The passive device layer 140 may include multiple passive devices arranged in a spaced array on the same horizontal plane. For example... Figure 11 As shown, the innermost redistribution layer 121a of the first glass-based redistribution structure 120a includes a passive device layer 140. The passive device layer 140 consists of multiple passive devices arranged in a spaced array between the first metal wiring layer 1212a and the first vias 1213a of the first redistribution layer 121a, with each passive device corresponding to each first via 1213a. The upper surfaces of the multiple passive devices are coplanar with the lower surfaces of the first metal wiring layer 1212a, and the lower surfaces of the multiple passive devices are coplanar with the upper surfaces of the multiple first vias 1213a; thus, multiple passive devices on the same horizontal plane constitute a passive device layer 140. This direct integration of passive devices into the redistribution structure avoids additional assembly processes, improving integration density and reliability. This integration method is particularly suitable for packaging applications of AI chips and high-performance computing chips that require high-density decoupling capacitors.

[0090] In one or more embodiments, the passive device can be a capacitor, resistor, or inductor; wherein the capacitor can be a MIM capacitor formed by an electrode plate-insulating layer-electrode plate. Thus, the capacitance density of a single-layer passive device layer 140 can reach tens of nF / mm². 2 The capacitance density of the multi-layer, multi-material interposer stacked substrate 1 can reach the required several hundred nF / mm². 2 In one or more embodiments, the electrode plate material of the MIM capacitor may be a conductive metal such as aluminum, copper or titanium, and the insulating layer material may be silicon dioxide, silicon nitride or a high dielectric constant material.

[0091] Similarly, please refer to Figure 21 Each silicon carbide sub-substrate 20 includes a silicon carbide core board 210, two silicon carbide-based redistribution structures 220, and a silicon carbide-based metal bonding layer 230.

[0092] The silicon carbide core board 210 has a through-hole 211; that is, the silicon carbide core board 210 has a through-hole 211 that vertically penetrates the silicon carbide core board 210. Using silicon carbide as the core board material, silicon carbide possesses excellent thermal conductivity and mechanical strength, which can effectively disperse heat sources, reduce thermal resistance, and simplify the heat dissipation system. The second conductive via 211 is fabricated using deep reactive ion etching, high-temperature annealing to form a single-crystal graphene layer, followed by PVD sputtering of a seed layer, metal electroplating filling, and surface CMP.

[0093] A second conductive via 211 may be provided between two silicon carbide-based redistribution structures 220, providing an electrical connection path between the two silicon carbide-based redistribution structures 220. There may be one or more second conductive vias 211, each containing a conductive material within the silicon carbide via. This conductive material may be copper, aluminum, silver, gold, molybdenum, titanium, or a combination thereof. The second conductive via 211 may have an upper surface and a lower surface spaced apart from each other in a vertical direction. The upper surface of the second conductive via 211 may be coplanar with the third side 210a of the silicon carbide core board 210, and the lower surface of the second conductive via 211 may be coplanar with the fourth side 210b of the silicon carbide core board 210. The upper surface of the second conductive via 211 may be connected to the silicon carbide-based redistribution structure 220a of the third side 210a, and the lower surface of the second conductive via 211 may be connected to the silicon carbide-based redistribution structure 220b of the fourth side 210b.

[0094] Additionally, each second conductive via 211 can have any suitable shape, including, for example, a cylindrical shape. In one or more other embodiments, each second conductive via 211 can have a vertically symmetrical tapered shape.

[0095] Two silicon carbide-based redistribution structures 220 are formed one-to-one on opposite sides (i.e., the third side 210a and the fourth side 210b) of the silicon carbide core board 210 and are electrically interconnected through a second conductive via 211; each silicon carbide-based redistribution structure 220 has at least two redistribution layers (e.g., 221a or 221b). The redistribution structure on the third side 210a of the silicon carbide core board 210 can be defined as the first silicon carbide-based redistribution structure 220a; the redistribution structure on the fourth side 210b of the silicon carbide core board 210 can be defined as the second silicon carbide-based redistribution structure 220b.

[0096] The first silicon carbide-based redistribution structure 220a includes at least two third redistribution layers 221a. Each third redistribution layer 221a may include a third dielectric layer 2211a, a third metal wiring layer 2212a, and a plurality of third vias 2213a; each third via 2213a electrically connects the third metal wiring layers 2212a of two adjacent third redistribution layers 221a, and the third metal wiring layers 2212a and the third vias 2213a may be included in or surrounded in the third dielectric layer 2211a.

[0097] The third dielectric layer 2211a may be stacked in the vertical direction. The third dielectric layer 2211a may include an insulating material, such as a photosensitive imaging dielectric resin prepared by combining an epoxy resin and a photoinitiator, and may further include photosensitive polyimide and / or inorganic fillers, but is not limited thereto. The third metal wiring layer 2212a and the third via 2213a may be provided as conductive patterns, and the conductive patterns may be positioned within the third dielectric layer 2211a. The third metal wiring layer 2212a may be provided to extend horizontally within the third dielectric layer 2211a. The third via 2213a may penetrate one or more of the third dielectric layers 2211a in the vertical direction, thereby contacting and electrically connecting with some wiring patterns in the third metal wiring layer 2212a. The metal linewidth or spacing of the third metal wiring layer 2212a is ≥5 μm, and the metal thickness is ≥5 μm. According to some specific embodiments, the third via 2213a may have any suitable shape, including, for example, a tapered or cylindrical shape. The third metal wiring layer 2212a and the third via 2213a are made of conductive metals, such as copper, aluminum, titanium, tantalum, molybdenum and their alloys, but not limited to these.

[0098] The second silicon carbide-based redistribution structure 220b includes at least two fourth redistribution layers 221b. Each fourth redistribution layer 221b may include a fourth dielectric layer 2211b, a fourth metal wiring layer 2212b, and a plurality of fourth vias 2213b; each fourth via 2213b electrically connects the fourth metal wiring layers 2212b of two adjacent fourth redistribution layers 221b, and the fourth metal wiring layers 2212b and the fourth vias 2213b may be included in or surrounded in the fourth dielectric layer 2211b. The fourth dielectric layers 2211b may be stacked in the vertical direction. The fourth dielectric layer 2211b may include an insulating material, such as a photosensitive imaging dielectric resin prepared by combining epoxy resin and a photoinitiator, and may further include photosensitive polyimide and / or inorganic fillers, but is not limited thereto. The fourth metal wiring layer 2212b and the fourth vias 2213b may be provided as conductive patterns, and the conductive patterns may be positioned in the fourth dielectric layer 2211b. A fourth metal wiring layer 2212b may be provided to extend horizontally within a fourth dielectric layer 2211b. A fourth via 2213b may penetrate one or more fourth dielectric layers 2211b in a vertical direction, thereby contacting and electrically connecting with some wiring patterns in the fourth metal wiring layer 2212b. The fourth metal wiring layer 2212b has a metal linewidth or spacing ≥ 5 μm and a metal thickness ≥ 5 μm. According to some specific embodiments, the fourth via 2213b may have any suitable shape, including, for example, a tapered or cylindrical shape. The fourth metal wiring layer 2212b and the fourth via 2213b are made of conductive metals, such as copper, aluminum, titanium, tantalum, molybdenum, and their alloys, but are not limited thereto.

[0099] A silicon carbide-based metal bonding layer 230 is disposed on the side of each silicon carbide-based redistribution structure 220 away from the silicon carbide core board 210 and is electrically connected to the silicon carbide-based redistribution structure 220; two adjacent silicon carbide sub-substrates 20 are stacked and bonded through the silicon carbide-based metal bonding layer 230; adjacent silicon carbide sub-substrates 20 and glass sub-substrates 10 are stacked and bonded through the silicon carbide-based metal bonding layer 230 and the glass-based metal bonding layer 130; that is, a metal bonding layer is disposed on the lower surface (the side away from the silicon carbide core board 210) of the first silicon carbide-based redistribution structure 220a, which can be defined as the first silicon carbide-based metal bonding layer 230a; a metal bonding layer is also disposed on the upper surface (the side away from the silicon carbide core board 210) of the second silicon carbide-based redistribution structure 220b, which can be defined as the second silicon carbide-based metal bonding layer 230b. Thus, a multilayer silicon carbide sub-substrate 20 can be stacked by bonding two vertically opposite first silicon carbide-based metal bonding layers 230a and 230b; a silicon carbide sub-substrate 20 and a glass sub-substrate 10 can be stacked by bonding two vertically opposite first silicon carbide-based metal bonding layers 230a and 130b. In one or more embodiments, the silicon carbide-based metal bonding layers 230 are a plurality of bumps spaced apart on the side of the silicon carbide-based redistribution structure 220 away from the silicon carbide core board 210.

[0100] Specifically, the bumps, as a concrete implementation of the silicon carbide-based metal bonding layer 230, can adopt spherical or columnar structures. Spherical bumps include, but are not limited to, reflowable solderable materials such as solder balls and gold balls; columnar bumps are preferably copper column structures, and their height can be precisely controlled through electroplating. The spacing of the bump array must meet the alignment accuracy requirements when adjacent silicon carbide sub-substrates 20 are stacked, and when adjacent silicon carbide sub-substrates 20 are stacked with glass sub-substrates 10. The electrical connection between the bumps and the redistribution structure is achieved by fabricating a bump under-metal (UBM) layer on the outermost metal wiring layer of the redistribution structure, followed by forming the bump structure through ball placement or electroplating.

[0101] Thus, the staggered arrangement of bumps effectively releases the thermal stress generated during stacking, avoiding interface delamination caused by differences in thermal expansion coefficients. Secondly, the bump structure can compensate for the flatness error between substrates through plastic deformation during bonding, improving the bonding yield. In addition, the air gaps formed by the bump array facilitate the full filling of the filling material 30, thereby improving the heat dissipation performance of the overall structure. Compared with the traditional monolithic single-material substrate that requires the processing of multiple redistribution layers in one go, this embodiment utilizes the bonding of silicon carbide-based metal bonding layer 230 and glass-based metal bonding layer 130 to significantly reduce the process difficulty of multi-layer stacking while ensuring the reliability of electrical interconnection.

[0102] In one or more specific embodiments, the bumps on one of the silicon carbide-based redistribution structures 220 of the silicon carbide sub-substrate 20 are solder balls or gold balls, and the bumps on the other silicon carbide-based redistribution structure 220 are copper pillars. For example, the bumps on the first silicon carbide-based redistribution structure 220a are copper pillars, and the bumps on the second silicon carbide-based redistribution structure 220b are solder balls or gold balls.

[0103] Specifically, when solder balls or gold balls are used as bump materials, their low melting points allow for interconnection of the silicon carbide-based metal bonding layer 230 during bonding via hot pressing or reflow soldering. When copper pillars are used as bump materials, their high mechanical strength and excellent conductivity enable them to withstand mechanical stress during stacking and ensure high-quality electrical signal transmission. The combination of these two bump materials allows for differentiated bonding: solder balls or gold balls provide good wettability and interfacial adhesion, while copper pillars provide structural support and current carrying capacity. As a preferred embodiment, the diameter of the solder balls can be controlled between 80-250 μm, the diameter of the gold balls between 30-80 μm, and the height of the copper pillars can be set to 20-50 μm with a diameter matching the solder / gold balls.

[0104] The thickness of the silicon carbide sub-substrate 20 thus formed can be ≥150 μm. The thickness of the silicon carbide sub-substrate 20 is set to 150 μm or more primarily based on the following considerations: In multilayer interposer stacked structures, excessively thin sub-substrates are insufficient in terms of mechanical strength, thermal stability, and processing yield. Insufficient thickness may cause warping or cracking of the substrate during high-temperature bonding, affecting stacking accuracy and reliability.

[0105] In addition, power devices can be integrated into the core board or redistribution structure of the silicon carbide sub-substrate 20, and the power devices are electrically connected to the redistribution structure. Power devices (such as MOSFETs and diodes) can be directly fabricated based on the silicon carbide core board (through mature semiconductor processes such as ion implantation and high-temperature annealing, the source, drain, and gate structures of the devices are formed on the surface or inside of the core board), without the need for additional "heterogeneous integration" (such as mounting silicon-based power devices onto other substrates), reducing interface contact resistance and reliability risks; the fabricated power devices can be directly electrically connected to external circuits (such as glass sub-substrate 10 and chips) through the redistribution structure (metal wiring layer and vias of the RDL) of the silicon carbide sub-substrate 20 itself, without the need for additional wire bonding. The integration process adopts the existing method of integrating power devices on silicon carbide substrates, which will not be described in detail here.

[0106] The bonding gaps between two adjacent sub-substrates are filled with filler material 30 to form a multi-material interposer stacked substrate 1. That is, after the multi-layer sub-substrates are stacked and bonded, filler material 30 can be filled into the bonding gaps between every two adjacent sub-substrates. The filler material 30 can be provided adjacent to and surrounding each bonding bump of the metal bonding layer. The filler material 30 can be LCM (Liquid Composite Molding), LMUF (Liquid Molding Underfill), CUF (Post-Fill Underfill), high thermal conductivity filler, prepreg, or NCF film. Underfill is preferred as it eliminates air gaps at the bonding interface, forming a vertical heat dissipation channel from the chip to the substrate, improving overall heat dissipation performance; it also releases thermal stress during the stacking process, preventing interface delamination. The total thickness of the multi-material interposer stacked substrate 1 after bonding is ≤1.4 mm, balancing structural thinness and mechanical stability.

[0107] It should be noted that the number of redistribution layers in the redistribution structure of each sub-substrate (glass sub-substrate 10, silicon carbide sub-substrate 20) of the multi-material interposer stacked substrate 1 can be customized as needed to ensure that the redistribution structure includes at least two redistribution layers (e.g., 121a or 121b); and the number of redistribution layers in the redistribution structure of different sub-substrates of the multi-material interposer stacked substrate 1 can be the same or different. For example, Figure 1The multi-material interposer stacked substrate 1 shown has three sub-substrates: upper, middle, and lower. The upper sub-substrate is a silicon carbide sub-substrate 20, the middle sub-substrate is a glass sub-substrate 10, and the lower sub-substrate is a glass sub-substrate. The first silicon carbide-based redistribution structure 220a of the upper silicon carbide sub-substrate 20 has two layers of third redistribution layer 221a, and the second silicon carbide-based redistribution structure 220b has three layers of fourth redistribution layer 221b. Alternatively, the first silicon carbide-based redistribution structure 220a may have three layers of third redistribution layer 221a, and the second silicon carbide-based redistribution structure 220b may have two layers of fourth redistribution layer 221b. Or, the first silicon carbide-based redistribution structure 220a may have three layers of third redistribution layer 221a, and the second silicon carbide-based redistribution structure 220b may have three layers of fourth redistribution layer 221b. Similarly, the first glass-based redistribution structure 120a of the glass sub-substrate has two first redistribution layers 121a, and the second glass-based redistribution structure 120b has three second redistribution layers 121b; alternatively, the first glass-based redistribution structure 120a may have three first redistribution layers 121a, and the second glass-based redistribution structure 120b may have two second redistribution layers 121b; alternatively, the first glass-based redistribution structure 120a may have three first redistribution layers 121a, and the second glass-based redistribution structure 120b may have three second redistribution layers 121b. Likewise, the number of redistribution layers in the glass-based redistribution structure 120 of the lower glass sub-substrate 10 may be the same as or different from that of the middle glass sub-substrate 10. Preferably, the number of redistribution layers in the redistribution structure of each sub-substrate does not exceed four layers.

[0108] In one specific implementation, such as Figure 1 As shown, the top sub-substrate of the multi-material interposer stacked substrate 1 is a silicon carbide sub-substrate 20. In this way, the top silicon carbide sub-substrate 20 can effectively disperse the heat source of the chip and reduce thermal resistance.

[0109] Furthermore, in one or more embodiments, the glass core plates 110 of at least two glass sub-substrates 10 are made of different glass materials. Specifically, the glass material of the glass core plate 110 can be selected from at least two of borosilicate glass, aluminosilicate glass, quartz glass, or soda-lime glass. For example, the middle glass sub-substrate 10 can use borosilicate glass with a lower coefficient of thermal expansion to improve dimensional stability, while the lower glass sub-substrate 10 can use aluminosilicate glass with higher mechanical strength to enhance structural support. Thus, by using a combination of different glass materials, the performance of each glass sub-substrate 10 can be specifically optimized: glass combinations with different coefficients of thermal expansion can alleviate interlayer thermal stress, glass materials with different dielectric constants can achieve impedance matching of the signal transmission layer, and glass combinations with complementary mechanical properties can simultaneously meet the requirements of structural strength and thinness. This can solve the overall performance bottleneck problem caused by the performance limitations of a single glass material in multilayer stacked structures, and has a better comprehensive performance adaptability compared to traditional single glass material solutions. Therefore, based on the overall thermal-mechanical-electric simulation, different glass substrates can be selected for the glass sub-substrate 10 to meet the requirements of overall stress, warpage, transmission loss, processing capability, etc.

[0110] In one or more embodiments, the dielectric layers in the redistribution structures of different sub-substrates from top to bottom may also use different dielectric materials to meet requirements such as overall stress, warpage, and transmission loss. That is, the dielectric layer of the redistribution layer in the redistribution structure of the glass sub-substrates 10 is made of a different material than the dielectric layer of the redistribution layer in the redistribution structure of the silicon carbide sub-substrates 20.

[0111] Figure 2 A schematic flowchart illustrating a method for fabricating a multi-material interposer stacked substrate according to one or more embodiments is shown.

[0112] Please refer to Figure 2 This application proposes a method for fabricating a multi-material interposer stacked substrate, comprising the following steps:

[0113] S1: Provide at least one glass core board with conductive through holes and at least one silicon carbide core board;

[0114] S2: A rewiring structure is provided on each of the opposite sides of each of the core boards; each of the rewiring structures has at least two redistribution layers;

[0115] S3: Provide a metal bonding layer on the side of each redistribution structure away from the core board, and cut the wafer to form multiple sub-substrates, wherein the glass wafer is cut into a glass sub-substrate and the silicon carbide wafer is cut into a silicon carbide sub-substrate.

[0116] S4: The plurality of sub-substrates are stacked and bonded sequentially along the stacking direction using the metal bonding layer, and filler material is filled into the bonding gap between two adjacent sub-substrates.

[0117] In other words, this method enables large-scale mass production of sub-substrates by fabricating redistribution structures and metal bonding layers on large-size glass wafers and then cutting them into multiple glass sub-substrates, and by fabricating redistribution structures and metal bonding layers on large-size silicon carbide wafers and then cutting them into multiple silicon carbide sub-substrates. After cutting into multiple glass and silicon carbide sub-substrates, each sub-substrate can be independently inspected to select qualified sub-substrates for subsequent stacking. Process defects in a single sub-substrate only result in the scrapping of that sub-substrate, avoiding the failure of the entire wafer due to local defects in traditional monolithic substrates, thus improving yield. Devices can be integrated into the sub-substrates, and the integrated devices are 3D fused with the wiring layer, increasing integration density. The filling material optimizes heat dissipation and structural stability.

[0118] Therefore, by separately fabricating glass sub-substrate 10 and silicon carbide sub-substrate 20 and then stacking and bonding them, the following advantages are achieved: the sub-substrate fabrication process is independently controllable. Glass sub-substrate 10 adopts the mature laser-induced wet etching (TGV) process, while silicon carbide sub-substrate 20 combines deep reactive ion etching (DRIE) and high-temperature annealed graphene layer processes, ensuring the stable performance of each sub-substrate; the sub-substrates can be processed in parallel, significantly shortening the overall process flow time; after cutting, each sub-substrate is independently inspected, and qualified products are selected for stacking, avoiding the scrapping of the entire sheet due to local defects in traditional monolithic substrates, and significantly improving the yield; the design of integrating passive devices in glass sub-substrate 10 and power devices in silicon carbide sub-substrate 20 achieves functional modularity without occupying additional substrate surface space; during stacking, the selection and order of sub-substrates are optimized based on thermo-mechanical-electrical simulation, and with the help of high thermal conductivity filler materials, interlayer thermal stress is effectively relieved, thermal resistance is reduced, and heat dissipation efficiency is improved; the bump structure bonding can compensate for the flatness error between substrates through plastic deformation, improving bonding accuracy and reliability. Compared with the traditional single-material substrate for processing multiple RDLs in one go, the process difficulty and cost are significantly reduced.

[0119] Figures 3-20 This is a schematic cross-sectional view of a substrate illustrating the steps of a method for fabricating a multi-material interposer stacked substrate according to one or more embodiments. For brevity, descriptions overlapping with the previous figures will be omitted, and the differences will be primarily described. The glass core 110, glass-based redistribution structure 120, and glass-based metal bonding layer 130 manufactured in the method described below; the silicon carbide core 210, silicon carbide-based redistribution structure 220, and silicon carbide-based metal bonding layer 230 can be or correspond to Figure 1The glass core 110, glass-based redistribution structure 120, and glass-based metal bonding layer 130 shown herein, as well as the silicon carbide core 210, silicon carbide-based redistribution structure 220, and silicon carbide-based metal bonding layer 230, and therefore, can be used hereinafter. Figure 1 The same reference numerals are shown in the figures.

[0120] refer to Figures 3-10 First, the glass sub-substrate 10 is fabricated. For example... Figure 3 As shown, a glass core board 110 is provided. The thickness of the glass core board 110 is greater than 700 μm. The glass core board 110 is an 8-inch glass wafer. Then, the surface of the glass core board 110 is cleaned.

[0121] refer to Figure 4 The glass core plate 110 is subjected to laser-induced wet etching to obtain TGV holes. Laser induction involves using a pulsed laser to create continuous modified regions on the glass. Compared to unmodified glass, modified glass has a faster etching rate in hydrofluoric acid or alkaline systems. Based on this phenomenon, through holes, blind holes, or through grooves and blind grooves can be fabricated on the glass. Specifically, one of nanosecond lasers, picosecond lasers, or femtosecond lasers is first used to create modified regions on the glass, and then the laser-treated glass is immersed in a hydrofluoric acid solution or alkaline solution for etching, resulting in highly uniform glass through holes and blind holes. Subsequently, metal material is filled into the TGV holes to form a first conductive through hole 111. The metal material may include conductive materials, such as copper, aluminum, silver, gold, molybdenum, titanium, and combinations thereof. The upper surface of the first conductive through hole 111 may be coplanar with the upper surface of the glass core plate 110. Specifically, a seed layer can be sputtered by PVD, followed by a conductive layer electroplated with metal, and finally CMP surface treatment. In this embodiment, the first conductive via 111 is fabricated by first forming a blind via, then forming a metal material within the blind via, and finally fabricating a single-sided redistribution structure. In other embodiments, the first conductive via 111 can also be fabricated directly as a through-hole penetrating the first side 110a and the second side 110b of the glass core plate 110, then forming a metal material within the through-hole, and finally fabricating a double-sided redistribution structure simultaneously.

[0122] refer to Figure 5 The first metal wiring layer 1212a may be provided on the first side 110a of the glass core plate 110 and cover one surface of the first conductive via 111, so that the two are electrically connected.

[0123] refer to Figure 6A first dielectric layer 1211a can be laminated on the first side 110a of the glass core board 110 and on the first metal wiring layer 1212a. Then, a first via 1213a is formed in the first dielectric layer 1211a. One or more first vias 1213a can penetrate one or more first dielectric layers 1211a and contact the first metal wiring layer 1212a. Then, one or more stacked films (first dielectric layers) are laminated on the upper surface of the first dielectric layer 1211a, and the first metal wiring layer 1212a and the first via 1213a of each first redistribution layer 121a are fabricated accordingly to complete the fabrication of the first glass substrate redistribution structure 120a. The first dielectric layer 1211a can be a wet film, a dry film, or a non-photosensitive material. The wet film is coated, baked, exposed, and developed. The dry film is applied by roller or vacuum lamination, baked, exposed, and developed. The non-photosensitive material is applied by roller or vacuum lamination, baked, and laser drilling.

[0124] Subsequently, a first glass-based metal bonding layer 130a is fabricated on the outer surface of the first redistribution layer 121a, the outermost layer of the first glass-based redistribution structure 120a. The fabrication of the first glass-based metal bonding layer 130a can involve forming a passivation layer, a metal under bump (UBM) layer, and a conductive layer on the first redistribution layer 121a, followed by forming bumps, such as solder balls or gold balls, on the conductive layer.

[0125] refer to Figure 7 Next, a temporary bonding adhesive is applied to the temporary carrier and baked to temporarily bond with the first glass-based metal bonding layer 130a of the glass core board 110, so as to temporarily protect the first glass-based metal bonding layer 130a and the first glass-based redistribution structure 120a on that side.

[0126] refer to Figure 8 Then, the glass core plate 110 with the temporary carrier plate is flipped over, and the back side of the glass core plate 110 is thinned to expose the first conductive through hole 111.

[0127] Next, refer to Figure 9A second glass-based rewiring structure 120b is fabricated on the second side 110b of the glass core board 110. Specifically, a second metal wiring layer 1212b is first provided on the second side 110b of the glass core board 110, covering one surface of the first conductive via 111, thereby electrically connecting the two. Then, a second dielectric layer 1211b is laminated onto the second side 110b of the glass core board 110 and the second metal wiring layer 1212b, and subsequently, a second via 1213b is formed in the second dielectric layer 1211b. One or more second vias 1213b can penetrate one or more second dielectric layers 1211b and contact the second metal wiring layer 1212b. Subsequently, one or more stacked films (second dielectric layers) are laminated on the upper surface of the second dielectric layer 1211b, and correspondingly, the second metal wiring layer 1212b and the second via 1213b of the second redistribution layer 121b are fabricated to complete the fabrication of the second glass-based redistribution structure 120b. The second dielectric layer 1211b can be a wet film, a dry film, or a non-photosensitive material. The wet film process involves coating, baking, exposure, and development; the dry film process involves roller or vacuum lamination, baking, exposure, and development; and the non-photosensitive material process involves roller or vacuum lamination, baking, and laser drilling.

[0128] Then, a second glass-based metal bonding layer 130b is fabricated on the outer surface of the second redistribution layer 121b, the outermost layer of the second glass-based redistribution structure 120b. The fabrication of the second glass-based metal bonding layer 130b can be achieved by forming a passivation layer on the second redistribution layer 121b, followed by window electroplating to form bumps, such as copper pillars.

[0129] Then, refer to Figure 10 Laser debonding is used to remove the temporary carrier board, and then the wafer is cut to form multiple glass sub-substrates 10.

[0130] Additionally, when making such Figure 11When the glass sub-substrate 10 is used, a passive device layer 140, such as a MIM capacitor, can be provided on the first metal wiring layer 1212a. The electrode plate below the MIM capacitor is in contact with the first metal wiring layer 1212a. Specifically, the MIM capacitor can be fabricated by physical vapor deposition (PVD) or chemical mechanical polishing (CMP) processes to create flat electrodes, and by using plasma-enhanced chemical vapor deposition (PECVD) and deep reactive ion etching (DRIE) processes to create a high-precision insulating layer. Preferably, the upper and lower electrode materials of the MIM capacitor can be aluminum + aluminum or aluminum + copper. The aluminum substrate is fabricated by physical vapor deposition (PVD) and deep reactive ion etching (DRIE) processes; the copper substrate is fabricated by photolithography + electroplating + CMP; the dielectric layer material is silicon nitride, and a high-precision insulating layer is created using plasma-enhanced chemical vapor deposition (PECVD) and deep reactive ion etching (DRIE) processes. The MIM size range is: 50 μm × 50 μm × 3 μm to 500 μm × 500 μm × 5 μm.

[0131] In one or more embodiments, each glass sub-substrate 10 of the multi-material interposer stacked substrate 1 can be made of different glass substrates; thus, when manufacturing each glass sub-substrate 10, glass core boards of different glass materials can be used to perform the above-mentioned processing steps, thereby obtaining multiple glass sub-substrates 10 of various glass materials. Then, based on the thermo-mechanical-electrical simulation of the overall structure of the multi-material interposer stacked substrate 1, the selection and matching of each layer of glass sub-substrate 10 can be performed, and stacking and bonding can be carried out. The multi-material interposer stacked substrate 1 obtained in this way can meet the requirements of overall stress, warpage, transmission loss, processing capability, etc.

[0132] Similarly, refer to Figures 12-19 To fabricate a silicon carbide sub-substrate 20. For example... Figure 12 As shown, a silicon carbide core board 210 is provided. The silicon carbide core board 210 is a 6 / 8-inch silicon carbide wafer. Then, the surface of the silicon carbide core board 210 is cleaned.

[0133] refer to Figure 13The silicon carbide core board 210 is patterned using photolithography, and TCV holes are obtained through deep reactive ion etching. After resist removal, a single-crystal graphene layer is formed by high-temperature annealing at 1250℃-1450℃. Subsequently, metal material is filled into the TCV holes to form a second conductive via 211. The metal material may include conductive materials, such as copper, aluminum, silver, gold, molybdenum, titanium, and combinations thereof. The upper surface of the second conductive via 211 may be coplanar with the upper surface of the silicon carbide core board 210. Specifically, a seed layer can be sputtered by PVD, followed by metal electroplating of a conductive layer, and finally surface CMP. In this embodiment, the fabrication of the second conductive via 211 involves first forming blind vias, then forming metal material within the blind vias, and finally fabricating a one-sided redistribution structure. In other embodiments, the second conductive via 211 can be directly fabricated as a via penetrating the third side 210a and the fourth side 210b of the silicon carbide core board 210, and then a metal material can be formed in the via, and a double-sided redistribution structure can be fabricated at the same time.

[0134] refer to Figure 14 The third metal wiring layer 2212a can be provided on the third side 210a of the silicon carbide core board 210 and covers one surface of the second conductive via 211, so that the two are electrically connected.

[0135] refer to Figure 15 The third dielectric layer 2211a can be laminated on the third side 210a and the third metal wiring layer 2212a of the silicon carbide core board 210, and then a third via 2213a is formed in the third dielectric layer 2211a. One or more third vias 2213a can penetrate one or more third dielectric layers 2211a and contact the third metal wiring layer 2212a. Then, one or more stacked films (first dielectric layers) are laminated on the upper surface of the third dielectric layer 2211a, and the third metal wiring layer 2212a and the third via 2213a of each third redistribution layer 221a are fabricated accordingly to complete the fabrication of the first silicon carbide-based redistribution structure 220a. The third dielectric layer 2211a can be made of wet film, dry film, or non-photosensitive material. The wet film is made of coating, baking, exposure, and development process. The dry film is made of roller or vacuum lamination, baking, exposure, and development process. The non-photosensitive material is made of roller or vacuum lamination, baking, and laser drilling process.

[0136] Subsequently, a first silicon carbide-based metal bonding layer 230a is fabricated on the outer surface of the third redistribution layer 221a, the outermost layer of the first silicon carbide-based redistribution structure 220a. The fabrication of the first silicon carbide-based metal bonding layer 230a can involve forming a passivation layer, a metal under bump (UBM) layer, and a conductive layer on the third redistribution layer 221a, followed by forming bumps, such as solder balls or gold balls, on the conductive layer.

[0137] refer to Figure 16Next, a temporary bonding adhesive is applied to the temporary carrier board and baked to temporarily bond it to the first silicon carbide-based metal bonding layer 230a of the silicon carbide core board 210, so as to temporarily protect the first silicon carbide-based metal bonding layer 230a and the first silicon carbide-based redistribution structure 220a on that side.

[0138] refer to Figure 17 Then, the silicon carbide core board 210 with the temporary carrier board is flipped over, and the back side of the silicon carbide core board 210 is thinned to expose the second conductive through hole 211.

[0139] Next, refer to Figure 18 A second silicon carbide-based redistribution structure 220b is fabricated on the fourth side 210b of the silicon carbide core board 210. Specifically, a fourth metal wiring layer 2212b is first provided on the fourth side 210b of the silicon carbide core board 210, covering one surface of the second conductive via 211, thereby electrically connecting the two. Then, a fourth dielectric layer 2211b is laminated onto the fourth side 210b and the fourth metal wiring layer 2212b of the silicon carbide core board 210, and a fourth via 2213b is formed in the fourth dielectric layer 2211b. One or more fourth vias 2213b can penetrate one or more fourth dielectric layers 2211b and contact the fourth metal wiring layer 2212b. Subsequently, one or more stacked films (second dielectric layers) are laminated on the upper surface of the fourth dielectric layer 2211b, and the fourth metal wiring layer 2212b and the fourth via 2213b of the fourth redistribution layer 221b of each layer are fabricated accordingly to complete the fabrication of the second silicon carbide-based redistribution structure 220b. The fourth dielectric layer 2211b can be a wet film, a dry film, or a non-photosensitive material. The wet film process involves coating, baking, exposure, and development; the dry film process involves roller or vacuum lamination, baking, exposure, and development; and the non-photosensitive material process involves roller or vacuum lamination, baking, and laser drilling.

[0140] Then, a second silicon carbide-based metal bonding layer 230b is fabricated on the outer surface of the fourth redistribution layer 221b, the outermost layer of the second silicon carbide-based redistribution structure 220b. The fabrication of the second silicon carbide-based metal bonding layer 230b can be achieved by forming a passivation layer on the fourth redistribution layer 221b, followed by window electroplating to form bumps, such as copper pillars.

[0141] Then, refer to Figure 19 Laser debonding is used to remove the temporary substrate, and then the wafer is cut to form multiple silicon carbide sub-substrates 20.

[0142] Next, according to design requirements, the glass sub-substrate 10 and the silicon carbide sub-substrate 20 are aligned and thermo-bonded using metal bonding layers, thus completing the multi-layer stacking process, for example... Figure 20The first glass-based metal bonding layer 130a of the middle glass sub-substrate 10 and the second glass-based metal bonding layer 130b of the lower glass sub-substrate 10 are aligned and thermo-pressed together. Then, the second glass-based metal bonding layer 130b of the middle glass sub-substrate 10 is aligned and thermo-pressed together with the second silicon carbide-based metal bonding layer 230b of the upper silicon carbide sub-substrate 20 to form... Figure 20 The stacked bodies. The hot-press bonding temperature is 250-300℃; the pressure is 5-10MPa; and the time is 5-10min.

[0143] In addition, the number of stacked layers can be designed according to actual needs.

[0144] Finally, refer to Figure 1 The bonding gaps between two adjacent sub-substrates of the above-mentioned stack are filled with material 30 to form a multi-material interposer stack substrate 1. For example, a certain amount of adhesive is applied to the bottom edge of the substrate using the underfill method. After the adhesive fills the entire gap between the substrates under capillary action, it is thermo-cured to make the adhesive solid, thereby achieving the functions of bonding / supporting / protecting.

[0145] As can be seen from the above, the multiple glass sub-substrates 10 and multiple silicon carbide sub-substrates 20 of the multi-material interposer stacked substrate 1 can be processed in parallel, shortening the process flow. Furthermore, each glass sub-substrate 10 contains a glass core plate 110, and each silicon carbide sub-substrate 20 contains a silicon carbide core plate 210, which can reduce the warping of the overall structure. Adjacent sub-substrates are aligned and bonded through a metal bonding layer, which can improve the product yield.

[0146] In one or more embodiments, the redistribution structures of each glass sub-substrate 10 and each silicon carbide sub-substrate 20 of the multi-material interposer stacked substrate 1 can be fabricated using different insulating materials for the dielectric layer. Thus, when fabricating each glass sub-substrate 10 and each silicon carbide sub-substrate 20, multiple glass core boards of the same glass material and multiple silicon carbide core boards of the same silicon carbide material can be used for processing. During the fabrication of the redistribution structure, each core board uses a different insulating material to fabricate the dielectric layer of the redistribution structure, thereby obtaining multiple glass sub-substrates 10 and multiple silicon carbide sub-substrates 20 with various dielectric layer materials. Subsequently, based on the thermo-mechanical-electrical simulation of the overall structure of the multi-material interposer stacked substrate 1, the selection and combination of each glass sub-substrate 10 and silicon carbide sub-substrate 20 can be performed for stacking and bonding. The resulting multi-material interposer stacked substrate 1 can meet requirements such as overall stress, warpage, transmission loss, and processing capability.

[0147] refer to Figure 21According to one or more embodiments of the present invention, a semiconductor packaging structure is also proposed, comprising the multi-material interposer stacked substrate 1 described above and a semiconductor chip. The semiconductor chip may include a high-bandwidth memory (HBM) 2 and a graphics processing unit (GPU) chip 3; both the HBM 2 and the GPU chip 3 are flip-chip mounted on the uppermost silicon carbide sub-substrate 20. However, the embodiments are not limited to this, and semiconductor chips other than SOCs or HBMs may be provided, such as logic chips: central processing units (CPUs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), or memory chips: dynamic random access memory (DRAM) chips and NAND chips.

[0148] The high-bandwidth memory (HBM) 2 is a stacked multilayer chip, with an underfill adhesive filling the space between adjacent chip layers. Additionally, an underfill adhesive is also filled between the HBM 2 / GPU chip 3 and the multi-material interposer stack substrate 1. The underfill layer may include epoxy resin or a mixture of two or more silicon materials. The side of the multi-material interposer stack substrate 1 facing away from the semiconductor chips is connected to a PCB board, enabling electrical interconnection with external circuitry.

[0149] When the top sub-substrate is a silicon carbide sub-substrate 20, and the middle and bottom sub-substrates are both glass sub-substrates 10, the warpage of the multi-material interposer stacked substrate 1 on the PCB is compared with the warpage of a traditional multilayer board (i.e., multiple RDLs are fabricated on a single glass core board), as shown below. Figure 22 and Figure 23 As shown, the overall warpage of the multi-material interposer stacked substrate 1 in this embodiment after being mounted is approximately 101 μm; the overall warpage of a conventional multilayer board after being mounted is approximately 118 μm. The warpage reduction of the multi-material interposer stacked substrate 1 in this embodiment is approximately 14%. Furthermore, heat dissipation simulations were performed on the multi-material interposer stacked substrate 1 and the conventional multilayer board, such as... Figure 24 As shown, the temperature of the heat source position of the multi-material interposer stacked substrate 1 in this embodiment (that is, the temperature of the top silicon carbide 20 position of the flip chip) is 45.18°C, while the temperature of the heat source position of the conventional multilayer board is 52.88°C. The heat dissipation effect of the multi-material interposer stacked substrate 1 in this embodiment is improved by 14.6%.

[0150] Therefore, this semiconductor packaging structure utilizes the three-dimensional stacking of multi-material interposers and device integration to achieve high-density heterogeneous integration and reduce package size; the integrated passive and power devices can replace external components, reducing the number of external components in the package; the silicon carbide sub-substrate 20 and the filling material 30 work together to improve heat dissipation efficiency and suppress chip heat accumulation, solving the three core pain points of high bandwidth, high thermal management, and high-density integration in HBM and GPU interconnection, and is suitable for high-performance computing fields such as AI servers and high-end graphics cards.

[0151] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0152] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0153] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0154] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0155] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0156] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A multi-material interposer stacked substrate, characterized in that, include: At least one glass sub-substrate and at least one silicon carbide sub-substrate are disposed along the stacking direction, wherein both the glass sub-substrate and the silicon carbide sub-substrate comprise: The core board has a through hole, which is filled with a conductive material to form a conductive through hole; Two redistribution structures are formed on opposite sides of the core board, corresponding to each other, and are electrically interconnected through the conductive vias; each redistribution structure has at least two redistribution layers; A metal bonding layer is disposed on the side of each redistribution structure opposite to the core board and is electrically connected to the redistribution structure; The core plate of the glass sub-substrate is made of glass, and the core plate of the silicon carbide sub-substrate is made of silicon carbide. Along the stacking direction, any two adjacent sub-substrates are stacked and bonded through the metal bonding layer, and the bonding gap between the two adjacent sub-substrates is filled with filler material to form the multi-material interposer stacked substrate; wherein, the type combination of the two adjacent sub-substrates is selected from one of the following: (a) a silicon carbide sub-substrate and a glass sub-substrate; (b) two glass sub-substrates; (c) two silicon carbide sub-substrates; and at least one of the type combinations of the two adjacent sub-substrates is (a). The metal bonding layer consists of multiple bumps spaced apart on the side of the redistribution structure opposite to the core board; one of the bumps on the redistribution structure of the sub-substrate is a solder ball or a gold ball, and the other bump on the redistribution structure is a copper pillar. The core plates of at least two of the glass sub-substrates are made of different glass materials; in the redistribution structures of at least two of the glass sub-substrates, the dielectric layer of the redistribution layer is made of different materials; the dielectric layer of the redistribution layer in the redistribution structure of the glass sub-substrates is made of a different material than the dielectric layer of the redistribution layer in the redistribution structure of the silicon carbide sub-substrates.

2. The multi-material interposer stacked substrate as described in claim 1, characterized in that, The top sub-substrate of the multi-material interposer stacked substrate is the silicon carbide sub-substrate.

3. The multi-material interposer stacked substrate as described in claim 1, characterized in that, The redistribution structure of the glass sub-substrate integrates a passive device layer, which includes capacitors, inductors, or resistors. The passive device layer is included in at least one redistribution layer of the redistribution structure or between two adjacent redistribution layers, and is electrically connected to the redistribution layer.

4. The multi-material interposer stacked substrate as described in claim 2, characterized in that, Power devices are integrated in the core board or redistribution structure of the silicon carbide sub-substrate, and the power devices are electrically connected to the redistribution structure.

5. The multi-material interposer stacked substrate as described in claim 3, characterized in that, The redistribution layer includes a dielectric layer, a metal wiring layer, and a plurality of vias; the vias electrically connect the metal wiring layers of two adjacent redistribution layers, the passive device layer is included in the dielectric layer, and the passive device is electrically connected to the metal wiring layer and the vias.

6. The multi-material interposer stacked substrate as described in claim 1, characterized in that, The filler material includes LCM material, LMUF material, CUF material, thermally conductive adhesive, prepreg, or NCF film.

7. A method for manufacturing a multi-material interposer stacked substrate according to any one of claims 1-6, characterized in that, Includes the following steps: Provide at least one glass core board with conductive through holes and at least one silicon carbide core board; A rewiring structure is provided on each of the opposite sides of each of the core boards; each of the rewiring structures has at least two redistribution layers; A metal bonding layer is provided on the side of each redistribution structure away from the core board, and the wafer is cut to form multiple sub-substrates, wherein the glass wafer is cut to form a glass sub-substrate, and the silicon carbide wafer is cut to form a silicon carbide sub-substrate. The plurality of sub-substrates are sequentially stacked and bonded along the stacking direction using the metal bonding layer, and the bonding gap between two adjacent sub-substrates is filled with filler material.

8. The method for fabricating a multi-material interposer stacked substrate as described in claim 7, characterized in that, Stacking and bonding the plurality of sub-substrates using the metal bonding layer includes stacking and bonding two adjacent glass sub-substrates using the metal bonding layer, and stacking and bonding adjacent glass sub-substrates and silicon carbide sub-substrates through the metal bonding layer using the metal bonding layer; the top sub-substrate of the multi-material interposer stacked substrate is the silicon carbide sub-substrate.

9. The method for fabricating a multi-material interposer stacked substrate as described in claim 8, characterized in that, A redistribution structure is provided on each of the opposite sides of each of the core boards; each redistribution structure has at least two redistribution layers including: A redistribution structure is provided on each of the opposite sides of the glass core board, and a passive device layer is provided in at least one of the redistribution structures; each redistribution structure has at least two redistribution layers; the passive device layer is provided in at least one redistribution layer of the redistribution structure or between two adjacent redistribution layers.

10. The method for fabricating a multi-material interposer stacked substrate as described in claim 9, characterized in that, The provision of a single wiring structure includes providing a dielectric layer, a metal wiring layer and a plurality of vias, and the provision of a passive device layer includes providing the passive device layer in the dielectric layer.

11. The method for fabricating a multi-material interposer stacked substrate as described in claim 10, characterized in that, The passive device layer consists of multiple passive devices arranged in a spaced array on the same horizontal plane, and each passive device is connected to the metal wiring layer and the multiple vias.

12. The method for fabricating a multi-material interposer stacked substrate as described in claim 7, characterized in that, Power devices are integrated in the core board or redistribution structure of the silicon carbide sub-substrate, and the power devices are electrically connected to the redistribution structure of the silicon carbide sub-substrate.

13. The method for fabricating a multi-material interposer stacked substrate as described in claim 7, characterized in that, The metal bonding layer includes a plurality of spaced bumps that are electrically connected to the redistribution structure on the side of the redistribution structure opposite to the core board.

14. The method for fabricating a multi-material interposer stacked substrate as described in claim 7, characterized in that, The provision of a glass core board with conductive vias includes providing glass core boards of at least two different glass materials, and forming the conductive vias on each of the glass core boards; Furthermore, each glass core board having the conductive via is provided with the redistribution structure and the metal bonding layer, and each wafer is cut to form at least two types of glass sub-substrates; The at least two types of glass sub-substrates and the silicon carbide sub-substrates are stacked and bonded using the metal bonding layer.

15. The method for fabricating a multi-material interposer stacked substrate as described in claim 7, characterized in that, The filler material includes LCM material, LMUF material, CUF material, thermally conductive adhesive, prepreg, or NCF film.

16. A semiconductor packaging structure, characterized in that, The substrate includes a multi-material interposer stacked substrate as described in any one of claims 1-6, or a multi-material interposer stacked substrate prepared by the manufacturing method described in any one of claims 7-15; A semiconductor chip is flip-chip mounted on the multi-material interposer stacked substrate and electrically connected to the metal bonding layer of the uppermost sub-substrate. as well as Bottom filler adhesive is used to fill the space between the semiconductor chip and the uppermost sub-substrate.

17. The semiconductor packaging structure as described in claim 16, characterized in that, The semiconductor chip includes a high-bandwidth memory (HBM) and a graphics processing unit (GPU) chip, both of which are flip-chip mounted on the uppermost sub-substrate. The side of the multi-material interposer stacked substrate facing away from the semiconductor chip is connected to the PCB board to achieve electrical interconnection with external circuits.

18. The semiconductor packaging structure as described in claim 17, characterized in that, The uppermost sub-substrate is a silicon carbide sub-substrate.

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