Glass interposer stack substrate and semiconductor package structure

Abstract

The application discloses a glass interposer stacked substrate and a semiconductor packaging structure, the glass interposer stacked substrate splits a traditional single substrate into independent glass sub-substrates with different glass materials, stacks through metal bonding and fills a filling material to form an interposer substrate integrated with multiple glass materials; in this way, the sub-substrates can be processed in parallel, the multilayer stacking process is simplified, the risk of alignment deviation and lamination defects is reduced, the manufacturing yield is significantly improved, and the processing time is shortened; high-density integration is realized through multilayer sub-substrate stacking, and based on the differences in thermal-electric-force characteristics of different chips in an AI module, glass substrates with different characteristics are adopted for glass sub-substrates at different levels, so that the problems of the prior art, such as complex multilayer process of a single glass material substrate, inability to meet the thermal-electric-force requirements of multiple chips, high signal loss, poor heat dissipation and high processing difficulty, are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor advanced packaging, and in particular to a glass interposer stacked substrate and a semiconductor packaging structure. BACKGROUND

[0002] Under the background of the rapid increase in demand for computing power of AI and high-performance computing chips, the heat density and signal transmission rate of chips such as GPU and HBM have been significantly improved. The traditional glass interposer substrate adopts a single substrate material and a multi-layer RDL wiring structure, which is difficult to take into account the differences in thermal-electric-mechanical properties of multiple chips, and faces many challenges such as low multi-layer wiring yield, high processing cost, thermal stress mismatch, signal transmission loss, and inability to meet the higher speed signal requirements between HBM and GPU. The multi-layer board formed by the multi-layer RDL wiring structure faces great challenges in terms of stacking alignment, interlayer thickness uniformity, interlayer interconnection precision control, and heat dissipation due to its extremely high lamination complexity. Any slight interlayer alignment deviation or lamination defect can cause signal integrity problems or internal short circuits. In addition, the difficulty of hole forming and electroplating processes increases exponentially, which significantly reduces the overall manufacturing yield compared to conventional layer boards. The technical scheme and route need to be improved.

[0003] The information disclosed in this background section is known to the inventors before the implementation of the present disclosure or is acquired in the process of implementing the present disclosure. Therefore, it may contain information that does not form the prior art known to the public. SUMMARY

[0004] To solve the above problems, the present application provides a glass interposer stacked substrate and a semiconductor packaging structure. By decomposing a single layer substrate into independent sub-substrates of different glass materials, modularizing the sub-substrate design and parallel processing, and then stacking multiple sub-substrates, the problems of multi-layer process complexity, inability to take into account the thermal-electric-mechanical requirements of multiple chips, high signal loss, poor heat dissipation, and high processing difficulty of single glass material substrates in the prior art are solved.

[0005] According to one or more embodiments, a glass interposer stacked substrate is provided, comprising:

[0006] At least three glass sub-substrates arranged in a stacking direction, each of the glass sub-substrates comprising:

[0007] A glass core plate having a glass through hole filled with a conductive material to form a conductive through hole;

[0008] Two redistribution structures are formed on opposite sides of the glass core board in one-to-one correspondence and are electrically interconnected through the conductive through holes; each of the redistribution structures has at least two redistribution layers, the redistribution layers including dielectric layers, metal wiring layers and a plurality of vias; the vias electrically connect the metal wiring layers of adjacent two of the redistribution layers;

[0009] A metal bonding layer is arranged on a side of each of the redistribution structures away from the glass core board and is electrically connected with the redistribution structure;

[0010] In the stacking direction, the glass core board of the glass sub-substrate on the top layer has a coefficient of thermal expansion less than 5 ppm / ℃ and a thermal conductivity of 1.2 W / (m·K), and the glass sub-substrate adopts silver metal wiring; the glass core board of the glass sub-substrate on the bottom layer has a coefficient of thermal expansion greater than 5 ppm / ℃, and the line width of the metal wiring layer of at least one redistribution structure of the glass sub-substrate gradually widens from the conductive through hole to the metal bonding layer; the glass core board of the glass sub-substrate between the top layer and the bottom layer has a dielectric constant of 4-7 and a dielectric loss of 0.007-0.009, and the glass sub-substrate adopts silver metal wiring;

[0011] In the stacking direction, any two adjacent glass sub-substrates are stacked and bonded through the metal bonding layer, and the bonding gap between the two adjacent glass sub-substrates is filled with a filling material to form the glass interposer stacked substrate.

[0012] The glass interposer stacked substrate according to the present application first splits a conventional single-material substrate into independent glass sub-substrates of different glass materials, and forms an interposer substrate integrated with multiple glass materials by metal bonding and filling of a filling material; in this way, the sub-substrates can be processed in parallel, simplifying the multi-layer stacking process, reducing the risk of alignment deviation and lamination defects, significantly improving the manufacturing yield and shortening the processing time; high-density integration is achieved by stacking multiple sub-substrates.

[0013] Secondly, based on the thermal-electric-force characteristic differences of different chips in the AI module, different levels of glass sub-substrate adopt different characteristic glass substrates, solving the defect that "single substrate cannot meet the needs of multiple chips"; for example, the top glass sub-substrate adopts low CTE glass to match the silicon chip, reduce the thermal stress between the chip and the substrate, and the top glass sub-substrate has good heat conduction performance, which can solve the local high heat problem after the flip of GPU / HBM. Furthermore, the top glass sub-substrate adopts silver metal wiring to reduce the loss of high-frequency signal transmission of the device, and further improve the thermal conductivity of the glass sub-substrate of this layer; the middle glass sub-substrate adopts a low dielectric loss glass substrate, which cooperates with the silver metal wiring to meet the integrity requirements of high-speed signal transmission between HBM and GPU above 2 Gbps, avoiding signal attenuation problems; the bottom glass sub-substrate adopts a medium CTE glass to relieve the overall thermal stress after multi-layer stacking, avoid substrate warping after PCB mounting, and the gradually widened metal wiring layer of at least one heavy wiring structure of the bottom glass sub-substrate can avoid metal fatigue caused by sudden changes in line width.

[0014] In addition, the high-thermal-conductivity material filled between adjacent glass sub-substrates eliminates the air gap at the bonding interface, improves the heat dissipation efficiency and structural reliability, and meets the high-density integration and high-thermal-management requirements of AI chips. Sub-substrate independent detection and screening can avoid local defects of traditional whole substrates leading to whole failure and reduce costs.

[0015] In addition, the glass interposer stacked substrate provided in the above-mentioned application can have the following additional technical features:

[0016] Optionally, at least one heavy wiring structure of the bottom glass sub-substrate has a first dielectric layer formed of a first dielectric material and a second dielectric layer formed of a second dielectric material, wherein the first dielectric layer is an epoxy material and is arranged adjacent to the glass core plate; and the second dielectric layer is a siloxane film and is arranged on the outermost metal wiring layer of the heavy wiring structure.

[0017] Optionally, along the stacking direction, the line width of the metal wiring layer of the heavy wiring structure of the top glass sub-substrate is 2 μm, and the line spacing is 2 μm; the line width of the heavy wiring structure of the bottom glass sub-substrate is 5 μm-10 μm, and the line spacing is 5 μm-10 μm; the line width of the metal wiring layer of the heavy wiring structure of the glass sub-substrate between the top and bottom layers is 3 μm-5 μm, and the line spacing is 3 μm-5 μm; and the metal wiring layer of the heavy wiring structure is arranged from dense to sparse from the top glass sub-substrate to the bottom glass sub-substrate.

[0018] Optionally, the glass core plate of the top glass sub-substrate is borosilicate glass, and the borosilicate glass is doped with Al2O3 thermal conductive particles.

[0019] Optionally, the conductive via and the metal wiring layer of the glass sub-substrate of the top layer each has a seed layer and a conductive layer covering the seed layer, the seed layer includes a titanium layer, or a titanium layer and a copper layer; and the conductive layer is a silver layer.

[0020] Optionally, the conductive via and the metal wiring layer of the glass sub-substrate between the top layer and the bottom layer each has a seed layer and a conductive layer covering the seed layer, the seed layer includes a titanium layer, or a titanium layer and a copper layer; and the conductive layer is a silver layer.

[0021] Optionally, the metal bonding layer is a plurality of bumps arranged at intervals on the redistribution structure away from the glass core substrate.

[0022] Further, the bump on one of the redistribution structures of the glass sub-substrate is a tin ball or a gold ball, and the bump on the other redistribution structure is a copper pillar.

[0023] Optionally, the filling material is an LCM material, an LMUF material, a CUF material, a thermal conductive adhesive, a prepreg, or an NCF film.

[0024] According to another aspect of one or more embodiments, there is provided a method for manufacturing a glass interposer stack substrate, comprising the following steps:

[0025] providing at least three glass core substrates with conductive vias;

[0026] providing a redistribution structure on each of the opposite sides of the glass core substrates; each of the redistribution structures has at least two redistribution layers; the redistribution layers include dielectric layers, metal wiring layers, and a plurality of vias; the vias electrically connect the metal wiring layers of two adjacent redistribution layers;

[0027] providing a metal bonding layer on the side of each of the redistribution structures away from the glass core substrate, and cutting the wafer to form at least three glass sub-substrates;

[0028] stack bonding the at least three glass sub-substrates in a stacking direction by using the metal bonding layer, and filling a filling material in the bonding gap between two adjacent glass sub-substrates to form the glass interposer stack substrate;

[0029] The glass core plate of the glass sub-substrate of the top layer has a thermal expansion coefficient of less than 5 ppm / ℃ and a thermal conductivity of 1.2 W / (m·K) along the stacking direction, and the glass sub-substrate adopts silver metal wiring; the glass core plate of the glass sub-substrate of the bottom layer has a thermal expansion coefficient of greater than 5 ppm / ℃, and the line width of the metal wiring layer of at least one heavy wiring structure of the glass sub-substrate gradually widens from the conductive via to the metal bonding layer; the glass core plate of the glass sub-substrate between the top layer and the bottom layer has a dielectric constant of 4-7 and a dielectric loss of 0.007-0.009, and the glass sub-substrate adopts silver metal wiring.

[0030] According to the manufacturing method of the glass interposer stacked substrate, the following advantages are achieved: the manufacturing process of the sub-substrate is independently controllable, parallel processing is avoided, and the risk of lamination defects in traditional one-time processing of multi-layer boards is avoided, the overall process flow time is greatly shortened, independent detection is performed on the single sub-subboard after cutting, and the qualified products are stacked to avoid the whole board being scrapped due to local defects of the traditional whole board, and the yield is significantly improved; the functional modular design enables the product to be iterated by replacing only the target sub-substrate, for example, by replacing the combination and stacking order of different glass sub-substrates according to different flip-chip.

[0031] According to one or more embodiments, a semiconductor package structure is provided, including the above-mentioned glass interposer stacked substrate, or the glass interposer stacked substrate manufactured by the above-mentioned manufacturing method.

[0032] A semiconductor chip is flip-chip mounted on the glass interposer stacked substrate and electrically connected to the metal bonding layer of the uppermost glass sub-substrate; and

[0033] A bottom filling glue is filled between the semiconductor chip and the uppermost glass sub-substrate.

[0034] Optionally, the semiconductor chip includes a high-bandwidth memory (HBM) and a graphics processing unit (GPU) chip, both of which are flip-chip mounted on the uppermost glass sub-substrate; and the side of the glass interposer stacked substrate away from the semiconductor chip is connected to a PCB board to realize electrical interconnection with an external circuit.

[0035] After the above-mentioned scheme is adopted, the present application has the following advantages:

[0036] 1. Manufacturing optimization: parallel processing of multiple glass material sub-substrates improves yield, shortens time, and realizes high-density integration; independent detection and screening of sub-substrates avoid local defects that cause the whole board to fail, thereby reducing costs.

[0037] 2. Performance adaptation: different properties of glass are used in different layers (low CTE / high thermal conductivity / silver wiring in the top layer, low dielectric loss in the middle layer, and medium CTE / gradual wiring in the bottom layer), which takes into account the thermal-electric-mechanical requirements of multiple chips and solves the defects that cannot be adapted by a single substrate. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 A cross-sectional schematic view of a glass interposer stacked substrate according to an embodiment of the present application;

[0039] Figure 2 A flowchart of a manufacturing method of a glass interposer stacked substrate according to an embodiment of the present application;

[0040] Figures 3-19 A cross-sectional schematic view of a substrate at each step of a manufacturing method of a glass interposer stacked substrate according to an embodiment of the present application;

[0041] Figure 20 A cross-sectional schematic view of a semiconductor package structure according to an embodiment of the present application;

[0042] Figure 21 A warpage cloud map of a glass interposer stacked substrate according to an embodiment of the present application, Warpage: 82 μm;

[0043] Figure 22 A warpage cloud map of a traditional multilayer board, Warpage: 122 μm.

[0044] REFERENCE NUMERALS:

[0045] Glass interposer stacked substrate 1;

[0046] Middle layer glass sub-substrate 10, middle layer glass core substrate 110, first side 110a, second side 110b, middle layer conductive via 111, middle layer redistribution structure 120, middle layer first redistribution structure 120a, first redistribution layer 121a, first dielectric layer 1211a, first metal wiring layer 1212a, first via 1213a, middle layer second redistribution structure 120b, second redistribution layer 121b, second dielectric layer 1211b, second metal wiring layer 1212b, second via 1213b, middle layer first metal bonding layer 130a, middle layer second metal bonding layer 130b;

[0047] Top layer glass sub-substrate 20, top layer glass core substrate 210, top layer conductive via 211, top layer redistribution structure 220, top layer first redistribution structure 220a, third redistribution layer 221a, third dielectric layer 2211a, third metal wiring layer 2212a, third via 2213a, top layer second redistribution structure 220b, fourth redistribution layer 221b, fourth dielectric layer 2211b, fourth metal wiring layer 2212b, fourth via 2213b, top layer first metal bonding layer 230a, top layer second metal bonding layer 230b;

[0048] Bottom layer glass sub-substrate 30, bottom layer glass core substrate 310, bottom layer conductive via 311, bottom layer redistribution structure 320, bottom layer first redistribution structure 320a, fifth redistribution layer 321a, fifth dielectric layer 3211a, fifth metal wiring layer 3212a, fifth via 3213a, bottom layer second redistribution structure 320b, sixth redistribution layer 321b, sixth dielectric layer 3211b, sixth metal wiring layer 3212b, sixth via 3213b, bottom layer first metal bonding layer 330a, bottom layer second metal bonding layer 330b;

[0049] Filler material 40;

[0050] High bandwidth memory HBM 2;

[0051] Graphics processing unit GPU chip 3. DETAILED DESCRIPTION

[0052] Embodiments of the present application are described below in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the drawings are exemplary and are intended to explain the present application, and should not be understood as limiting the present application.

[0053] For a better understanding of the above technical solutions, the exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough and complete understanding of the present application and to convey the scope of the present application to those skilled in the art.

[0054] It should be noted that in this document, the direction parallel to the main surface of the core substrate can be referred to as the horizontal direction (X direction), and the direction perpendicular to the horizontal direction (X direction) and perpendicular to the main surface of the core substrate can be referred to as the vertical direction (Z direction), which is also the stacking direction.

[0055] The present application is proposed based on the consideration of the inventors that glass packaging substrates such as 24-layer substrates still face great challenges in terms of stacking alignment, dielectric thickness uniformity, interlayer interconnection precision control, and heat dissipation due to their extremely high lamination complexity. Any slight interlayer alignment deviation or lamination defect can lead to signal integrity problems or internal layer short circuits. Moreover, the difficulty of via formation and electroplating processes increases exponentially, resulting in a significantly lower overall manufacturing yield than conventional layer boards. In addition, single-material glass substrates are difficult to meet the thermal, electrical, and mechanical demands of multiple chips.

[0056] Therefore, according to the glass interposer stacked substrate according to one or more embodiments, a conventional single-material substrate is first split into independent glass sub-substrates of different glass materials, stacked by metal bonding and filled with a filling material, forming an interposer substrate integrated with multiple glass materials. In this way, the sub-substrates can be processed in parallel, simplifying the stacking process of the multi-layer RDL structure, reducing the risk of alignment deviation and lamination defects, significantly improving the manufacturing yield and shortening the processing time. High-density integration is achieved through the stacking of multiple sub-substrates.

[0057] Secondly, based on the differences in thermal, electrical, and mechanical characteristics of different chips in the AI module, different levels of glass sub-substrates use glass substrates with different characteristics to solve the defect that a single substrate cannot meet the demands of multiple chips. For example, the top glass sub-substrate uses low-CTE glass to match silicon chips and reduce thermal stress between the chips and the substrate. In addition, the top glass sub-substrate has good thermal conductivity, which can solve the problem of local high heat after the inversion of GPU / HBM. Furthermore, the top glass sub-substrate uses silver metal wiring to reduce the loss of high-frequency signal transmission of the device and further improve the thermal conductivity of the glass sub-substrate. The middle glass sub-substrate uses a low-dielectric loss glass substrate with silver metal wiring to meet the integrity requirements of high-speed signal transmission above 2 Gbps between HBM and GPU, avoiding signal attenuation problems. The bottom glass sub-substrate uses a medium-CTE glass to alleviate the overall thermal stress after multi-layer stacking and avoid substrate warping after PCB mounting. In addition, the gradual widening of the metal wiring layer of at least one heavy wiring structure of the bottom glass sub-substrate can avoid metal fatigue caused by sudden changes in line width.

[0058] In addition, the high-thermal-conductivity material filled between adjacent glass sub-substrates eliminates the air gap at the bonding interface, improves the heat dissipation efficiency and structural reliability, and meets the high-density integration and high-thermal-management requirements of AI chips. Sub-substrate independent detection and screening can avoid the problem of whole substrate failure caused by local defects of traditional whole substrates, reducing costs.

[0059] Figure 1 A glass interposer stacked substrate according to one or more embodiments is shown.

[0060] Reference Figure 1The glass interposer stack substrate 1 comprises at least three glass sub-substrates arranged along a stacking direction, each glass sub-substrate comprising: a glass core plate having a glass through hole filled with a conductive material to form a conductive through hole; two redistribution structures formed on opposite sides of the glass core plate and electrically interconnected by the conductive through hole; each redistribution structure has at least two redistribution layers, the redistribution layer comprises a dielectric layer, a metal wiring layer and a plurality of vias; the via electrically connects the metal wiring layers of two adjacent redistribution layers; a metal bonding layer is arranged on the side of each redistribution structure away from the glass core plate and is electrically connected with the redistribution structure; along the stacking direction, the thermal expansion coefficient of the glass core plate of the top glass sub-substrate is less than 5 ppm / ℃, the thermal conductivity is 1.2 W / (m·K), and the glass sub-substrate uses silver metal wiring; the thermal expansion coefficient of the glass core plate of the bottom glass sub-substrate is greater than 5 ppm / ℃, and the line width of the metal wiring layer of at least one redistribution structure of the glass sub-substrate gradually widens from the conductive through hole to the metal bonding layer; the dielectric constant of the glass core plate of the glass sub-substrate between the top layer and the bottom layer is 4-7, the dielectric loss is 0.007-0.009, and the glass sub-substrate uses silver metal wiring; any two adjacent glass sub-substrates are stacked and bonded by the metal bonding layer along the stacking direction, and the bonding gap between the two adjacent glass sub-substrates is filled with a filling material to form the glass interposer stack substrate 1.

[0061] That is, the glass interposer stack substrate 1 is stacked and bonded by the metal bonding layer of adjacent glass sub-substrates with at least three glass sub-substrates of different physical properties; thus, the single-layer substrate is divided into independent sub-substrates with different physical properties by different glass materials, and the glass interposer substrate integrated with multiple glass materials is formed by stacking and bonding with the metal bonding layer and filling the filling material. For example Figure 1 The glass interposer stack substrate 1 comprises three glass sub-substrates, i.e. a middle glass sub-substrate 10, a top glass sub-substrate 20 and a bottom glass sub-substrate 30, which have different physical properties, wherein the top glass sub-substrate 20 is used for flip-chip, and requires high heat dissipation performance and low loss of high-frequency signal transmission; the middle glass sub-substrate 10 is used to connect the top glass sub-substrate 20 and the bottom glass sub-substrate 30, and requires low loss of high-frequency signal transmission; the bottom glass sub-substrate 30 is connected with a PCB board, and requires good support performance and dispersed wiring to alleviate the stress at the connection between the PCB terminal pad and the glass sub-substrate. Of course, according to other embodiments of the present application, the glass sub-substrates of the glass interposer stack substrate 1 are not limited to Figure 1 three layers, but can be four or more layers.

[0062] In particular, the structures of the glass sub-substrates are substantially the same, with the middle layer glass sub-substrate 10 as an example. Please refer to Figures 3-19 The middle layer glass sub-substrate 10 includes a middle layer glass core substrate 110, two middle layer redistribution structures 120, and a middle layer metal bonding layer, such as 130a or 130b.

[0063] The middle layer glass core substrate 110 has a through middle layer conductive via 111; that is, the middle layer glass core substrate 110 has a through middle layer conductive via 111 vertically penetrating the middle layer glass core substrate 110. A glass material with low dielectric loss is used as the core substrate, such as borosilicate glass. The borosilicate glass with a dielectric constant of 4-7 and a dielectric loss of 0.007-0.009 is selected. The glass can achieve a larger package at the panel level, so that parallel processing of each middle layer glass sub-substrate 10 is possible, thus shortening the processing time and reducing the manufacturing cost.

[0064] The middle layer conductive via 111 can be provided between the two middle layer redistribution structures 120 and provide an electrical connection path between the two middle layer redistribution structures 120. The middle layer conductive via 111 can be one or more, each middle layer conductive via 111 containing a conductive material within the via, the conductive material including a seed layer and a conductive layer, the seed layer covering the inner wall of the glass via, and the conductive layer covering the seed layer; wherein the seed layer is a titanium layer and a copper layer, or a titanium layer alone; the conductive layer is a silver layer. The Young's modulus of silver material is lower than that of copper material, so that the thermal stress generated between silver and glass is smaller, which can avoid the case of TGV crack; in addition, the silver material has smaller resistivity and larger thermal conductivity compared with the copper material, so that the glass sub-substrate can have better performance in high-frequency signal transmission and heat dissipation of high-power devices. The middle layer conductive via 111 can have an upper surface and a lower surface spaced apart from each other in the vertical direction. The upper surface of the middle layer conductive via 111 can be coplanar with the first side 110a of the middle layer glass core substrate 110, and the lower surface of the middle layer conductive via 111 can be coplanar with the second side 110b of the middle layer glass core substrate 110. The upper surface of the middle layer conductive via 111 can be connected to the middle layer redistribution structure 120a of the first side 110a, and the lower surface of the middle layer conductive via 111 can be connected to the middle layer redistribution structure 120b of the second side 110b.

[0065] In addition, each middle layer conductive via 111 can have any suitable shape, including, for example, a cylindrical shape. In one or more other embodiments, each middle layer conductive via 111 can have a conical shape that is symmetric about a top and bottom.

[0066] Two middle layer redistribution structures 120 are formed on the opposite sides (i.e. the first side 110a and the second side 110b) of the middle layer glass core board 110 respectively and are electrically interconnected by the middle layer conductive via hole 111; each middle layer redistribution structure 120 has at least two redistribution layers, such as 121a or 121b. The redistribution structure on the first side 110a of the middle layer glass core board 110 can be defined as the middle layer first redistribution structure 120a; the redistribution structure on the second side 110b of the middle layer glass core board 110 can be defined as the middle layer second redistribution structure 120b.

[0067] The middle layer first redistribution structure 120a includes at least two first redistribution layers 121a. Each first redistribution layer 121a can include a first dielectric layer 1211a, a first metal wiring layer 1212a and a plurality of first vias 1213a; each first via 1213a electrically connects the first metal wiring layers 1212a of two adjacent first redistribution layers 121a, and the first metal wiring layer 1212a and the first via 1213a can be included or surrounded in the first dielectric layer 1211a.

[0068] The first dielectric layer 1211a can be stacked in the vertical direction. The first dielectric layer 1211a can include an insulating material such as a photosensitive imaging dielectric resin prepared by combining an epoxy resin and a photoinitiator, and can further include a photosensitive polyimide and / or an inorganic filler, without being limited thereto. The first metal wiring layer 1212a and the first via 1213a can be provided as a conductive pattern, and the conductive pattern can be positioned in the first dielectric layer 1211a. The first metal wiring layer 1212a can be provided to extend in the horizontal direction in the first dielectric layer 1211a. The first via 1213a can penetrate one or more first dielectric layers 1211a in the vertical direction, thereby contacting and electrically connecting some wiring patterns in the first metal wiring layer 1212a. Among them, the minimum line width / line spacing of the first metal wiring layer 1212a is 3 μm / 3 μm-5 μm / 5 μm, and the metal thickness is 3 μm / 3 μm-5 μm / 5 μm. According to some specific embodiments, the first via 1213a can have any suitable shape, including, for example, a tapered shape or a cylindrical shape. The first metal wiring layer 1212a and the first via 1213a are made of a conductive metal, which includes a seed layer and a conductive layer, the seed layer is covered on the surface of the glass core board or the first dielectric layer 1211a, and the conductive layer is covered on the seed layer; wherein the seed layer is a titanium layer and a copper layer, or a titanium layer alone; the conductive layer is a silver layer. The Young's modulus of silver material is lower than that of copper material, so that the thermal stress generated between silver and glass is smaller; in addition, the silver material has smaller resistivity and larger thermal conductivity compared with the copper material, so that the glass sub-substrate can have better performance in high-frequency signal transmission of devices and heat dissipation of high-power devices.

[0069] The middle layer second heavy wiring structure 120b includes at least two layers of second redistribution layers 121b. Each layer of second redistribution layer 121b can include a second dielectric layer 1211b, a second metal wiring layer 1212b, and a plurality of second vias 1213b; each second via 1213b electrically connects the second metal wiring layer 1212b of two adjacent second redistribution layers 121b, and the second metal wiring layer 1212b and the second via 1213b can be included or surrounded in the second dielectric layer 1211b. The second dielectric layer 1211b can be stacked in the vertical direction. The second dielectric layer 1211b can include an insulating material such as a photosensitive imaging dielectric resin prepared by combining an epoxy resin and a photoinitiator, and can further include a photosensitive polyimide and / or inorganic fillers, without being limited thereto. The second metal wiring layer 1212b and the second via 1213b can be provided as a conductive pattern, and the conductive pattern can be positioned in the second dielectric layer 1211b. The second metal wiring layer 1212b can be provided to extend in the horizontal direction in the second dielectric layer 1211b. The second via 1213b can penetrate one or more second dielectric layers 1211b in the vertical direction, thereby contacting and electrically connecting some wiring patterns in the second metal wiring layer 1212b. Among them, the minimum line width / line spacing of the second metal wiring layer 1212b is 3 μm / 3 μm-5 μm / 5 μm, and the metal thickness is 3 μm / 3 μm-5 μm / 5 μm. According to some specific embodiments, the second via 1213b can have any suitable shape, including, for example, a tapered shape or a cylindrical shape. The second metal wiring layer 1212b and the second via 1213b are made of a conductive metal including a seed layer and a conductive layer, the seed layer is covered on the surface of the glass core plate or the first dielectric layer 1211a, and the conductive layer is covered on the seed layer; wherein the seed layer is a titanium layer and a copper layer, or a titanium layer alone; the conductive layer is a silver layer. The Young's modulus of silver material is lower than that of copper material, so that the thermal stress generated between silver and glass is smaller; in addition, the silver material has smaller resistivity and larger thermal conductivity compared with the copper material, so that the glass sub-substrate can have better performance in high-frequency signal transmission of devices and heat dissipation of high-power devices.

[0070] The middle layer metal bonding layer (e.g., 130a or 130b) is arranged on the side of each middle layer redistribution structure 120 away from the middle layer glass core plate 110 and is electrically connected with the middle layer redistribution structure 120; any two adjacent glass sub-plates are stacked and bonded through the metal bonding layer along the stacking direction; that is, the lower surface (the side away from the middle layer glass core plate 110) of the middle layer first redistribution structure 120a is provided with a metal bonding layer, which can be defined as the middle layer first metal bonding layer 130a; the upper surface (the side away from the middle layer glass core plate 110) of the middle layer second redistribution structure 120b is also provided with a metal bonding layer, which can be defined as the middle layer second metal bonding layer 130b. In this way, the stacking of the multi-layer glass sub-plates can be achieved by using two metal bonding layers opposite in the vertical direction for bonding. In one or more embodiments, the middle layer metal bonding layer (e.g., 130a or 130b) is a plurality of bumps arranged at intervals on the side of the middle layer redistribution structure 120 away from the middle layer glass core plate 110.

[0071] Specifically, the bump, as a specific implementation form of the middle layer metal bonding layer (e.g., 130a or 130b), can adopt a spherical or columnar structure. The spherical bump includes but is not limited to a solder ball, a gold ball and other reflow solderable materials; the columnar bump is preferably a copper column structure, and the height thereof can be accurately controlled through an electroplating process. The arrangement pitch of the bump array needs to meet the alignment accuracy requirement when the adjacent glass sub-plates are stacked. The electrical connection of the bump and the redistribution structure is achieved by the following way: a under bump metal (UBM) layer is made on the outermost metal wiring layer of the redistribution structure, and then a bump structure is formed through a ball planting or electroplating process.

[0072] In this way, the interval arrangement of the bumps can effectively release the thermal stress generated in the stacking process and avoid the interface delamination caused by the difference in the thermal expansion coefficient; secondly, the bump structure can compensate for the flatness error between the substrates through plastic deformation during bonding, thereby improving the bonding yield; in addition, the air gap formed by the bump array is beneficial to the full filling of the filling material 40, thereby improving the heat dissipation performance of the overall structure. Compared with the traditional monolithic substrate which needs to process multiple redistribution layers at one time, the bonding of the middle layer metal bonding layer (e.g., 130a or 130b) in the embodiment can significantly reduce the process difficulty of multi-layer stacking while ensuring the reliability of electrical interconnection.

[0073] In one or more specific embodiments, the bump on one of the middle layer redistribution structures 120 of the middle layer glass sub-plate 10 is a solder ball or a gold ball, and the bump on the other middle layer redistribution structure 120 is a copper column. For example, the bump on the middle layer first redistribution structure 120a is a copper column, and the bump on the middle layer second redistribution structure 120b is a solder ball or a gold ball.

[0074] Specifically, the tin ball or gold ball as the bump material has a low melting point, and the interconnection of the middle metal bonding layer (e.g., 130a or 130b) can be achieved by hot pressing or reflow soldering in the bonding process. The copper pillar as the bump material has high mechanical strength and excellent electrical conductivity, and can withstand mechanical stress in the stacking process and ensure the quality of electrical signal transmission. The combination of the two kinds of bump materials can achieve differentiated bonding: the tin ball or gold ball provides good wettability and interface bonding force, and the copper pillar provides structural support and current carrying capacity. As a preferred embodiment, the diameter of the tin ball can be controlled to be 50-200 μm, the diameter of the gold ball can be controlled to be 50-100 μm, and the height of the copper pillar can be set to 50-150 μm, and the diameter matches that of the tin ball / gold ball.

[0075] The thickness of the middle glass sub-substrate 10 formed in this way can be ≥ 150 μm.

[0076] Similarly, for the top glass sub-substrate 20, the structure and principle of the top glass sub-substrate 20 are substantially the same as those of the middle glass sub-substrate 10 described above, except that the top glass core plate 210 of the top glass sub-substrate 20 uses a glass material with a low thermal expansion coefficient and a high thermal conductivity coefficient as the core plate, such as borosilicate glass doped with Al2O3 thermal conductive particles. The doping of metal ions or metal oxides to improve the thermal conductivity of the material is a prior art and will not be described in detail here. In this way, the thermal expansion coefficient of the top glass core plate 210 is less than 5 ppm / ℃, for example, the thermal expansion coefficient is selected to be 3 ppm / ℃, and the thermal conductivity is 1.2 W / (m·K), which ensures the heat dissipation effect of the top glass sub-substrate 20.

[0077] The top conductive via 211 and the metal wiring layer of the top glass sub-substrate 20 also have a seed layer and a conductive layer covering the seed layer, the seed layer includes a titanium layer, or a titanium layer and a copper layer; and the conductive layer is a silver layer. In this way, the glass sub-substrate can have better performance in high-frequency signal transmission and heat dissipation of high-power devices.

[0078] In addition, each third redistribution layer 221a of the top first redistribution structure 220a of the top glass sub-substrate 20 includes a third dielectric layer 2211a, a third metal wiring layer 2212a, and a third via 2213a, wherein the minimum line width / space of the third metal wiring layer 2212a is 2 μm, and the metal thickness is 2 μm. Each fourth redistribution layer 221b of the top second redistribution structure 220b of the top glass sub-substrate 20 includes a fourth dielectric layer 2211b, a fourth metal wiring layer 2212b, and a fourth via 2213b, wherein the minimum line width / space of the fourth metal wiring layer 2212b is 2 μm, and the metal thickness is 2 μm.

[0079] Please refer to Figure 18The bottom glass sub-substrate 30 includes a bottom glass core substrate 310, two bottom redistribution structures 320, and a bottom metal bonding layer (e.g., 330a or 330b).

[0080] The bottom glass core substrate 310 has a bottom conductive via 311 therethrough; that is, the bottom glass core substrate 310 has a bottom conductive via 311 that vertically penetrates the bottom glass core substrate 310. The core substrate is made of a glass material with a medium coefficient of thermal expansion, such as soda-lime glass. The CTE of the bottom glass core substrate 310 made of soda-lime is greater than 5 ppm / °C, such as a CTE of 9 ppm / °C, which is between the top borosilicate glass and the PCB board, alleviating the overall thermal stress after the multilayer stacking, avoiding the warping of the substrate after the PCB is mounted.

[0081] The bottom conductive via 311 can be provided between the two bottom redistribution structures 320 and provide an electrical connection path between the two bottom redistribution structures 320. The bottom conductive via 311 can be one or more, each bottom conductive via 311 includes a conductive material within the via, which can be copper, aluminum, silver, gold, molybdenum, titanium, or a combination thereof. The bottom conductive via 311 can have an upper surface and a lower surface spaced apart from each other in a vertical direction. The upper surface of the bottom conductive via 311 can be connected to the bottom redistribution structure 320a, and the lower surface of the bottom conductive via 311 can be connected to the bottom redistribution structure 320b.

[0082] In addition, each bottom conductive via 311 can have any suitable shape, including, for example, a cylindrical shape. In one or more other embodiments, each bottom conductive via 311 can have a conical shape that is symmetric about a vertical axis.

[0083] The two bottom redistribution structures 320 are formed on opposite sides of the bottom glass core substrate 310 and are electrically interconnected by the bottom conductive via 311; each bottom redistribution structure 320 has at least two redistribution layers (e.g., 321a or 321b). Among them, the redistribution structure on one side of the bottom glass core substrate 310 can be defined as a bottom first redistribution structure 320a; the redistribution structure on the other side of the bottom glass core substrate 310 can be defined as a bottom second redistribution structure 320b.

[0084] The bottom first redistribution structure 320a includes at least two fifth redistribution layers 321a. Each layer of the fifth redistribution layer 321a can include a fifth dielectric layer 3211a, a fifth metal wiring layer 3212a, and a plurality of fifth vias 3213a; each fifth via 3213a electrically connects the fifth metal wiring layer 3212a of the two adjacent fifth redistribution layers 321a, and the fifth metal wiring layer 3212a and the fifth via 3213a can be included or surrounded in the fifth dielectric layer 3211a.

[0085] The fifth dielectric layers 3211a can be stacked in a vertical direction. The bottom first heavy wiring structure 320a includes at least two kinds of dielectric materials, for example, the first dielectric material is an epoxy material, which is disposed adjacent to the bottom glass core substrate 310; the second dielectric material is a silicone film, which is disposed on the outermost metal wiring layer of the bottom first heavy wiring structure 320a. In this way, the first dielectric material has a large adhesion to the glass substrate, which can ensure the structural stability during reflow soldering of the bottom glass sub-base plate 30; and the second dielectric material covers the surface of the outermost wiring layer, which can absorb the stress caused by the thermal expansion difference between the wiring and the dielectric layer during thermal cycling, thereby avoiding cracking of the dielectric layer. In addition to the first dielectric material and the second dielectric material, the remaining fifth dielectric layers 3211a can also use photosensitive polyimide or other non-photosensitive materials. The fifth metal wiring layer 3212a and the fifth via 3213a can be provided as conductive patterns, and the conductive patterns can be positioned in the fifth dielectric layer 3211a. The fifth metal wiring layer 3212a can be provided as extending in a horizontal direction in the fifth dielectric layer 3211a. The fifth via 3213a can penetrate one or more fifth dielectric layers 3211a in a vertical direction, thereby contacting and electrically connecting with some wiring patterns in the fifth metal wiring layer 3212a. The minimum metal line width / spacing of the fifth metal wiring layer 3212a electrically connected with the bottom conductive via 311 is 5 μm / 5 μm-10 μm / 10 μm, and the metal thickness is 5 μm-10 μm, and then gradually increases in the direction of the bottom first metal bonding layer 330a, for example, the minimum line width / spacing of the fifth metal wiring layer 3212a of the innermost layer (i.e., the layer adjacent to and electrically connected with the bottom conductive via 311) is 5 μm / 5 μm, the minimum line width / spacing of the fifth metal wiring layer 3212a of the second innermost layer adjacent to the innermost layer is 7 μm / 7 μm, and so on, and the minimum line width / spacing of the fifth metal wiring layer 3212a of the outermost layer (adjacent to the bottom first metal bonding layer 330a) is 10 μm / 10 μm; the gradually increasing metal line width / spacing of the fifth metal wiring layer 3212a can be achieved by changing the exposure size of the photoresist, thereby achieving different line width / spacing; in this way, the gradually increasing metal line width / spacing of the fifth metal wiring layer 3212a can avoid metal fatigue caused by sudden change of line width, thereby reducing the wiring breakage rate after thermal cycling. According to some specific embodiments, the fifth via 3213a can have any suitable shape, including, for example, a tapered shape or a cylindrical shape. The fifth metal wiring layer 3212a and the fifth via 3213a are made of a conductive metal, for example, copper, aluminum, titanium, tantalum, molybdenum, and alloys thereof, but are not limited thereto.

[0086] The second bottom layer redistribution structure 320b includes at least two layers of sixth redistribution layers 321b. Each layer of the sixth redistribution layers 321b can include a sixth dielectric layer 3211b, a sixth metal wiring layer 3212b, and a plurality of sixth vias 3213b; each of the sixth vias 3213b electrically connects the sixth metal wiring layers 3212b of two adjacent layers of the sixth redistribution layers 321b, and the sixth metal wiring layers 3212b and the sixth vias 3213b can be included in or surrounded by the sixth dielectric layer 3211b. The sixth dielectric layers 3211b can be stacked in the vertical direction. The sixth dielectric layer 3211b can include an insulating material such as a photosensitive imaging dielectric resin prepared by combining an epoxy resin and a photoinitiator, and can further include a photosensitive polyimide and / or inorganic fillers, and can be the same as the fifth dielectric layer 3211a described above, without being limited thereto. The sixth metal wiring layer 3212b and the sixth via 3213b can be provided as a conductive pattern, and the conductive pattern can be positioned in the sixth dielectric layer 3211b. The sixth metal wiring layer 3212b can be provided to extend in the horizontal direction in the sixth dielectric layer 3211b. The sixth via 3213b can penetrate one or more sixth dielectric layers 3211b in the vertical direction, thereby contacting and electrically connecting some of the wiring patterns in the sixth metal wiring layer 3212b. The minimum metal line width / space of the sixth metal wiring layer 3212b electrically connected to the bottom layer conductive via 311 is 5 μm / 5 μm-10 μm / 10 μm, and the metal thickness is 5 μm-10 μm. Preferably, the metal line width / space of the sixth metal wiring layer 3212b gradually increases in the direction toward the second bottom layer metal bonding layer 330b, for example, the minimum line width / space of the sixth metal wiring layer 3212b of the innermost layer (i.e., the layer adjacent to and electrically connected to the bottom layer conductive via 311) is 5 μm / 5 μm, the minimum line width / space of the sixth metal wiring layer 3212b of the second innermost layer adjacent to the innermost layer is 7 μm / 7 μm, and so on, and the minimum line width / space of the sixth metal wiring layer 3212b of the outermost layer adjacent to the second bottom layer metal bonding layer 330b is 10 μm / 10 μm. Of course, in other embodiments, the metal line width / space of the sixth metal wiring layer 3212b of each layer of the second bottom layer redistribution structure 320b can also be the same. According to some specific embodiments, the sixth via 3213b can have any suitable shape, including, for example, a tapered shape or a cylindrical shape. The sixth metal wiring layer 3212b and the sixth via 3213b are made of a conductive metal, for example, copper, aluminum, titanium, tantalum, molybdenum, and alloys thereof, but are not limited thereto.

[0087] As can be seen from the above, along the stacking direction, from the top layer glass sub-base plate 20 to the bottom layer glass sub-base plate 30, the metal wiring layers of the redistribution structure are arranged from dense to sparse.

[0088] The bottom metal bonding layer (e.g., 330a or 330b) is arranged on the side of each bottom redistribution structure 320 away from the bottom glass core plate 310 and is electrically connected with the bottom redistribution structure 320; that is, the lower surface (the side away from the bottom glass core plate 310) of the bottom first redistribution structure 320a is provided with a metal bonding layer, which can be defined as a bottom first metal bonding layer 330a; the upper surface (the side away from the bottom glass core plate 310) of the bottom second redistribution structure 320b is also provided with a metal bonding layer, which can be defined as a bottom second metal bonding layer 330b. In this way, the stacking of the multi-layer glass sub-base plate can be achieved by bonding with two metal bonding layers opposite in the vertical direction. In one or more embodiments, the bottom metal bonding layer (e.g., 330a or 330b) is a plurality of bumps arranged at intervals on the side of the bottom redistribution structure 320 away from the bottom glass core plate 310.

[0089] Specifically, the bump, as a specific implementation form of the bottom metal bonding layer (e.g., 330a or 330b), can adopt a spherical or columnar structure. Among them, the spherical bump includes but is not limited to a solder ball, a gold ball and other reflow solderable materials; the columnar bump is preferably a copper column structure, and the height thereof can be accurately controlled through an electroplating process. The arrangement pitch of the bump array needs to meet the alignment accuracy requirement when the adjacent glass sub-base plates are stacked. The electrical connection of the bump and the redistribution structure is achieved by the following way: a under bump metal (UBM) layer is made on the outermost metal wiring layer of the redistribution structure, and then a bump structure is formed through a ball planting or electroplating process.

[0090] In this way, the interval arrangement of the bumps can effectively release the thermal stress generated in the stacking process and avoid interface delamination caused by the difference in the coefficient of thermal expansion; secondly, the bump structure can compensate for the flatness error between the substrates through plastic deformation during bonding, thereby improving the bonding yield; in addition, the air gap formed by the bump array is beneficial to the full filling of the filling material 40, thereby improving the heat dissipation performance of the overall structure. Compared with the traditional monolithic substrate which needs to process multiple redistribution layers at one time, the bonding of the bottom metal bonding layer (e.g., 330a or 330b) in the embodiment significantly reduces the process difficulty of multi-layer stacking while ensuring the reliability of electrical interconnection.

[0091] In one or more specific embodiments, the bump on one of the bottom redistribution structures 320 of the bottom glass sub-base plate 30 is a solder ball or a gold ball, and the bump on the other bottom redistribution structure 320 is a copper column. For example, the bump on the bottom first redistribution structure 320a is a copper column, and the bump on the bottom second redistribution structure 320b is a solder ball or a gold ball.

[0092] Specifically, the tin ball or gold ball as the bump material has a low melting point, and the interconnection of the bottom metal bonding layer (e.g., 330a or 330b) can be achieved by hot pressing or reflow soldering in the bonding process. The copper pillar as the bump material has high mechanical strength and excellent electrical conductivity, and can withstand mechanical stress in the stacking process and ensure the quality of electrical signal transmission. The combination of the two kinds of bump materials can achieve differentiated bonding: the tin ball or gold ball provides good wettability and interface bonding force, and the copper pillar provides structural support and current carrying capacity. As a preferred embodiment, the diameter of the tin ball can be controlled to be 50-200 μm, the diameter of the gold ball can be controlled to be 50-100 μm, and the height of the copper pillar can be set to 50-150 μm, and the diameter matches that of the tin ball / gold ball.

[0093] The thickness of the bottom glass sub-substrate 30 formed in this way can be ≥ 150 μm. The thickness of the bottom glass sub-substrate 30 is set to be 150 μm and above, mainly based on the following consideration: in a multi-layer interposer stack structure, a too thin sub-substrate has insufficient mechanical strength, thermal stability and processing yield. Insufficient thickness can cause the substrate to warp or break during high-temperature bonding, affecting the stacking accuracy and reliability.

[0094] The bonding gap between two adjacent glass sub-substrates is filled with a filling material 40 to form a glass interposer stack substrate 1. That is, after the bonding of the multi-layer glass sub-substrate stack, the filling material 40 can be filled in the bonding gap between each adjacent two glass sub-substrates. The filling material 40 can be provided adjacent to and around each bonding bump of the metal bonding layer. The filling material 40 can adopt an LMUF material (liquid mold underfill material), a CUF material (post-filling underfill material), a high thermal conductivity filling adhesive, a prepreg or an NCF film. Preferably, an underfill adhesive can eliminate the air gap at the bonding interface, form a vertical heat dissipation channel from the chip to the substrate, and improve the overall heat dissipation performance; at the same time, it can release the thermal stress in the stacking process and avoid interface delamination. The total thickness of the bonded glass interposer stack substrate 1 is ≤ 1.4 mm, which balances the structure thinning and mechanical stability.

[0095] It should be noted that the number of redistribution layers of the redistribution structure in each sub-substrate (middle glass sub-substrate 10, top glass sub-substrate 20, bottom glass sub-substrate 30) of the glass interposer stack substrate 1 can be customized as needed, so that it meets the requirement that the redistribution structure includes at least two redistribution layers; and the number of redistribution layers of the redistribution structure in different glass sub-substrates of the glass interposer stack substrate 1 can be the same or different. For example, Figure 1The glass interposer stack substrate 1 shown has three sub-substrates, an upper sub-substrate, a middle sub-substrate and a lower sub-substrate, wherein the upper sub-substrate is a top glass sub-substrate 20, the middle sub-substrate is a middle glass sub-substrate 10, and the lower sub-substrate is a bottom glass sub-substrate 30; the top first redistribution structure 220a of the upper top glass sub-substrate 20 has two layers of third redistribution layers 221a, and the top second redistribution structure 220b has three layers of fourth redistribution layers 221b; alternatively, the top first redistribution structure 220a has three layers of third redistribution layers 221a, and the top second redistribution structure 220b has two layers of fourth redistribution layers 221b; alternatively, the top first redistribution structure 220a has three layers of third redistribution layers 221a, and the top second redistribution structure 220b has three layers of fourth redistribution layers 221b. Similarly, the middle first redistribution structure 120a of the middle glass sub-substrate 10 has two layers of first redistribution layers 121a, and the middle second redistribution structure 120b has three layers of second redistribution layers 121b; alternatively, the middle first redistribution structure 120a has three layers of first redistribution layers 121a, and the middle second redistribution structure 120b has two layers of second redistribution layers 121b; alternatively, the middle first redistribution structure 120a has three layers of first redistribution layers 121a, and the middle second redistribution structure 120b has three layers of second redistribution layers 121b. Similarly, the number of layers of redistribution layers of the redistribution structure 320 of the bottom glass sub-substrate 30 can be the same as or different from that of the middle glass sub-substrate 10. Preferably, the number of layers of redistribution layers of the redistribution structure of each sub-substrate is not more than four.

[0096] Figure 2 A flowchart of a method for manufacturing a glass interposer stack substrate according to one or more embodiments is shown.

[0097] Reference is made to Figure 2 The present application provides a method for manufacturing a glass interposer stack substrate, comprising the following steps:

[0098] S1: providing at least three glass core plates having conductive vias;

[0099] S2: providing a redistribution structure on each of the opposite sides of each of the glass core plates; each of the redistribution structures has at least two redistribution layers; the redistribution layers comprise dielectric layers, metal wiring layers and a plurality of vias; the vias electrically connect the metal wiring layers of two adjacent redistribution layers;

[0100] S3: providing a metal bonding layer on the side of each of the redistribution structures away from the glass core plate, and cutting the wafer to form at least three glass sub-substrates;

[0101] S4: The at least three types of glass sub-substrates are sequentially stacked and bonded along the stacking direction using the metal bonding layer, and the bonding gap between two adjacent glass sub-substrates is filled with filler material to form the glass interlayer stacked substrate.

[0102] Along the stacking direction, the glass core of the top glass sub-substrate has a coefficient of thermal expansion of less than 5 ppm / ℃ and a thermal conductivity of 1.2 W / (m·K), and the glass sub-substrate uses silver metal wiring; the glass core of the bottom glass sub-substrate has a coefficient of thermal expansion of greater than 5 ppm / ℃, and the linewidth of the metal wiring layer of at least one wiring structure of the glass sub-substrate gradually widens from the conductive via to the metal bonding layer; the glass core of the glass sub-substrate located between the top and bottom layers has a dielectric constant of 4-7 and a dielectric loss of 0.007-0.009, and the glass sub-substrate uses silver metal wiring.

[0103] In other words, this method enables large-scale mass production of sub-substrates by fabricating redistribution structures and metal bonding layers on large-size glass wafers of different materials, and then cutting them into various glass sub-substrates. After cutting into multiple glass sub-substrates, each sub-substrate can be independently inspected to select qualified sub-substrates for subsequent stacking. Process defects in a single sub-substrate only result in the scrapping of that sub-substrate, avoiding the failure of the entire wafer due to local defects in traditional monolithic substrates, thus improving yield. The functional modular design allows only the target sub-substrate to be replaced during product iteration. For example, different combinations and stacking orders of glass sub-substrates can be replaced according to different flip chips.

[0104] Figures 3-19 This diagram illustrates a cross-sectional view of a substrate showing the steps of a method for fabricating a glass interlayer stacked substrate according to one or more embodiments. For brevity, descriptions overlapping with the previous figures will be omitted, and the differences will be primarily described. The middle glass sub-substrate 10, top glass sub-substrate 20, and bottom glass sub-substrate 30 manufactured in the method described below can be or correspond to Figure 1 The middle glass sub-substrate 10, the top glass sub-substrate 20, and the bottom glass sub-substrate 30 shown herein, and therefore, can be used hereinafter. Figure 1 The same reference numerals are shown in the figures.

[0105] refer to Figures 3-10 First, the middle glass sub-substrate 10 is fabricated. For example... Figure 3 As shown, a middle glass core board 110 is provided. The thickness of the middle glass core board 110 is greater than 700 μm. The middle glass core board 110 is an 8-inch glass wafer. Then, the middle glass core board 110 is subjected to surface cleaning treatment.

[0106] refer to Figure 4The TGV hole is obtained by laser induction and wet etching on the middle glass core plate 110. Laser induction is to use a pulsed laser to act on the glass to produce a continuous denatured area. Compared with the glass in the non-denatured area, the denatured glass has a faster etching rate in a hydrofluoric acid system or an alkaline system. Based on this phenomenon, a through hole, a blind hole or a through groove, a blind groove can be made on the glass. Specifically, one of a nanosecond laser, a picosecond laser and a femtosecond laser is used to produce a denatured area on the glass, and then the glass treated by the laser is placed in a hydrofluoric acid solution or an alkaline solution for etching; a glass through hole or a blind hole with high uniformity is obtained. Subsequently, a metal material is filled in the TGV hole to form a middle conductive via hole 111. The metal material can include a seed layer and a conductive layer, the seed layer covers the inner wall of the glass through hole, and the conductive layer covers the seed layer; wherein the seed layer is a titanium layer and a copper layer, or a titanium layer alone; the conductive layer is a silver layer. The seed layer can be formed by PVD, and the conductive layer can be electroplated silver, chemical plated silver or silver paste filling. The upper surface of the middle conductive via hole 111 can be coplanar with the upper surface of the middle glass core plate 110. Specifically, the seed layer can be sputtered by PVD, then the conductive layer is electroplated, and finally the surface is CMP. In this embodiment, the middle conductive via hole 111 is first formed as a blind hole, then the metal material is formed in the blind hole, and then a single-sided redistribution structure is made. In other embodiments, the middle conductive via hole 111 can be directly made as a through hole penetrating the first side 110a and the second side 110b of the middle glass core plate 110, then the metal material is formed in the through hole, and then a double-sided redistribution structure is made at the same time.

[0107] Reference Figure 5 The first metal wiring layer 1212a can be provided on the first side 110a of the middle glass core plate 110 and cover a surface of the middle conductive via hole 111, so that the two are electrically connected.

[0108] Reference Figure 6 The first dielectric layer 1211a can be laminated on the first side 110a of the middle glass core plate 110 and the first metal wiring layer 1212a, and then the first via hole 1213a is formed in the first dielectric layer 1211a. One or more first via holes 1213a can penetrate one or more first dielectric layers 1211a and contact the first metal wiring layer 1212a. Then one or more lamination films (first dielectric layer) are laminated on the upper surface of the first dielectric layer 1211a, and the first metal wiring layer 1212a and the first via hole 1213a of each layer of the first redistribution layer 121a are made accordingly to complete the manufacture of the middle first redistribution structure 120a. Wherein, the first dielectric layer 1211a can adopt wet film, dry film, non-photosensitive material; wet film adopts coating, baking, exposure, development, curing process, dry film adopts roller or vacuum film lamination, baking, exposure, development, curing process, and non-photosensitive material adopts roller or vacuum film lamination, baking, laser drilling process.

[0109] Subsequently, the middle first metal bonding layer 130a is formed on the outer surface of the outermost first redistribution layer 121a of the middle first redistribution structure 120a. The middle first metal bonding layer 130a can be formed by forming a passivation layer, an under bump metal (UBM) layer and a conductive layer on the first redistribution layer 121a, and then forming bumps, such as tin balls or gold balls, on the conductive layer.

[0110] Referring to Figure 7 temporarily bonding to the middle first metal bonding layer 130a of the middle glass core board 110, to temporarily protect the middle first metal bonding layer 130a and the middle first redistribution structure 120a of the surface.

[0111] Referring to Figure 8 Subsequently, the middle glass core board 110 with the temporary carrier is flipped over, and the back surface of the middle glass core board 110 is thinned to expose the middle conductive via 111.

[0112] Subsequently, referring to Figure 9 The middle second redistribution structure 120b is formed on the second side 110b of the middle glass core board 110. Specifically, a second metal wiring layer 1212b is provided on the second side 110b of the middle glass core board 110 and covers a surface of the middle conductive via 111, so that the two are electrically connected. Then, a second dielectric layer 1211b is laminated on the second side 110b of the middle glass core board 110 and the second metal wiring layer 1212b, and then a second via 1213b is formed in the second dielectric layer 1211b. One or more second vias 1213b can penetrate one or more second dielectric layers 1211b and contact the second metal wiring layer 1212b. Then, one or more lamination films (second dielectric layers) are laminated on the upper surface of the second dielectric layer 1211b, and the second metal wiring layer 1212b and the second via 1213b of the second redistribution layer 121b of each layer are formed accordingly to complete the formation of the middle second redistribution structure 120b. The second dielectric layer 1211b can be a wet film, a dry film or a non-photosensitive material. The wet film is processed by coating, baking, exposure, development and curing. The dry film is processed by roller or vacuum film lamination, baking, exposure, development and curing. The non-photosensitive material is processed by roller or vacuum film lamination, baking and laser drilling.

[0113] Then, the middle second metal bonding layer 130b is formed on the outer surface of the outermost second redistribution layer 121b of the middle second redistribution structure 120b. The middle second metal bonding layer 130b can be formed by forming a passivation layer on the second redistribution layer 121b, and then window plating to form bumps, such as copper pillars.

[0114] Then, referring to Figure 10 , laser debonding is used to remove the temporary carrier, and then the wafer is die-bonded and cut to form a plurality of middle glass sub- substrates 10.

[0115] The top glass sub-substrate 20 is made in the same way as the middle glass sub-substrate 10 described above, and will not be described in detail here.

[0116] Similarly, referring to Figures 11-18 , the bottom glass sub-substrate 30 is made. As shown in Figure 11 , a bottom glass core plate 310 is provided, the thickness of the bottom glass core plate 310 is greater than 700 μm, the bottom glass core plate 310 is an 8-inch glass wafer, and then the bottom glass core plate 310 is subjected to surface cleaning treatment.

[0117] Referring to Figure 12 , the bottom glass core plate 310 described above is subjected to laser induction and wet etching to obtain a TGV hole. Laser induction is to use a pulsed laser to act on the glass to produce a continuous denatured region. Compared with the glass in the non-denatured region, the denatured glass has a faster etching rate in a hydrofluoric acid system or an alkaline system. Based on this phenomenon, a through hole, a blind hole, or a through groove, a blind groove can be made on the glass. Specifically, one of a nanosecond laser, a picosecond laser, and a femtosecond laser is used to produce a denatured region on the glass, and then the laser-processed glass is placed in a hydrofluoric acid solution or an alkaline solution for etching; a glass through hole with high uniformity is obtained. Subsequently, a metal material is filled in the TGV hole to form a bottom conductive via 311. The metal material can include, for example, copper, aluminum, silver, gold, molybdenum, titanium, and combinations thereof. The upper surface of the bottom conductive via 311 can be coplanar with the upper surface of the bottom glass core plate 310. Specifically, a PVD sputtering seed layer can be formed, followed by metal electroplating of a conductive layer, and finally surface CMP. In this embodiment, the bottom conductive via 311 is made by first forming a blind hole, then forming a metal material in the blind hole, and then making a single-sided redistribution structure. In other embodiments, the bottom conductive via 311 can also be directly made into a through hole penetrating through both opposite sides of the bottom glass core plate 310, then a metal material is formed in the through hole, and then a double-sided redistribution structure is simultaneously made.

[0118] Referring to Figure 13 , a fifth metal wiring layer 3212a can be provided on one side of the bottom glass core plate 310 and cover a surface of the bottom conductive via 311, so that the two are electrically connected.

[0119] Referring to Figure 14The fifth dielectric layer 3211a can be laminated on one side of the bottom glass core board 310 and on the fifth metal wiring layer 3212a, and then the fifth via hole 3213a is formed in the fifth dielectric layer 3211a. One or more fifth via holes 3213a can penetrate one or more fifth dielectric layers 3211a and contact the fifth metal wiring layer 3212a. Then, one or more laminated films (first dielectric layer) are laminated on the upper surface of the fifth dielectric layer 3211a, and the fifth metal wiring layer 3212a and the fifth via hole 3213a of the fifth redistribution layer 321a of each layer are made accordingly to complete the manufacture of the bottom first redistribution structure 320a. In the bottom first redistribution structure 320a, the line width of the fifth metal wiring layer 3212a gradually widens from the bottom conductive via hole 311 to the bottom first metal bonding layer 330a; the metal line width / pitch of the gradually widened fifth metal wiring layer 3212a can achieve different line width and pitch by changing the photoresist exposure size. Different fifth dielectric layers 3211a can be made of different dielectric materials; specifically, the innermost fifth dielectric layer 3211a (i.e. adjacent to the bottom glass core board 310) is made of epoxy resin material, which can be made into a photosensitive imaging dielectric resin with a photo initiator, in the form of a dry film or a wet film, the wet film adopts coating, baking, exposure, development, curing process, and the dry film adopts roller or vacuum film lamination, baking, exposure, development, curing process. The outermost fifth dielectric layer 3211a (i.e. adjacent to the bottom metal bonding layer, such as 330a or 330b) is made of silicone film, which is in the form of a dry film and adopts coating, baking, exposure, development, curing process. In addition to epoxy resin material and silicone film, the remaining fifth dielectric layers 3211a can also be made of photosensitive polyimide or other non-photosensitive materials, and the non-photosensitive materials adopt roller or vacuum film lamination, baking, laser drilling process.

[0120] Subsequently, the bottom first metal bonding layer 330a is made on the outer surface of the outermost fifth redistribution layer 321a of the bottom first redistribution structure 320a. The bottom first metal bonding layer 330a can be made by forming a passivation layer, an under bump metal (UBM) layer and a conductive layer on the fifth redistribution layer 321a, and then forming bumps such as tin balls or gold balls on the conductive layer.

[0121] Reference Figure 15 Then, the temporary bonding glue is coated on the temporary carrier board, baked, and faced with the bottom first metal bonding layer 330a of the bottom glass core board 310 to temporarily protect the bottom first metal bonding layer 330a and the bottom first redistribution structure 320a of the face.

[0122] Reference Figure 16The bottom glass core plate 310 with the temporary carrier plate is then flipped over and the back of the bottom glass core plate 310 is thinned to expose the bottom conductive via 311.

[0123] Next, referring to Figure 17 A bottom second redistribution layer 320b is formed on the second side 110b of the bottom glass core plate 310; specifically, a sixth metal wiring layer 3212b is first provided on the bottom glass core plate 310 and covers a surface of the bottom conductive via 311 so that the two are electrically connected. A sixth dielectric layer 3211b is then laminated on the bottom glass core plate 310 and the sixth metal wiring layer 3212b, and sixth vias 3213b are then formed in the sixth dielectric layer 3211b. One or more sixth vias 3213b can penetrate one or more sixth dielectric layers 3211b and contact the sixth metal wiring layer 3212b. One or more build-up films (second dielectric layers) are then laminated on the upper surface of the sixth dielectric layer 3211b, and the sixth metal wiring layer 3212b and the sixth vias 3213b of the sixth redistribution layer 321b of each layer are formed accordingly to complete the formation of the bottom second redistribution layer 320b. The sixth dielectric layer 3211b can be a wet film, a dry film, or a non-photosensitive material; the wet film uses a coating, baking, exposure, and development process, the dry film uses a roller or vacuum film lamination, baking, exposure, and development process, and the non-photosensitive material uses a roller or vacuum film lamination, baking, and laser drilling process.

[0124] A bottom second metal bonding layer 330b is then formed on the outer surface of the sixth redistribution layer 321b of the outermost layer of the bottom second redistribution layer 320b. The bottom second metal bonding layer 330b can be formed by forming a passivation layer on the sixth redistribution layer 321b and then windowing and electroplating to form bumps, such as copper pillars.

[0125] Next, referring to Figure 18 The temporary carrier plate is removed using laser disassembly bonding, and the wafer is then film-laminated and diced to form a plurality of bottom glass sub- substrates 30.

[0126] Next, the top glass sub-substrate 20, the middle glass sub-substrate 10, and the bottom glass sub-substrate 30 are aligned according to design requirements and are thermocompression bonded through the metal bonding layers to sequentially complete multilayer stacking, for example Figure 19 The middle first metal bonding layer 130a of the middle glass sub-substrate 10 and the bottom second metal bonding layer 330b of the bottom glass sub-substrate 30 are aligned and are thermocompression bonded, and then the middle second metal bonding layer 130b of the middle glass sub-substrate 10 and the top second metal bonding layer 230b of the top glass sub-substrate 20 are aligned and are thermocompression bonded to form Figure 19The thermal compression bonding temperature is 250-300℃, the pressure is 5-10Mpa, and the time is 5-10min.

[0127] In addition, the number of stacked layers of the stack can be designed according to actual needs.

[0128] Finally, referring to Figure 1 The bonding gap filling material 40 between the two adjacent sub-boards of the stack is filled to form a glass interposer stack substrate 1. For example, the Underfill method is used to coat a certain amount of glue on the bottom edge of the substrate. After the glue fills the gap between the substrates by capillary action, the glue is heat-cured to become solid, achieving the functions of adhesion, support and protection.

[0129] As can be seen from the above, the glass sub-boards of the glass interposer stack substrate 1 can be processed in parallel, the process flow is shortened, and each glass sub-board contains a glass core board, which can reduce the overall warpage; the two adjacent sub-boards are aligned and bonded by the metal bonding layer, which can improve the yield of the product. In the glass interposer stack substrate 1, when the CTE of the top glass core board 210 is 3 ppm / ℃, the CTE of the middle glass core board 110 is 6 ppm / ℃, and the CTE of the bottom glass core board 310 is 9 ppm / ℃, as shown in Figure 21 , the overall warpage of the glass interposer stack substrate 1 after lamination is about 82 μm, while the overall warpage of the traditional multilayer board (i.e. one glass core board with multiple RDLs) after lamination is about 122 μm (referring to Figure 22 ), the warpage of the glass interposer stack substrate 1 of the present embodiment is greatly reduced.

[0130] Referring to Figure 20 , according to one or more embodiments of the present application, a semiconductor package structure is also provided, which includes the above-mentioned glass interposer stack substrate 1 and a semiconductor chip. The semiconductor chip can include a high bandwidth memory HBM 2 and a graphics processing unit GPU chip 3; the high bandwidth memory HBM 2 and the graphics processing unit GPU chip 3 are flip-chip mounted on the top glass sub-board 20. However, the embodiments are not limited thereto, and semiconductor chips other than SOC or HBM can be provided, such as logic chips: central processing unit (CPU) field programmable gate array (FPGA), digital signal processor (DSP), application specific integrated circuit (ASIC), or memory chips: dynamic random access memory (DRAM) chip and NAND chip.

[0131] Among them, the high bandwidth memory HBM 2 is a stacked multilayer chip, and a bottom filling glue is filled between two adjacent layers of chips. In addition, the high bandwidth memory HBM 2 / graphic processing unit GPU chip 3 is also filled with a bottom filling glue between the glass interlayer stacked substrate 1. The bottom filling layer can include epoxy or two or more silicon mixed materials. The side of the glass interlayer stacked substrate 1 away from the semiconductor chip is connected to the PCB board, realizing electrical interconnection with the external circuit.

[0132] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0133] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0134] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0135] In the present application, unless otherwise explicitly specified and limited, the "upper" or "lower" of the first feature to the second feature can include the direct contact of the first and second features, or can include the contact of the first and second features through another feature between them. Moreover, the "above", "over" and "on" of the first feature to the second feature includes the vertical direction of the first feature above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The "below", "under" and "under" of the first feature to the second feature includes the vertical direction of the first feature below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0136] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative expression of the above terms should not be understood as necessarily referring to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in an appropriate manner. In addition, those skilled in the art can combine and integrate different embodiments or examples described in the present specification.

[0137] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary, and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, substitutions and variations to the above-described embodiments within the scope of the present application.

Claims

1. A glass interposer stacked substrate, characterized in that, include: At least three glass sub-substrates disposed along the stacking direction, each of the glass sub-substrates comprising: A glass core board having a through-hole in the glass, wherein the through-hole is filled with a conductive material to form a conductive through-hole; Two redistribution structures are formed on opposite sides of the glass core board, corresponding to each other, and are electrically interconnected through the conductive vias; each redistribution structure has at least two redistribution layers, each redistribution layer including a dielectric layer, a metal wiring layer and a plurality of vias; the vias electrically connect the metal wiring layers of two adjacent redistribution layers; A metal bonding layer is disposed on the side of each redistribution structure opposite to the glass core board and is electrically connected to the redistribution structure; the metal bonding layer consists of a plurality of protrusions spaced apart on the side of the redistribution structure opposite to the glass core board. The bumps on one of the redistribution structures of the glass sub-substrate are solder balls or gold balls, and the bumps on the other redistribution structure are copper pillars. Along the stacking direction, the glass core of the top glass sub-substrate has a coefficient of thermal expansion of less than 5 ppm / ℃ and a thermal conductivity of 1.2 W / (m·K), and the glass sub-substrate uses silver metal wiring; the glass core of the bottom glass sub-substrate has a coefficient of thermal expansion of greater than 5 ppm / ℃, and the linewidth of the metal wiring layer of at least one wiring structure of the glass sub-substrate gradually widens from the conductive via to the metal bonding layer; the glass core of the glass sub-substrate located between the top and bottom layers has a dielectric constant of 4-7 and a dielectric loss of 0.007-0.009, and the glass sub-substrate uses silver metal wiring; Along the stacking direction, any two adjacent glass sub-substrates are stacked and bonded through the metal bonding layer, and the bonding gap between the two adjacent glass sub-substrates is filled with a filler material to form the glass interposer stacked substrate.

2. The glass interposer stacked substrate as described in claim 1, characterized in that, At least one of the redistribution structures of the underlying glass sub-substrate has a first dielectric layer formed of a first dielectric material and a second dielectric layer formed of a second dielectric material, wherein the first dielectric layer is an epoxy resin material and is disposed adjacent to the glass core; the second dielectric layer is a siloxane film and is disposed on the outermost metal wiring layer of the redistribution structure.

3. The glass interposer stacked substrate as described in claim 1, characterized in that, Along the stacking direction, the linewidth of the metal wiring layer of the redistribution structure of the top glass sub-substrate is 2 μm and the line spacing is 2 μm; the linewidth of the redistribution structure of the bottom glass sub-substrate is 5 μm-10 μm and the line spacing is 5 μm-10 μm; the linewidth of the metal wiring layer of the redistribution structure of the glass sub-substrate located between the top and bottom layers is 3 μm-5 μm and the line spacing is 3 μm-5 μm; from the top glass sub-substrate to the bottom glass sub-substrate, the metal wiring layers of the redistribution structure are arranged from dense to sparse.

4. The glass interposer stacked substrate as described in claim 1, characterized in that, The glass core of the top glass sub-substrate is borosilicate glass, and the borosilicate glass is doped with Al2O3 thermally conductive particles.

5. The glass interposer stacked substrate as described in claim 1, characterized in that, The conductive vias and metal wiring layers of the top glass sub-substrate each have a seed layer and a conductive layer covering the seed layer. The seed layer includes a titanium layer, or a titanium layer and a copper layer; the conductive layer is a silver layer.

6. The glass interposer stacked substrate as described in claim 1, characterized in that, The conductive vias and metal wiring layers of the glass sub-substrate located between the top and bottom layers each have a seed layer and a conductive layer covering the seed layer. The seed layer includes a titanium layer, or a titanium layer and a copper layer; the conductive layer is a silver layer.

7. The glass interposer stacked substrate as described in claim 1, characterized in that, The filler material is LCM material, LMUF material, CUF material, thermally conductive adhesive, prepreg, or NCF film.

8. A method for fabricating a glass interposer stacked substrate, characterized in that, Includes the following steps: Provide at least three types of glass core boards with conductive through holes; A redistribution structure is provided on each of the opposite sides of each of the glass core boards; each redistribution structure has at least two redistribution layers; the redistribution layer includes a dielectric layer, a metal wiring layer and a plurality of vias; the vias electrically connect the metal wiring layers of two adjacent redistribution layers; A metal bonding layer is provided on the side of each redistribution structure opposite to the glass core, and the wafer is diced to form at least three types of glass sub-substrates; providing the metal bonding layer includes providing a plurality of spaced bumps that are electrically connected to the redistribution structure on the side of the redistribution structure opposite to the glass core; the bumps on one of the redistribution structures of the glass sub-substrates are solder balls or gold balls, and the bumps on the other redistribution structure are copper pillars; The at least three types of glass sub-substrates are sequentially stacked and bonded along the stacking direction using the metal bonding layer, and the bonding gap between two adjacent glass sub-substrates is filled with filler material to form the glass interlayer stacked substrate. Along the stacking direction, the glass core of the top glass sub-substrate has a coefficient of thermal expansion of less than 5 ppm / ℃ and a thermal conductivity of 1.2 W / (m·K), and the glass sub-substrate uses silver metal wiring; the glass core of the bottom glass sub-substrate has a coefficient of thermal expansion of greater than 5 ppm / ℃, and the linewidth of the metal wiring layer of at least one wiring structure of the glass sub-substrate gradually widens from the conductive via to the metal bonding layer; the glass core of the glass sub-substrate located between the top and bottom layers has a dielectric constant of 4-7 and a dielectric loss of 0.007-0.009, and the glass sub-substrate uses silver metal wiring.

9. The method for fabricating a glass interposer stacked substrate as described in claim 8, characterized in that, The filler material is LCM material, LMUF material, CUF material, thermally conductive adhesive, prepreg, or NCF film.

10. A semiconductor packaging structure, characterized in that, The glass interposer stacked substrate includes any one of claims 1-7, or the glass interposer stacked substrate prepared by the manufacturing method of claim 8 or 9; A semiconductor chip is flip-chip mounted on the glass interposer stack substrate and electrically connected to the metal bonding layer of the uppermost glass sub-substrate. as well as Bottom filler adhesive is used to fill the space between the semiconductor chip and the uppermost glass sub-substrate.

11. The semiconductor packaging structure as described in claim 10, characterized in that, The semiconductor chip includes a high-bandwidth memory (HBM) and a graphics processing unit (GPU) chip, both of which are flip-chip mounted on the uppermost glass sub-substrate. The side of the glass interposer stack substrate facing away from the semiconductor chip is connected to the PCB board to achieve electrical interconnection with external circuits.

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