Offset information calculation method

By identifying the tangent at the symmetrical point of the wafer edge notch using a vision component, and combining the resolution and coordinate axis calibration information, the wafer offset is calculated. This solves the problem of low efficiency in acquiring offset information in existing wafer alignment devices, and achieves efficient wafer alignment.

CN121452966AActive Publication Date: 2026-02-03JIANGSU JIANGLING SEMICON CO LTD

Patent Information

Application Number
CN202610019781.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-01-07
Publication Date
2026-02-03
Estimated Expiration
2046-01-07

AI Technical Summary

Technical Problem

In the prior art, wafer alignment devices are inefficient in acquiring offset information between two wafers, and multiple image processing steps are cumbersome.

Method used

A vision component is used to acquire the image to be processed between the first wafer and the second wafer. By identifying the tangent and mirror lines at the symmetrical points of the notch, the distance information and angular offset are calculated. The lateral offset is obtained by fitting the resolution and coordinate axis calibration information.

Benefits of technology

It improves the efficiency of offset information acquisition, simplifies the image processing flow, and enhances the efficiency of wafer alignment.

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Abstract

The invention relates to the field of semiconductor manufacturing, and discloses an offset information calculation method. The offset information calculation method comprises the following steps: acquiring a first to-be-processed image and at least one second to-be-processed image acquired by a visual component between a first wafer and a second wafer which are oppositely arranged; processing the first to-be-processed image to obtain first distance information and angle offset; processing the second to-be-processed image to obtain second distance information; and performing fitting calculation on the first distance information and the second distance information to obtain a first transverse offset and a second transverse offset of the second wafer relative to the first wafer, and taking the first transverse offset, the second transverse offset and the angle offset as offset information. According to the offset information calculation method provided by the embodiment of the invention, the acquisition efficiency of the offset information between the two wafers is improved.
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Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a method for calculating offset information. BACKGROUND

[0002] Before bonding two wafers, the two wafers need to be aligned with each other. In the related art, a wafer alignment device collects edge images of multiple positions of the two wafers, and then relies on processing of the multiple images to control the alignment of the two wafers with each other. In the related art, the process of processing the multiple images is relatively cumbersome, resulting in low efficiency of obtaining offset information between the two wafers. SUMMARY

[0003] Embodiments of the present application provide a method for calculating offset information, which improves the efficiency of obtaining offset information between two wafers.

[0004] In a first aspect, the embodiments of the present application provide a method for calculating offset information, which includes: obtaining a first to-be-processed image and at least one second to-be-processed image collected by a vision assembly between a first wafer and a second wafer placed oppositely, the first to-be-processed image including an image of a first notch of an edge of the first wafer and an image of a second notch of an edge of the second wafer, the second to-be-processed image including an image of part of the edge of the first wafer and an image of part of the edge of the second wafer, the first notch and the second notch being symmetrical patterns; processing the first to-be-processed image to obtain first distance information and an angle offset, including: determining a first boundary line in the first to-be-processed image, and identifying a first contour line and a second contour line on two sides of the first boundary line in the first to-be-processed image, the first contour line and the second contour line corresponding to the edge of the first wafer and the edge of the second wafer respectively, determining the first distance information and the angle offset based on a first tangent line at a symmetrical point of a notch in the first contour line and a second tangent line at a symmetrical point of a notch in a mirror line of the second contour line; processing the second to-be-processed image to obtain second distance information, the first distance information and the second distance information respectively representing offset pixel values of the second wafer relative to the first wafer in the corresponding to-be-processed image; performing fitting calculation on the first distance information and the second distance information to obtain a first lateral offset and a second lateral offset of the second wafer relative to the first wafer, and taking the first lateral offset, the second lateral offset, and the angle offset as the offset information.

[0005] According to the foregoing embodiments of the first aspect of the present application, a line connecting the collection positions of any two to-be-processed images does not pass through the center of the first wafer.

[0006] According to any one of the foregoing embodiments of the first aspect of the application, the determining the first boundary line in the first to-be-processed image comprises: obtaining boundary line information of the visual component, the boundary line information being position information of a boundary line between two sub-images in the to-be-processed image obtained by the visual component; and determining the first boundary line in the first to-be-processed image based on the boundary line information of the visual component that captured the first to-be-processed image.

[0007] According to any one of the foregoing embodiments of the first aspect of the application, before the determining the first distance information and the angle offset based on the first tangent line at the symmetric point of the notch in the first contour line and the second tangent line at the symmetric point of the notch in the mirror image line of the second contour line, the processing the first to-be-processed image to obtain the first distance information and the angle offset further comprises: constructing a first mirror image line, the first mirror image line being symmetrical to the second contour line about the first boundary line axis, the first mirror image line having a third notch corresponding to a mirror image of the second notch on the second contour line; obtaining the first tangent line at the symmetric point of the first notch in the first contour line; and obtaining the second tangent line at the symmetric point of the third notch in the first mirror image line.

[0008] According to any one of the foregoing embodiments of the first aspect of the application, the determining the first distance information and the angle offset based on the first tangent line at the symmetric point of the notch in the first contour line and the second tangent line at the symmetric point of the notch in the mirror image line of the second contour line comprises: constructing a first reference line, the first reference line being perpendicular to the first boundary line and bisecting the first to-be-processed image; obtaining a first intersection point of the first tangent line and the first reference line, and a second intersection point of the second tangent line and the first reference line; and taking a distance between the first intersection point and the second intersection point as the first distance information; and obtaining the angle offset according to an included angle between the first tangent line and the second tangent line.

[0009] According to any one of the foregoing embodiments of the first aspect of the application, the processing of the second to-be-processed image to obtain second distance information comprises: determining a second boundary line in the second to-be-processed image based on boundary line information of a vision component that acquires the second to-be-processed image; performing feature recognition in the second to-be-processed image to obtain a third contour line and a fourth contour line located on two sides of the second boundary line, the third contour line corresponding to a partial edge of the first wafer, and the fourth contour line corresponding to a partial edge of the second wafer; constructing a second mirror line and a second reference line, the second mirror line being axisymmetric about the second boundary line with respect to the fourth contour line, and the second reference line being parallel to the second boundary line and intersecting the third contour line and the second mirror line; obtaining a third intersection point of the third contour line and the second reference line, and obtaining a fourth intersection point of the second mirror line and the second reference line, and taking a distance between the third intersection point and the fourth intersection point as the second distance information.

[0010] According to any one of the foregoing embodiments of the first aspect of the application, the fitting calculation of the first distance information and the second distance information to obtain a first lateral offset and a second lateral offset of the second wafer relative to the first wafer comprises: obtaining resolution calibration information and coordinate axis calibration information corresponding to a vision component, wherein the resolution calibration information is a mapping relationship between a size of a single pixel in a to-be-processed image acquired by the vision component and an actual physical size, and the coordinate axis calibration information is a mapping relationship between a rectangular coordinate axis in the to-be-processed image acquired by the vision component and a first lateral direction and a second lateral direction, the first lateral direction and the second lateral direction being orthogonal in a plane parallel to the first wafer; and fitting to obtain the first lateral offset and the second lateral offset according to the first distance information, the second distance information, the resolution calibration information, and the coordinate axis calibration information.

[0011] According to any one of the foregoing embodiments of the first aspect of the application, the method further comprises: obtaining a third to-be-processed image acquired by the vision component, and processing the third to-be-processed image to obtain third distance information, the third to-be-processed image comprising an image of a partial edge of the first wafer and an image of a partial edge of the second wafer; and fitting to obtain the first lateral offset and the second lateral offset according to the first distance information, the second distance information, the resolution calibration information, and the coordinate axis calibration information comprises: fitting to obtain the first lateral offset and the second lateral offset according to the first distance information, the second distance information, the third distance information, the resolution calibration information, and the coordinate axis calibration information.

[0012] According to any one of the foregoing embodiments of the first aspect of the application, the visual assembly comprises a camera, a light source, a semi-transparent beam splitter, and a beam splitter prism, the camera, the semi-transparent beam splitter, and the beam splitter prism are sequentially arranged along a preset axis, the light source is located on one side of the preset axis, an outlight surface of the light source faces the semi-transparent beam splitter, and an outgoing light ray of the light source can be reflected by the semi-transparent beam splitter and projected to the beam splitter prism, the beam splitter prism can extend to between the first wafer and the second wafer placed opposite to each other, the beam splitter prism comprises a first inclined surface inclined toward the first wafer and a second inclined surface inclined toward the second wafer, the first inclined surface and the second inclined surface are symmetrically arranged, and the camera is configured to acquire a to-be-processed image, the to-be-processed image comprising an image of the first wafer and an image of the second wafer.

[0013] According to any one of the foregoing embodiments of the first aspect of the application, the method for obtaining the demarcation line information of the visual assembly comprises: acquiring, by the visual assembly, a calibration image of a calibration block installed at the beam splitter prism, the calibration block comprising a first calibration part and a second calibration part symmetrically arranged, the first calibration part and the second calibration part are both located on an image acquisition focal plane corresponding to the visual assembly; and obtaining the demarcation line information corresponding to the visual assembly according to the calibration image.

[0014] In a second aspect, the embodiments of the application provide a visual assembly for a wafer alignment device, the visual assembly comprising a camera, a light source, a semi-transparent beam splitter, and a beam splitter prism, the camera, the semi-transparent beam splitter, and the beam splitter prism are sequentially arranged along a preset axis, the light source is located on one side of the preset axis, an outlight surface of the light source faces the semi-transparent beam splitter, an outgoing light ray of the light source can be reflected by the semi-transparent beam splitter and projected to the beam splitter prism, the beam splitter prism can extend to between a first wafer and a second wafer placed opposite to each other, the beam splitter prism comprises a first inclined surface inclined toward the first wafer and a second inclined surface inclined toward the second wafer, the first inclined surface and the second inclined surface are symmetrically arranged, and the camera is configured to acquire a to-be-processed image, the to-be-processed image comprising an image of the first wafer and an image of the second wafer.

[0015] According to the foregoing embodiments of the second aspect of the application, the visual assembly further comprises a lens housing and a lens group, the camera and the beam splitter prism are respectively located at opposite ends of the lens housing, the semi-transparent beam splitter and the lens group are located in the lens housing, and the lens group is located between the semi-transparent beam splitter and the beam splitter prism.

[0016] In a third aspect, the embodiments of the present application provide a wafer alignment device, comprising: a base; a first carrier installed on the base, the first carrier being configured to carry a first wafer; a second carrier spaced apart from the first carrier along a longitudinal direction, the second carrier being configured to carry a second wafer; an adjusting assembly installed on the base and connected with the second carrier, the adjusting assembly being configured to drive the second carrier to move relative to the first carrier; at least two visual assemblies according to any one of the foregoing embodiments of the wafer offset information calculation method of the first aspect of the present application, distributed around the second carrier, in a state where the first carrier carries the first wafer and the second carrier carries the second wafer, the beam splitter prism of each visual assembly is located at an edge of the first wafer along a transverse direction and between the first wafer and the second wafer along the longitudinal direction, and each visual assembly is configured to acquire a corresponding image to be processed; and a control unit communicatively connected with the visual assemblies and the adjusting assembly, the control unit being configured to obtain offset information of the second wafer relative to the first wafer by using the wafer offset information calculation method, and control the adjusting assembly to drive the second carrier to move according to the offset information, so that the second wafer is aligned with the first wafer.

[0017] According to any one of the foregoing embodiments of the third aspect of the present application, for any two image acquisition positions of the visual assemblies, a line connecting the two image acquisition positions does not pass through the center of the first wafer.

[0018] According to any one of the foregoing embodiments of the third aspect of the present application, the wafer alignment device further comprises: a first support connecting the first carrier with the base, the first carrier being located on a side of the second carrier away from the base.

[0019] According to any one of the foregoing embodiments of the third aspect of the present application, the adjusting assembly comprises a first adjusting seat, a second adjusting seat, and a connecting disc, the first adjusting seat is installed on the base, the second adjusting seat is installed on the first adjusting seat, the connecting disc is installed on the second adjusting seat, the second carrier is installed on the connecting disc, the first adjusting seat is configured to drive the second adjusting seat to move along one of a first transverse direction and a second transverse direction, the second adjusting seat is configured to drive the connecting disc to move along the other of the first transverse direction and the second transverse direction, the connecting disc is configured to drive the second carrier to rotate, and the first transverse direction is orthogonal to the second transverse direction.

[0020] According to any one of the foregoing embodiments of the third aspect of the present application, the edge of the first wafer has a first notch, the edge of the second wafer has a second notch, the plurality of vision assemblies include a first vision assembly, a second vision assembly, and a third vision assembly, the first vision assembly is configured to acquire a to-be-processed image including an image of the first notch and an image of the second notch, and the wafer alignment device further includes a first mounting rack and a second mounting rack, the first mounting rack and the second mounting rack are respectively arranged on opposite sides of the first carrier, the first vision assembly is mounted on the base through the first mounting rack, and the second vision assembly and the third vision assembly are mounted on the base through the second mounting rack, and the second vision assembly and the third vision assembly are symmetrically arranged on the second mounting rack.

[0021] In a fourth aspect, the embodiments of the present application provide a wafer bonding system, which includes the wafer alignment device according to any one of the foregoing embodiments of the third aspect of the present application.

[0022] In a fifth aspect, the embodiments of the present application provide a computer readable storage medium, which has a computer program / instruction, and the computer program / instruction is executed by a processor to implement the offset information calculation method according to any one of the foregoing embodiments of the first aspect of the present application.

[0023] In a sixth aspect, the embodiments of the present application provide a control unit, which includes a memory, a processor, and a computer program stored on the memory and running on the processor, and the processor executes the program to implement the offset information calculation method according to any one of the foregoing embodiments of the first aspect of the present application.

[0024] In a seventh aspect, the embodiments of the present application provide a computer program product, which includes a computer program / instruction, and the computer program / instruction is executed by a processor to implement the steps of the offset information calculation method according to any one of the foregoing embodiments of the first aspect of the present application.

[0025] According to the offset information calculation method of this application embodiment, a first image to be processed and at least one second image to be processed are obtained between a first wafer and a second wafer placed opposite each other; the first image to be processed is processed to obtain first distance information and angular offset; the second image to be processed is processed to obtain second distance information; the first distance information and the second distance information are fitted and calculated to obtain a first lateral offset and a second lateral offset of the second wafer relative to the first wafer, and the first lateral offset, the second lateral offset, and the angular offset are used as offset information. After obtaining the offset information, it is convenient to align the second wafer with the first wafer according to the offset information, thereby realizing the operation of aligning the second wafer with the first wafer. The steps for processing the first image to be processed include: determining a first boundary line in the first image to be processed, and identifying a first contour line and a second contour line located on both sides of the first boundary line and corresponding to the edges of the first and second wafers, respectively. Based on a first tangent line at a symmetrical point of a notch in the first contour line and a second tangent line at a symmetrical point of a notch in the mirror image of the second contour line, the offset-related information in two aspects can be obtained efficiently using the tangent lines, namely, determining the first distance information and the angular offset. The above processing of the first image to be processed improves the efficiency of obtaining offset information, thereby facilitating the improvement of the efficiency of aligning the second wafer with the first wafer. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0027] Figure 1 This is a perspective schematic diagram of one embodiment of the visual component according to this application; Figure 2 This is a frontal view schematic diagram of one embodiment of the visual component according to this application; Figure 3 This is a half-section schematic diagram of one embodiment of the visual component according to this application; Figure 4 This is a flowchart illustrating one embodiment of the offset information calculation method according to this application; Figure 5 This is an image schematic diagram of a first image to be processed, as exemplified in one embodiment of the offset information calculation method of this application; Figure 6 This is an example of a second image to be processed in one embodiment of the offset information calculation method of this application; Figure 7 This is an image schematic diagram of a third image to be processed, exemplified in one embodiment of the offset information calculation method of this application; Figure 8is a top view structural schematic diagram of a step of acquiring a first to-be-processed image and at least one second to-be-processed image acquired by a vision assembly between the first wafer and the second wafer in relative placement in an embodiment of the offset information calculation method according to the present application; Figure 9 is a front view structural schematic diagram of a step of acquiring a first to-be-processed image and at least one second to-be-processed image acquired by a vision assembly between the first wafer and the second wafer in relative placement in an embodiment of the offset information calculation method according to the present application; Figure 10 is a three-dimensional schematic diagram of a calibration block in an embodiment of the offset information calculation method according to the present application; Figure 11 is a front view structural schematic diagram of a step of acquiring a calibration image of a calibration block installed at a light-splitting prism by a vision assembly in an embodiment of the offset information calculation method according to the present application; Figure 12 is a flowchart of a step of processing the first to-be-processed image to obtain first distance information and an angle offset in an embodiment of the offset information calculation method according to the present application; Figure 13 is a structural schematic diagram of the first to-be-processed image in a step of processing the first to-be-processed image in an embodiment of the offset information calculation method according to the present application; Figure 14 is a flowchart of a step of processing the second to-be-processed image to obtain second distance information in an embodiment of the offset information calculation method according to the present application; Figure 15 is a structural schematic diagram of the second to-be-processed image in a step of processing the second to-be-processed image in an embodiment of the offset information calculation method according to the present application; Figure 16 is a flowchart of a step of processing the third to-be-processed image to obtain third distance information in an embodiment of the offset information calculation method according to the present application; Figure 17 is a structural schematic diagram of the third to-be-processed image in a step of processing the third to-be-processed image in an embodiment of the offset information calculation method according to the present application; Figure 18 is a three-dimensional schematic diagram of an embodiment of a wafer alignment device according to the present application; Figure 19 is a front view schematic diagram of an embodiment of a wafer alignment device according to the present application; Figure 20 is a top view schematic diagram of an embodiment of a wafer alignment device according to the present application; Figure 21 is an electrical connection structural schematic diagram of an embodiment of a wafer alignment device according to the present application; Figure 22 is a perspective view of an adjusting assembly in an embodiment of a wafer alignment device according to the present application; Figure 23 is a schematic diagram of a hardware structure of an embodiment of a control unit according to the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments (or, “modes of implementation”) of the present application will be clearly and completely described herein with reference to the accompanying drawings. When the following description refers to the accompanying drawings, identical numbers in different drawings represent identical or similar elements unless otherwise indicated.

[0029] If the present embodiments involve directional indications or positional relationships (for example, up, down, left, right, front, back, inner, outer, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are used only to explain the relative positional relationships, movement conditions, etc. between the components in a certain posture (as shown in the drawings); if the certain posture changes, the directional indications or positional relationships also change accordingly. In addition, the terms “first”, “second”, etc. in the present embodiments are used only for the convenience of description, and cannot be understood as indicating or implying relative importance.

[0030] The present embodiments provide a vision assembly for collecting images containing two wafers at the same time. Figure 1 、 Figure 2 、 Figure 3 is a perspective view, an elevation view, and a half-section view of an embodiment of a vision assembly according to the present application. The vision assembly 100 includes a camera 110, a light source 120, a semi-transparent beam splitter 130, and a beam splitter prism 140, which are arranged along a preset axis L1 in sequence.

[0031] The light source 120 is located on one side of the preset axis L1, and the light exit surface of the light source 120 faces the semi-transparent beam splitter 130. The light rays emitted by the light source 120 can be reflected by the semi-transparent beam splitter 130 and projected toward the beam splitter prism 140. The beam splitter prism 140 can extend between the oppositely placed first wafer and second wafer, and the beam splitter prism 140 includes a first inclined surface 141 inclined toward the first wafer and a second inclined surface 142 inclined toward the second wafer, which are symmetrically arranged. The camera 110 is configured to acquire a to-be-processed image, which includes an image of the first wafer and an image of the second wafer. Specifically, each to-be-processed image includes an image of part of the edge of the first wafer and an image of part of the edge of the second wafer.

[0032] According to the visual assembly 100 in the embodiment of the present application, the visual assembly 100 is used for a wafer alignment device, and the visual assembly 100 comprises a camera 110, a light source 120, a semi-transparent beam splitter 130, and a beam splitter prism 140. The beam splitter prism 140 can be extended between the first wafer and the second wafer placed oppositely, and the beam splitter prism 140 comprises a first inclined surface 141 inclined towards the first wafer and a second inclined surface 142 inclined towards the second wafer, and the first inclined surface 141 and the second inclined surface 142 are symmetrically arranged. The light rays emitted by the light source 120 can be reflected by the semi-transparent beam splitter 130 and projected to the beam splitter prism 140, and the beam splitter prism 140 divides the incident light into two parts and focuses them on the surfaces of the first wafer and the second wafer respectively. The light rays reflected by the two wafers (the first wafer and the second wafer) pass through the beam splitter prism 140 and the semi-transparent beam splitter 130 in turn and are imaged by the camera 110, so that the image captured by the camera 110 includes the image of part of the edge of the first wafer and the image of part of the edge of the second wafer. In the embodiment of the present application, a single set of visual assembly 100 can capture the image of part of the edge of the first wafer and the image of part of the edge of the second wafer, and the single set of visual assembly 100 replaces two sets of visual assemblies in the traditional wafer alignment device to obtain the edge images of the first wafer and the second wafer, thereby facilitating the reduction of the cost of the wafer alignment device and the significant improvement of the image acquisition efficiency.

[0033] In the embodiment, the beam splitter prism 140 is a triangular prism, and the triangular prism can be an isosceles triangle. In the case that the incident light rays can be focused on the surface of the wafer through the triangular prism, the top angle of the isosceles triangle can be flexibly selected according to the placement position and angle of the wafer, such as including a right-angle side and two 45° angle sides. The right-angle side of the beam splitter prism 140 is located on a preset axis L1, and the beam splitter prism 140 is arranged symmetrically about a preset plane passing through the preset axis L1 and parallel to the first wafer (and also parallel to the second wafer) between the first wafer and the second wafer to be aligned with each other.

[0034] In some embodiments, the visual assembly 100 further comprises a lens housing 150 and a lens group 160. The camera 110 and the beam splitter prism 140 are respectively located at opposite ends of the lens housing 150. The semi-transparent beam splitter 130 and the lens group 160 are located in the lens housing 150. The lens group 160 is located between the semi-transparent beam splitter 130 and the beam splitter prism 140.

[0035] In the embodiment, the angle between the semi-transparent beam splitter 130 and the preset axis L1 can be flexibly set as the light emitting direction of the light source 120 changes, while the reflected light of the semi-transparent beam splitter 130 is kept parallel to the preset axis L1. For example, the semi-transparent beam splitter 130 is set at an angle of 45° with the preset axis L1, and the light emitting direction of the light source 120 is set at an angle of 45° with the semi-transparent beam splitter 130. In the embodiment, the light source 120 is arranged on one side of the visual assembly 100, and the incident light is focused on the two wafer surfaces by the semi-transparent beam splitter 130 and the beam splitting prism 140, which can significantly simplify the light source setting architecture and improve the overall stability of the visual assembly.

[0036] In some embodiments, the beam splitting prism 140 can be directly fixedly connected with the lens housing 150. In some embodiments, the beam splitting prism 140 can be indirectly fixedly connected with the lens housing 150, for example, the beam splitting prism 140 is arranged in a spaced manner with the lens housing 150, and is connected with each other through other connecting members, or is connected to other components through other connecting members.

[0037] In some embodiments of the present application, the visual assembly 100 can extend between the first wafer and the second wafer to be aligned with each other and collect the to-be-processed image, and at this time, the to-be-processed image includes the image of part of the edge of the first wafer and the image of part of the edge of the second wafer. The present application also discloses an offset information calculation method, which can determine the offset information between the first wafer and the second wafer based on the to-be-processed image.

[0038] Figure 4 is a flow diagram of an embodiment of the offset information calculation method according to the present application, and the offset information calculation method includes steps S110 to S140.

[0039] In step S110, a first to-be-processed image and at least one second to-be-processed image collected by the visual assembly between the relatively placed first wafer and the second wafer are obtained. In the embodiment, the visual assembly is the visual assembly 100 of any one of the foregoing embodiments. The camera 110 of the visual assembly 100 is used to obtain the to-be-processed image, and the to-be-processed image includes the image of the first wafer and the image of the second wafer. In the embodiment, the image acquisition is performed at at least two acquisition positions by the visual assembly to obtain at least two to-be-processed images, which include the first to-be-processed image and at least one second to-be-processed image. In the embodiment, the first notch and the second notch are symmetrical patterns.

[0040] Figure 5 is an image diagram of an example of the first to-be-processed image in an embodiment of the offset information calculation method according to the present application. Figure 6is a schematic diagram of a second to-be-processed image in an example of an embodiment of the offset information calculation method according to the present application. The first to-be-processed image includes an image of a first notch of a first wafer edge and an image of a second notch of a second wafer edge, and the second to-be-processed image includes an image of part of the first wafer edge and an image of part of the second wafer edge.

[0041] In the present embodiment, the notch includes a physical mark indicating a wafer direction and located at a wafer edge. The wafer can include a wafer itself, or a carrier plate, an interposer, etc. that needs to be attached to the wafer / die in advanced processes. The wafer shape can be circular, rectangular, etc. In the present embodiment, at least two to-be-processed images can be acquired, wherein the first to-be-processed image is acquired at the notch, and other to-be-processed images can be acquired at other edges of the wafer as needed, such as the smooth edge of a circular wafer, the corner of a rectangular wafer, the smooth edge, etc. The actual requirement can be determined, which is not limited here.

[0042] Optionally, in some embodiments, the offset information calculation method further includes: acquiring a third to-be-processed image acquired by the vision assembly. Figure 7 is a schematic diagram of a third to-be-processed image in an example of an embodiment of the offset information calculation method according to the present application. The third to-be-processed image includes an image of part of the first wafer edge and an image of part of the second wafer edge.

[0043] Figure 8 、 Figure 9 is a top view structural schematic diagram and a front view structural schematic diagram of the step of acquiring the first to-be-processed image and the at least one second to-be-processed image by the vision assembly between the relatively placed first wafer and the second wafer in an embodiment of the offset information calculation method according to the present application. The to-be-processed image can be acquired in various ways, such as by at least two vision assemblies at different positions to acquire images respectively, or by one vision assembly rotating and moving at the wafer edge to acquire images in turn. The line between the acquisition positions of any two to-be-processed images does not pass through the wafer center.

[0044] As Figure 8 、 Figure 9In one example, the image acquisition is performed by the vision assembly 100 at the first acquisition position TP1, the second acquisition position TP2, and the third acquisition position TP3 respectively to obtain three to-be-processed images, for example, the first to-be-processed image, the second to-be-processed image, and the third to-be-processed image. The line connecting any two of the first acquisition position TP1, the second acquisition position TP2, and the third acquisition position TP3 does not pass through the center of the wafer. The number of the vision assembly 100 can be at least two, for example, the vision assembly 100 is arranged at the first acquisition position TP1, the second acquisition position TP2, and the third acquisition position TP3, and the beam splitter prism 140 of each vision assembly 100 is located at the edge of the first wafer W1 in the lateral direction and between the first wafer W1 and the second wafer W2 in the longitudinal direction, and each vision assembly 100 is configured to acquire the to-be-processed image at the corresponding acquisition position.

[0045] In an alternative example, the image acquisition is performed by the vision assembly 100 at the first acquisition position TP1 and the second acquisition position TP2 respectively to obtain two to-be-processed images, for example, the first to-be-processed image and the second to-be-processed image. The line connecting the first acquisition position TP1 and the second acquisition position TP2 does not pass through the center of the wafer.

[0046] In an alternative example, the number of the vision assembly 100 is one, which is arranged to rotate and move at the edge of the first wafer and sequentially acquire images at different positions, for example, the first acquisition position TP1, the second acquisition position TP2, and the third acquisition position TP3, to obtain three to-be-processed images, for example, the first to-be-processed image, the second to-be-processed image, and the third to-be-processed image. The line connecting any two of the first acquisition position TP1, the second acquisition position TP2, and the third acquisition position TP3 does not pass through the center of the wafer.

[0047] As Figure 4 In step S120, the first to-be-processed image is processed to obtain the first distance information and the angle offset. The first distance information respectively represents the offset pixel value of the second wafer relative to the first wafer in the first to-be-processed image.

[0048] In the embodiment, the step S120 of processing the first to-be-processed image to obtain the first distance information and the angle offset includes: determining the first boundary line in the first to-be-processed image, and identifying the first contour line and the second contour line on the two sides of the first boundary line in the first to-be-processed image, which respectively correspond to the edge of the first wafer and the edge of the second wafer; determining the first distance information and the angle offset based on the first tangent line at the symmetric point of the notch in the first contour line and the second tangent line at the symmetric point of the notch in the mirror line of the second contour line.

[0049] In some embodiments, the step of determining the first boundary line in the first to-be-processed image can comprise: obtaining boundary line information of the vision assembly, the boundary line information being position information of a boundary line between two sub-images in a to-be-processed image obtained by the vision assembly; and determining the first boundary line in the first to-be-processed image based on the boundary line information of the vision assembly that captured the first to-be-processed image.

[0050] There are various ways to process the to-be-processed image to obtain distance information and angular offset, such as constructing and training a neural network model (e.g., in the model, features are extracted by an encoder, optimized by spatial attention, pooling, global information extraction, etc., and distance information and angular offset are output by a multilayer perceptron), inputting the to-be-processed image into the trained neural network model, and obtaining distance information and angular offset.

[0051] Due to the symmetrical arrangement of the light splitting prism 140 in the vision assembly 100 in the embodiments of the present application, the to-be-processed image includes images of positions of the upper and lower wafers (the first wafer and the second wafer) that are symmetrical to each other. If the upper and lower wafers are completely aligned, the features (such as edge lines, positioning marks, notches) of the upper and lower wafers in the image should also be symmetrical on the image. If there is an offset between the upper and lower wafers, the features of the upper and lower wafers will also be offset on the image. Therefore, the embodiments of the present application can also use this point to calculate the offset information of the upper and lower wafers in the physical space based on the offset of the features on the image.

[0052] Specifically, the boundary line information of the vision assembly 100 can be obtained, the boundary line information being position information of a boundary line between two sub-images in a to-be-processed image obtained by the vision assembly 100, one of the two sub-images being obtained via the first inclined surface 141 and the other being obtained via the second inclined surface 142. In some embodiments, the boundary line information can include coordinate information of the symmetry axis of the two sub-images, such as the midpoint coordinate information of the image in the horizontal direction, so as to divide the boundary line on the corresponding image based on the coordinate information.

[0053] According to the boundary line information, a boundary line can be divided in the to-be-processed image, two contour lines located on both sides of the to-be-processed image are obtained through feature recognition, the two contour lines correspond to part of the edges of the upper and lower wafers, respectively, a mirror line of one contour line on the other side of the boundary line is determined according to the principle of axis symmetry, and finally the angular offset and the distance information of the image dimension are determined through the position difference between the mirror line and the contour line on the same side of the boundary line.

[0054] For example, for the first to-be-processed image containing notches, a first reference line can be constructed, the first reference line being perpendicular to the first boundary line and bisecting the first to-be-processed image; a first tangent line at a symmetry point of the first notch in the first contour line is obtained, and a second tangent line at a symmetry point of the third notch in the first mirror image line is obtained; a first intersection point of the first tangent line and the first reference line is obtained, a second intersection point of the second tangent line and the first reference line is obtained, and a distance between the first intersection point and the second intersection point is taken as the first distance information; and an angle offset is obtained according to an included angle between the first tangent line and the second tangent line.

[0055] In some embodiments, the step of processing the first to-be-processed image to obtain the first distance information and the angle offset can include: obtaining boundary line information of the visual assembly, the boundary line information being position information of a boundary line between two sub-images in a to-be-processed image obtained by the visual assembly 100, one of the two sub-images being obtained via the first inclined surface 141 and the other being obtained via the second inclined surface 142; determining a first boundary line in the first to-be-processed image based on the boundary line information of the visual assembly from which the first to-be-processed image is collected; and processing the first to-be-processed image based on the first boundary line to obtain the first distance information and the angle offset.

[0056] The visual assembly can be the visual assembly 100 of any of the preceding embodiments, and the visual assembly 100 includes a camera 110, a light source 120, a semi-transparent beam splitter 130, and a beam splitter prism 140, which are arranged in sequence along a preset axis L1. The light source 120 is located on one side of the preset axis L1, and an emitting surface of the light source 120 faces the semi-transparent beam splitter 130. The light emitted by the light source 120 can be reflected by the semi-transparent beam splitter 130 and projected toward the beam splitter prism 140. The beam splitter prism 140 can extend between the oppositely placed first wafer and second wafer, and the beam splitter prism 140 includes a first inclined surface 141 inclined toward the first wafer and a second inclined surface 142 inclined toward the second wafer, which are symmetrically arranged. The camera 110 is configured to obtain a to-be-processed image, which includes an image of the first wafer and an image of the second wafer.

[0057] In some embodiments, the step of obtaining the boundary line information of the visual assembly can include: obtaining, by the visual assembly, a calibration image of a calibration block installed at the beam splitter prism, the calibration block including a first calibration portion and a second calibration portion symmetrically arranged, both of which are located on an image acquisition focal plane corresponding to the visual assembly; and obtaining the boundary line information corresponding to the visual assembly according to the calibration image.

[0058] Figure 10 is a perspective view of a calibration block according to an embodiment of the offset information calculation method of the present application,Figure 11 This is a frontal structural diagram illustrating the acquisition of a calibration image of a calibration block mounted at a beam splitter using a vision component in one embodiment of the offset information calculation method according to this application. Figure 10 The light rays are indicated by dashed lines. The calibration block 900 includes a first calibration section 910 and a second calibration section 920 symmetrically arranged. When calibrating the vision component 100 to obtain boundary line information, the calibration block 900 can be installed at the beam splitter 140. With the calibration block 900 installed at the beam splitter 140, both the first calibration section 910 and the second calibration section 920 are located on the image acquisition focal plane of the corresponding vision component 100. With the calibration block 900 installed at the beam splitter 140, the vision component 100 acquires a calibration image of the calibration block 900 installed at the beam splitter 140, and then obtains the boundary line information corresponding to the vision component 100 based on this calibration image.

[0059] like Figure 8 In this embodiment, at least two visual components 100, including a first visual component 100a, a second visual component 100b, and a third visual component 100c, are used as an example. The first visual component 100a, the second visual component 100b, and the third visual component 100c are sequentially located at a first acquisition position TP1, a second acquisition position TP2, and a third acquisition position TP3. In one example, the boundary line information of the first visual component 100a, the second visual component 100b, and the third visual component 100c are denoted as T1, T2, and T3, respectively. In one example, the boundary line information can be the endpoint coordinates (in the camera world) of the boundary line between two sub-images in the image to be processed.

[0060] In this embodiment, both the first notch and the second notch are symmetrical patterns.

[0061] Figure 12 This is a flowchart illustrating the process of processing a first image to be processed to obtain first distance information and angular offset, according to one embodiment of the offset information calculation method of this application. Figure 13 This is a schematic diagram of the structure of a first image to be processed, processed according to one embodiment of the offset information calculation method of this application. In some embodiments, the first image to be processed may be rotated first; in some embodiments, the first image to be processed may not be rotated. This embodiment describes the process without rotating the first image to be processed. The steps of processing the first image to be processed to obtain the first distance information and the angle offset may include steps S121 to S125.

[0062] In step S121, a first dividing line T1 is determined in the first image to be processed.

[0063] In step S122, a first contour line Q1 and a second contour line Q2 are identified in the first to-be-processed image and located on two sides of the first boundary line T1, and correspond to edges of the first wafer W1 and the second wafer W2 respectively. The first contour line Q1 corresponds to a partial edge of the first wafer W1, and the second contour line Q2 corresponds to a partial edge of the second wafer W2.

[0064] Then, in step S125, based on a first tangent line K1 at a symmetric point of the notch in the first contour line Q1 and a second tangent line K2 at a symmetric point of the notch in the mirror line of the second contour line Q2, the first distance information dy1 and the angle offset U are determined.

[0065] In the present embodiment, before step S125 of determining the first distance information dy1 and the angle offset U based on the first tangent line K1 at the symmetric point of the notch in the first contour line Q1 and the second tangent line K2 at the symmetric point of the notch in the mirror line of the second contour line Q2, the step of processing the first to-be-processed image to obtain the first distance information and the angle offset further includes steps S123 and S124.

[0066] In step S123, a first mirror line P1 is constructed. The first mirror line P1 is axially symmetrical about the first boundary line T1 with respect to the second contour line Q2, and the first mirror line P1 has a third notch J3 corresponding to a mirror image of the second notch J2 on the second contour line Q2.

[0067] In step S124, a first tangent line K1 at a symmetric point R1 of the first notch J1 in the first contour line Q1 is obtained, and a second tangent line K2 at a symmetric point R3 of the third notch J3 in the first mirror line P1 is obtained.

[0068] In the present embodiment, step S125 of determining the first distance information dy1 and the angle offset U based on the first tangent line K1 at the symmetric point of the notch in the first contour line Q1 and the second tangent line K2 at the symmetric point of the notch in the mirror line of the second contour line Q2 can include: constructing a first reference line V1, the first reference line V1 being perpendicular to the first boundary line T1 and dividing the first to-be-processed image in half; obtaining a first intersection point F1 of the first tangent line K1 and the first reference line V1, obtaining a second intersection point F2 of the second tangent line K2 and the first reference line V1, taking a distance between the first intersection point F1 and the second intersection point F2 as the first distance information dy1; and obtaining the angle offset U according to an included angle between the first tangent line K1 and the second tangent line K2.

[0069] As Figure 4In step S130, the second to-be-processed image is processed to obtain second distance information. The first distance information and the second distance information respectively represent the offset pixels of the second wafer relative to the first wafer in the corresponding to-be-processed image. Therefore, the second distance information respectively represents the offset pixels of the second wafer relative to the first wafer in the second to-be-processed image.

[0070] Figure 14 FIG. 6 is a flowchart of a process of processing the second to-be-processed image to obtain second distance information according to an embodiment of the offset information calculation method of the present application, Figure 15 FIG. 7 is a schematic diagram of a structure of the second to-be-processed image according to an embodiment of the offset information calculation method of the present application. In some embodiments, the second to-be-processed image can be first processed by rotation, and in some embodiments, the second to-be-processed image can also not be processed by rotation. In this embodiment, a case of processing the second to-be-processed image by clockwise rotation of 90° is taken as an example for description.

[0071] In some embodiments, the step of processing the second to-be-processed image to obtain the second distance information can include steps S131 to S134.

[0072] In step S131, based on the boundary line information of the vision component 100 that collects the second to-be-processed image, a second boundary line T2 is determined in the second to-be-processed image.

[0073] In step S132, feature recognition is performed in the second to-be-processed image to obtain a third contour line Q3 and a fourth contour line Q4 located on two sides of the second boundary line T2. The third contour line Q3 corresponds to a part of the edge of the first wafer W1, and the fourth contour line Q4 corresponds to a part of the edge of the second wafer W2.

[0074] In step S133, a second mirror line P2 and a second reference line V2 are constructed. The second mirror line P2 is axially symmetrical about the second boundary line T2 with respect to the fourth contour line Q4, and the second reference line V2 is parallel to the second boundary line T2 and intersects the third contour line Q3 and the second mirror line P2.

[0075] In step S134, a third intersection point F3 of the third contour line Q3 and the second reference line V2 is obtained, a fourth intersection point F4 of the second mirror line P2 and the second reference line V2 is obtained, and a distance between the third intersection point F3 and the fourth intersection point F4 is taken as the second distance information dy2.

[0076] Optionally, in some embodiments, the offset information calculation method further includes: obtaining a third to-be-processed image collected by the vision component, and processing the third to-be-processed image to obtain third distance information. The third to-be-processed image includes an image of a part of the edge of the first wafer and an image of a part of the edge of the second wafer.

[0077] Figure 16 This is a flowchart illustrating the process of processing a third image to obtain third distance information according to one embodiment of the offset information calculation method of this application. Figure 17 This is a schematic diagram of the structure of a third image to be processed, processed according to one embodiment of the offset information calculation method of this application. In some embodiments, the third image to be processed may be rotated first; in some embodiments, the third image to be processed may not be rotated. This embodiment illustrates the process of first rotating the third image to be processed counterclockwise by 90° as an example.

[0078] In some embodiments, processing the third image to be processed to obtain third distance information may include steps S161 to S164.

[0079] In step S161, a third boundary line T3 is determined in the third image to be processed based on the boundary line information of the visual component 100 that acquires the third image to be processed.

[0080] In step S162, feature recognition is performed in the third image to be processed to obtain the fifth contour line Q5 and the sixth contour line Q6 located on both sides of the third boundary line T3. The fifth contour line Q5 corresponds to a portion of the edge of the first wafer W1, and the sixth contour line Q6 corresponds to a portion of the edge of the second wafer W2.

[0081] In step S163, a third mirror line P3 and a third reference line V3 are constructed. The third mirror line P3 is symmetrical to the sixth contour line Q6 about the third boundary line T3, and the third reference line V3 is parallel to the third boundary line T3 and intersects the fifth contour line Q5 and the third mirror line P3.

[0082] In step S164, the fifth intersection point F5 of the fifth contour line Q5 and the third reference line V3 is obtained, and the sixth intersection point F6 of the third mirror line P3 and the third reference line V3 is obtained. The distance between the fifth intersection point F5 and the sixth intersection point F6 is used as the third distance information dy3.

[0083] In step S140, the first distance information and the second distance information are fitted and calculated to obtain the first lateral offset and the second lateral offset of the second wafer relative to the first wafer, and the first lateral offset, the second lateral offset, and the angle offset are used as offset information.

[0084] There are multiple ways to implement this, such as using large models, intelligent agents, machine learning models, deep learning models, etc., to enable them to learn and have the ability to directly output offset information through a certain amount of sample data.

[0085] For example, the first lateral offset N1 and the second lateral offset N2 can be solved based on the at least two distance information, resolution calibration information of the vision component, and coordinate axis calibration information.

[0086] In some embodiments, the step S130 of performing fitting calculation on the first distance information dy1 and the second distance information dy2 to obtain the first lateral offset N1 and the second lateral offset N2 of the second wafer relative to the first wafer includes: obtaining resolution calibration information and coordinate axis calibration information corresponding to the vision component; and fitting the first lateral offset N1 and the second lateral offset N2 according to the first distance information dy1, the second distance information dy2, the resolution calibration information, and the coordinate axis calibration information.

[0087] The resolution calibration information is a mapping relationship between a size of a single pixel in a to-be-processed image obtained by the vision component 100 and an actual physical size. In one example, taking at least two vision components 100 including a first vision component 100a, a second vision component 100b, and a third vision component 100c as an example, the obtained resolution calibration information of the first vision component 100a, the second vision component 100b, and the third vision component 100c are denoted as Size1, Size2, and Size3, respectively. One example of the resolution calibration information Size1 of the first vision component 100a is 2 um / pixel.

[0088] The coordinate axis calibration information is a mapping relationship between a right-angle coordinate axis in a to-be-processed image obtained by the vision component 100 and a first lateral direction X and a second lateral direction Y, the first lateral direction X and the second lateral direction Y being orthogonal in a plane parallel to the first wafer W1. That is, the coordinate axis calibration information is a mapping relationship between two right-angle coordinate axes of a camera world of each vision component 100 and the first lateral direction X and the second lateral direction Y in a real world. In one example, taking at least two vision components 100 including a first vision component 100a, a second vision component 100b, and a third vision component 100c as an example, the obtained coordinate axis calibration information of the first vision component 100a is denoted as AxisX1 and AxisY1, the obtained coordinate axis calibration information of the second vision component 100b is denoted as AxisX2 and AxisY2, and the obtained coordinate axis calibration information of the third vision component 100c is denoted as AxisX3 and AxisY3.

[0089] Optionally, in some of the above-mentioned embodiments, the offset information calculation method further comprises: acquiring a third to-be-processed image captured by the vision assembly, and processing the third to-be-processed image to obtain third distance information dy3, the third to-be-processed image comprising an image of part of the first wafer edge and an image of part of the second wafer edge. At this time, the step of fitting the first lateral offset N1 and the second lateral offset N2 according to the first distance information dy1, the second distance information dy2, the resolution calibration information, and the coordinate axis calibration information can comprise: fitting the first lateral offset N1 and the second lateral offset N2 according to the first distance information dy1, the second distance information dy2, the third distance information dy3, the resolution calibration information, and the coordinate axis calibration information.

[0090] In one example, the first distance information dy1, the second distance information dy2, the third distance information dy3, the entire resolution calibration information Size1, Size2, Size3, and the entire coordinate axis calibration information AxisX1, AxisY1, AxisX2, AxisY2, AxisX3, AxisY3 have the following relationship with the first lateral offset N1 and the second lateral offset N2:

[0091] In one example, according to the relationship of the above formula, the first lateral offset N1 and the second lateral offset N2 are fitted by the least square method, and in other embodiments, the first lateral offset N1 and the second lateral offset N2 can also be fitted by other alternative fitting algorithms.

[0092] According to the offset information calculation method of the embodiments of the present application, at each image acquisition position, part of the first wafer W1 edge image and part of the second wafer W2 edge image can be simultaneously captured by a single set of vision assembly 100, and the edge images of the first wafer W1 and the second wafer W2 are obtained by replacing the two sets of vision assemblies in the traditional wafer alignment device with a single set of vision assembly 100, thereby reducing the cost of the wafer alignment device and significantly improving the image acquisition efficiency. According to the offset information calculation method of the embodiments of the present application, the first to-be-processed image and at least one second to-be-processed image captured by the vision assembly are acquired; the first to-be-processed image is processed to obtain the first distance information and the angle offset, and the second to-be-processed image is processed to obtain the second distance information; the first distance information and the second distance information are fitted and calculated to obtain the first lateral offset and the second lateral offset of the second wafer relative to the first wafer, and the first lateral offset, the second lateral offset, and the angle offset are taken as the offset information. After obtaining the offset information, the second wafer W2 can be aligned with the first wafer W1 according to the offset information, and the operation of aligning the second wafer W2 with the first wafer W1 is realized.

[0093] According to the offset information calculation method, the first to-be-processed image and the at least one second to-be-processed image collected by the vision assembly between the relatively placed first wafer W1 and the second wafer W2 are obtained; the first to-be-processed image is processed to obtain first distance information and an angle offset; the second to-be-processed image is processed to obtain second distance information; the first distance information and the second distance information are fitted and calculated to obtain a first lateral offset and a second lateral offset of the second wafer relative to the first wafer, and the first lateral offset, the second lateral offset and the angle offset are taken as the offset information. After obtaining the offset information, the second wafer W2 and the first wafer W1 can be aligned according to the offset information, and the operation of aligning the second wafer W2 and the first wafer W1 is realized. The step of processing the first to-be-processed image includes: determining a first boundary line T1 in the first to-be-processed image, and identifying a first contour line Q1 and a second contour line Q2 in the first to-be-processed image, which are located on both sides of the first boundary line T1 and correspond to the edges of the first wafer W1 and the second wafer W2 respectively, based on a first tangent K1 at a symmetric point of a notch in the first contour line Q1 and a second tangent K2 at a symmetric point of a notch in a mirror line of the second contour line Q2, and using the tangents, two aspects of offset related information can be efficiently obtained, that is, the first distance information dy1 and the angle offset U are determined. The above processing of the first to-be-processed image improves the efficiency of obtaining the offset information, thereby facilitating the improvement of the efficiency of aligning the second wafer W2 and the first wafer W1.

[0094] The wafer alignment device provided in the embodiments of the present application includes a base, two bearing members respectively bearing upper and lower wafers, a vision assembly collecting an image containing part of the edge regions of the upper and lower wafers, a control unit calculating offset information between the upper and lower wafers based on to-be-processed images, and an adjusting assembly adjusting the positions of the wafers to align the upper and lower wafers.

[0095] Specifically, the vision assembly can be arranged on the base of the wafer alignment device in various ways.

[0096] In some embodiments, at least two vision assemblies are arranged at different collection positions of the wafer edge of the wafer alignment device. For example, two vision assemblies are mounted on the base and sequentially arranged at a first collection position and a second collection position. The two vision assemblies collect images of the upper and lower wafers at the first collection position and the second collection position, respectively, to obtain two to-be-processed images, for example, a first to-be-processed image and a second to-be-processed image. The line between the first collection position and the second collection position does not pass through the center of the wafer. For example, three vision assemblies are mounted on the base and sequentially arranged at a first collection position, a second collection position, and a third collection position. The vision assemblies at the first collection position, the second collection position, and the third collection position collect images of the upper and lower wafers to obtain three to-be-processed images, for example, a first to-be-processed image, a second to-be-processed image, and a third to-be-processed image. The line between any two of the first collection position, the second collection position, and the third collection position does not pass through the center of the wafer.

[0097] In some embodiments, a single vision assembly is arranged on the base of the wafer alignment device by a movable member. The movable member is used to drive the vision assembly to move along the wafer edge. In an example, the movable member is a sliding assembly. For example, the movable member can drive the vision assembly to move to a first collection position and a second collection position. The vision assembly collects images of the upper and lower wafers when it is stopped at the first collection position and the second collection position, respectively, to obtain two to-be-processed images. For example, the movable member can drive the vision assembly to move to a first collection position, a second collection position, and a third collection position. The vision assembly collects images of the upper and lower wafers when it is stopped at the first collection position, the second collection position, and the third collection position, respectively, to obtain three to-be-processed images.

[0098] Figure 18 、 Figure 19 、 Figure 20 is a perspective view, a front view, and a top view of an embodiment of the wafer alignment device according to the present application, Figure 21 is a schematic diagram of an electrical connection structure of an embodiment of the wafer alignment device according to the present application. The wafer alignment device includes a base 200, a first carrier 300, a second carrier 400, an adjusting assembly 500, at least two vision assemblies 100, and a control unit 600.

[0099] The vision assembly 100 is the vision assembly 100 of any of the preceding embodiments, or the vision assembly 100 in the offset information calculation method of any of the preceding embodiments. The control unit 600 obtains the offset information of the second wafer W2 relative to the first wafer W1 by the offset information calculation method of any of the preceding embodiments.

[0100] The first carrier 300 is installed on the base 200, and is used to carry the first wafer W1. The second carrier 400 is arranged along the longitudinal direction and spaced apart from the first carrier 300, and is used to carry the second wafer W2. The adjusting assembly 500 is installed on the base 200 and connected with the second carrier 400. The adjusting assembly 500 is used to drive the second carrier 400 to move relative to the first carrier 300.

[0101] Each visual assembly 100 comprises a camera 110, a light source 120, a semi-transparent beam splitter 130, and a beam splitter prism 140, which are arranged along a preset axis L1 in sequence. The light source 120 is located on one side of the preset axis L1, and the light emitting surface of the light source 120 faces the semi-transparent beam splitter 130. The light emitted by the light source 120 can be reflected by the semi-transparent beam splitter 130 and projected to the beam splitter prism 140. The beam splitter prism 140 can extend between the first wafer W1 and the second wafer W2 arranged oppositely. The beam splitter prism 140 comprises a first inclined surface 141 inclined toward the first wafer and a second inclined surface 142 inclined toward the second wafer, and the first inclined surface 141 and the second inclined surface 142 are symmetrically arranged. The camera 110 is used to acquire a to-be-processed image, which comprises an image of the first wafer and an image of the second wafer.

[0102] At least two visual assemblies 100 are distributed around the second carrier 400. In the state that the first carrier 300 carries the first wafer W1 and the second carrier 400 carries the second wafer W2, the beam splitter prism 140 of each visual assembly 100 is located along the transverse direction at the edge of the first wafer W1 and along the longitudinal direction between the first wafer W1 and the second wafer W2. Each visual assembly 100 is used to acquire a corresponding to-be-processed image. The to-be-processed image comprises an image of part of the edge of the first wafer W1 and an image of part of the edge of the second wafer W2.

[0103] The control unit 600 is in communication connection with the visual assembly 100 and the adjusting assembly 500. The control unit 600 obtains the offset information of the second wafer W2 relative to the first wafer W1 by using the offset information calculation method of any one of the foregoing embodiments. The control unit 600 is used to control the adjusting assembly 500 to drive the second carrier 400 to move, so that the second wafer W2 is aligned with the first wafer W1.

[0104] The control unit 600 can be a computer device such as a host computer or a special server, or an electronic device capable of executing a computer program.

[0105] The wafer alignment device according to the embodiment of the present application comprises a first bearing 300, a second bearing 400, an adjusting assembly 500, at least two visual assemblies 100 and a control unit 600. The first bearing 300 is used for bearing a first wafer W1, and the second bearing 400 is used for bearing a second wafer W2. Each visual assembly 100 comprises a camera 110, a light source 120, a semi-transparent beam splitter 130 and a beam splitter prism 140. The beam splitter prism 140 can extend to between the oppositely placed first wafer W1 and second wafer W2. The beam splitter prism 140 comprises a first inclined surface 141 inclined towards the first wafer W1 and a second inclined surface 142 inclined towards the second wafer W2. The first inclined surface 141 and the second inclined surface 142 are symmetrically arranged. The beam splitter prism 140 of each visual assembly 100 is located along a transverse direction at an edge of the first wafer W1 and along a longitudinal direction between the first wafer W1 and the second wafer W2. Each visual assembly 100 is used for acquiring a corresponding to-be-processed image. The camera 110 acquires the to-be-processed image via the beam splitter prism 140. The to-be-processed image comprises an image of part of the edge of the first wafer W1 and an image of part of the edge of the second wafer W2. In the embodiment of the present application, at each image acquisition position, part of the edge of the first wafer W1 and part of the edge of the second wafer W2 can be simultaneously acquired by a single set of visual assemblies 100. The single set of visual assemblies 100 is used for acquiring the edge images of the first wafer W1 and the second wafer W2, thereby reducing the cost of the wafer alignment device and significantly improving the image acquisition efficiency. The control unit 600 can acquire offset information of the second wafer W2 relative to the first wafer W1. The control unit 600 can control the adjusting assembly 500 to drive the second bearing 400 to move, so that the second wafer W2 is aligned with the first wafer W1, thereby realizing the operation of aligning the second wafer W2 with the first wafer W1.

[0106] For any two image acquisition positions of the visual assemblies 100, a line connecting the two image acquisition positions does not pass through the center of the first wafer W1. Figures 18 to 21 In one example, the number of visual assemblies 100 is three. Taking at least two visual assemblies 100 as an example, the at least two visual assemblies 100 comprise a first visual assembly 100a, a second visual assembly 100b and a third visual assembly 100c. The first visual assembly 100a, the second visual assembly 100b and the third visual assembly 100c are sequentially arranged at a first acquisition position, a second acquisition position and a third acquisition position. For any two acquisition positions of the first acquisition position, the second acquisition position and the third acquisition position, a line connecting the two acquisition positions does not pass through the center of the first wafer W1.

[0107] In an alternative example, the number of visual components 100 is two, and the two visual components 100 are arranged in sequence at the first collection position and the second collection position. The line connecting the first collection position and the second collection position does not pass through the center of the first wafer. The number of visual components 100 can also be, for example, four, five, or other numbers, and the line connecting the image collection positions of any two visual components 100 does not pass through the center of the first wafer W1.

[0108] In yet another alternative example, the number of visual components 100 is one, and the visual component 100 is arranged to move in rotation at the edge of the first wafer and sequentially collect images at different positions, such as the first collection position, the second collection position, and the third collection position, to obtain three images to be processed. Among the first collection position, the second collection position, and the third collection position, the line connecting any two collection positions does not pass through the center of the first wafer. Alternatively, the visual component 100 moves in rotation at the edge of the first wafer and sequentially collects images at the first collection position and the second collection position to obtain two images to be processed. The line connecting the first collection position and the second collection position does not pass through the center of the first wafer.

[0109] In some embodiments, the wafer alignment device further comprises a first support 700. The first support 700 connects the first carrier 300 with the base 200. The first carrier 300 is located on the side of the second carrier 400 away from the base 200. The number of first supports 700 can be one or more than two. In an example, the wafer alignment device comprises two first supports 700, and the two first supports 700 are symmetrically or uniformly distributed around the outer periphery of the first carrier 300.

[0110] In the above embodiments, the first support 700 connects the first carrier 300 with the base 200, which can ensure the positional stability of the first carrier 300 and enable the first carrier 300 to stably hang on the side of the second carrier 400 away from the base 200.

[0111] In some embodiments, the second carrier 400 can limit the second wafer W2 carried thereby, so that when the adjustment assembly 500 drives the movement of the second carrier 400, the second wafer W2 can move synchronously with the second carrier 400. For example, the second carrier 400 limits the second wafer W2 by a publicly known vacuum adsorption method, so that the second wafer W2 is adsorbed on the second carrier 400.

[0112] Figure 22is a perspective view of an adjustment assembly in an embodiment of a wafer alignment device according to the present application, in some embodiments, the adjustment assembly 500 comprises a first adjustment seat 510, a second adjustment seat 520, and a connecting plate 530. The first adjustment seat 510 is mounted to the base 200, the second adjustment seat 520 is mounted to the first adjustment seat 510, the connecting plate 530 is mounted to the second adjustment seat 520, and the second carrier 400 is mounted to the connecting plate 530.

[0113] The first adjustment seat 510 is configured to move the second adjustment seat 520 along one of the first lateral direction X and the second lateral direction Y. The second adjustment seat 520 is configured to move the connecting plate 530 along the other of the first lateral direction X and the second lateral direction Y. The connecting plate 530 is configured to rotate the second carrier 400. The first lateral direction X and the second lateral direction Y are orthogonal to each other. In this embodiment, the connecting plate 530 rotates the second carrier 400 about a rotation center line that is perpendicular to a plane on which the second carrier 400 is located, and the rotation center line is substantially located at the center of the second carrier 400.

[0114] The adjustment assembly 500 comprises the first adjustment seat 510, the second adjustment seat 520, and the connecting plate 530. The first adjustment seat 510 and the second adjustment seat 520 are configured to move the second carrier 400 together with the second wafer W2 along the first lateral direction X and the second lateral direction Y, so that the planar position of the second wafer W2 can be aligned with the planar position of the first wafer Wl. The connecting plate 530 is configured to rotate the second carrier 400 together with the second wafer W2, so that the second wafer W2 can be aligned with the first wafer Wl in the angular dimension.

[0115] The control unit 600 sends adjustment instructions to a controller (not shown in the figure) of the adjustment assembly 500 based on the offset information. The controller of the adjustment assembly 500 can move the first adjustment seat 510, the second adjustment seat 520, and / or the connecting plate 530 based on the adjustment instructions to adjust the pose of the second carrier 400 together with the second wafer W2. In other embodiments, the pose of the second carrier 400 together with the second wafer W2 can also be adjusted manually according to the offset information through adjustment knobs on the first adjustment seat 510, the second adjustment seat 520, and the connecting plate 530.

[0116] The edge of the first wafer Wl has a first notch, and the edge of the second wafer W2 has a second notch. In this embodiment, the plurality of vision assemblies 100 comprises a first vision assembly 100a, a second vision assembly 100b, and a third vision assembly 100c. The first vision assembly 100a is configured to acquire a to-be-processed image comprising an image of the first notch and an image of the second notch.

[0117] In some embodiments, the wafer alignment device further comprises a first mounting frame 810 and a second mounting frame 820, the first mounting frame 810 and the second mounting frame 820 are respectively arranged on opposite sides of the first carrier 300. The first vision assembly 100a is mounted on the base 200 through the first mounting frame 810. The second vision assembly 100b and the third vision assembly 100c are mounted on the base 200 through the second mounting frame 820, and the second vision assembly 100b and the third vision assembly 100c are symmetrically arranged on the second mounting frame 820.

[0118] In one example, the first mounting frame 810 and the second mounting frame 820 are respectively arranged on opposite sides of the first carrier 300 along the first transverse direction X, so that the first vision assembly 100a is located on one side of the first carrier 300 along the first transverse direction X, and the second vision assembly 100b and the third vision assembly 100c are located on the other side of the first carrier 300 along the first transverse direction X. The second vision assembly 100b and the third vision assembly 100c are arranged at intervals along the second transverse direction Y.

[0119] In the above embodiment, the plurality of vision assemblies 100 includes the first vision assembly 100a, the second vision assembly 100b, and the third vision assembly 100c, and the first vision assembly 100a, the second vision assembly 100b, and the third vision assembly 100c are respectively located at different positions of the first wafer W1 in the circumferential direction, so as to obtain the to-be-processed images at three positions in the circumferential direction. Among the to-be-processed images obtained by the first vision assembly 100a, the image of the first notch and the image of the second notch are included. By obtaining the to-be-processed images at three positions in the circumferential direction, the control unit 600 can process a plurality of to-be-processed images to obtain offset information, and then control the adjustment assembly 500 to drive the second carrier 400 to move according to the offset information, so as to align the second wafer W2 with the first wafer W1.

[0120] In some embodiments, the first mounting frame 810 is configured to translate the first vision assembly 100a, and the second mounting frame 820 is configured to translate the second vision assembly 100b and the third vision assembly 100c. For example, the wafer alignment device further comprises a first translation assembly (not shown) and a second translation assembly (not shown). The first translation assembly is in driving connection with the first mounting frame 810, and is configured to translate the first mounting frame 810 along with the first vision assembly 100a. The second translation assembly is in driving connection with the second mounting frame 820, and is configured to translate the second mounting frame 820 along with the second vision assembly 100b and the third vision assembly 100c. During the wafer alignment stage, the beam splitter 140 of the first vision assembly 100a, the second vision assembly 100b and the third vision assembly 100c extends between the first wafer W1 and the second wafer W2, and is located at the edge of the first wafer W1 and the second wafer W2. During other stages, such as the unloading stage, the beam splitter 140 of the first vision assembly 100a, the second vision assembly 100b and the third vision assembly 100c is withdrawn from between the first wafer W1 and the second wafer W2, i.e., the beam splitter 140 of the first vision assembly 100a, the second vision assembly 100b and the third vision assembly 100c is translated in a direction away from the first carrier 300.

[0121] In some embodiments, the wafer alignment device further comprises a tilt angle adjustment assembly (not shown) and a height adjustment assembly (not shown). The tilt angle adjustment assembly and the height adjustment assembly are in connection with the vision assembly 100. The tilt angle adjustment assembly is configured to adjust the tilt angle of the preset axis L1 of the vision assembly 100 relative to the first wafer W1 (or relative to the second wafer W2, or relative to the horizontal plane). The height adjustment assembly is configured to adjust the height position of the vision assembly 100 in the direction perpendicular to the first wafer W1. In one example, the first vision assembly 100a is mounted on the first mounting frame 810 through the tilt angle adjustment assembly and the height adjustment assembly. The second vision assembly 100b is mounted on the second mounting frame 820 through the tilt angle adjustment assembly and the height adjustment assembly. The third vision assembly 100c is mounted on the second mounting frame 820 through the tilt angle adjustment assembly and the height adjustment assembly. By providing the tilt angle adjustment assembly and the height adjustment assembly, the imaging light between the first inclined surface 141 of the beam splitter 140 and the first wafer W1 is perpendicular to the first wafer W1, and the imaging light between the second inclined surface 142 of the beam splitter 140 and the second wafer W2 is perpendicular to the second wafer W2, by adjusting the tilt angle and the height position of the vision assembly 100. In addition, the first wafer W1 and the second wafer W2 are both located on the image acquisition focal plane of the vision assembly 100, so as to obtain higher quality images to be processed.

[0122] In some embodiments, the step S140 of controlling the adjusting assembly 500 to drive the second carrier 400 to move so that the second wafer W2 is aligned with the first wafer W1 according to the offset information comprises the following steps: controlling the adjusting assembly 500 to drive the second carrier 400 to translate along the first lateral direction X by a first lateral offset N1; controlling the adjusting assembly 500 to drive the second carrier 400 to translate along a second lateral direction Y by a second lateral offset N2, the second lateral direction Y being orthogonal to the first lateral direction X; and controlling the adjusting assembly 500 to drive the second carrier 400 to rotate by an angular offset U.

[0123] In some embodiments, after the adjusting assembly 500 is controlled to drive the second carrier 400 to move according to the offset information, the corresponding plurality of to-be-processed images can be acquired again by the plurality of visual assemblies 100, and the offset information of the second wafer W2 relative to the first wafer W1 can be obtained again based on the plurality of to-be-processed images. If the offset information meets the accuracy requirement, it is determined that the second wafer W2 is aligned with the first wafer W1. If the offset information does not meet the accuracy requirement, the adjusting assembly 500 can be controlled again to drive the second carrier 400 to move based on the offset information until the offset information meets the accuracy requirement.

[0124] The embodiments of the present application also provide a wafer bonding system, which comprises the wafer alignment device of any one of the foregoing embodiments. The wafer bonding system aligns the second wafer W2 with the first wafer W1 by the wafer alignment device before bonding the second wafer W2 with the first wafer W1.

[0125] The wafer alignment device comprises a base 200, a first carrier 300, a second carrier 400, an adjusting assembly 500, at least two visual assemblies 100 of any one of the foregoing embodiments, and a control unit 600.

[0126] The first carrier 300 is installed on the base 200, and the first carrier 300 is used to carry the first wafer W1. The second carrier 400 is arranged along a longitudinal direction and spaced apart from the first carrier 300, and the second carrier 400 is used to carry the second wafer W2. The adjusting assembly 500 is installed on the base 200 and connected with the second carrier 400. The adjusting assembly 500 is used to drive the second carrier 400 to move relative to the first carrier 300.

[0127] Each vision assembly 100 comprises a camera 110, a light source 120, a semi-transparent beam splitter 130, and a beam splitter prism 140, the camera 110, the semi-transparent beam splitter 130, and the beam splitter prism 140 are arranged along a preset axis L1 in sequence. The light source 120 is located on one side of the preset axis L1, and an outgoing surface of the light source 120 faces the semi-transparent beam splitter 130, and outgoing light of the light source 120 can be reflected by the semi-transparent beam splitter 130 and projected to the beam splitter prism 140. The beam splitter prism 140 can extend between the oppositely arranged first wafer W1 and the second wafer W2, and the beam splitter prism 140 comprises a first inclined surface 141 inclined toward the first wafer and a second inclined surface 142 inclined toward the second wafer, and the first inclined surface 141 and the second inclined surface 142 are symmetrically arranged. The camera 110 is configured to acquire a to-be-processed image, and the to-be-processed image comprises an image of the first wafer and an image of the second wafer.

[0128] At least two vision assemblies 100 are distributed around the second carrier 400. In a state where the first carrier 300 carries the first wafer W1 and the second carrier 400 carries the second wafer W2, the beam splitter prism 140 of each vision assembly 100 is located laterally at an edge of the first wafer W1 and longitudinally between the first wafer W1 and the second wafer W2, and each vision assembly 100 is configured to acquire a corresponding to-be-processed image. The to-be-processed image comprises an image of part of the edge of the first wafer W1 and an image of part of the edge of the second wafer W2.

[0129] The control unit 600 is in communication connection with the vision assembly 100 and the adjustment assembly 500. The control unit 600 is configured to obtain offset information of the second wafer W2 relative to the first wafer W1 based on at least two to-be-processed images acquired by the plurality of vision assemblies 100, and the control unit 600 obtains the offset information of the second wafer W2 relative to the first wafer W1 by using any of the foregoing offset information calculation methods. The control unit 600 is configured to control the adjustment assembly 500 to drive the second carrier 400 to move according to the offset information, so that the second wafer W2 is aligned with the first wafer W1.

[0130] The wafer bonding system according to the embodiments of the present application comprises the wafer alignment device of any of the preceding embodiments, and the wafer bonding system aligns the second wafer W2 to the first wafer W1 by the wafer alignment device before bonding the second wafer W2 to the first wafer W1. The wafer alignment device comprises a first carrier 300 for carrying the first wafer W1, a second carrier 400 for carrying the second wafer W2, an adjusting assembly 500, at least two vision assemblies 100, and a control unit 600. Each vision assembly 100 comprises a camera 110, a light source 120, a semi-transparent beam splitter 130, and a beam splitter prism 140. The beam splitter prism 140 is capable of extending between the oppositely placed first wafer W1 and second wafer W2, and the beam splitter prism 140 comprises a first inclined surface 141 inclined towards the first wafer W1 and a second inclined surface 142 inclined towards the second wafer W2, and the first inclined surface 141 and the second inclined surface 142 are symmetrically arranged. The beam splitter prism 140 of each vision assembly 100 is located along a transverse direction at an edge of the first wafer W1 and along a longitudinal direction between the first wafer W1 and the second wafer W2, and each vision assembly 100 is used to acquire a corresponding to-be-processed image. The camera 110 acquires the to-be-processed image via the beam splitter prism 140, and the to-be-processed image comprises an image of part of the edge of the first wafer W1 and an image of part of the edge of the second wafer W2. In the embodiments of the present application, at each image acquisition position, part of the edge of the first wafer W1 and part of the edge of the second wafer W2 can be simultaneously acquired by a single set of vision assemblies 100, and the edge images of the first wafer W1 and the second wafer W2 are acquired by a single set of vision assemblies 100 instead of two sets of vision assemblies in a conventional wafer alignment device, so that the cost of the wafer alignment device is reduced and the image acquisition efficiency is significantly improved. The control unit 600 can acquire offset information of the second wafer W2 relative to the first wafer W1, and the control unit 600 can control the adjusting assembly 500 to drive the second carrier 400 to move according to the offset information, so that the second wafer W2 is aligned to the first wafer W1, thereby realizing the operation of aligning the second wafer W2 to the first wafer W1.

[0131] The embodiments of the present application further provide a control unit. Figure 23 FIG. 1 is a schematic diagram of a hardware structure of a control unit according to an embodiment of the present application. The control unit comprises a memory 610, a processor 620, and a computer program stored in the memory 610 and running on the processor 620, and the processor implements the offset information calculation method according to any of the preceding embodiments of the present application when executing the program. The memory 610 is electrically connected to the processor 620.

[0132] In particular, the processor 620 can include a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or can be configured to implement one or more integrated circuits that embody the embodiments of the present application.

[0133] The memory 610 can include mass storage for data or instructions. As an example and not by way of limitation, the memory 610 can include a hard disk drive (HDD), a floppy disk drive, flash memory, an optical disc (e.g., a compact disc (CD) or DVD), a tape drive, a USB drive, or a combination of two or more of these. The memory 610 can include removable or non-removable (or fixed) media, where appropriate. The memory 610 can be internal or external to the integrated gateway disaster recovery device, where appropriate. In particular embodiments, the memory 610 is non-volatile, solid-state memory. In particular embodiments, the memory 610 includes read-only memory (ROM). Where appropriate, this ROM can be mask-programmed ROM, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), electrically alterable ROM (EAROM), or flash memory or a combination of two or more of these. The memory 610 can be a single memory or divided into separate physical memory units.

[0134] In one example, the control device also includes a communications interface 630 and a bus 640. The processor 620, the memory 610, and the communications interface 630 are connected through the bus 640 and communicate with each other in the manner described supra.

[0135] The communications interface 630 is used mainly for implementing the communication between the modules, devices, units and / or apparatuses in the embodiments of the present application.

[0136] The bus 640 includes hardware, software, or both, that couples components of the online data traffic metering device to each other in a form that allows each of the components to communicate with one another. As an example and not by way of limitation, the bus can include an accelerated graphics port (AGP) or other graphics bus, an enhanced industry standard architecture (EISA) bus, a front-side bus (FSB), a HyperTransport (HT) interconnect, an industry standard architecture (ISA) bus, an infiniband (IB) interconnect, a low pin count (LPC) bus, a memory bus, a microchannel architecture (MCA) bus, a peripheral component interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a serial advanced technology attachment (SATA) bus, a video electronics standards board (VLB) bus, or another suitable bus or interconnect, or a combination of two or more of these. Where appropriate, the bus 640 can include one or more buses. Although the present application is described and shown with respect to particular buses, the present application contemplates any suitable bus or interconnect.

[0137] In addition, in combination with the offset information calculation method in the above-described embodiments, the embodiments of the present application can provide a computer readable storage medium for implementation. The computer readable storage medium has computer programs / instructions stored thereon, and the computer programs / instructions are executed by a processor to implement the offset information calculation method according to any of the preceding embodiments of the present application.

[0138] The embodiments of the present application also provide a computer program product, which includes computer programs / instructions, and the computer programs / instructions are executed by a processor to implement the steps of the offset information calculation method according to any of the preceding embodiments of the present application.

[0139] The present application is not limited to the specific configurations and processes described above and shown in the drawings. For the sake of brevity, detailed descriptions of well-known methods are omitted. In the above-described embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications, and additions, or change the order of the steps, after understanding the spirit of the present application.

[0140] The functional blocks shown in the structural block diagrams above can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a functional card, and the like. When implemented in software, the elements of the present application are program or code segments used to perform the required tasks. The program or code segments can be stored in a machine readable medium or transmitted through a data signal carried in a carrier wave over a transmission medium or communication link. The "machine readable medium" can include any medium capable of storing or transmitting information. Examples of the machine readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, and the like. The code segments can be downloaded via a computer network such as the Internet, an intranet, and the like.

[0141] It should be noted that the technical solutions or technical features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of the present application is not limited to the precise structures described in the above embodiments and shown in the drawings; any modifications, equivalent replacements, improvements, and the like made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for calculating offset information, characterized in that, include: The vision component acquires a first image to be processed and at least one second image to be processed between two relatively placed wafers. The first image to be processed includes an image of a first notch at the edge of the first wafer and an image of a second notch at the edge of the second wafer. The second image to be processed includes an image of a portion of the edge of the first wafer and an image of a portion of the edge of the second wafer. The first notch and the second notch are both symmetrical patterns. The first image to be processed is processed to obtain first distance information and angle offset, including: determining a first dividing line in the first image to be processed, and identifying a first contour line and a second contour line located on both sides of the first dividing line in the first image to be processed and corresponding to the edge of the first wafer and the edge of the second wafer, respectively; and determining the first distance information and angle offset based on the first tangent line at the symmetrical point of the notch in the first contour line and the second tangent line at the symmetrical point of the notch in the mirror line of the second contour line. The second image to be processed is processed to obtain second distance information. The first distance information and the second distance information respectively represent the offset pixel values ​​of the second wafer relative to the first wafer in the image to be processed. The first distance information and the second distance information are fitted and calculated to obtain the first lateral offset and the second lateral offset of the second wafer relative to the first wafer, and the first lateral offset, the second lateral offset, and the angular offset are used as the offset information.

2. The offset information calculation method according to claim 1, characterized in that, The line connecting any two acquisition locations of the images to be processed does not pass through the center of the first wafer.

3. The offset information calculation method according to claim 1, characterized in that, Determining the first boundary line in the first image to be processed includes: Obtain the boundary information of the visual component, wherein the boundary information is the position information of the boundary between two sub-images in the image to be processed, obtained by the visual component; Based on the boundary information of the visual components of the first image to be processed, a first boundary line is determined in the first image to be processed.

4. The offset information calculation method according to claim 1, characterized in that, Before determining the first distance information and angular offset based on the first tangent line at the symmetrical point of the notch in the first contour line and the second tangent line at the symmetrical point of the notch in the mirror image of the second contour line, the processing of the first image to be processed to obtain the first distance information and angular offset further includes: Construct a first mirror line, which is symmetrical to the second contour line about the first dividing line, and the first mirror line has a third notch that mirrors the second notch on the second contour line; Obtain the first tangent line in the first contour line at the symmetrical point of the first notch, and obtain the second tangent line in the first mirror line at the symmetrical point of the third notch.

5. The offset information calculation method according to claim 4, characterized in that, The determination of the first distance information and angular offset based on the first tangent line at the symmetrical point of the notch in the first contour line and the second tangent line at the symmetrical point of the notch in the mirror image line of the second contour line includes: Construct a first reference line, which is perpendicular to the first boundary line and bisects the first image to be processed. Obtain the first intersection point of the first tangent line and the first reference line, obtain the second intersection point of the second tangent line and the first reference line, and use the distance between the first intersection point and the second intersection point as the first distance information; The angular offset is obtained based on the angle between the first tangent and the second tangent.

6. The offset information calculation method according to claim 3, characterized in that, The process of processing the second image to obtain the second distance information includes: Based on the boundary information of the visual components of the second image to be processed, a second boundary line is determined in the second image to be processed; Feature recognition is performed in the second image to be processed to obtain a third contour line and a fourth contour line located on both sides of the second boundary line. The third contour line corresponds to a portion of the edge of the first wafer, and the fourth contour line corresponds to a portion of the edge of the second wafer. Construct a second mirror line and a second reference line, wherein the second mirror line is symmetrical to the fourth contour line about the second boundary line, and the second reference line is parallel to the second boundary line and intersects the third contour line and the second mirror line; Obtain the third intersection point of the third contour line and the second reference line, obtain the fourth intersection point of the second mirror line and the second reference line, and use the distance between the third intersection point and the fourth intersection point as the second distance information.

7. The offset information calculation method according to claim 1, characterized in that, The step of fitting and calculating the first distance information and the second distance information to obtain the first lateral offset and the second lateral offset of the second wafer relative to the first wafer includes: Obtain resolution calibration information and coordinate axis calibration information corresponding to the vision component. The resolution calibration information is the mapping relationship between the size of a single pixel in the image to be processed obtained by the vision component and the actual physical size. The coordinate axis calibration information is the mapping relationship between the rectangular coordinate axis in the image to be processed obtained by the vision component and the first horizontal axis and the second horizontal axis. The first horizontal axis and the second horizontal axis are orthogonal on a plane parallel to the first wafer. Based on the first distance information, the second distance information, the resolution calibration information, and the coordinate axis calibration information, the first lateral offset and the second lateral offset are fitted to obtain the first lateral offset and the second lateral offset.

8. The offset information calculation method according to claim 7, characterized in that, The method further includes: The third image to be processed is acquired by the vision component, and the third image to be processed is processed to obtain the third distance information. The third image to be processed includes images of a portion of the first wafer edge and images of a portion of the second wafer edge. The step of fitting the first lateral offset and the second lateral offset based on the first distance information, the second distance information, the resolution calibration information, and the coordinate axis calibration information includes: Based on the first distance information, the second distance information, the third distance information, the resolution calibration information, and the coordinate axis calibration information, the first lateral offset and the second lateral offset are fitted.

9. The offset information calculation method according to claim 3, characterized in that, The vision component includes a camera, a light source, a semi-transparent beam splitter, and a beam splitter prism, wherein the camera, the semi-transparent beam splitter, and the beam splitter prism are arranged sequentially along a preset axis. The light source is located on one side of the preset axis, and the light-emitting surface of the light source faces the semi-transparent beam splitter. The light emitted from the light source can be reflected by the semi-transparent beam splitter and projected onto the beam splitter prism. The beam splitter can extend between the first wafer and the second wafer, which are placed opposite each other. The beam splitter includes a first inclined surface inclined towards the first wafer and a second inclined surface inclined towards the second wafer, and the first inclined surface and the second inclined surface are symmetrically arranged. The camera is used to acquire an image to be processed, which includes an image of the first wafer and an image of the second wafer.

10. The offset information calculation method according to claim 9, characterized in that, The acquisition of the boundary information of the visual components includes: The calibration image of the calibration block installed at the beam splitter is acquired by the vision component. The calibration block includes a first calibration part and a second calibration part arranged symmetrically. The first calibration part and the second calibration part are both located on the image acquisition focal plane of the corresponding vision component. The boundary information corresponding to the visual component is obtained based on the calibration image.

Citation Information

Patent Citations

  • Wafer position correction method and device and storage medium

    CN114256118A

  • Wafer pre-alignment device and wafer pre-alignment method

    CN114695225A

  • Wafer gap detection method and wafer gap detection equipment

    CN116091417A

  • Wafer edge alignment method and system

    CN116759358A

  • Position offset detection method and system based on semiconductor wafer transmission

    CN118431121A

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