Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises an array substrate, an opposite substrate and a liquid crystal layer, wherein the array substrate and the opposite substrate are arranged in a box-to-box mode, and the liquid crystal layer is located between the array substrate and the opposite substrate. The array substrate comprises a first substrate, grid lines, data lines and a plurality of first auxiliary spacers, wherein the grid lines and the data lines are arranged on the side, close to a liquid crystal layer, of the first substrate and are arranged in an insulated and crossed mode, and the first auxiliary spacers are arranged on the sides, close to the liquid crystal layer, of the grid lines and the data lines. The extension directions of the first auxiliary spacers and the data lines are the same, and the orthographic projection of the first auxiliary spacers on the first substrate and the orthographic projection of the intersection area of the grid lines and the data lines on the first substrate are mutually overlapped; the opposite substrate comprises a second substrate and a plurality of second auxiliary spacers arranged on the side, close to the liquid crystal layer, of the second substrate; the extension directions of the second auxiliary spacers and the data lines are the same, the second auxiliary spacers and the first auxiliary spacers are in one-to-one correspondence, and the orthographic projections of the second auxiliary spacers on the first substrate and the orthographic projections of the first auxiliary spacers on the first substrate are at least partially overlapped.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) features small size, low power consumption, high image quality, no radiation, and portability. It has developed rapidly in recent years and has gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market.

[0003] A liquid crystal display (LCD) panel includes an array substrate and a color filter substrate disposed opposite each other, and a liquid crystal layer located between the array substrate and the color filter substrate. To support the array substrate and the color filter substrate during LCD panel assembly and ensure the required cell thickness, spacers (PS) are typically provided between the color filter substrate and the array substrate. These spacers usually include a main PS and a sub PS. The main PS is generally taller than the sub PS, and the area densities of the main and sub PS are maintained in a certain ratio. Summary of the Invention

[0004] This disclosure provides a display panel and a display device to improve the aperture ratio of the display panel.

[0005] This disclosure provides a display panel comprising an array substrate and a counter substrate disposed opposite each other, and a liquid crystal layer located between the array substrate and the counter substrate;

[0006] The array substrate includes: a first substrate, a plurality of gate lines and a plurality of data lines disposed on the side of the first substrate near the liquid crystal layer and arranged in an insulated manner, and a plurality of first auxiliary spacers disposed on the side of the gate lines and the data lines near the liquid crystal layer; wherein, the first auxiliary spacers extend in the same direction as the data lines, and the orthographic projection of the first auxiliary spacers on the first substrate overlaps with the orthographic projection of the intersection area of ​​the gate lines and the data lines on the first substrate.

[0007] The opposing substrate includes: a second substrate, and a plurality of second auxiliary spacers disposed on the side of the second substrate near the liquid crystal layer; wherein the second auxiliary spacers extend in the same direction as the data lines, each second auxiliary spacer corresponds to each first auxiliary spacer, and the orthographic projection of the second auxiliary spacer on the first substrate at least partially overlaps with the orthographic projection of the first auxiliary spacer on the first substrate.

[0008] In some embodiments, in the display panel provided in the present disclosure, the gate lines and the data lines intersect to define multiple rows and columns of pixel units. Each pixel unit includes multiple sub-pixels with different color resist colors. Sub-pixels in the same row have the same color resist color, while sub-pixels in the same column have different color resist colors. Sub-pixels in the same column are electrically connected to the same data line, and sub-pixels in different columns are electrically connected to different data lines. Each row of pixel units arranged along the pixel row direction is electrically connected to three rows of gate lines.

[0009] In some embodiments, in the display panel provided in the present disclosure, the orthographic projections of the first auxiliary spacer and the second auxiliary spacer on the first substrate are both strip-shaped, and the length of the first auxiliary spacer along the data line extension direction is greater than the length of the second auxiliary spacer along the data line extension direction.

[0010] In some embodiments, in the display panel provided in the present disclosure, the length of the first auxiliary spacer along the extension direction of the grid line is less than the length of the second auxiliary spacer along the extension direction of the grid line.

[0011] In some embodiments, in the display panel provided in the present disclosure, the length of the first auxiliary spacer along the extension direction of the grid line is greater than the length of the second auxiliary spacer along the extension direction of the grid line.

[0012] In some embodiments, in the display panel provided in the present disclosure, the orthographic projections of the first auxiliary spacer and the second auxiliary spacer on the first substrate are both strip-shaped, and the length of the first auxiliary spacer along the data line extension direction is less than the length of the second auxiliary spacer along the data line extension direction.

[0013] In some embodiments, in the display panel provided in the present disclosure, the length of the first auxiliary spacer along the extension direction of the grid line is greater than the length of the second auxiliary spacer along the extension direction of the grid line.

[0014] In some embodiments, in the display panel provided in the present disclosure, the length of the first auxiliary spacer along the extension direction of the grid line is less than the length of the second auxiliary spacer along the extension direction of the grid line.

[0015] In some embodiments, in the display panel provided in the present disclosure, the center line of the first auxiliary spacer along the data line extension direction coincides with the center line of the second auxiliary spacer along the data line extension direction.

[0016] In some embodiments, in the display panel provided in the present disclosure, the opposing substrate further includes: a black matrix and a filter layer located between the second substrate and the second auxiliary spacer, a first planarization layer located between the black matrix and the filter layer and the second auxiliary spacer, and a first alignment layer located on the side of the second spacer near the liquid crystal layer; the black matrix includes a plurality of openings, the filter layer includes a plurality of filters, and the orthographic projection of each filter on the second substrate covers the orthographic projection of the corresponding opening on the second substrate.

[0017] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes: a second planarization layer located between the gate line and the data line and the first spacer; a first transparent electrode layer located between the second planarization layer and the first spacer; a passivation layer located between the first transparent electrode layer and the first spacer; a second transparent electrode layer located between the passivation layer and the first spacer; and a second alignment layer located on the side of the first spacer near the liquid crystal layer.

[0018] In some embodiments, in the display panel provided in this disclosure, the array substrate further includes: a second planarization layer located between the gate lines and the data lines and the first spacer; a first transparent electrode layer located on the side of the second planarization layer near the liquid crystal layer; a passivation layer located on the side of the first transparent electrode layer near the liquid crystal layer; a second transparent electrode layer located on the side of the passivation layer near the liquid crystal layer; and a second alignment layer located on the side of the second transparent electrode layer near the liquid crystal layer; wherein...

[0019] The first spacer and the second planarization layer are an integral structure.

[0020] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes a plurality of first main spacers disposed in the same layer as the first auxiliary spacer, and the opposing substrate further includes a plurality of second main spacers disposed in the same layer as the second auxiliary spacer, wherein the sum of the thicknesses of the first main spacers and the second main spacers is greater than the sum of the thicknesses of the first auxiliary spacer and the second auxiliary spacer.

[0021] Each of the second main spacers corresponds one-to-one with each of the first main spacers. The orthographic projection of the second main spacer on the first substrate intersects with the orthographic projection of the first main spacer on the first substrate. Furthermore, the orthographic projections of the first main spacer and the second main spacer on the first substrate overlap with the orthographic projections of the intersection area of ​​the gate line and the data line on the first substrate.

[0022] In some embodiments, in the display panel provided in the present disclosure, neither the first auxiliary spacer nor the second auxiliary spacer is provided in the intersection area on both sides adjacent to the first main spacer and the second main spacer arranged in pairs along the extension direction of the grid line, and neither the first main spacer nor the second main spacer is provided.

[0023] In some embodiments, in the display panel provided in the present disclosure, the orthogonal projection of the black matrix on the first substrate covers the orthogonal projections of the gate line, the data line, the first auxiliary spacer, the second auxiliary spacer, the first main spacer, and the second main spacer on the first substrate.

[0024] In some embodiments, in the display panel provided in the present disclosure, the width of the black matrix corresponding to the areas where the paired first main spacers and the second main spacers are located along the extension direction of the grid line is greater than the width of the black matrix corresponding to the areas where the paired first auxiliary spacers and the second auxiliary spacers are located along the extension direction of the grid line, and the width of the black matrix corresponding to the areas where the paired first auxiliary spacers and the second auxiliary spacers are located along the extension direction of the grid line is greater than the width of the black matrix corresponding to the areas where no spacers are located along the extension direction of the grid line.

[0025] In some embodiments, in the display panel provided in the present disclosure, one of the first transparent electrode layer and the second transparent electrode layer is a planar electrode, and the other includes a plurality of slit electrodes.

[0026] Accordingly, this disclosure also provides a display device, including the display panel provided in the embodiments of this disclosure. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the pixel architecture of a display panel provided in an embodiment of the present disclosure;

[0029] Figure 2 A cross-sectional schematic diagram of a display panel provided in an embodiment of this disclosure;

[0030] Figure 3 for Figure 2 Top view schematic diagram of some film layers of the middle array substrate and the opposing substrate;

[0031] Figure 4 for Figure 2 Actual layout of the central array substrate under a microscope;

[0032] Figure 5 for Figure 2 Actual layout of the opposing substrate under a microscope;

[0033] Figure 6 For illustration only Figure 2 Top view of the first and second auxiliary septa;

[0034] Figure 7 For illustration only Figure 2 A top view showing that the first and second auxiliary spacers can be replaced;

[0035] Figure 8 For illustration only Figure 2 Another top view diagram showing that the first and second auxiliary septa can be replaced;

[0036] Figure 9 For illustration only Figure 2 Another top view diagram showing that the first and second auxiliary septa can be replaced;

[0037] Figure 10 A cross-sectional schematic diagram of another display panel provided in an embodiment of this disclosure;

[0038] Figure 11 For illustration only Figure 10 Top view of the first and second auxiliary septa;

[0039] Figure 12 For illustration only Figure 10 A top view showing that the first and second auxiliary spacers can be replaced;

[0040] Figure 13 For illustration only Figure 10 Another top view diagram showing that the first and second auxiliary septa can be replaced;

[0041] Figure 14 For illustration only Figure 10 Another top view diagram showing that the first and second auxiliary septa can be replaced;

[0042] Figure 15 For illustration only Figures 2-5 and Figure 10 Top view of the first and second main septa;

[0043] Figure 16This is a schematic diagram of the orthographic projection of the black matrix, the main spacer, and the auxiliary spacer on the second substrate.

[0044] Figure 17 This is a cross-sectional schematic diagram of a display device provided in an embodiment of the present disclosure;

[0045] Figure 18 A cross-sectional schematic diagram of another display device provided in an embodiment of this disclosure;

[0046] Figure 19 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0049] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0050] With the continuous maturation of liquid crystal display technology, LCD driving backplanes have gradually developed towards lower cost and lower power consumption. Currently, the driving backplane reduces the number of data signal channels by adding gate drive circuits (GOA) and gate lines for time-division driving, thereby reducing the number of driver chips (ICs) used. This is a key research focus in achieving low-cost, low-power multiple gate technology.

[0051] The most commonly used multi-gate pixel architecture is the Triple Gate (three gates, where each row of pixel units is driven by three rows of gate lines), such as... Figure 1 As shown, G1, G2... are gate lines, and D1, D2... are data lines. Each pixel unit includes multiple sub-pixels with different color resist colors (e.g., R, G, B). Multi-gate driving can reduce power consumption and cost, but it inevitably leads to a decrease in pixel aperture ratio, resulting in a decline in display quality.

[0052] In related technologies, the most commonly used spacer is a columnar spacer that abuts against the array substrate and the color filter substrate. The columnar spacer may slide due to external force and scratch the liquid crystal alignment layer (PI alignment layer), which will further cause poor liquid crystal alignment in the scratched area and the accompanying light leakage problem. In order to solve the problem of light leakage in the sub-pixel area caused by the columnar spacer scratching the liquid crystal alignment layer when the array substrate and the color filter substrate slides between the liquid crystal display panel, it is often necessary to increase the width of the black matrix pattern in the color filter substrate to improve the blocking effect, but this reduces the aperture ratio of the liquid crystal display panel. With the increasing demand for high-resolution and high-transmittance displays, related technologies have proposed a design using cross-strip spacers (XPS) on both sides of the display panel. This involves spacers on both the array substrate and the color filter substrate sides, with the spacers on the array substrate side and the color filter substrate side having an intersecting design. The spacers on each side are far from the opposite substrate, and each side's spacer is relatively short, making it difficult for the top of the spacer to contact the alignment layer and reducing the risk of scratching the substrate. This eliminates the need to increase the pattern width of the black matrix to improve the aperture ratio. However, because the spacers on the array substrate and color filter substrate sides are intersected, one side's spacers require an additional black matrix for shading on top of the original black matrix design, resulting in a loss of aperture ratio.

[0053] Therefore, while using Triple Gate to reduce power consumption and cost, how to maximize the aperture ratio has become a direction that needs to be studied and solved in this field.

[0054] This disclosure provides a display panel, such as... Figure 2 As shown, Figure 2 This is a cross-sectional view of a display panel, including an array substrate 1 and a counter substrate 2 disposed opposite each other, and a liquid crystal layer 3 located between the array substrate 1 and the counter substrate 2.

[0055] Specifically, such as Figures 2-4 As shown, Figure 3 for Figure 2 A top view of part of the film layers of the array substrate 1 and the opposing substrate 2. Figure 4 for Figure 2The actual layout of the array substrate under a microscope. The array substrate 1 includes: a first substrate 11, a plurality of gate lines (G1, G2...) and a plurality of data lines (D1, D2...) disposed on the side of the first substrate 11 near the liquid crystal layer 3 and disposed in an insulated manner, and a plurality of first auxiliary spacers 12 disposed on the side of the gate lines (G1, G2...) and data lines (D1, D2...) near the liquid crystal layer; wherein, the first auxiliary spacers 12 extend in the same direction as the data lines (D1, D2...), and the orthographic projection of the first auxiliary spacers 12 on the first substrate 11 overlaps with the orthographic projection of the intersection area of ​​the gate lines (G1, G2...) and data lines (D1, D2...) on the first substrate 11.

[0056] Specifically, such as Figure 2 , Figure 3 and Figure 5 As shown, Figure 5 for Figure 2 The actual layout of the opposing substrate under a microscope includes: a second substrate 21, and a plurality of second auxiliary spacers 22 disposed on the side of the second substrate 21 near the liquid crystal layer 3; wherein the second auxiliary spacers 22 extend in the same direction as the data lines (D1, D2...), each second auxiliary spacer 22 corresponds to each first auxiliary spacer 12, and the orthographic projection of the second auxiliary spacer 22 on the first substrate 11 at least partially overlaps with the orthographic projection of the first auxiliary spacer 12 on the first substrate 11.

[0057] It should be noted that, Figure 4 and Figure 5 After matching the boxes, Figure 4 The first auxiliary septum 12 and Figure 5 The second auxiliary spacer 22 in the middle corresponds one-to-one, forming Figure 3 The first auxiliary spacer 12 and the second auxiliary spacer 22 shown extend along the data line extension direction and overlap in orthographic projection.

[0058] The display panel provided in this embodiment of the present disclosure features an auxiliary spacer designed as a dual-sided structure of an array substrate and a counter substrate, with both auxiliary spacers extending along the data line extension direction. Specifically, the first and second auxiliary spacers overlap in a straight line along the data line extension direction after the enclosure is assembled. Because the critical dimension (CD) of the black matrix along the data line extension direction is wider, PS Mura can be prevented. Therefore, this disclosure does not require much additional black matrix to shield the auxiliary spacers, reducing the area of ​​the black matrix around the auxiliary spacers. This increases the effective display area, improves product transmittance, and enhances product competitiveness while preventing PS Mura. Furthermore, the increased contact area between the auxiliary spacers enhances friction, making them less prone to slippage and further preventing PS Mura. Compared to the XPS design in related technologies, the auxiliary spacers of this disclosure are smaller for the same contact area. Therefore, this disclosure can achieve the desired support effect, increase pixel aperture ratio, and achieve high transmittance specifications by using fewer auxiliary spacers and a narrower black matrix shielding distance.

[0059] In some embodiments, in the display panel provided in the present disclosure, such as Figure 1 , Figures 3-5 As shown, the gate lines (G1, G2...) and data lines (D1, D2...) intersect to define multiple rows and columns of pixel units P. Each pixel unit P includes multiple sub-pixels with different color resist colors (e.g., R, G, B). Sub-pixels in the same row have the same color resist color, while sub-pixels in the same column do not have completely identical color resist colors (e.g., arranged in RGBRGBRGB... pattern in the same column). Sub-pixels in the same column are electrically connected to the same data line, while sub-pixels in different columns are electrically connected to different data lines. Each row of pixel units P arranged along the pixel row direction is electrically connected to three rows of gate lines. That is, the pixel architecture of this embodiment is a Triple Gate, and multi-gate driving can reduce power consumption and cost. For example, the first row of pixel units P corresponds to the electrically connected gate lines (G1, G2, G3). The first row of sub-pixels R in the first row of pixel units P is electrically connected to G1. The second row of sub-pixels G in the first row of pixel units P is electrically connected to G2. The third row of sub-pixels B in the first row of pixel units P is electrically connected to G3. The second row of pixel units P corresponds to the electrically connected gate lines (G4, G5, G6). The first row of sub-pixels R in the second row of pixel units P is electrically connected to G4. The second row of sub-pixels G in the second row of pixel units P is electrically connected to G5. The third row of sub-pixels B in the second row of pixel units P is electrically connected to G6, and so on.

[0060] It should be noted that this disclosure uses a triple gate pixel architecture as an example, that is, each row of pixel units is driven by three rows of gate lines, but it is not limited to this; for example, the pixel architecture of this disclosure can also be driven by a single gate, a dual gate, or even more rows of gate lines.

[0061] In some embodiments, in the display panel provided in the present disclosure, such as Figures 3-6 As shown, Figure 6 For illustration only Figure 2 The diagram shows a top view of the first auxiliary spacer 12 and the second auxiliary spacer 22. The orthographic projections of both the first auxiliary spacer 12 and the second auxiliary spacer 22 onto the first substrate 11 are strip-shaped. The length a1 of the first auxiliary spacer 12 along the data lines (D1, D2…) can be greater than the length a2 of the second auxiliary spacer 22 along the data lines (D1, D2…). The length b1 of the first auxiliary spacer 12 along the gate lines (G1, G2…) can be less than the length b2 of the second auxiliary spacer 22 along the gate lines (G1, G2…). Specifically, this embodiment uses a relatively long and thin first auxiliary spacer 12 and a relatively short and thick second auxiliary spacer 22 as an example.

[0062] In some embodiments, in the display panel provided in the present disclosure, such as Figure 7 As shown, Figure 7 For illustration only Figure 2 The diagram shows a top view of an alternative first auxiliary spacer 12 and second auxiliary spacer 22. The orthographic projections of both the first auxiliary spacer 12 and the second auxiliary spacer 22 on the first substrate 11 are strip-shaped. The length a1 of the first auxiliary spacer 12 along the data lines (D1, D2…) can be greater than the length a2 of the second auxiliary spacer 22 along the data lines (D1, D2…). The length b1 of the first auxiliary spacer 12 along the gate lines (G1, G2…) can be greater than the length b2 of the second auxiliary spacer 22 along the gate lines (G1, G2…). Specifically, this embodiment uses a relatively long and thin first auxiliary spacer 12 and second auxiliary spacer 22 as an example.

[0063] In some embodiments, in the display panel provided in the present disclosure, such as Figure 8 As shown, Figure 8 For illustration only Figure 2 This is another top view showing that the first and second auxiliary spacers are interchangeable. The first auxiliary spacer 12 and the second auxiliary spacer 22 are both strip-shaped when projected onto the first substrate 11. The length a1 of the first auxiliary spacer 12 along the data lines (D1, D2…) can be less than the length a2 of the second auxiliary spacer 22 along the data lines (D1, D2…). The length b1 of the first auxiliary spacer 12 along the gate lines (G1, G2…) can be greater than the length b2 of the second auxiliary spacer 22 along the gate lines (G1, G2…). Specifically, this embodiment uses a relatively short and thick first auxiliary spacer 12 and a relatively long and thin second auxiliary spacer 22 as an example.

[0064] In some embodiments, in the display panel provided in the present disclosure, such as Figure 9 As shown, Figure 9 For illustration only Figure 2 This is another top view showing that the first and second auxiliary spacers are interchangeable. The orthographic projections of both the first auxiliary spacer 12 and the second auxiliary spacer 22 on the first substrate 11 are stripes. The length a1 of the first auxiliary spacer 12 along the data lines (D1, D2…) can be less than the length a2 of the second auxiliary spacer 22 along the data lines (D1, D2…). Similarly, the length b1 of the first auxiliary spacer 12 along the gate lines (G1, G2…) can be less than the length b2 of the second auxiliary spacer 22 along the gate lines (G1, G2…). Specifically, this embodiment uses a relatively long and thin first auxiliary spacer 12 and second auxiliary spacer 22 as an example.

[0065] It should be noted that, Figures 3-5 The shapes of the first auxiliary spacer 12 and the second auxiliary spacer 22 can be replaced with Figures 7-9 Any one of them.

[0066] It should be noted that, Figures 6-9 The examples all use the case that a1 is not equal to a2 and b1 is not equal to b2. Of course, it is also possible that a1 is equal to a2 and b1 is equal to b2.

[0067] In some embodiments, in the display panel provided in the present disclosure, such as Figures 6-9 As shown, the center line of the first auxiliary spacer 12 extending along the data lines (D1, D2...) coincides with the center line of the second auxiliary spacer 22 extending along the data lines (D1, D2...). This can further reduce the width of the black matrix extending along the gate lines (G1, G2...) and further improve the aperture ratio.

[0068] It should be noted that the above-mentioned centerline coincidence means that the centerlines roughly coincide. Due to the influence of the manufacturing process, the centerline of the first auxiliary spacer 12 extending along the data lines (D1, D2...) and the centerline of the second auxiliary spacer 22 extending along the data lines (D1, D2...) may have a certain deviation.

[0069] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2 , Figure 3 and Figure 5As shown, the opposing substrate 2 further includes: a black matrix 4 and a filter layer 5 located between the second substrate 21 and the second auxiliary spacer 22; a first planarization layer 6 located between the black matrix 4, the filter layer 5, and the second auxiliary spacer 22; and a first alignment layer 7 located on the side of the second spacer 22 near the liquid crystal layer 3. The black matrix 4 includes multiple openings, and the filter layer 5 includes multiple filters 51. The orthographic projection of each filter 51 on the second substrate 21 covers the orthographic projection of the corresponding opening on the second substrate 21. Specifically, the filters 51 may include a red filter (R), a green filter (G), and a blue filter (B).

[0070] In some embodiments, in the display panel provided in the present disclosure, such as Figures 2-4 As shown, the array substrate 1 further includes: a second planarization layer 8 located between the gate lines (G1, G2...) and data lines (D1, D2...) and the first spacer 12; a first transparent electrode layer 9 located between the second planarization layer 8 and the first spacer 12; a passivation layer 10 located between the first transparent electrode layer 9 and the first spacer 12; a second transparent electrode layer 20 located between the passivation layer 10 and the first spacer 12; and a second alignment layer 21 located on the side of the first spacer 12 near the liquid crystal layer 3.

[0071] In some embodiments, in the display panel provided in the present disclosure, such as Figure 3 , Figure 4 and Figure 10 As shown, the array substrate 1 further includes: a second planarization layer 8 located between the gate lines (G1, G2...) and data lines (D1, D2...) and the first spacer 12; a first transparent electrode layer 9 located on the side of the second planarization layer 8 near the liquid crystal layer 3; a passivation layer 10 located on the side of the first transparent electrode layer 9 near the liquid crystal layer 3; a second transparent electrode layer 20 located on the side of the passivation layer 10 near the liquid crystal layer 3; and a second alignment layer 21 located on the side of the second transparent electrode layer 20 near the liquid crystal layer 3; wherein,

[0072] The first spacer 12 and the second flat layer 8 are an integral structure.

[0073] In this way, the original pattern can be changed only when the second planarization layer 8 is formed, and the patterns of the first spacer 12 and the second planarization layer 8 can be formed in one patterning process. There is no need to add a separate process for preparing the first spacer 12, which can simplify the preparation process, save production costs, and improve production efficiency.

[0074] Specifically, the material of the second planarization layer 8 is an organic material, and the first spacer 12 and the second planarization layer 8 can be made using the half-tone mask (HTM) process.

[0075] In some embodiments, in the display panel provided in the present disclosure, such as Figure 10 and Figure 11 As shown, Figure 11 For illustration only Figure 10 A top view of the first auxiliary spacer 12 and the second auxiliary spacer 22, wherein the length a1 of the first auxiliary spacer 12 along the data lines (D1, D2...) can be greater than the length a2 of the second auxiliary spacer 22 along the data lines (D1, D2...), and the length b1 of the first auxiliary spacer 12 along the grid lines (G1, G2...) can be less than the length b2 of the second auxiliary spacer 22 along the grid lines (G1, G2...).

[0076] In some embodiments, in the display panel provided in the present disclosure, such as Figure 10 and Figure 12 As shown, Figure 12 For illustration only Figure 10 Another top view schematic diagram in which the first auxiliary spacer 12 and the second auxiliary spacer 22 can be replaced, wherein the length a1 of the first auxiliary spacer 12 along the data line (D1, D2...) can be greater than the length a2 of the second auxiliary spacer 22 along the data line (D1, D2...) and the length b1 of the first auxiliary spacer 12 along the grid line (G1, G2...) can be greater than the length b2 of the second auxiliary spacer 22 along the grid line (G1, G2...)

[0077] In some embodiments, in the display panel provided in the present disclosure, such as Figure 10 and Figure 13 As shown, Figure 13 For illustration only Figure 10 Another top view diagram in which the first auxiliary spacer 12 and the second auxiliary spacer 22 can be replaced, wherein the length a1 of the first auxiliary spacer 12 along the data line (D1, D2...) extension direction can be less than the length a2 of the second auxiliary spacer 22 along the data line (D1, D2...) extension direction, and the length b1 of the first auxiliary spacer 12 along the grid line (G1, G2...) extension direction can be greater than the length b2 of the second auxiliary spacer 22 along the grid line (G1, G2...) extension direction.

[0078] In some embodiments, in the display panel provided in the present disclosure, such as Figure 10 and Figure 14 As shown, Figure 14 For illustration only Figure 10Another top view diagram in which the first auxiliary spacer 12 and the second auxiliary spacer 22 can be replaced, wherein the length a1 of the first auxiliary spacer 12 along the data line (D1, D2...) extension direction can be less than the length a2 of the second auxiliary spacer 22 along the data line (D1, D2...) extension direction, and the length b1 of the first auxiliary spacer 12 along the grid line (G1, G2...) extension direction can be less than the length b2 of the second auxiliary spacer 22 along the grid line (G1, G2...) extension direction.

[0079] It should be noted that, Figures 11-14 The examples all use the case that a1 is not equal to a2 and b1 is not equal to b2. Of course, it is also possible that a1 is equal to a2 and b1 is equal to b2.

[0080] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2 and Figure 10 As shown, one of the first transparent electrode layer 9 and the second transparent electrode layer 20 is a planar electrode, and the other includes multiple slit electrodes. For example, the second transparent electrode layer 20 is a planar electrode, and the first transparent electrode layer 9 includes multiple slit electrodes. Exemplarily, one of the first transparent electrode layer 9 and the second transparent electrode layer 20 is a pixel electrode, and the other is a common electrode.

[0081] Specifically, such as Figures 2-4 and Figure 10 As shown, the array substrate 1 further includes: a light-shielding layer 22 located between the first substrate 11 and the second planarization layer 8; a buffer layer 23 located between the light-shielding layer 22 and the second planarization layer 8; an active layer 24 located between the buffer layer 23 and the second planarization layer 8; an interlayer gate insulating layer 25 located between the active layer 24 and the second planarization layer 8; a gate metal layer 26 located between the gate insulating layer 25 and the second planarization layer 8; an interlayer insulating layer 27 located between the gate metal layer 26 and the second planarization layer 8; and a source / drain metal layer 28 located between the interlayer insulating layer 27 and the second planarization layer 8. The gate metal layer 26 may include a gate electrode G, a gate line, etc., and the source / drain metal layer 28 may include a source electrode S, a drain electrode D, a data line, a common signal line com, etc. The active layer 24, the gate electrode G, the source electrode S, and the drain electrode D constitute a thin-film transistor. Each slit electrode of the first transparent electrode layer 9 is electrically connected to the drain electrode D through a via penetrating the second planarization layer 8, thereby enabling the input of electrical signals to the slit electrodes via the thin-film transistor.

[0082] In some embodiments, in the display panel provided in the present disclosure, such as Figures 2-5 , Figure 10 and Figure 15 As shown, Figure 15 For illustration only Figures 2-5 and Figure 10A top view of the first main spacer 31 and the second main spacer 32. The array substrate 1 also includes a plurality of first main spacers 31 disposed in the same layer as the first auxiliary spacer 12, and the opposing substrate 2 also includes a plurality of second main spacers 32 disposed in the same layer as the second auxiliary spacer 22.

[0083] Each second main spacer 32 corresponds one-to-one with each first main spacer 31. The orthographic projection of the second main spacer 32 on the first substrate 11 intersects with the orthographic projection of the first main spacer 31 on the first substrate 11. The orthographic projections of the first main spacer 31 and the second main spacer 32 on the first substrate 11 overlap with the orthographic projections of the intersection areas of the gate lines (G1, G2...) and data lines (D1, D2...) on the first substrate 11.

[0084] Specifically, such as Figures 2-5 , Figure 10 and Figure 15 As shown, the main spacer in this embodiment adopts a double-sided spacer cross design. For example, the second main spacer 32 and the first main spacer 31 overlap in a cross shape. This results in a relatively large distance between the edge of the first main spacer 31 and the edge of the second main spacer 32, and also a relatively large distance between the edge of the second main spacer 32 and the edge of the first main spacer 31. When the spacers slide, the spacers on each side are less likely to scratch out the black matrix area and damage the orientation layer on the opposite side. Therefore, the main spacer design provided in this embodiment has good resistance to PS Mura. Simultaneously, the main spacers do not affect the aperture ratio. Therefore, the product designed with both main and auxiliary spacers provided in this disclosure has both good resistance to PS Mura and high transmittance.

[0085] Specifically, such as Figure 2 and Figure 10 As shown, the sum of the thicknesses of the first main spacer 31 and the second main spacer 32 is greater than the sum of the thicknesses of the first auxiliary spacer 12 and the second auxiliary spacer 22. Under normal circumstances, the cell thickness of the display panel is supported by the paired design of the first main spacer 31 and the second main spacer 32. When the display panel is subjected to vertical external force or is under low temperature conditions, the cell thickness of the display panel decreases. For example, the array substrate moves closer to the opposing substrate, causing the main spacer to be over-compressed and unable to provide sufficient support. Alternatively, one side of the main spacer may be cut off, and the main spacer may not contact the opposing substrate and therefore cannot provide sufficient support. In this case, the auxiliary spacer will gradually move closer to and contact the opposing substrate, providing sufficient support and maintaining the uniformity of the cell thickness.

[0086] It should be noted that the thickness of the first main spacer 31 can be greater than the thickness of the first auxiliary spacer 12, and the thickness of the second main spacer 32 can be greater than the thickness of the second auxiliary spacer 22; alternatively, the thickness of the first main spacer 31 can be the same as the thickness of the first auxiliary spacer 12, and the thickness of the second main spacer 32 can be greater than the thickness of the second auxiliary spacer 22; or the thickness of the second main spacer 32 can be the same as the thickness of the second auxiliary spacer 22, and the thickness of the first main spacer 31 can be greater than the thickness of the first auxiliary spacer 12.

[0087] Specifically, in this embodiment of the disclosure, the thickness of the first main spacer 31 is the same as the thickness of the first auxiliary spacer 12, and the thickness of the second main spacer 32 is greater than the thickness of the second auxiliary spacer 22.

[0088] In some embodiments, in the display panel provided in the present disclosure, such as Figure 4 and Figure 5 As shown, in the intersection areas (areas A1 and A2) adjacent to the paired first main spacers 31 and 32 along the extension direction of the gate lines (G1, G2...), neither the first auxiliary spacer 12 nor the second auxiliary spacer 22 is provided, nor are the first main spacers 31 or 32 provided. This is because the difference between the second main spacer 32 and the second auxiliary spacer 22 on the opposing substrate 2 side is generally small, and the second main spacer 32 is a positioning PS. Therefore, auxiliary spacers are generally not provided on the left and right sides of the main spacers to achieve better alignment between the array substrate 1 and the opposing substrate 2.

[0089] In some embodiments, in the display panel provided in the present disclosure, such as Figures 3-5 As shown, the orthographic projection of the black matrix 4 onto the first substrate 11 covers the gate lines (G1, G2…), data lines (D1, D2…), the first auxiliary spacer 12, the second auxiliary spacer 22, the first main spacer 31, and the second main spacer 32 onto the first substrate 11. Because the first auxiliary spacer 12 and the second auxiliary spacer 22 adopt a linear overlapping design along the data line extension direction, the width of the black matrix 4 on the left and right sides of the first auxiliary spacer 12 and the second auxiliary spacer 22 can be reduced, thereby increasing the aperture ratio of the display panel.

[0090] In some embodiments, in the display panel provided in the present disclosure, such as Figure 16 As shown, Figure 16This is a schematic diagram of the orthographic projection of the black matrix 4, main spacers (31 and 32), and auxiliary spacers (12 and 22) on the second substrate 2. The width W1 of the black matrix 4 corresponding to the regions where the paired first main spacers 31 and 32 are located, extending along the gate lines (G1, G2…), is greater than the width W2 of the black matrix 4 corresponding to the regions where the paired first auxiliary spacers 12 and 22 are located, extending along the gate lines (G1, G2…). Similarly, the width W2 of the black matrix 4 corresponding to the regions where the paired first auxiliary spacers 12 and 22 are located, extending along the gate lines (G1, G2…), is greater than the width W3 of the black matrix 4 corresponding to the regions where no spacers are located, extending along the gate lines (G1, G2…). By designing the width of the black matrix 4 according to the presence and shape of the spacers, the aperture ratio can be further improved.

[0091] Optionally, the design of the auxiliary spacers in the display panel provided in this disclosure can be applied to curved screen products, especially long curved screens. Since there will be relative sliding between the PSs in the bending direction when the curved screen is bent, when the long side of the auxiliary spacer in this disclosure is parallel to the bending direction of the curved screen, the overlapping area of ​​the spacers on both sides in this direction is large, resulting in a larger relative sliding distance between the PSs. This makes it less likely for the PSs to slide out when the screen bends, and reduces the risk of PS mura.

[0092] Through testing by the inventors of this case, it was found that the design of the auxiliary spacer used in the display panel provided in this disclosure embodiment can increase the aperture ratio by about 5.1% compared with the cross-shaped auxiliary spacer design in the related technology; and can increase the aperture ratio by about 11.2% compared with the columnar auxiliary spacer design in the related technology, thereby achieving a higher transmittance product specification.

[0093] It should be noted that other essential components of the display panel are all known to those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0094] Based on the same inventive concept, this disclosure also provides a display device, including the display panel described above. Since the principle by which this display device solves the problem is similar to that of the display panel described above, the implementation of the display device provided in this disclosure can refer to the implementation of the display panel described above, and repeated details will not be elaborated further.

[0095] In some embodiments, in the display device provided in the present disclosure, such as Figure 17 and Figure 18 As shown, it also includes a backlight module 100 located on the light-incident side of the array substrate 1.

[0096] In some embodiments, in the display device provided in this disclosure, the backlight module 100 can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature light-emitting diodes (Mini LEDs, Micro LEDs, etc.).

[0097] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0098] In specific implementation, the display device provided in the embodiments of this disclosure is a liquid crystal display device. The liquid crystal display device also includes other necessary components and parts, such as a housing, a main circuit board, a power cord, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here and should not be regarded as a limitation of this disclosure.

[0099] In specific implementation, the display device provided in the embodiments of this disclosure may be a full-screen display device or a flexible display device, etc., and is not limited thereto.

[0100] In specific implementation, the display device provided in the embodiments of this disclosure can be as follows: Figure 19The image shows a full-screen mobile phone. Of course, the display device provided in this embodiment can also be any product or component with display function, such as an in-vehicle display, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on this disclosure. This display device includes, but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in this embodiment. In other words, the display device provided in this embodiment may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0101] This disclosure provides a display panel and display device. By designing the auxiliary spacers as a dual-sided structure of an array substrate and a counter substrate, with both auxiliary spacers extending along the data line extension direction, the first and second auxiliary spacers overlap in a straight line along the data line extension direction after being aligned. Because the critical dimension (CD) of the black matrix along the data line extension direction is wider, PS Mura can be prevented. Therefore, this disclosure does not require much additional black matrix to shield the auxiliary spacers, reducing the area of ​​the black matrix around the auxiliary spacers. This increases the effective display area while preventing PS Mura, improving product transmittance and enhancing product competitiveness. Furthermore, the increased contact area between the auxiliary spacers enhances friction, making them less prone to slippage and further preventing PS Mura. Compared to the XPS design in related technologies, the auxiliary spacers of this disclosure are smaller for the same contact area. Therefore, this disclosure can achieve the desired support effect, increase pixel aperture ratio, and achieve high transmittance specifications by using smaller auxiliary spacer sizes and narrower black matrix shielding distances.

[0102] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0103] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein, It includes an array substrate and a counter substrate arranged in a cell, and a liquid crystal layer located between the array substrate and the counter substrate; The array substrate includes: a first substrate, a plurality of gate lines and a plurality of data lines disposed on the side of the first substrate near the liquid crystal layer and arranged in an insulated manner, and a plurality of first auxiliary spacers disposed on the side of the gate lines and the data lines near the liquid crystal layer; wherein, the first auxiliary spacers extend in the same direction as the data lines, and the orthographic projection of the first auxiliary spacers on the first substrate overlaps with the orthographic projection of the intersection area of ​​the gate lines and the data lines on the first substrate. The opposing substrate includes: a second substrate, and a plurality of second auxiliary spacers disposed on the side of the second substrate near the liquid crystal layer; wherein the second auxiliary spacers extend in the same direction as the data lines, each second auxiliary spacer corresponds to each first auxiliary spacer, and the orthographic projection of the second auxiliary spacer on the first substrate at least partially overlaps with the orthographic projection of the first auxiliary spacer on the first substrate.

2. The display panel according to claim 1, wherein, The grid lines and the data lines intersect to define multiple rows and columns of pixel units. Each pixel unit includes multiple sub-pixels with different color resist colors. Sub-pixels in the same row have the same color resist color, while sub-pixels in the same column have different color resist colors. Sub-pixels in the same column are electrically connected to the same data line, while sub-pixels in different columns are electrically connected to different data lines. Each row of pixel units arranged along the pixel row direction is electrically connected to three rows of grid lines.

3. The display panel according to claim 2, wherein, The orthographic projections of the first auxiliary spacer and the second auxiliary spacer on the first substrate are both strip-shaped, and the length of the first auxiliary spacer along the data line extension direction is greater than the length of the second auxiliary spacer along the data line extension direction.

4. The display panel according to claim 3, wherein, The length of the first auxiliary spacer along the extension direction of the grid line is less than the length of the second auxiliary spacer along the extension direction of the grid line.

5. The display panel according to claim 3, wherein, The length of the first auxiliary spacer along the extension direction of the grid line is greater than the length of the second auxiliary spacer along the extension direction of the grid line.

6. The display panel according to claim 2, wherein, The orthographic projections of the first auxiliary spacer and the second auxiliary spacer on the first substrate are both strip-shaped, and the length of the first auxiliary spacer along the data line extension direction is less than the length of the second auxiliary spacer along the data line extension direction.

7. The display panel according to claim 6, wherein, The length of the first auxiliary spacer along the extension direction of the grid line is greater than the length of the second auxiliary spacer along the extension direction of the grid line.

8. The display panel according to claim 6, wherein, The length of the first auxiliary spacer along the extension direction of the grid line is less than the length of the second auxiliary spacer along the extension direction of the grid line.

9. The display panel according to any one of claims 1-8, wherein, The centerline of the first auxiliary spacer along the extension direction of the data line coincides with the centerline of the second auxiliary spacer along the extension direction of the data line.

10. The display panel according to any one of claims 1-8, wherein, The opposing substrate further includes: a black matrix and a filter layer located between the second substrate and the second auxiliary spacer, a first planarization layer located between the black matrix and the filter layer and the second auxiliary spacer, and a first alignment layer located on the side of the second spacer near the liquid crystal layer; the black matrix includes a plurality of openings, the filter layer includes a plurality of filters, and the orthographic projection of each filter on the second substrate covers the orthographic projection of the corresponding opening on the second substrate.

11. The display panel according to claim 10, wherein, The array substrate further includes: a second planarization layer located between the gate line and the data line and the first spacer; a first transparent electrode layer located between the second planarization layer and the first spacer; a passivation layer located between the first transparent electrode layer and the first spacer; a second transparent electrode layer located between the passivation layer and the first spacer; and a second alignment layer located on the side of the first spacer near the liquid crystal layer.

12. The display panel according to claim 10, wherein, The array substrate further includes: a second planarization layer located between the gate lines and the data lines and the first spacer; a first transparent electrode layer located on the side of the second planarization layer near the liquid crystal layer; a passivation layer located on the side of the first transparent electrode layer near the liquid crystal layer; a second transparent electrode layer located on the side of the passivation layer near the liquid crystal layer; and a second alignment layer located on the side of the second transparent electrode layer near the liquid crystal layer; wherein... The first spacer and the second planarization layer are an integral structure.

13. The display panel according to claim 11 or 12, wherein, The array substrate further includes a plurality of first main spacers disposed in the same layer as the first auxiliary spacer, and the opposing substrate further includes a plurality of second main spacers disposed in the same layer as the second auxiliary spacer. The sum of the thicknesses of the first main spacers and the second main spacers is greater than the sum of the thicknesses of the first auxiliary spacer and the second auxiliary spacer. Each of the second main spacers corresponds one-to-one with each of the first main spacers. The orthographic projection of the second main spacer on the first substrate intersects with the orthographic projection of the first main spacer on the first substrate. Furthermore, the orthographic projections of the first main spacer and the second main spacer on the first substrate overlap with the orthographic projections of the intersection area of ​​the gate line and the data line on the first substrate.

14. The display panel according to claim 13, wherein, Along the extension direction of the grid line, neither the first auxiliary spacer nor the second auxiliary spacer is provided in the intersection area on either side adjacent to the first main spacer and the second main spacer that are arranged in pairs, nor are the first main spacer or the second main spacer provided in either side.

15. The display panel according to claim 13, wherein, The orthogonal projection of the black matrix on the first substrate covers the orthogonal projections of the gate line, the data line, the first auxiliary spacer, the second auxiliary spacer, the first main spacer, and the second main spacer on the first substrate.

16. The display panel according to claim 15, wherein, The width of the black matrix corresponding to the areas where the paired first main spacers and second main spacers are located, along the extension direction of the grid line, is greater than the width of the black matrix corresponding to the areas where the paired first auxiliary spacers and second auxiliary spacers are located, along the extension direction of the grid line. The width of the black matrix corresponding to the areas where the paired first auxiliary spacers and second auxiliary spacers are located, along the extension direction of the grid line, is greater than the width of the black matrix corresponding to the areas where no spacers are located, along the extension direction of the grid line.

17. The display panel according to any one of claims 13-16, wherein, One of the first transparent electrode layer and the second transparent electrode layer is a planar electrode, and the other includes multiple slit electrodes.

18. A display device, wherein, Includes the display panel according to any one of claims 1 to 17.

Images