Array substrate, display panel, manufacturing method, display device and electronic device

Abstract

The invention provides an array substrate. The array substrate comprises a substrate; the stacking structure is arranged on the substrate; and a plurality of first substrate spacers. The array substrate further comprises a plurality of pixel opening areas and spacer areas located between the adjacent pixel opening areas, and the height of the stacking structures arranged in the spacer areas is larger than that of the stacking structures arranged in the pixel opening areas. The plurality of first substrate spacers are arranged in the spacer regions, and the stacked structures of the spacer regions comprise metal spacer layers located at the upper parts at the positions where the first substrate spacers are arranged; and the plurality of first substrate spacers comprise a part of the stacked structure of the metal spacer layer in the orthographic projection area on the substrate, which is higher than the stacked structure in the pixel opening area. The invention further provides a display panel, a display device, an electronic device, a manufacturing method of the array substrate and a manufacturing method of the display panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate and its manufacturing method, a display panel and its manufacturing method, a display device and an electronic device. Background Technology

[0002] A liquid crystal display (LCD) panel typically comprises an array substrate and a color film (CF) substrate stacked together, with liquid crystal filling the space between them. To maintain the stability and cell thickness uniformity of the LCD panel, multiple photospacers (PS) are usually placed between the array substrate and the CF substrate to support them. By using multiple photospacers, the overall thickness uniformity of the LCD panel can be improved, as well as the LCD panel's tolerance to liquid crystal fluctuations, thereby increasing the yield rate of the LCD panel.

[0003] Organic layer (ORG) coating is used in the manufacturing process of liquid crystal display panels. Due to the smoothing effect of the ORG, the spacers in conventional spacer designs are relatively flat. When the display panel is subjected to pressure, the spacers on the color filter substrate side can slide into the opening area of ​​the thin film transistor (TFT), scratching the alignment layer in the opening area, affecting liquid crystal alignment, and causing light leakage, resulting in spacer-related inhomogeneity (PSMura). Furthermore, in existing solutions, the spacers on both the array substrate side and the color filter substrate side are manufactured by the same factory that produces the color filter substrate, significantly impacting production capacity. Summary of the Invention

[0004] This disclosure provides an array substrate and its manufacturing method, a display panel and its manufacturing method, a display device, and an electronic device to ensure that the spacers on the color filter substrate side do not easily slide when the display panel is pressed, thereby avoiding PS Mura.

[0005] This disclosure provides an array substrate, including: a substrate; a stacked structure disposed on the substrate; and a plurality of first substrate spacers, wherein the array substrate further includes a plurality of pixel opening regions and a spacing region located between adjacent pixel opening regions, the height of the stacked structure disposed in the spacing region is greater than the height of the stacked structure disposed in the pixel opening region, the plurality of first substrate spacers are disposed in the spacing region, the stacked structure in the spacing region includes an upper metal spacer layer at the location where the first substrate spacers are disposed, and the plurality of first substrate spacers include a portion of the stacked structure in the orthographic projection area of ​​the metal spacer layer on the substrate that is higher than the stacked structure located in the pixel opening region.

[0006] According to an embodiment of this disclosure, the array substrate further includes: a plurality of data lines extending in a first direction; and a plurality of gate lines extending in a second direction intersecting the first direction, wherein the orthographic projection of each of the plurality of first substrate spacers on the substrate at least partially overlaps with the orthographic projection of one of the plurality of data lines on the substrate.

[0007] According to embodiments of this disclosure, the plurality of first substrate spacers include first spacers corresponding to main spacers on the color filter substrate and second spacers corresponding to auxiliary spacers on the color filter substrate.

[0008] According to an embodiment of this disclosure, the dimension of the second spacer in the first direction is smaller than the dimension of the first spacer in the first direction, or the dimension of the second spacer in the second direction is larger than the dimension of the first spacer in the second direction.

[0009] According to embodiments of this disclosure, at least a portion of the second spacer has a dimension smaller than that of the first spacer in the first direction, and at least a portion of the second spacer has a dimension larger than that of the first spacer in the second direction.

[0010] According to an embodiment of this disclosure, the second spacer includes a main spacer and secondary spacers disposed on both sides of the main spacer in the first direction, wherein the orthographic projection of the secondary spacers on the substrate at least partially overlaps with the orthographic projection of one of the plurality of gate lines on the substrate.

[0011] According to an embodiment of this disclosure, the secondary septum includes a plurality of sub-septum disposed in the second direction.

[0012] According to an embodiment of this disclosure, the secondary spacer is located at a higher level than the primary spacer in a direction perpendicular to the substrate.

[0013] According to an embodiment of this disclosure, each of the first spacers disposed in the same row in the second direction is aligned in the second direction, and at least one second spacer disposed in the same row in the second direction and other second spacers are not aligned in the second direction.

[0014] According to an embodiment of this disclosure, at least one second spacer disposed in the same row in the second direction and the first spacer are not aligned in the second direction.

[0015] This disclosure provides a display panel, including: a first substrate; and a second substrate disposed opposite to the first substrate. The first substrate includes: a first substrate; a stacked structure disposed on the first substrate facing the second substrate; and a plurality of first substrate spacers. The second substrate includes: a second substrate; a black matrix disposed on the second substrate facing the first substrate; and a plurality of second substrate spacers disposed on the black matrix. The plurality of first substrate spacers corresponds one-to-one with the plurality of second substrate spacers. The first substrate includes a plurality of pixel aperture regions and a spacing region located between adjacent pixel aperture regions. The height of the stacked structure disposed in the spacing region is greater than the height of the stacked structure disposed in the pixel aperture region. The plurality of first substrate spacers are disposed in the spacing region. The stacked structure in the spacing region includes an upper metal spacer layer at the location where the first substrate spacers are disposed, and the plurality of first substrate spacers include a portion of the stacked structure in the orthographic projection area of ​​the metal spacer layer on the substrate that is higher than the stacked structure in the pixel aperture region.

[0016] According to an embodiment of this disclosure, the first substrate further includes a plurality of data lines extending in a first direction and a plurality of gate lines extending in a second direction intersecting the first direction. The orthographic projection of each of the plurality of first substrate spacers on the first substrate at least partially overlaps with the orthographic projection of one of the plurality of data lines on the first substrate, and the orthographic projection of each of the plurality of first substrate spacers on the first substrate at least partially overlaps with the orthographic projection of a corresponding second substrate spacer among the plurality of second substrate spacers on the first substrate.

[0017] According to embodiments of this disclosure, the plurality of second substrate spacers include main spacers and auxiliary spacers, wherein the height of the main spacer in a third direction perpendicular to the first substrate is greater than the height of the auxiliary spacer in that third direction. The plurality of first substrate spacers include first spacers corresponding to the main spacers and second spacers corresponding to the auxiliary spacers.

[0018] According to an embodiment of this disclosure, the dimension of the second spacer in the first direction is smaller than the dimension of the first spacer in the first direction, or the dimension of the second spacer in the second direction is larger than the dimension of the first spacer in the second direction.

[0019] According to embodiments of this disclosure, at least a portion of the second spacer has a dimension smaller than that of the first spacer in the first direction, and at least a portion of the second spacer has a dimension larger than that of the first spacer in the second direction.

[0020] According to an embodiment of this disclosure, the second spacer includes a main spacer and secondary spacers disposed on both sides of the main spacer in the first direction, wherein the orthographic projection of the secondary spacer on the first substrate at least partially overlaps with the orthographic projection of one of the plurality of gate lines on the first substrate.

[0021] According to an embodiment of this disclosure, the secondary septum includes a plurality of sub-septum disposed in the second direction.

[0022] According to an embodiment of this disclosure, the secondary septum is located at a higher level than the main septum in the third direction.

[0023] According to an embodiment of this disclosure, each of the first spacers disposed in the same row in the second direction is aligned in the second direction, and at least one second spacer disposed in the same row in the second direction and other second spacers are not aligned in the second direction.

[0024] According to an embodiment of this disclosure, at least one second spacer disposed in the same row in the second direction and the first spacer are not aligned in the second direction.

[0025] According to an embodiment of this disclosure, the first substrate is an array substrate, and the second substrate is a color filter substrate.

[0026] According to an embodiment of this disclosure, the color filter substrate further includes a plurality of color resist layers disposed between the black matrices.

[0027] According to embodiments of this disclosure, the plurality of color resist layers include: a blue color resist layer, a green color resist layer, and a red color resist layer.

[0028] This disclosure also provides a display device, including a display panel according to an embodiment of this disclosure.

[0029] This disclosure also provides an electronic device, including a display device according to embodiments of this disclosure.

[0030] This disclosure also provides a method for fabricating an array substrate, comprising: preparing a substrate; preparing a stacked structure on the substrate; and forming a plurality of first substrate spacers through the stacked structure, wherein the array substrate includes a plurality of pixel opening regions and a spacing region located between adjacent pixel opening regions, the height of the stacked structure disposed in the spacing region is greater than the height of the stacked structure disposed in the pixel opening region, the plurality of first substrate spacers are disposed in the spacing region, and forming a plurality of first substrate spacers through the stacked structure includes: forming a metal spacer layer on the upper part of the stacked structure in the spacing region to form the plurality of first substrate spacers by means of a metal exposure process.

[0031] This disclosure also provides a method for manufacturing a display panel, including: preparing a first substrate; preparing a second substrate; and assembling the first substrate and the second substrate together to form the display panel. Preparing the first substrate includes: preparing a first substrate; preparing a stacked structure on the first substrate; and forming a plurality of first substrate spacers through the stacked structure. Preparing the second substrate includes: preparing a second substrate; preparing a black matrix on the second substrate; and preparing a plurality of second substrate spacers on the black matrix. The plurality of first substrate spacers corresponds one-to-one with the plurality of second substrate spacers. The first substrate includes a plurality of pixel opening regions and a spacing region located between adjacent pixel opening regions. The height of the stacked structure disposed in the spacing region is greater than the height of the stacked structure disposed in the pixel opening region. The plurality of first substrate spacers are disposed in the spacing region, and forming the plurality of first substrate spacers through the stacked structure includes: forming a metal spacer layer on the upper part of the stacked structure in the spacing region where the plurality of first substrate spacers are to be formed using a metal exposure process.

[0032] The array substrate and its fabrication method, the display panel and its fabrication method, the display device and the electronic device of the present disclosure, since the spacers on the array substrate side include a metal spacer layer, can increase the friction with the corresponding spacers on the color filter substrate side, ensuring that the spacers on the color filter substrate side are not prone to slippage when the display panel is pressed, thereby avoiding PS Mura. Furthermore, the high-performance exposure machine of the array substrate fabrication plant can be used to achieve precise control of various spacer shapes, improving the accuracy of the solution. Attached Figure Description

[0033] The accompanying drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0034] Figure 1A This is a cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0035] Figure 1B This is another cross-sectional schematic view of the array substrate according to an embodiment of the present disclosure;

[0036] Figure 2A This is a cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure;

[0037] Figure 2B This is another cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure;

[0038] Figure 3 This is a top view of a display panel according to an embodiment of the present disclosure;

[0039] Figure 4 This is another top view schematic diagram of a display panel according to an embodiment of the present disclosure;

[0040] Figure 5A This is another top view schematic diagram of a display panel according to an embodiment of the present disclosure;

[0041] Figure 5B To extend Figure 5A A cross-sectional view of line AA in the diagram;

[0042] Figure 6 This is another top view schematic diagram of a display panel according to an embodiment of the present disclosure;

[0043] Figure 7 This is another top view schematic diagram of a display panel according to an embodiment of the present disclosure;

[0044] Figure 8 This is another top view schematic diagram of a display panel according to an embodiment of the present disclosure;

[0045] Figure 9 A flowchart illustrating a method for fabricating an array substrate according to an embodiment of the present disclosure is shown;

[0046] Figure 10 A flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure is shown.

[0047] For clarity, the accompanying drawings are not necessarily drawn to scale, and the same reference numerals will always be used to refer to the same or similar elements. The configurations shown in the drawings are merely examples and should not be construed as limiting in any way. Detailed Implementation

[0048] To enable those skilled in the art to better understand the technical solutions of this disclosure, the display panel, its manufacturing method, and display device including the display panel provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0049] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0050] Organic film coating is typically used in the manufacturing process of liquid crystal display panels. Due to the smoothing effect of the organic film, the spacers are relatively flat. When the display panel is subjected to pressure, the spacers on the color filter substrate side can slide into the opening area of ​​the thin-film transistor, scratching the alignment layer in the opening area, affecting the liquid crystal alignment, and thus causing light leakage, resulting in PS Mura.

[0051] According to the display panel of the present disclosure, the spacers on the array substrate side are formed with a metal layer, thereby increasing the distance between the alignment layer of the array substrate and the spacers on the color filter substrate side. This ensures that when the display panel is pressed, the spacers on the color filter substrate side do not easily slide and come into contact with the alignment layer of the array substrate, thereby avoiding PS Mura. At the same time, the spacers on the array substrate side are formed with a metal layer, which makes the pattern more accurate and has less impact on the aperture ratio.

[0052] Figure 1A and Figure 1B This is a cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure. Figure 2A and Figure 2B This is a cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure. Figure 3 This is a top view of a display panel according to an embodiment of the present disclosure.

[0053] like Figure 1A and Figure 1B As shown, the array substrate according to an embodiment of the present disclosure includes a substrate, a stacked structure disposed on the substrate, and a plurality of first substrate spacers 107 formed by the stacked structure. The array substrate includes a plurality of pixel opening regions and a spacing region located between adjacent pixel opening regions. The height of the stacked structure disposed in the spacing region is greater than the height of the stacked structure disposed in the pixel opening region. The plurality of first substrate spacers 107 are disposed in the spacing region and include a metal spacer layer disposed on the upper part of a portion of the stacked structure in the spacing region, and the plurality of first substrate spacers include a portion of the stacked structure in the orthographic projection region of the metal spacer layer on the first substrate that is higher than the stacked structure located in the pixel opening region.

[0054] like Figure 2A and Figure 2BAs shown, the display panel according to an embodiment of this disclosure includes a first substrate and a second substrate disposed opposite to the first substrate. The first substrate includes a first substrate, a stacked structure disposed on the first substrate facing the second substrate, and a plurality of first substrate spacers 107 formed by the stacked structure. The second substrate includes a second substrate, a black matrix disposed on the second substrate facing the first substrate, and a plurality of second substrate spacers 108 disposed on the black matrix. The plurality of first substrate spacers 107 correspond one-to-one with the plurality of second substrate spacers 108. The first substrate includes a plurality of pixel opening regions and a spacing region located between adjacent pixel opening regions. The height of the stacked structure disposed in the spacing region is greater than the height of the stacked structure disposed in the pixel opening region. The plurality of first substrate spacers 107 are disposed in the spacing region and include a metal spacer layer disposed on the upper part of a portion of the stacked structure in the spacing region, and the plurality of first substrate spacers include a portion of the stacked structure in the orthographic projection area of ​​the metal spacer layer on the first substrate that is higher than the stacked structure located in the pixel opening region.

[0055] In the context of this disclosure, a spacer that includes a metal spacer layer will be referred to as a metal spacer (MPS).

[0056] According to embodiments of this disclosure, such as Figure 1A and Figure 2A As shown, the first substrate can be a glass substrate, and the stacked structure of the spacer region (or wiring region) formed on the first substrate can sequentially include: a gate layer, a gate insulating layer (GI), an active layer (IGZO), a source / drain layer (SD), a first dielectric layer (PVX1), an organic film layer (ORG), a metal oxide layer (ITO), a metal spacer layer, and a second dielectric layer (PVX2). In some embodiments, the metal oxide layer (ITO) and the metal spacer layer are in direct contact to achieve electrical connection between the metal oxide layer (ITO) and the metal spacer layer.

[0057] According to embodiments of this disclosure, such as Figure 1B and Figure 2B As shown, the first substrate can be a glass substrate, and the stacked structure of the spacer region (or wiring region) formed on the first substrate can sequentially include: a gate layer, a gate insulating layer (GI), an active layer (IGZO), a source drain layer (SD), a first dielectric layer (PVX1), an organic film layer (ORG), a metal oxide layer (ITO), a second dielectric layer (PVX2), and a metal spacer layer.

[0058] See Figures 1A to 2B The stacked structure of the pixel opening region formed on the first substrate may sequentially include: a gate insulating layer (GI), a first dielectric layer (PVX1), an organic film layer (ORG), a metal oxide layer (ITO), and a second dielectric layer (PVX2). Furthermore, Figures 1A to 2B The first substrate and the second substrate are also shown to each include an alignment layer (PI), the alignment layer of the first substrate covering the first substrate spacer 107 and the stacked structure, and the alignment layer of the second substrate covering the second substrate spacer 108 and the black matrix.

[0059] like Figures 1A to 2B As shown, the stacked structure of the pixel aperture region formed on the substrate does not include a gate layer, a source / drain layer (SD), and a metal spacer layer. Because there is a height difference between the stacked structure formed in the spacer region and the stacked structure formed in the pixel aperture region, a first substrate spacer 107 (MPS) can be formed through the stacked structure in the spacer region. The height of the first substrate spacer 107 is determined by the heights of the gate layer, the source / drain layer (SD), and the metal spacer layer. In other words, with the same thickness of the same film layers, the height difference formed by the remaining film layers constitutes the first substrate spacer 107.

[0060] Apart from Figures 1A to 2B The exemplary stacked structure shown may further include other layers not shown in the figures, as can the stacked structure formed in the spacing region. Similarly, the stacked structure formed in the pixel aperture region may further include other layers not shown in the figures. For example, although not shown in the figures, those skilled in the art will understand that a second metal oxide layer may also be formed in the pixel aperture region, which may be formed on the first substrate or on the second substrate.

[0061] See Figure 2A and Figure 2B Liquid crystal (not shown) can be filled between the first and second substrates and a display panel can be formed after cell assembly. At the locations corresponding to the pixel opening areas, the thickness of the liquid crystal layer (i.e., cell gap, CG) can be appropriately configured to various dimensions according to specific process requirements.

[0062] According to embodiments of this disclosure, such as Figure 2A and Figure 2B As shown, the second substrate can be a glass substrate, the black matrix can be formed on the second substrate, and the second substrate spacers 108 can be formed on the black matrix, with each second substrate spacer 108 corresponding one-to-one with a first substrate spacer 107 on the first substrate. The orthographic projection of the black matrix on the first substrate at least partially overlaps with the stacked structure of the spacer regions formed on the first substrate. In some embodiments, the orthographic projection of the black matrix on the first substrate completely covers the stacked structure of the spacer regions formed on the first substrate.

[0063] According to embodiments of this disclosure, such as Figure 2A and Figure 2BAs shown, the plurality of second substrate spacers 108 include a main spacer 1081 and an auxiliary spacer 1082. The height of the main spacer 1081 in a third direction perpendicular to the first substrate is greater than the height of the auxiliary spacer 1082 in the third direction. The plurality of first substrate spacers 107 include a first spacer 1071 corresponding to the main spacer 1081 and a second spacer 1072 corresponding to the auxiliary spacer 1082.

[0064] According to embodiments of this disclosure, the first substrate may be an array substrate, and the second substrate may be a color filter substrate.

[0065] See Figure 2A and Figure 2B The second substrate can be a color filter substrate, except... Figure 2A and Figure 2B In addition to the second substrate, the black matrix, and the second substrate spacer 108 formed on the black matrix, the second substrate may further include a plurality of color resist layers (not shown) disposed between the black matrices. The black matrices on the second substrate correspond to the spacing regions (or wiring regions) of the first substrate, and the plurality of color resist layers on the second substrate correspond to the pixel opening regions of the first substrate. The plurality of color resist layers may include color resist layers of different colors, for example, a blue color resist layer, a green color resist layer, and a red color resist layer.

[0066] According to embodiments of this disclosure, such as Figure 3 As shown, the first substrate also includes a plurality of data lines 101 extending in a first direction D1, and a plurality of gate lines 102 extending in a second direction D2 intersecting the first direction D1. The orthographic projection of each of the plurality of first substrate spacers 107 on the first substrate at least partially overlaps with the orthographic projection of one of the plurality of data lines 101 on the first substrate, and the orthographic projection of each of the plurality of first substrate spacers 107 on the first substrate at least partially overlaps with the orthographic projection of the corresponding second substrate spacer 108 of the plurality of second substrate spacers 108 on the first substrate.

[0067] See Figure 3The first substrate may further include a common electrode line 103 and a common via 105, with the common electrode line 103 connected to the common electrode 110 via the common connection via 105. In some embodiments, the common electrode 110 and the metal spacer layer are in direct contact to achieve electrical connection between the common electrode 110 and the metal spacer layer, thereby reducing the resistance of the common electrode 110 and preventing the metal spacer layer from floating. Furthermore, the first substrate may also include a plurality of thin-film transistors 104, with data lines 101 connected to the source of the thin-film transistors 104, gate lines 102 connected to the gate of the thin-film transistors 104, and the drain of the thin-film transistors 104 connected to a pixel electrode (not shown) via a drain via 106. The thin-film transistors 104 also include an active layer 109. Figure 3 The first substrate is shown to include a metal oxide layer, which can be used as a common electrode 110. The material of the metal oxide layer may include a transparent oxide, such as indium tin oxide (ITO).

[0068] like Figure 3 As shown, the width of the first substrate spacer 107 in the second direction D2 is wider than that of the data line 101. Typically, the width of the data line can be, for example, about 3 μm, and the width of the first substrate spacer 107 can be, for example, about 15 μm. The length of the first substrate spacer 107 in the first direction D1 can be, for example, about 30 μm. For example, the first substrate spacer 107 can be formed as 14 μm × 28 μm (dimension in the second direction D2 × dimension in the first direction D1). It should be understood that the specific values ​​shown are merely examples, and those skilled in the art can appropriately configure various dimensions according to specific process requirements. In some embodiments, the two ends of the first substrate spacer 107 in the first direction D1 can at least partially overlap with the gate line 102 and the common electrode line 103, respectively, thereby increasing the height of these two ends and preventing the sliding of the second substrate spacer 108. In some embodiments, the two ends of the first substrate spacer 107 in the first direction D1 may extend beyond the regions of the gate line 102 and the common electrode line 103, respectively. Increasing the length of the first substrate spacer 107 in the first direction D1 can prevent the second substrate spacer 108 from slipping out and does not substantially reduce the aperture ratio.

[0069] like Figure 3 As shown, the data line 101 is bent at the position of the spacer, so that the distance from the center of the data line 101 in the second direction D2 to the two adjacent drain vias 106 is approximately the same, and the distance from the center of the first substrate spacer 107 in the second direction D2 to the two adjacent drain vias 106 is also approximately the same.

[0070] According to embodiments of this disclosure, when the display panel is not subjected to external force, there is a certain mutual compressive force between the protrusions formed by the main spacer 1081 and the corresponding first spacer 1071. This can improve the display panel's ability to resist external forces and enhance its stability. When the display panel is subjected to external pressure, the main spacer 1081 is further compressed, causing the auxiliary spacer 1082 to contact the corresponding second spacer 1072, thereby further providing support for the display panel. For example, when the main spacer 1081 and the first spacer 1071 are mutually compressed, the first spacer 1071 deforms towards the first substrate under the compression of the main spacer 1081. Since the first spacer 1071 includes a metal spacer layer disposed on the upper part, and the morphology of the metal spacer layer can be precisely controlled through a metal exposure process, the friction between the first spacer 1071 and the main spacer 1081 is increased. This ensures that the main spacer 1081 is not easily slipped when the display panel is subjected to external pressure, thereby preventing the spacer from sliding into the opening area of ​​the thin-film transistor 104, scratching the alignment layer in the opening area, affecting the liquid crystal alignment, and thus causing light leakage and PS Mura. In addition, since the metal spacer layer can be formed by using a high-performance exposure machine in the factory that manufactures the array substrate through a metal exposure process, precise control of various spacer morphologies can be achieved, improving the accuracy of the solution.

[0071] According to embodiments of this disclosure, such as Figure 3 As shown, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the first direction D1 can be smaller than the size of the first spacer 1071 corresponding to the main spacer 1081 in the first direction D1.

[0072] See Figure 3 The figure shows a main spacer 1081 located at the center and auxiliary spacers 1082 located on both sides of the main spacer 1081. For example, the first spacer 1071 corresponding to the main spacer 1081 can be formed as 14μm × 28μm (dimension in the second direction D2 × dimension in the first direction D1), and the second spacer 1072 corresponding to the auxiliary spacers 1082 can be formed as 14μm × 15μm (dimension in the second direction D2 × dimension in the first direction D1). It should be understood that the specific values ​​shown are only examples, and those skilled in the art can appropriately configure various dimensions according to specific process requirements.

[0073] According to embodiments of this disclosure, by reducing the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the first direction D1, the aperture ratio (AR) can be maximized.

[0074] According to the embodiments of this disclosure, by increasing the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the first direction D1, the sliding distance of the auxiliary spacer can be increased, preventing the spacer from slipping off.

[0075] like Figure 3 As shown, the dimension of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 can be substantially equal to the dimension of the first spacer 1071 corresponding to the main spacer 1081 in the second direction D2, but this disclosure is not limited thereto. See also Figure 4 According to embodiments of this disclosure, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 may be greater than or less than the size of the first spacer 1071 corresponding to the main spacer 1081 in the second direction D2. In some embodiments, the second spacer 1072 may include both a second spacer 1072 whose size in the second direction D2 is greater than that of the first spacer 1071 in the second direction D2 and a second spacer 1072 whose size in the second direction D2 is less than that of the first spacer 1071 in the second direction D2. In some embodiments, among two adjacent second spacers 1072 on both sides of the first spacer 1071, one second spacer 1072 may have a size in the second direction D2 greater than that of the first spacer 1071 in the second direction D2, and the other second spacer 1072 may have a size in the second direction D2 less than that of the first spacer 1071 in the second direction D2.

[0076] According to embodiments of this disclosure, when designing the position of the first substrate spacer 107 corresponding to the main spacer 1081 and the auxiliary spacer 1082, it is necessary to avoid adjacent vias (including, for example, common vias 105 and drain vias 106) to allow for clearance with the vias. Therefore, when designing the shape of the first substrate spacer 107, while maintaining sufficient clearance with the vias on both sides, the dimensions of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 can be appropriately increased to increase the contact area with the auxiliary spacer 1082, thereby increasing the friction. For example, the first spacer 1071 corresponding to the main spacer 1081 can be formed as 14μm × 28μm (dimension in the second direction D2 × dimension in the first direction D1), and the second spacer 1072 corresponding to the auxiliary spacer 1082 can be formed as 27.5μm × 15μm or 23.5μm × 15μm (dimension in the second direction D2 × dimension in the first direction D1). It should be understood that the specific values ​​shown are merely examples, and those skilled in the art can appropriately configure various dimensions according to specific process requirements.

[0077] According to embodiments of this disclosure, the second spacer 1072 corresponding to the auxiliary spacer 1082 may have a smaller dimension in the first direction D1 than the first spacer 1071 corresponding to the main spacer 1081 in the first direction D1. Alternatively, the second spacer 1072 corresponding to the auxiliary spacer 1082 may have a larger dimension in the first direction D1 than the first spacer 1071 corresponding to the main spacer 1081 in the first direction D1. Alternatively, at least one second spacer 1072 corresponding to the auxiliary spacer 1082 may have a larger dimension in the first direction D1 than the first spacer 1071 corresponding to the main spacer 1081 in the first direction D1, and at least one second spacer 1072 corresponding to the auxiliary spacer 1082 may have a smaller dimension in the first direction D1 than the first spacer 1071 corresponding to the main spacer 1081 in the first direction D1.

[0078] According to embodiments of this disclosure, at least one second spacer 1072 corresponding to the auxiliary spacer 1082 may have a larger dimension in the second direction D2 than the first spacer 1071 corresponding to the main spacer 1081 in the second direction D2. Alternatively, at least one second spacer 1072 corresponding to the auxiliary spacer 1082 may have a smaller dimension in the second direction D2 than the first spacer 1071 corresponding to the main spacer 1081 in the second direction D2.

[0079] According to the embodiments of this disclosure, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the first direction D1 can be smaller than the size of the first spacer 1071 corresponding to the main spacer 1081 in the first direction D1, and the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 can be larger than the size of the first spacer 1071 corresponding to the main spacer 1081 in the second direction D2.

[0080] Figure 5A This is another top view of a display panel according to an embodiment of the present disclosure.

[0081] like Figure 5A As shown, with Figure 3 Compared to the embodiments shown, in Figure 5A In the illustrated embodiment, the second spacer 1072 corresponding to the auxiliary spacer 1082 includes a main spacer 10721 and sub-spacers 10722 disposed on both sides of the main spacer 10721 in the first direction D1. The orthographic projection of the sub-spacer 10722 on the first substrate at least partially overlaps with the orthographic projection of one of the plurality of gate lines 102 on the first substrate. Figure 5AThe image shows a main septum 1081 located in the center, and auxiliary septums 1082 located on both sides of the main septum 1081.

[0082] According to embodiments of this disclosure, the secondary spacer 10722 can be used as a barrier to block the sliding of the auxiliary spacer 1082 in the first direction D1. Figure 5A As shown, the orthographic projection of the barrier formed by the secondary spacer 10722 on the first substrate can at least partially overlap with the orthographic projection of one of the multiple gate lines 102 on the first substrate, and / or can at least partially overlap with the orthographic projection of the common electrode line 103 on the first substrate.

[0083] According to embodiments of this disclosure, see Figure 5B The auxiliary spacer 10722 can be located at a higher level than the main spacer 10721 in a direction perpendicular to the first substrate, thereby better blocking the sliding of the auxiliary spacer 1082 in the first direction D1.

[0084] It should be recognized that, for clarity, in Figure 5B The cross-sectional view schematically shows only the auxiliary septum 1082 and the corresponding second septum 1702; the orientation layer covering the septum is not shown, nor are the stacked structure and black matrix. Furthermore, the second septum 1702 is schematically represented by the metal septum layer on top of it. Those skilled in the art should also recognize that, although... Figure 5B It is shown that the sub-spacer 10722 may be located at a higher level than the main spacer 10721 in a direction perpendicular to the first substrate, but this disclosure is not limited thereto. According to an embodiment of this disclosure, the sub-spacer 10722 may be located at the same level as the main spacer 10721 in a direction perpendicular to the first substrate.

[0085] like Figure 6 As shown, a secondary spacer 10722 can be provided on only one side of the main spacer 10721 in the first direction D1.

[0086] According to embodiments of this disclosure, such as Figure 5A and Figure 6 As shown, the width of the secondary spacer 10722 in the second direction D2 is substantially the same as the width of the main spacer 10721 in the second direction D2. Alternatively, the width of the secondary spacer 10722 in the second direction D2 may differ from the width of the main spacer 10721 in the second direction D2, and may be greater or less than the width of the main spacer 10721 in the second direction D2. It should be understood that those skilled in the art can appropriately configure various dimensions according to specific process requirements.

[0087] Figure 7 This is another top view of a display panel according to an embodiment of the present disclosure.

[0088] like Figure 7 As shown, with Figure 5A Compared to the embodiments shown, in Figure 7 In the illustrated embodiment, the second spacer 1072 corresponding to the auxiliary spacer 1082 includes a main spacer 10721 and secondary spacers 10722' disposed on both sides of the main spacer 10721 in the first direction D1, wherein the secondary spacers 10722' include a plurality of sub-spacers disposed in the second direction D2. Figure 7 The image shows a main septum 1081 located in the center, and auxiliary septums 1082 located on both sides of the main septum 1081.

[0089] According to embodiments of this disclosure, the secondary septum 10722' can be formed into multiple sub-septums, thereby facilitating the recovery of septums after displacement. For example... Figure 7 As shown, the dimensions of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 can be appropriately adjusted according to the specific location of the vias (including, for example, common via 105 and drain via 106). For example, the dimensions of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the left side of the figure in the second direction D2 can be made as large as possible while satisfying the requirement to avoid the vias, so as to increase the contact area with the auxiliary spacer 1082 and thus increase the friction. For example, the distance between the two vias (two drain vias 106) shown on the left side of the figure can be 33.55 μm. Therefore, the dimensions of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 can be formed to be 23.4 μm. That is, the dimensions of the main spacer 10721 in the second direction D2 are formed to be 23.4 μm, and the sub-spacer 10722' can be formed as three sub-spacers.

[0090] For example, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the right side of the figure in the second direction D2 can be smaller than the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the left side of the figure in the second direction D2, provided that the via is avoided. For example, the distance between the two vias (drain via 106 and common via 105) shown on the right side of the figure can be 24.55 μm. Therefore, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 can be formed to be 14.4 μm. That is, the size of the main spacer 10721 in the second direction D2 can be formed to be 14.4 μm, and the sub-spacer 10722' can be formed as two sub-spacers. Therefore, the number of sub-spacers included in the secondary spacer 10722' formed on the left side of the figure corresponding to the auxiliary spacer 1082 can be different from the number of sub-spacers included in the secondary spacer 10722' formed on the right side of the figure corresponding to the auxiliary spacer 1082. Specifically, the number of sub-spacers included in the secondary spacer 10722' formed on the left side of the figure corresponding to the auxiliary spacer 1082 can be greater than the number of sub-spacers included in the secondary spacer 10722' formed on the right side of the figure corresponding to the auxiliary spacer 1082. It should be understood that the specific values ​​shown are only examples, and those skilled in the art can appropriately configure various sizes and the number of sub-spacers according to specific process requirements.

[0091] Alternatively, a secondary spacer 10722' may be provided only on one side of the main spacer 10721 in the first direction D1, and the secondary spacer 10722' may be formed into a plurality of sub-spacers.

[0092] Alternatively, a secondary spacer 10722' can be provided on one side of the main spacer 10721 in the first direction D1. The secondary spacer 10722' can be formed into a plurality of sub-spacers, and a secondary spacer 10722' can be provided on the other side of the main spacer 10721 in the first direction D1. Figure 5A and Figure 6 The secondary septum shown is 10722.

[0093] According to embodiments of this disclosure, such as Figure 7 As shown, the width of the secondary spacer 10722' in the second direction D2 is substantially the same as the width of the main spacer 10721 in the second direction D2. Alternatively, the width of the secondary spacer 10722' in the second direction D2 may differ from the width of the main spacer 10721 in the second direction D2, and may be greater or less than the width of the main spacer 10721 in the second direction D2. It should be understood that those skilled in the art can appropriately configure various dimensions according to specific process requirements.

[0094] According to the embodiments of this disclosure, the first substrate spacer 107 is formed as a metal spacer including a metal spacer layer. Therefore, the metal spacer layer can be formed by using a high-performance exposure machine in a factory that manufactures array substrates through a metal exposure process, so as to achieve precise control of various morphologies of the spacer and improve the accuracy of the solution.

[0095] Figure 8 This is another top view of a display panel according to an embodiment of the present disclosure.

[0096] like Figure 8 As shown, with Figure 3 Compared to the embodiments shown, in Figure 8 In the embodiment shown, the first substrate spacers 107 (including first spacer 1071 and second spacer 1072) disposed in the same row are not aligned in the second direction D2.

[0097] Specifically, see Figure 8 In the same row, the first spacers 1071 corresponding to the main spacer 1081 may be aligned in the second direction D2, while at least one second spacer 1072 corresponding to the auxiliary spacer 1082 and other second spacers 1072 corresponding to the auxiliary spacer 1082 may not be aligned in the second direction D2, and at least one second spacer 1072 corresponding to the auxiliary spacer 1082 and the first spacer 1071 corresponding to the main spacer 1081 may not be aligned in the second direction D2. Figure 8 The diagram shows a main spacer 1081 located in the center, and auxiliary spacers 1082 located on either side of the main spacer 1081. It should be understood that the term "alignment" as used herein specifically refers to the center alignment of the components.

[0098] Although Figure 8 The diagram shows a second spacer 1072 corresponding to the auxiliary spacer 1082 and a first spacer 1071 corresponding to the main spacer 1081, which have different dimensions in the first direction D1. However, this disclosure is not limited thereto; the second spacer 1072 corresponding to the auxiliary spacer 1082 and the first spacer 1071 corresponding to the main spacer 1081 can have the same dimensions in the first direction D1. Although in Figure 8 The diagram shows a second spacer 1072 corresponding to the auxiliary spacer 1082, excluding the main spacer and the secondary spacer. However, this disclosure is not limited thereto; the second spacer 1072 corresponding to the auxiliary spacer 1072 may include, for example, Figure 5A and Figure 6 The main spacer 10721 and the secondary spacer 10722 shown, and / or as shown in the figure, are as follows: Figure 7 The main septum 10721 and the secondary septum 10722' are shown.

[0099] By setting the second spacer 1072 corresponding to the auxiliary spacer 1082 to be misaligned with the first spacer 1071 corresponding to the main spacer 1081 in the second direction D2 and including different offset directions, it can be ensured that at least part of the second spacer 1072 can be supported when the auxiliary spacer 1082 is offset in a certain direction. It can also reduce the total area of ​​the second spacer 1072 and increase the opening ratio.

[0100] According to embodiments of this disclosure, a display device is also provided, including a display panel according to various embodiments of this disclosure.

[0101] According to embodiments of the present disclosure, an electronic device is also provided, including a display device according to embodiments of the present disclosure, which includes a display panel according to various embodiments of the present disclosure.

[0102] Because a display panel according to an embodiment of this disclosure is used, when the display panel is not subjected to external pressure, there is a certain mutual compressive force between the protrusions formed by the main spacer and the corresponding first spacer. This improves the display panel's resistance to external forces and enhances its stability. When the display panel is subjected to external pressure, the main spacer is further compressed, causing the auxiliary spacer to contact the corresponding second spacer, thereby providing further support for the display panel. Since the first substrate spacer includes a metal spacer layer disposed on the upper part, the friction between the first substrate spacer and the corresponding second substrate spacer is increased. This ensures that the second substrate spacer is not easily slipped when the display panel is subjected to external pressure, thereby preventing the spacer from sliding into the opening area of ​​the thin-film transistor, scratching the alignment layer in the opening area, affecting liquid crystal alignment, and causing light leakage, resulting in PS Mura. Furthermore, since a high-performance exposure machine in a factory that manufactures array substrates can be used to form the metal spacer layer through a metal exposure process, precise control of various spacer morphologies can be achieved, improving the accuracy of the solution.

[0103] Figure 9 A flowchart illustrating a method for fabricating an array substrate according to an embodiment of the present disclosure is shown.

[0104] like Figure 9 As shown, the method for manufacturing an array substrate according to an embodiment of the present disclosure includes the following steps S11 to S13.

[0105] In step S11, a substrate is prepared.

[0106] In step S12, a stacked structure is fabricated on the substrate.

[0107] In step S13, a plurality of first substrate spacers are formed by stacking structures.

[0108] According to an embodiment of this disclosure, the array substrate includes a plurality of pixel opening regions and a spacer region located between adjacent pixel opening regions. The height of the stacked structure disposed in the spacer region is greater than the height of the stacked structure disposed in the pixel opening regions. A plurality of first substrate spacers are disposed in the spacer region. The formation of a plurality of first substrate spacers by the stacked structure (i.e., step S13) includes: forming a metal spacer layer on the upper part of the stacked structure in the spacer region to form a plurality of first substrate spacers by a metal exposure process.

[0109] According to the array substrate fabrication method of this disclosure, since a metal spacer layer is formed on the top of a stacked structure of multiple first substrate spacers to be formed in the spacer area by a metal exposure process, the friction between the first substrate spacers and the corresponding second substrate spacers is increased. This ensures that the second substrate spacers are not easily slipped when the display panel is subjected to external pressure, thereby preventing the spacers from sliding into the opening area of ​​the thin-film transistor, scratching the alignment layer in the opening area, affecting the liquid crystal alignment, and causing light leakage and PS Mura. In addition, since a high-performance exposure machine in the array substrate fabrication factory can be used to form the metal spacer layer by a metal exposure process, precise control of various spacer morphologies can be achieved, improving the accuracy of the solution.

[0110] Figure 10 A flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure is shown.

[0111] like Figure 10 As shown, the method for manufacturing a display panel according to an embodiment of the present disclosure includes the following steps S100 to S300.

[0112] In step S100, a first substrate is prepared.

[0113] In step S200, a second substrate is prepared.

[0114] In step S300, the first substrate and the second substrate are assembled to form a display panel.

[0115] The preparation of the first substrate (i.e., step S100) includes the following steps S110 to S130.

[0116] In step S110, a first substrate is prepared.

[0117] In step S120, a stacked structure is prepared on the first substrate.

[0118] In step S130, a plurality of first substrate spacers are formed by stacking structures.

[0119] The preparation of the second substrate (i.e., step S200) includes the following steps S210 to S230.

[0120] In step S210, a second substrate is prepared.

[0121] In step S220, a black matrix is ​​prepared on the second substrate.

[0122] In step S230, a plurality of second substrate spacers are prepared on the black matrix.

[0123] According to embodiments of this disclosure, a plurality of first substrate spacers correspond one-to-one with a plurality of second substrate spacers. The first substrate includes a plurality of pixel opening regions and a spacer region located between adjacent pixel opening regions. The height of the stacked structure disposed in the spacer region is greater than the height of the stacked structure disposed in the pixel opening region. The plurality of first substrate spacers are disposed in the spacer region, and the formation of the plurality of first substrate spacers by the stacked structure (i.e., step S130) includes: forming a metal spacer layer on the upper part of the stacked structure in the spacer region to form the plurality of first substrate spacers by a metal exposure process.

[0124] According to the display panel manufacturing method of this disclosure, during cell assembly, there is a certain mutual compressive force between the protrusions formed by the second substrate spacer and the corresponding first substrate spacer. This improves the display panel's resistance to external forces and enhances its stability. Since a metal spacer layer is formed on the top of the stacked structure of multiple first substrate spacers in the spacer area using a metal exposure process, the friction between the first substrate spacers and the corresponding second substrate spacers is increased. This ensures that the second substrate spacers are less prone to sliding when the display panel is subjected to external pressure, thereby preventing the spacers from sliding into the opening area of ​​the thin-film transistor, scratching the alignment layer in the opening area, affecting liquid crystal alignment, and causing light leakage and PS Mura. Furthermore, since a high-performance exposure machine in a factory that manufactures array substrates can be used to form the metal spacer layer through a metal exposure process, precise control of various spacer morphologies can be achieved, improving the accuracy of the solution.

[0125] For ease of description, spatial relative terms such as “below,” “above,” “to the left,” and “to the right” are used herein to describe the relationship between one element or feature shown in the accompanying drawings and another element(s). It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. For example, if the device in the figures were inverted, an element described as “below other elements or features” would therefore be oriented “above other elements or features.” Thus, the exemplary term “below” can cover both orientations of “below” and “above.” The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0126] For ease of description, ordinal numbers such as "first," "second," and "third" may be used in this document. These ordinal numbers are used only to distinguish one element or feature from another (some) elements or features, and not to restrict the order of these elements or features.

[0127] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the said feature, integral, step, operation, element, and / or component is specified, but the presence or addition of at least one other feature, integral, step, operation, element, component, and / or group thereof is not excluded.

[0128] Exemplary embodiments have been disclosed herein, and while specific terminology has been used, it is used and should be interpreted only in a general illustrative sense and is not intended to be limiting. In some embodiments, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. An array substrate, comprising: Substrate; A stacked structure disposed on the substrate; as well as Multiple first substrate spacers, The array substrate further includes multiple pixel opening regions and a spacing region between adjacent pixel opening regions. The height of the stacked structure disposed in the spacing region is greater than the height of the stacked structure disposed in the pixel opening region. The multiple first substrate spacers are disposed in the spacing region. The stacked structure of the spacing region includes an upper metal spacer layer at the location where the first substrate spacers are disposed. The multiple first substrate spacers include the portion of the stacked structure of the metal spacer layer in the orthogonal projection area on the substrate that is higher than the stacked structure in the pixel opening region.

2. The array substrate according to claim 1, wherein, The stacked structure includes a metal oxide layer, and the metal spacer layer is located directly on the metal oxide layer.

3. The array substrate according to claim 1, further comprising: Multiple data lines extending in the first direction; as well as Multiple grid lines extending in a second direction intersecting the first direction The orthographic projection of each of the plurality of first substrate spacers on the substrate at least partially overlaps with the orthographic projection of one of the plurality of data lines on the substrate.

4. The array substrate according to claim 3, wherein, The plurality of first substrate spacers include first spacers corresponding to the main spacers on the color filter substrate and second spacers corresponding to the auxiliary spacers on the color filter substrate.

5. The array substrate according to claim 4, wherein, The dimension of the second spacer in the first direction is smaller than the dimension of the first spacer in the first direction, or The dimension of the second spacer in the second direction is greater than the dimension of the first spacer in the second direction.

6. The array substrate according to claim 4, wherein, At least a portion of the second spacer has a smaller dimension in the first direction than the first spacer has in the first direction, and At least a portion of the second spacer has a dimension in the second direction that is larger than that of the first spacer in the second direction.

7. The array substrate according to claim 4, wherein, The second spacer includes a main spacer and secondary spacers disposed on both sides of the main spacer in the first direction. The orthographic projection of the sub-spacer onto the substrate at least partially overlaps with the orthographic projection of one of the plurality of grid lines onto the substrate.

8. The array substrate according to claim 7, wherein, The secondary septum includes a plurality of sub-septum disposed in the second direction.

9. The array substrate according to claim 7 or 8, wherein, The secondary spacer is located at a higher level than the main spacer in a direction perpendicular to the substrate.

10. The array substrate according to claim 4, wherein, The first spacers arranged in the same row in the second direction are aligned in the second direction. At least one second spacer and other second spacers arranged in the same row in the second direction are not aligned in the second direction.

11. A display panel, comprising: First substrate; as well as The second substrate is disposed opposite to the first substrate. The first substrate includes: First substrate; A stacked structure disposed on the first substrate facing the second substrate; and Multiple first substrate spacers, The second substrate includes: Second substrate; A black matrix disposed on the second substrate facing the first substrate; and Multiple second substrate spacers disposed on the black matrix The plurality of first substrate spacers correspond one-to-one with the plurality of second substrate spacers. The first substrate includes a plurality of pixel opening regions and a spacing region located between adjacent pixel opening regions. The height of the stacked structure disposed in the spacing region is greater than the height of the stacked structure disposed in the pixel opening region. The plurality of first substrate spacers are disposed in the spacing region. The stacked structure in the spacing region includes an upper metal spacer layer at the location where the first substrate spacers are disposed. The plurality of first substrate spacers include the portion of the stacked structure of the metal spacer layer in the orthogonal projection area on the substrate that is higher than the stacked structure located in the pixel opening region.

12. The display panel according to claim 11, wherein, The stacked structure includes a metal oxide layer, and the metal spacer layer is located directly on the metal oxide layer.

13. The display panel according to claim 12, wherein, The first substrate further includes a plurality of data lines extending in a first direction, and a plurality of gate lines extending in a second direction intersecting the first direction. The orthographic projection of each of the plurality of first substrate spacers on the first substrate at least partially overlaps with the orthographic projection of one of the plurality of data lines on the first substrate, and The orthographic projection of each of the plurality of first substrate spacers on the first substrate at least partially overlaps with the orthographic projection of the corresponding second substrate spacer of the plurality of second substrate spacers on the first substrate.

14. The display panel according to claim 13, wherein, The plurality of second substrate spacers include main spacers and auxiliary spacers, wherein the height of the main spacers in a third direction perpendicular to the first substrate is greater than the height of the auxiliary spacers in that third direction. The plurality of first substrate spacers include a first spacer corresponding to the main spacer and a second spacer corresponding to the auxiliary spacer.

15. The display panel according to claim 14, wherein, The dimension of the second spacer in the first direction is smaller than the dimension of the first spacer in the first direction, or The dimension of the second spacer in the second direction is greater than the dimension of the first spacer in the second direction.

16. The display panel according to claim 14, wherein, At least a portion of the second spacer has a smaller dimension in the first direction than the first spacer has in the first direction, and At least a portion of the second spacer has a dimension in the second direction that is larger than that of the first spacer in the second direction.

17. The display panel according to claim 14, wherein, The second spacer includes a main spacer and secondary spacers disposed on both sides of the main spacer in the first direction. The orthographic projection of the sub-spacer on the first substrate at least partially overlaps with the orthographic projection of one of the plurality of gate lines on the first substrate.

18. The display panel according to claim 17, wherein, The secondary septum includes a plurality of sub-septum disposed in the second direction.

19. The display panel according to claim 17 or 18, wherein, The secondary septum is positioned at a higher level than the main septum in the third direction.

20. The display panel according to claim 14, wherein, The first spacers arranged in the same row in the second direction are aligned in the second direction. At least one second spacer and other second spacers arranged in the same row in the second direction are not aligned in the second direction.

21. A display device comprising a display panel according to any one of claims 11 to 20.

22. An electronic device comprising the display device according to claim 21.

23. A method for fabricating an array substrate, comprising: Substrate preparation; A stacked structure is fabricated on the substrate; as well as Multiple first substrate spacers are formed through the stacked structure. The array substrate includes multiple pixel opening regions and a spacing region between adjacent pixel opening regions. The height of the stacked structure disposed in the spacing region is greater than the height of the stacked structure disposed in the pixel opening regions. The multiple first substrate spacers are disposed in the spacing regions. The formation of the multiple first substrate spacers by the stacked structure includes: forming a metal spacer layer on the upper part of the stacked structure in the spacing region to form the multiple first substrate spacers by a metal exposure process.

24. A method for manufacturing a display panel, comprising: Fabrication of the first substrate includes: Prepare the first substrate; A stacked structure is fabricated on the first substrate; and Multiple first substrate spacers are formed through the stacked structure. Fabrication of a second substrate includes: Fabrication of a second substrate; A black matrix is ​​fabricated on the second substrate; and Multiple second substrate spacers are fabricated on the black matrix. The first substrate and the second substrate are assembled to form the display panel, wherein the plurality of first substrate spacers correspond one-to-one with the plurality of second substrate spacers. The first substrate includes a plurality of pixel opening areas and a spacing area located between adjacent pixel opening areas. The height of the stacked structure disposed in the spacing area is greater than the height of the stacked structure disposed in the pixel opening area. The plurality of first substrate spacers are disposed in the spacing area, and forming the plurality of first substrate spacers by the stacked structure includes: forming a metal spacer layer on the upper part of the stacked structure in the spacing area to form the plurality of first substrate spacers by a metal exposure process.

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