Chip IP signal connection verification environment automatic generation method
Patent Information
- Application Number
- CN202511572169.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-30
- Publication Date
- 2026-02-03
Smart Images
Figure CN121455834A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of integrated circuit verification technology, in particular to a chip IP signal connection verification environment automatic generation method. BACKGROUND
[0002] With the increase of the number and complexity of chip IPs, the scale of the verification environment has increased explosively. The current mainstream verification environment needs to include four core components of stimulus generation, data collection, result comparison and error alarm. Each component needs to be deeply adapted to the IP interface protocol. However, the diversity of IP interface protocols leads to a reuse rate of less than 40% of the verification environment. More than 30% of the environment components need to be redeveloped for each new IP protocol. The verification environment code is large in size, and it is time-consuming and laborious to manually build the verification environment. The debugging time of the environment accounts for 35% of the verification cycle. The existing verification environment building method still has the following technical defects: (1) The manual building efficiency is extremely low. The existing technology relies on engineers to manually write verification environment codes based on templates. It takes tens of thousands of lines of code to build a verification environment. At the same time, more than 100 parameters need to be configured for each IP. The single IP environment configuration time is more than 2 hours, and it is also difficult to ensure that the parameter configuration error rate is reduced.
[0003] (2) Poor environment compatibility. The interface implementations of different IP suppliers are different. The existing verification environment needs to manually modify the protocol adaptation code. It takes several days to adapt to new IPs, and the environment compatibility only covers about 60% of the mainstream IP models.
[0004] (3) Low reuse of stimulus and verification components. Traditional stimulus generation components use hard coding. The signal format is designed for specific IPs. When the IP type is changed, the stimulus logic needs to be redeveloped, and the component reuse rate is low. The verification component needs to be manually written to compare the rules. It takes a long time to add a new verification scenario.
[0005] (4) The environment is disconnected from the modeling results. In the existing technology, the IP connection modeling results cannot be directly used for environment construction. Engineers need to manually extract modeling data and convert it into environment parameters. The data conversion time accounts for one-fifth of the environment building cycle, and the conversion error rate is high. SUMMARY
[0006] The purpose of the present application is to overcome the shortcomings of the prior art and provide a chip IP signal connection verification environment automatic generation method to realize full automation and efficient generation of the verification environment.
[0007] The purpose of the present application is achieved by the following technical solutions: A chip IP signal connection verification environment automatic generation method comprises: Step 1, model analysis and parameter extraction, obtain the existing data filtering, protocol identification, parameter standardization and conflict secondary check processing on structured model, output standardized parameter table; Step 2, construct verification template library according to verification component type, verification component type includes protocol adaptation, excitation generation, check component and environment framework, protocol adaptation class template library contains standard protocol adaptation code template, excitation generation class template library is divided into bus excitation template, timing excitation template and data excitation template according to signal type, check component class template library contains data consistency check template, timing compliance check template and protocol compliance check template, environment framework class template library includes environment framework code template constructed based on UVM 1.2 and VMM 2.0 standards; Step 3, based on standardized parameter table and template library, match template library by identifying protocol type and parameter characteristics, inject standardized parameters into identified template, and generate executable verification components according to template; Step 4, automatically instantiate generated components, configure component communication according to connection relationship, construct topology code for describing interface or module connection relationship, automatically configure UVM environment parameters, automatically modify protocol adaptation code due to differences between IP suppliers, and finally output executable verification environment; The executable verification environment includes component code, topology code, configuration file and data file; Step 5, automatically generate basic test cases or generate custom test cases, and perform local or distributed simulation by automatically assigning and scheduling test cases; Basic test cases include connection correctness test, protocol compliance test and data transmission test.
[0008] Further, the step 1 specifically includes: Obtain the constructed triple node directed graph model from the JSON-LD format model file, and the triple node directed graph model stores the connection relationship and weight data between IP nodes, signal nodes and constraint nodes by using Neo4j graph database; The user customizes the parameter type configuration filtering rule to be reserved, extracts the core parameters required by the verification environment according to the filtering rule, and eliminates redundant information; Extract the protocol type field of the signal node for protocol identification, and automatically match the standard attributes in the protocol library according to the protocol type; Uniform the heterogeneous parameters; For the low confidence conflicts in the model that have not been solved, perform timing compatibility check again; Construct a standardized parameter table using the extracted and processed parameters, and each entry of the standardized parameter table contains IP identification, protocol type, signal parameter, constraint parameter and connection relationship.
[0009] Further, the method for constructing the verification template library in step 2 is to directly obtain from an existing template library or to design and adapt a template according to the requirements of a self-developed IP, and the customized template is added to the template library after being audited.
[0010] Further, after the construction of the verification template library in step 2, the protocol update documents of mainstream IP manufacturers are dynamically and periodically crawled through a crawler technology, and the protocol template library is automatically updated; and the templates in the verification template library are subjected to version control by using Git, so as to realize version backtracking of the template library.
[0011] Further, the step 3 specifically comprises: The protocol adaptation template is matched according to the protocol type, then the subdivided template is matched according to the signal parameter, when there is no matching template, the basic template is automatically generated, and a template requirement work order is pushed to the development team; The standardized parameters are injected into the template through the Velocity template engine, the fixed static parameters are replaced with placeholders in the template, the timing constraint parameters are injected into the monitoring threshold definition position of the verification template, and the connection configuration parameters are injected into the connection configuration statement of the agent; The component code in multiple languages is generated, including SystemVerilog code, C code and simulation startup script component code.
[0012] Further, the generation of the customized test case specifically comprises that a user configures a test scene through a visual interface, and the system automatically generates test case code.
[0013] Further, the step 5 further comprises: The simulation log is automatically collected, the test result is analyzed, and a test report is generated, wherein the test report comprises error type, error position and timing violation detail information; The failed test case is iteratively optimized, the error reason is automatically located, and error repair suggestions are pushed.
[0014] The beneficial effects of the present application are: 1) Compared with the traditional manual construction method, the environmental construction efficiency of the present application is exponentially improved.
[0015] 2) The compatibility and reusability are significantly enhanced, 30 kinds of mainstream interface protocols are supported, 98% of IP models are covered, the traditional tool is only 60%, the time consumption of new IP adaptation is shortened from 3 days to 10 minutes, the adaptation efficiency is improved by 432 times; the parameterized template design greatly improves the component reuse rate, and the IP type needs to be replaced without redeveloping the component, only the parameter configuration needs to be modified; the generated environment supports mainstream simulation tools such as Synopsys VCS, Cadence Xcelium and Mentor Questa, and the tool adaptation success rate can reach 100%.
[0016] 3) Deeply cooperate with modeling results, realize end-to-end automatic conversion of modeling results to verification environment, reduce data conversion time consumption and conversion error rate; potential conflicts identified in the modeling stage can be directly used for verification environment check rule configuration, and achieve full coverage of conflict verification.
[0017] 4) Test coverage and error positioning ability are outstanding, compared with the coverage rate of the test case automatically generated by manual writing, the coverage rate is improved, and the scene test case customization is supported, which meets the personalized verification demand; the error positioning accuracy is also much higher than manual positioning, and the error repair time is greatly shortened from 24 hours to 2 hours, and the repair efficiency is improved by 12 times. BRIEF DESCRIPTION OF DRAWINGS
[0018] Fig. 1 A flowchart of a chip IP signal connection verification environment automatic generation method provided by the application is shown in the figure; Fig. 2 A structure diagram of the triple-node directed graph model. DETAILED DESCRIPTION
[0019] The technical solutions of the application will be described below in conjunction with the embodiments, obviously, the described embodiments are only part of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the application.
[0020] Reference Figs. 1-2 , the application provides a technical solution: A chip IP signal connection verification environment automatic generation method, as Fig. 1 shown, comprising the following steps 1-4: Step 1, model analysis and parameter extraction, obtaining the existing data filtering, protocol identification, parameter standardization and conflict secondary check processing of structured model, outputting the standardized parameter table; In this embodiment, the step 1 specifically comprises: Obtain the triple-node directed graph model constructed from the JSON-LD format model file, the triple-node directed graph model adopts Neo4j graph database to store the connection relationship and weight data between IP nodes, signal nodes and constraint nodes; the structure diagram of the triple-node directed graph model is shown in Fig. 2 .
[0021] The user customizes the parameter type configuration filtering rule to be reserved, extracts the core parameters required by the verification environment according to the filtering rule, and eliminates redundant information such as IP supplier address and non-verification related data; Extract the protocol type field of the signal node for protocol identification, and automatically match the standard attributes in the protocol library according to the protocol type, such as the “ADDR_WIDTH” and “DATA_WIDTH” attributes of AXI4-Lite; Unified format of heterogeneous parameters, for example: “bit width 32bit” and “width = 32” are unified into “WIDTH:32”; For low-confidence conflicts that are not resolved in the model, perform timing compatibility checks again, such as checking whether “setuptime = 1ns” and “clock period = 2ns” are compatible; Use the extracted and processed parameters to build a standardized parameter table, and each entry in the standardized parameter table contains five categories of information data: IP identification, protocol type, signal parameter, constraint parameter, and connection relationship. Standardized parameter representation, for example: Step 2, build a verification template library according to verification component types, including protocol adaptation, stimulus generation, verification components, and environment framework. The protocol adaptation template library contains standard protocol adaptation code templates, the stimulus generation template library is divided into bus stimulus templates, timing stimulus templates, and data stimulus templates, the verification component template library contains data consistency verification templates, timing compliance verification templates, and protocol compliance verification templates, and the environment framework template library includes environment framework code templates based on UVM 1.2 and VMM 2.0 standards; The above four template libraries can cover more than 95% of mainstream verification scenarios. The protocol adaptation template library contains adaptation code templates for 30 standard protocols such as AXI4 / AXI4-Lite / APB4 / PCIe5.0 / USB4.0, which are designed with parameters, such as parameter DATA_WIDTH = 32, supporting 1-1024 bit width dynamic configuration; The stimulus generation template library is divided into bus stimulus templates, timing stimulus templates, and data stimulus templates, supporting random stimulus, directional stimulus, and scenario-based stimulus such as DDR initialization scenario after CPU startup. The verification component template library supports multi-dimensional verification rule combination; The environment framework template library: environment framework templates based on UVM 1.2 and VMM 2.0 standards, containing basic code of tb_top, env, agent, driver, monitor, and scoreboard components, supporting component automatic instantiation and connection.
[0022] The method for building the verification template library in step 2 is to directly obtain from the existing template library or to customize the adaptation template according to the demand for self-developed IP. The customized template is reviewed and added to the template library after being approved.
[0023] Step 2 also includes: after the construction of the verification template library is completed, the protocol update documents of mainstream IP vendors are dynamically and regularly crawled through the crawler technology to automatically update the protocol template library; Git is used for version control of the templates in the verification template library to realize version backtracking of the template library.
[0024] Step 3, based on the standardized parameter table and the template library, the protocol type and parameter characteristics are matched with the template library, the standardized parameters are injected into the identified template, and the executable verification component is generated according to the template. Step 3 specifically includes: The protocol adaptation template is matched according to the protocol type, and then the signal parameter is matched with the subdivided template. When there is no matching template, the basic template is automatically generated, the basic template contains a configurable parameter interface, and the template demand work order is pushed to the development team; The standardized parameters are injected into the template through the Velocity template engine, the fixed static parameters are replaced with placeholders in the template, the timing constraint parameters are injected into the monitoring threshold definition position of the verification template, and the connection configuration parameters are injected into the connection configuration statement of the agent; The component code in multiple languages is generated, including SystemVerilog code, C code and simulation startup script component code.
[0025] Step 3 adopts a two-dimensional matching algorithm of protocol priority-parameter matching. First, the protocol type is identified for primary matching, and the protocol is matched with the corresponding adaptation template, such as UART protocol matching UART adaptation template. Further, the signal parameter is matched for secondary matching, and the signal parameter is matched with the corresponding appropriate bit data template, such as DATA_WIDTH=8 UART matching 8-bit data template and DATA_WIDTH=16 matching 16-bit data template.
[0026] In the generated component code in multiple languages, the SystemVerilog code is specifically the UVM component (driver, monitor, scoreboard) code, which conforms to IEEE 1800-2017 standard, the C code is specifically the generated excitation data file (such as DDR initialization data), which supports hex / bin format, and the TCL script is specifically the simulation startup script, such as vcs compilation script and verdi waveform loading script, which supports mainstream simulation tools of Synopsys, Cadence and Mentor.
[0027] Step 4, automatically instantiate the generated components, configure the communication between components according to the connection relationship, such as connecting the output of the DDRmonitor to the comparison port of the scoreboard; build topology code for describing the connection relationship of interfaces or modules, specifically generate the tb_top module, including DUT (design under test) interface connection, clock reset module instantiation, virtual interface (virtual interface) transmission; automatically configure UVM environment parameters, including simulation time, log level, waveform saving range; automatically modify the protocol adaptation code for the differences caused by different IP vendors, such as AXI burst length limitation, add burst length judgment logic in the driver; finally output the executable verification environment; the executable verification environment includes component code, topology code, configuration file and data file, specifically as follows: (1) Component code: all generated UVM component code (.sv file); (2) Topology code: tb_top.sv, interface file (.sv); (3) Configuration file: uvm_config_db configuration script, simulation script (.tcl); (4) Data file: stimulus data file (.hex), expected result file (.txt).
[0028] Step 5, automatically generate basic test cases or generate custom test cases, and perform local or distributed simulation by automatically assigning and scheduling test cases, that is, the system automatically assigns a batch of test cases to a single server to perform local simulation tasks or multiple servers to perform distributed simulation tasks; basic test cases include connection correctness test, protocol compliance test and data transmission test.
[0029] The custom test case generation specifically includes: users configure the test scenario through the visual interface, and the system automatically generates test case code.
[0030] Further, the step 5 further includes: automatically collect simulation logs, analyze test results, and generate test reports, including error type, error location, and timing violation detail information; Iterative optimization for failed test cases, automatically locate error causes, and push error repair suggestions.
[0031] Next, taking an implementable certain vehicle-grade MCU chip project as an example, the configured hardware environment is as follows: main server: Intel Xeon Platinum 8480+ processor (64 cores 128 threads), 256GB DDR5 memory, 4TB NVMe solid state disk; distributed nodes: 8 slave servers (configuration same as the main server), connected through InfiniBand HDR network (100Gbps) to support low-latency data transmission; storage device: 100TBNAS storage, used to store template library, generated environment code, simulation log, supporting 1GB read-write rate per second.
[0032] The project (40nm process) contains 120 IP modules, including CAN FD, Ethernet, SPI, I2C interfaces, etc., and after applying the method of the application: The verification environment construction time is shortened from 30 days to 2.5 hours, and the efficiency is improved by 288 times; 85 test cases are automatically generated, covering 92% of the connection verification scenarios, which is 70% higher than manual writing (50 use cases); 6 errors are captured in real time during the simulation process, including 3 signal direction conflicts, 2 timing constraint violations, and 1 protocol adaptation error, with an average error location time of 15 minutes, and all are repaired in the design stage; The verification period is shortened from the traditional 90 days to 45 days, and the project development cost is reduced by 40%.
[0033] The above experimental data show that, compared with the traditional manual building method, the environment construction efficiency of the method of the application is exponentially improved.
[0034] The above is only a preferred embodiment of the application, and it should be understood that the application is not limited to the form disclosed herein, and should not be considered as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein, by the above teaching or related art or knowledge. The modification and change made by the person skilled in the art without departing from the spirit and scope of the application shall be within the protection scope of the claims attached to the application.
Claims
1. A chip IP signal connection verification environment automatic generation method, characterized by, Comprise: Step 1, model analysis and parameter extraction, obtain the existing data filtering, protocol identification, parameter standardization and conflict secondary check processing on structured model, output standardized parameter table; Step 2, according to the type of verification component to build verification template library, verification component type includes protocol adaptation, excitation generation, check component and environment framework, protocol adaptation class template library contains standard protocol adaptation code template, excitation generation class template library is divided into bus excitation template, timing excitation template, data excitation template according to signal type, check component class template library contains data consistency check template, timing compliance check template, protocol compliance check template, environment framework class template library includes environment framework code template based on UVM1.2, VMM 2.0 standard construction; Step 3, based on the standardized parameter table and template library, by identifying the protocol type and parameter characteristics matching template library, the standardized parameters are injected into the identified template, and the executable verification component is generated according to the template; Step 4, automatically instantiate the generated component, configure the communication between components according to the connection relationship, build the topology code for describing the connection relationship of interface or module, automatically configure the UVM environment parameters, automatically modify the protocol adaptation code due to the difference between IP suppliers, and finally output the executable verification environment; The executable verification environment includes component code, topology code, configuration file and data file; Step 5, automatically generate basic test cases or generate custom test cases, and perform local or distributed simulation by automatically assigning and scheduling test cases; The basic test cases include connection correctness test, protocol compliance test and data transmission test.
2. The chip IP signal connection verification environment automatic generation method according to claim 1, characterized in that: The step 1 specifically comprises: Obtain the constructed triple node directed graph model from the JSON-LD format model file, and the triple node directed graph model uses Neo4j graph database to store the connection relationship and weight data between IP nodes, signal nodes and constraint nodes; The user customizes the parameter type configuration filtering rule to be reserved, extracts the core parameters required by the verification environment according to the filtering rule, and eliminates redundant information; The protocol type field of the signal node is extracted for protocol identification, and the standard attributes in the protocol library are automatically matched according to the protocol type; Uniform the heterogeneous parameters; For the low confidence conflicts in the model, perform timing compatibility check again; Use the extracted and processed parameters to build a standardized parameter table, and each entry of the standardized parameter table contains IP identification, protocol type, signal parameter, constraint parameter and connection relationship.
3. The method of claim 1, wherein the method further comprises: determining a plurality of IP signals of the IP core; and determining a plurality of IP signals of the chip. The method for building the verification template library in step 2 is to directly obtain from the existing template library or to customize the adaptation template according to the demand of self-developed IP, and the customized template is added to the template library after being audited.
4. The method of claim 1, wherein the method further comprises: generating a chip IP signal connection verification environment automatically. The step 2 further comprises: after the construction of the verification template library is completed, the protocol update document of mainstream IP manufacturers is dynamically and periodically grabbed through the crawler technology, and the protocol template library is automatically updated; Git is used for version control of the templates in the verification template library, so as to realize version backtracking of the template library.
5. The method of claim 1, wherein the method further comprises: determining a plurality of IP signals of the IP core; determining a plurality of IP signals of the chip; and determining a plurality of IP signals of the chip IP signal connection verification environment. The step 3 specifically comprises: Matching protocol adaptation templates by protocol type, and then matching subdivision templates by signal parameters, when no matching template is found, automatically generating a basic template, and pushing a template requirement work order to the development team; Injecting standardized parameters into templates through the Velocity template engine, replacing placeholders in templates with fixed static parameters, injecting time sequence constraint parameters into the monitoring threshold definition position of the verification template, and injecting connection configuration parameters into the connection configuration statements of the agent; Generating multilingual component codes, including SystemVerilog codes, C codes, and simulation startup script component codes.
6. The method of claim 1, wherein the method further comprises: generating a chip IP signal connection verification environment automatically. The generating custom test cases specifically comprises: a user configuring a test scene through a visual interface, and the system automatically generating test case codes.
7. The method of claim 1, wherein the method further comprises: generating a chip IP signal connection verification environment automatically. The step 5 further comprises: Automatically collecting simulation logs, analyzing test results, and generating a test report, wherein the test report comprises error types, error positions, and time sequence violation details; Iteratively optimizing failed test cases, automatically locating error causes, and pushing error repair suggestions.