Memory control method and storage device

Abstract

The application provides a memory control method and a storage device. The method is applied to a storage device including a memory module, and the memory module includes a plurality of blocks. When a garbage collection mechanism is triggered, at least one garbage collection source block is determined. Distribution information of valid data of the garbage collection source block is obtained. Based on the distribution information, at least one quantization parameter used to represent data distribution characteristics is calculated. Based on a preset decision model, a decision value is obtained according to the quantization parameter. According to the decision value and a preset baseline, a reading mode of this time of garbage collection is determined, and the reading mode includes a first mode and a second mode. Based on the determined reading mode, valid data in the garbage collection source block is read and written into a target block. By dynamically matching the data distribution characteristics and the optimal reading mode, the garbage collection efficiency is significantly improved, and the overall performance of the storage device is improved.

Description

Technical Field

[0001] This application relates to the field of memory control, and more particularly to a memory control method and a memory device. Background Technology

[0002] NAND Flash, as a non-volatile storage medium, is widely used in storage devices such as SD, eMMC, UFS, and SSD. Due to its physical characteristics of "erasure before write" and inability to be directly overwritten, data updates are written to a new physical address, while the data at the original address becomes invalid. This results in an interleaved distribution of valid and invalid data in the storage space, thus requiring a garbage collection process to reclaim storage blocks containing invalid data to obtain contiguous free space.

[0003] In conventional garbage collection schemes, the garbage collection mechanism is often triggered by the data writing process, and it consistently uses the multi-plane reading pattern employed during data writing to move valid data. This fixed-pattern scheme is simple to design, but it lacks consideration for the distribution of valid data within the garbage collection source block.

[0004] Therefore, how to provide a garbage collection reading method that can adapt to the characteristics of data distribution in order to optimize performance is an urgent problem to be solved in this field. Summary of the Invention

[0005] In view of this, this application provides a memory control method and a storage device to solve or partially solve the above problems.

[0006] In a first aspect, this application provides a memory control method applied to a storage device including a memory module. The memory module includes multiple planes, each plane including multiple blocks, and each block including multiple physical pages. The method includes: in response to triggering a garbage collection mechanism, determining at least one garbage collection source block; acquiring distribution information of valid data in the garbage collection source block; calculating at least one quantization parameter to characterize the data distribution features based on the distribution information; obtaining a decision value based on a preset decision model and the quantization parameter; determining the read mode for this garbage collection based on the decision value and a preset baseline, wherein the read mode includes a first mode suitable for continuous data reading (also referred to as QRW_mode) and a second mode suitable for discrete data reading (also referred to as QR4K_mode); and reading valid data in the garbage collection source block based on the determined read mode and writing the valid data to a target block.

[0007] A second aspect of this application provides a storage device, comprising: a connection interface for electrically connecting to a host system; a memory module including a plurality of planes, each plane including a plurality of blocks, each block including a plurality of physical pages; and a memory controller including error checking and correction circuitry, a buffer memory, and memory control circuitry, electrically connected to the connection interface and the memory module; wherein the memory controller is configured to perform the memory control method as described in the first aspect.

[0008] This application provides a memory control method and a storage device. The method is applied to a storage device including a memory module. The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple physical pages. When a garbage collection mechanism is triggered, at least one garbage collection source block is identified; the distribution information of valid data in the garbage collection source block is obtained; based on the distribution information, at least one quantization parameter is calculated to characterize the data distribution features; based on a preset decision model, a decision value is obtained according to the quantization parameter; based on the decision value and a preset baseline, the read mode for this garbage collection is determined, including a first mode and a second mode; based on the determined read mode, valid data in the garbage collection source block is read and written to the target block. By dynamically matching data distribution features with the optimal read mode, garbage collection efficiency is significantly improved, performance jitter of the storage device is reduced, and the overall performance of the storage device and user experience are enhanced. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, and these are all within the protection scope of this application.

[0010] Figure 1 A structural block diagram of an exemplary memory storage system according to an embodiment of this application is shown.

[0011] Figure 2 A structural block diagram of an exemplary memory controller according to an embodiment of this application is shown.

[0012] Figure 3 A structural block diagram of an exemplary management memory module according to an embodiment of this application is shown.

[0013] Figure 4 A schematic diagram of an exemplary memory controller according to an embodiment of this application is shown.

[0014] Figure 5 A flowchart of an exemplary memory control method according to an embodiment of this application is shown. Detailed Implementation

[0015] The technical solution of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] It should be particularly noted that similar substitutions and modifications made to this application are obvious to those skilled in the art, and they are all considered to be included in this application. Those skilled in the art can obviously make modifications or appropriate alterations and combinations to the methods and applications described herein without departing from the content, spirit, and scope of this application to implement and apply the technology of this application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0017] Figure 1 A schematic diagram of an exemplary memory storage system 100 according to an embodiment of this application is shown.

[0018] like Figure 1 As shown, the memory storage system 100 includes a host system 102 and a storage device 104. The host system 102 can be any type of computer system, such as a laptop computer, desktop computer, smartphone, tablet computer, industrial computer, etc. The storage device 104 is used to store data from the host system 102. The storage device 104 may include a solid-state drive, a USB flash drive, or other types of non-volatile storage devices. The host system 102 can be electrically connected to the storage device 104 via a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCI Express) interface, a Universal Serial Bus (USB) interface, or other types of connection interfaces. Therefore, the host system 102 can store data to and / or read data from the storage device 104.

[0019] Storage device 104 may include a connection interface 1041, a memory module 1042, and a memory controller 1043. The connection interface 1041 is used to connect storage device 104 to host system 102. Storage device 104 can communicate with host system 102 via connection interface 1041.

[0020] Memory module 1042 is used to store data. Memory module 1042 may include a non-volatile memory module. Memory module 1042 includes an array of memory cells. The memory cells in memory module 1042 store data in the form of voltage. In some embodiments, memory module 1042 may be a NAND flash memory module (NAND Flash).

[0021] Memory controller 1043 is connected to connection interface 1041 and memory module 1042. Memory controller 1043 can be used to control storage device 104; for example, memory controller 1043 can control connection interface 1041 and memory module 1042 for data access and data management. For example, memory controller 1043 may include a central processing unit (CPU), graphics processing unit (GPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices.

[0022] In some embodiments, the memory controller 1043 is also referred to as a flash memory controller or flash memory module. The memory module 1042 may receive a sequence of instructions from the memory controller 1043 and read data stored in the memory cells according to the sequence of instructions.

[0023] Figure 2 A schematic diagram of an exemplary memory controller 1043 according to an embodiment of this application is shown.

[0024] Please refer to Figure 1 and Figure 2 The memory controller 1043 includes a host system interface 12, a memory interface 16, and a memory control circuit 14. The host system interface 12 is used to connect to the host system 102 via a connection interface 1041 for communication with the host system 102. The memory interface 16 is used to connect to the memory module 1042 for access to the memory module 1042.

[0025] Memory control circuitry 14 is connected to host system interface 12 and memory interface 16. Memory control circuitry 14 can be used to control or manage the overall or partial operation of memory controller 1043. For example, memory control circuitry 14 can communicate with host system 102 via host system interface 12 and access memory module 1042 via memory interface 16. For example, memory control circuitry 14 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 14 is equivalent to the description of memory controller 1043.

[0026] In some embodiments, the memory controller 1043 may further include a buffer memory 20. The buffer memory 20 is connected to the memory control circuitry 14 and is used to cache data. For example, the buffer memory 20 may be used to cache instructions from the host system 102, data from the host system 102, and / or data from the memory module 1042. In particular, the logical-to-physical mapping table and its higher-level address management unit are typically resident or cached in the buffer memory 20 to support high-speed access and updates.

[0027] In some embodiments, the memory controller 1043 may further include an error checking and correction circuit 22. The error checking and correction circuit 22 is connected to the memory control circuit 14 and is used to encode and decode data to ensure data integrity. For example, the error checking and correction circuit 22 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In some embodiments, the memory controller 1043 may also include other types of circuit modules (e.g., power management circuits), which are not limited in this application.

[0028] In some embodiments, the memory controller 1043 may further include a power management circuit 18. The power management circuit 18 is connected to the memory control circuit 14 and is used to control the power supply to the storage device 104.

[0029] Figure 3 A schematic diagram of an exemplary memory management module according to an embodiment of this application is shown.

[0030] Please refer to Figures 1 to 3 The memory module 1042 includes multiple physical units 301(1)-301(B). Each physical unit includes multiple storage units for non-volatile data storage.

[0031] In some embodiments, an entity unit may include an entity programming unit. In some embodiments, an entity programming unit is also referred to as an entity programming unit. In some embodiments, an entity programming unit may be considered as an entity page.

[0032] In some embodiments, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and this application does not impose any limitations. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and this application is not limited to this.

[0033] In some embodiments, a physical programming unit is the smallest unit of synchronously written data in the memory module 1042. For example, when performing a programming operation (also known as a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0034] In some embodiments, an entity erasure unit may comprise multiple entity programmatic units. In some embodiments, an entity erasure unit may be considered as an entity block (or simply a block).

[0035] In some embodiments, multiple programmed units in a physical erase unit can be erased simultaneously. For example, when an erase operation is performed on a physical erase unit, an erase voltage can be applied to multiple programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0036] In some embodiments, the memory controller 1043 may logically associate entity units 301(0)-301(A) and 301(A+1)-301(B) with data area 31 and idle area 32, respectively. Entity units 301(0)-301(A) in data area 31 all store data (also referred to as user data) from host system 102. For example, any entity unit in data area 31 may store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in idle area 32 do not store any data (e.g., valid data).

[0037] In some embodiments, if a unit does not store valid data, it may be associated with the free zone 32. Furthermore, units in the free zone 32 may be erased to clear the data within them. In some embodiments, units in the free zone 32 are also referred to as idle units. In some embodiments, the free zone 32 is also referred to as the free pool.

[0038] In some embodiments, when data needs to be stored, the memory control circuit 14 may select one or more physical units from the idle area 32 and instruct the memory module 1042 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used cyclically between the data area 31 and the idle area 32.

[0039] In some embodiments, the memory control circuit 14 may configure multiple logic units 302(0)-302(C) to map physical units (i.e., physical units 301(0)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0040] In some embodiments, if a physical unit is currently mapped by any logical unit, the memory control circuit 14 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 14 can determine that this physical unit does not currently store any valid data.

[0041] In some embodiments, the memory control circuit 14 may record the mapping relationship between logical units and physical units in at least one management table (also known as a logic-to-physical mapping table, or L2P table). In some embodiments, the memory control circuit 14 may instruct the memory module 1042 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logical address to physical address mapping table).

[0042] Non-volatile memory modules, such as NAND Flash, are widely used in storage devices such as SD (Secure Digital), eMMC (embedded MultiMediaCard), UFS (Universal Flash Storage), and SSD (Solid State Drive) 104.

[0043] NAND Flash has the physical characteristic of "erasure before write" and cannot be directly overwritten. When data is updated, new data is written to a new physical address, while the old data at the original address is marked as invalid. This results in a mixed distribution of valid and invalid data in the NAND Flash storage space. Therefore, a garbage collection process is needed to reclaim storage blocks containing invalid data in order to obtain available contiguous free space.

[0044] In conventional garbage collection schemes, the garbage collection mechanism is often triggered by the data write process and consistently uses the multi-plane read mode employed during data writing to move valid data. Taking QRW_mode (Queued Read / Write_mode, a multi-plane read mode for continuous data reading) as an example, QRW_mode assumes that valid data in a block is continuously distributed, and during garbage collection, it moves valid data in the order of physical pages. This fixed-mode scheme is simple to design, but it lacks consideration for the distribution of valid data in the garbage collection source block. In practical applications, the distribution of valid data may be highly discrete. Continuing to use QRW_mode, designed for continuous data, in such scenarios will lead to a significant decrease in read efficiency, a prolonged garbage collection time, and ultimately cause performance fluctuations and overall performance degradation in storage devices (such as UFS).

[0045] Besides QRW_mode, there is also QR4k_mode (a 4K read mode). QRW_mode is suitable for reading continuous data, while QR4k_mode is more efficient when reading discrete data. However, existing technologies lack an intelligent, quantitative mechanism to assess the "continuity and discreteness" of data distribution in real time and dynamically select the most suitable read mode for garbage collection operations accordingly. Therefore, how to provide a garbage collection read method that can adapt to data distribution characteristics to optimize performance is an urgent problem to be solved in this field.

[0046] To address at least the aforementioned problems, this application provides a memory control method and a storage device. The method is applied to a storage device including a memory module. The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple physical pages. When a garbage collection mechanism is triggered, at least one garbage collection source block is identified; distribution information of valid data in the garbage collection source block is obtained; based on the distribution information, at least one quantization parameter is calculated to characterize the data distribution features; based on a preset decision model, a decision value is obtained according to the quantization parameter; based on the decision value and a preset baseline, a read mode for this garbage collection is determined, including a first mode and a second mode; valid data in the garbage collection source block is read based on the determined read mode, and the valid data is written to the target block.

[0047] In one embodiment, Figure 4 A schematic diagram of an exemplary memory controller 1043 according to an embodiment of this application is shown.

[0048] like Figure 4 As shown, when the garbage collection mechanism is triggered, the memory controller 1043 can identify at least one garbage collection source block 402, which is the physical block selected to perform garbage collection, in which the valid data inside will be moved, and then erased and reclaimed.

[0049] At the start of garbage collection, the memory controller 1043 can read the distribution information (such as an L2P table or valid bitmap) of valid data from the garbage collection source block 402 and obtain global parameters such as the current load, wear status, and available space of the storage device 104. Based on the distribution information of valid data, the memory controller 1043 (or the memory control circuit 14, which will be described as an example below) can perform parameter calculation and feature extraction. The memory controller 1043 can calculate at least one quantization parameter to characterize the data distribution features based on the distribution information of valid data.

[0050] See Figure 5 , Figure 5A flowchart of a memory control method 500 provided in an embodiment of a patent application is shown. Method 500 can be applied to systems containing memory modules (…). Figure 2 The storage device of the memory module 1042 shown (shown) Figure 2 The storage device 104 shown includes a memory module comprising multiple planes, each plane comprising blocks, each block comprising multiple physical pages, and memory control circuitry 14 is configured to perform this method. Method 500 may include the following steps.

[0051] In step 502, in response to triggering the Garbage Collection (GC) mechanism, at least one garbage collection source block is identified. The triggering condition may be an insufficient number of free blocks or a periodic background maintenance task.

[0052] In step 504, the distribution information of valid data in the garbage collection source block is obtained. This information is usually obtained from the Logical to Physical Address Mapping Table (L2P table) and combined with the valid bitmap maintained for the garbage collection source block to comprehensively determine whether each physical page stores valid data.

[0053] In step 506, based on the distribution information, at least one quantization parameter is calculated to characterize the data distribution features. These parameters convert the continuity and discreteness of the data distribution into computable numerical values.

[0054] In step 508, a decision value is obtained based on a preset decision model and quantification parameters. This decision model is used to evaluate the expected benefits of using different reading modes.

[0055] In step 510, based on the decision value and the preset baseline, the read mode for this garbage collection is determined. The read mode includes a first mode and a second mode. The first mode can be a multi-plane read mode suitable for continuous data reading (e.g., Queued Read / Write_mode, QRW_mode), and the second mode can be a cell read mode suitable for discrete data reading (e.g., 4K read mode, QR4K_mode).

[0056] In step 512, valid data in the garbage collection source block is read based on the determined read mode and written to the target block.

[0057] The above solution enables a shift from a fixed model to a dynamic selection, thus solving the problem of waste recycling efficiency dynamically changing with data distribution.

[0058] In one embodiment, a specific definition of the aforementioned quantization parameters is provided. Specifically, the quantization parameters include a first counting parameter (C_vpage), a second counting parameter (C_vplane), and a third counting parameter (C_ivpage). The first counting parameter represents the number of page units that contain valid data across multiple planes at the same page address during this garbage collection. The second counting parameter represents the total number of physical planes containing valid data during this garbage collection. The third counting parameter represents the number of consecutive page address intervals that are invalid across all planes during this garbage collection. These three parameters accurately characterize the distribution of valid data in the physical space of the memory module 1042 (garbage collection source block 402) from different dimensions.

[0059] Specifically, the counting rule for the first counting parameter is: as long as there is at least one valid data across all planes at the same page address, that page address is counted as one unit. More precisely, if there is valid data at the same page address across N planes, C_vpage is incremented by only 1, not N. This parameter reflects the degree of "column alignment" of valid data across multiple plane dimensions; a smaller value indicates better alignment and higher data continuity.

[0060] Specifically, the counting rule for the second counting parameter is as follows: for each distinct plane containing valid data, the second counting parameter increments. This parameter reflects the "breadth of distribution" of the data along the plane dimension; the smaller the value, the more concentrated the valid data is in a few planes.

[0061] Specifically, the counting rule for the third counting parameter is as follows: After continuously scanning page addresses, whenever a page address interval (containing one or more consecutive page addresses) is encountered such that all corresponding pages at every page address within that interval are invalid, it is counted as an invalid interval, and C_ivpage is incremented by 1. This parameter directly quantifies the degree of gaps or fragmentation in the data; a larger value indicates more discrete the data.

[0062] By introducing these three parameters with clear physical meaning, this embodiment transforms the fuzzy data distribution characteristics into numerical values ​​that can be accurately calculated and compared, providing a basis for subsequent decision-making.

[0063] In one embodiment, a memory control circuit 14 is also proposed to obtain a decision value based on a preset decision model and quantification parameters, including: the decision model is a proportional calculation model and the decision value is a proportional value R;

[0064] Specifically, the memory control circuit 14 calculates the proportion value R based on the first counting parameter, the second counting parameter, the third counting parameter, and their respective weighting coefficients. For example, the decision value R can be calculated using the following formula:

[0065]

[0066] in, , , These are configurable weighting coefficients, whose values ​​can be set based on experimental data or experience, for example, W1=0.5, W2=0.3, W3=0.2, used to adjust the influence of each parameter on the decision. A small constant (e.g., 0.001) is used to prevent division by zero errors in the denominator. The model uses parameters reflecting the data's continuity potential (e.g., the first and second counting parameters) as the numerator and parameters reflecting the data's discreteness (the third counting parameter) as the denominator, comprehensively evaluating them using a proportional value R. The model is simple, computationally inexpensive, and can quickly determine the continuity tendency of the data distribution, making it suitable for scenarios with high real-time decision-making requirements.

[0067] In one embodiment, a memory control circuit 14 is also proposed to obtain a decision value based on a preset decision model and quantification parameters, including: the decision model is a multi-feature weighted scoring model, and the decision value corresponding to this model is a comprehensive score. The memory control circuit 14 calculates this comprehensive score based on the weighted sum of multiple feature parameters.

[0068]

[0069] in, , , These are configurable weighting coefficients, which can be obtained through training or preset according to storage device preferences, used to adjust the influence of each parameter on the decision. The overall score is then compared to a threshold to select a mode.

[0070] Specifically, the feature parameters include the following: a first feature parameter F1 characterizing the alignment and clustering degree of effective data across multiple planes, a second feature parameter F2 characterizing the data void rate, and a third feature parameter F3 characterizing the cost-effectiveness ratio of mode switching.

[0071] In detail, F1 is calculated based on the first and second counting parameters, for example, F1 = first counting parameter / second counting parameter, used to measure the average number of aligned page addresses spanned by each valid data plane. F2 is calculated based on the third counting parameter and the total number of pages in the garbage collection source block. For example, F2 = third counting parameter / total number of pages, representing the proportion of invalid intervals to the total page address space. F3 is calculated based on the estimated total time required to complete this garbage collection using both the first and second modes, as well as the mode switching overhead. For example,

[0072] F3 = (Estimated_Time_QRW - Estimated_Time_QR4K) / T_switch, representing the cost-effectiveness ratio of mode switching. Estimated_Time_QRW represents the estimated time required to complete waste collection using the first mode, Estimated_Time_QR4K represents the estimated time required to complete waste collection using the second mode, and T_switch represents the time required to switch between the two modes.

[0073] The above embodiments extract features from multiple dimensions (alignment, void ratio, time cost-effectiveness) for a more refined comprehensive evaluation. This allows for more comprehensive consideration of decision-making factors, enabling better choices in more complex scenarios. Especially when data distribution characteristics are not obvious, cross-validation through multi-dimensional information can improve the accuracy of decision-making.

[0074] In a further preferred embodiment, the aforementioned feature parameters may further include a fourth feature parameter F4 for quantizing the data continuity of the chip select signal (ChipEnable, CE) to support optimization in multi-die parallel scenarios. The overall score is as follows:

[0075]

[0076] in, , , These are configurable weighting coefficients used to adjust the influence of each parameter on the decision.

[0077] In one embodiment, the memory control circuit 14 determines the read mode for the current garbage collection based on the decision value and a preset baseline. This includes: the memory control circuit 14 determines the read mode for the current garbage collection to be a first mode in response to a decision value greater than the preset baseline; and determines the read mode for the current garbage collection to be a second mode in response to a decision value less than or equal to the preset baseline. For example, when using the aforementioned ratio value R, a preset threshold A_mode is used. If R > A_mode, it indicates that the data is more discrete, so the second mode, which is more suitable for discrete reading, is selected; otherwise, the first mode is selected. This comparison step realizes the conversion from continuous quantities (decision values) to discrete selection (mode instructions), with clear rules, suitable for implementation in embedded firmware, ensuring the stability and predictability of the decision.

[0078] For example, assume the total number of pages in the garbage collection source block is Total_Pages=1024, and the number of planes is 6. By scanning the valid bitmap, we obtain C_vpage=120 (indicating that there is valid data on 120 pages), C_vplane=5 (indicating that valid data is distributed across 5 different planes), and C_ivpage=15 (indicating that there are 15 consecutive invalid intervals). The weighting coefficients can be preset to W1=0.5, W2=0.3, and W3=0.2. =0.001, then the proportion R is calculated as follows:

[0079] R=(120*0.5+5*0.3) / (15*0.2+0.001) ≈20.1

[0080] If the preset baseline A_mode=10, then R>A_mode, so the second mode is selected for reading.

[0081] In one embodiment, a method for determining the reading mode for this garbage collection based on a decision value and a preset baseline is also proposed, including: acquiring the real-time status of the storage device 104 and dynamically adjusting the preset baseline according to the real-time status to obtain a dynamic variable; and determining the reading mode based on the decision value and the dynamic variable. The dynamic baseline can be calculated in the following way:

[0082]

[0083] The real-time status includes a wear factor F_wear related to the average number of erases of the memory module 1042, a capacity factor F_capacity related to the proportion of available space, and a quality of service factor F_Qos related to the command queue depth of the host system 102.

[0084] Specifically, for F_wear, its value decreases as wear increases, causing storage device 104 to tend to choose the more stable and reliable second mode later in the lifespan of memory module 1042. For F_capacity, its value increases as the number of free blocks in memory module 1042 decreases, causing storage device 104 to tend to choose the high-speed first mode when the number of free blocks in memory module 1042 is scarce, in order to quickly complete garbage collection and free up available space. For F_Qos, its value increases as queue depth increases, causing storage device 104 to prioritize the first mode when the host system 102 is under high load, in order to reduce the impact of garbage collection operations on the latency of foreground user I / O requests.

[0085] In one embodiment, the wear factor F_wear can be dynamically adjusted according to the average number of erase cycles (PECcycle) of the memory module 1042. For example, if the average PE < 1000, F_wear = 1.0; if 1000 ≤ PE < 3000, F_wear = 0.6; if PE ≥ 3000, F_wear = 0.4. The capacity factor F_capacity can be set according to the current available space ratio (i.e., the ratio of the number of free blocks to the total number of blocks). For example, if Free Ratio > 20%, F_capacity = 1.0; if 10% < Free Ratio ≤ 20%, F_capacity = 1.2; if Free Ratio ≤ 10%, F_capacity = 1.5.

[0086] The above embodiments enable read mode decisions to not only rely on static data characteristics, but also adapt to the global state of storage device 104, achieving a dynamic balance between performance, reliability, durability and quality of service, and improving the overall performance of storage device 104.

[0087] In one embodiment, before the memory control circuit 14 obtains a decision value based on a preset decision model and quantification parameters, it further includes: the memory control circuit 14 determining the category of at least one garbage collection source block based on the distribution information of valid data. This category includes a first category that is clearly suitable for a first mode, a second category that is clearly suitable for a second mode, and a third category whose mode is yet to be determined. The determination of the reading mode based on the decision value and a preset baseline is performed on garbage collection source blocks belonging to the third category. This embodiment introduces a pre-classification mechanism to pre-sort source blocks with extremely obvious characteristics and simple decision-making. This avoids performing complete and potentially complex decision calculations on all source blocks, thereby reducing the average decision-making overhead of the garbage collection process and improving processing efficiency.

[0088] In one embodiment, a memory control circuit 14 is also proposed to determine the category of at least one garbage collection source block based on the distribution information of valid data, including: after determining the garbage collection source block and before performing data transfer, quickly screening the determined at least one garbage collection source block based on quantization parameters or lightweight features extracted from the distribution information through pre-configured judgment rules or simple models to determine the category of at least one garbage collection source block; during the execution phase of the garbage collection mechanism, directly using a predetermined reading mode for garbage collection source blocks of the first and second categories; and for garbage collection source blocks of the third category, determining the reading mode for this garbage collection based on the decision value and a preset baseline.

[0089] For example, a lightweight rule could be: if the third counting parameter is 0, it is directly classified into the first category and the first mode is used; the lightweight feature is, for example, the third counting parameter itself, or the proportion of valid data pages to the total number of pages. If the third counting parameter is extremely large (e.g., exceeding half of the total number of pages), it is directly classified into the second category and the second mode is used; the rest are classified into the third category. This embodiment clearly defines the division of labor between rapid screening and fine-grained decision-making, maximizing decision-making efficiency while ensuring decision accuracy, and is particularly suitable for scenarios that require batch processing of multiple garbage collection source blocks.

[0090] In one embodiment, a memory control circuit 14 is also proposed to determine the read mode for this garbage collection based on the current load state of the storage device 104. The storage device 104 may include multiple load states, such as a high-performance mode, a low-power mode, and an emergency collection mode. Under different load states, the memory control circuit 14 can adjust the bias of its decision-making strategy, aligning the garbage collection strategy with the operational goals of the storage device 104. For example, it may more aggressively optimize the garbage collection speed when high performance is required, and focus more on energy efficiency when powered by battery.

[0091] In one embodiment, the memory control circuit 14 is also proposed to lower the preset baseline or adjust the weights used to calculate the decision value in response to the current load state being a first state or a second state; and to raise the preset baseline in response to the current load state being a third state. The first state is an emergency garbage collection state, the second state is a high-performance state, and the third state is an idle / background state.

[0092] Specifically, in emergency garbage collection or high-performance states, the preset baseline can be set to a low fixed value (e.g., 0), forcing the use of the second mode to release space as quickly as possible. In high-performance states, the weight of W3 in the proportional calculation model can be appropriately reduced, making the decision more inclined to choose the first mode. In idle or background states, the preset baseline can be increased (e.g., multiplied by a coefficient greater than 1, such as 1.5), making the decision more inclined to the first mode, reducing the frequency of mode switching, and reducing the additional power consumption and potential instability risks caused by frequent switching. In addition, in specific states such as low power consumption, energy efficiency can also be optimized by adjusting the weight coefficients in the decision model. For example, in low power consumption states, the weight of parameter W3 reflecting data dispersion in the proportional calculation model can be provided, making the decision more inclined to choose the more energy-efficient read mode (e.g., the second mode), thereby reducing overall power consumption. Thus, dynamic optimization of the strategy is achieved, enabling the same decision mechanism to achieve optimal effectiveness under different storage device 104 objectives.

[0093] In one embodiment, a memory control circuit 14 is proposed to obtain a decision value based on a preset decision model and quantified parameters. This includes: the decision model being a cost calculation model, which estimates the total time required to complete the current waste collection using both the first and second modes based on distribution information; and calculating the decision value representing the relative time advantage of the first mode based on the estimated total time. The memory control circuit 14 bypasses intermediate feature extraction and scoring, directly constructing mathematical models of the time consumption of the two modes, and makes a decision by comparing the estimated times. This makes the decision objective and direct (pursuing the shortest time), theoretically leading to a locally optimal solution, and is particularly suitable for application scenarios extremely sensitive to waste collection time.

[0094] In one embodiment, the memory control circuit 14 is also proposed to estimate the total time required to complete the current garbage collection using the first mode and the second mode, respectively, including: obtaining the average time cost of a read operation for performing a garbage collection in the first mode and the second mode, and the number of read operations required to perform the current garbage collection if the first mode and the second mode are used; and calculating the total time of the first mode and the total time of the second mode based on the average time cost and the number of read operations.

[0095] Specifically, total time (first mode) = T_mode1 * N_mode1;

[0096] Total time (second mode) = T_mode2 * N_mode2 + T_switch; where T_mode1 represents the average time cost of executing the first mode once; N_mode1 represents the number of read operations required in this garbage collection if the first mode is used; T_mode2 represents the average time cost of executing the second mode once; N_mode2 represents the number of read operations required in this garbage collection if the second mode is used; and T_switch represents the time required to switch between the two modes.

[0097] N_mode1 and N_mode2 can be accurately calculated using the L2P mapping table or valid bitmap of the prefetched source block. The valid bitmap is a data structure used to quickly identify whether a physical page contains valid data. During decision-making, the total time prediction values ​​of the two modes are directly compared, and the shorter-time solution is selected, thus shifting from heuristic judgment to accurate prediction. This clarifies the implementation of the cost model, making time estimation not just a concept but computable, enhancing the feasibility of the solution.

[0098] For example, =50μs, =20μs, =10μs. Based on the effective bitmap analysis, if the first mode is used, the required reading is... =30 times, requiring reading in the second mode. =80 times. Then the total time (first mode) = 50 * 30 = 1500 μs, and the total time (second mode) = 20 * 80 + 10 = 1610 μs. Therefore, the first mode should be selected to minimize the total time.

[0099] In one embodiment, the memory control circuit 14 further determines the read mode for this garbage collection based on the total time, including: in response to the total time of the first mode being less than the total time of the second mode, determining the read mode for this garbage collection as the first mode. By comparing the two total times calculated from the first mode and the second mode, the mode with the shorter time consumption is selected. This simple comparison rule ensures the optimality of the decision result in terms of time cost.

[0100] In one embodiment, the storage device 104 is also proposed to consist of multiple dies, and the method further includes: in response to the garbage collection source blocks being distributed across different dies, executing read mode decisions for each garbage collection source block in parallel. Utilizing the multi-die parallel architecture of the storage device 104, independent decision-making processes are initiated simultaneously for multiple source blocks. This reduces the overall decision latency of multi-block garbage collection tasks, preparing for subsequent parallel data migration.

[0101] In one embodiment, the memory control circuit 14 is also proposed to execute the read mode decision for each garbage collection source block in parallel, including: generating an initial mode suggestion for each garbage collection source block; in response to consistency in the mode suggestions of the garbage collection source blocks, concurrently reading each garbage collection source block using the read mode corresponding to the mode suggestion; and in response to inconsistency in the mode suggestions of the garbage collection source blocks, determining a cooperative scheme. This embodiment illustrates the transition from independent decision-making to cooperative execution. When the suggestions are consistent, direct concurrent execution is the most efficient. When the suggestions are inconsistent, a cooperative optimization problem is triggered, avoiding a reduction in the overall execution efficiency of the garbage collection operation of the storage device 104 due to independent optimal decisions for each block.

[0102] In one embodiment, a collaborative scheme for the memory control circuit 14 is proposed, which includes accepting mode switching overhead by sequentially executing different read modes, or uniformly using a single read mode. The memory control circuit 14 can choose the collaborative scheme based on global time estimation: that is, calculating the total time for sequentially executing different modes, and the total time for using the first mode or the second mode for all source blocks, and selecting the scheme with the shortest time among the three. This embodiment provides a concrete and operable path to resolve multi-block decision conflicts, ensuring that in multi-block concurrent garbage collection scenarios, the storage device 104 can still make near-optimal scheduling choices at the global level, improving performance robustness in complex scenarios.

[0103] In one embodiment, the system further includes a memory control circuit 14 that maintains a historical record table, periodically collects and records performance data of garbage collection execution, fine-tunes the weighting coefficients and preset baselines used to calculate decision values, and / or updates the historical record database. For example, the memory control circuit 14 can record quantification parameters, decision patterns, and actual time consumption in historical garbage collection events, and use offline analysis or online learning algorithms (e.g., gradient descent algorithms) to back-calculate better weighting coefficients or baselines. This embodiment introduces closed-loop feedback and machine learning concepts, enabling dynamic decision-making to have self-evolution capabilities. It can automatically adapt to the characteristics of the specific hardware platform (host system 102) and user usage patterns over time, continuously improving decision accuracy and garbage collection efficiency.

[0104] Figure 5 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 5 Each step can be implemented as multiple program codes or circuits, and this application does not impose any limitations. Furthermore, Figure 5 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this application does not impose any restrictions.

[0105] In summary, the memory control method and storage device proposed in the embodiments of this application, in response to triggering a garbage collection mechanism, determine at least one garbage collection source block; obtain distribution information of valid data in the garbage collection source block; calculate at least one quantization parameter to characterize the data distribution features based on the distribution information; obtain a decision value based on a preset decision model and the quantization parameter; determine the read mode for this garbage collection based on the decision value and a preset baseline; and read the valid data in the garbage collection source block based on the determined read mode and write the valid data to the target block. By dynamically matching the data distribution features with the optimal read mode, the garbage collection efficiency is significantly improved, the performance jitter of the storage device 104 is reduced, and the overall performance and user experience of the storage device 104 are improved.

[0106] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of this application. It should be noted that, for those skilled in the art, several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A memory control method, characterized in that, An application to a storage device comprising a memory module, the memory module comprising multiple planes, each plane comprising multiple blocks, each block comprising multiple physical pages, the method comprising: In response to triggering the garbage collection mechanism, at least one garbage collection source block is identified; Obtain the distribution information of valid data of the waste recycling source block; Based on the distribution information, at least one quantization parameter is calculated to characterize the data distribution features; wherein, the quantization parameter includes a first counting parameter, a second counting parameter, and a third counting parameter; the first counting parameter represents the number of page units that have valid data across multiple planes and at the same page address in this garbage collection; the second counting parameter represents the total number of physical planes with valid data in this garbage collection; the third counting parameter represents the number of consecutive page address intervals that are invalid on all planes in this garbage collection; Based on a pre-defined decision model, a decision value is obtained according to the quantification parameters; Based on the decision value and the preset baseline, the reading mode for this garbage collection is determined. The reading mode includes a first mode suitable for continuous data reading and a second mode suitable for discrete data reading. The valid data in the garbage collection source block is read based on the determined read mode, and the valid data is written to the target block.

2. The method according to claim 1, characterized in that, The process of obtaining a decision value based on a preset decision model and the quantification parameters includes: The decision model is a proportional calculation model, and the decision value is a proportional value. The ratio value is calculated based on the first counting parameter, the second counting parameter, the third counting parameter, and their respective weighting coefficients.

3. The method according to claim 1, characterized in that, The process of obtaining a decision value based on a preset decision model and the quantification parameters includes: The decision model is a multi-feature weighted scoring model, and the decision value is a comprehensive score. The comprehensive score is calculated based on a weighted sum of multiple feature parameters, including: a first feature parameter characterizing the alignment and clustering of effective data across multiple planes, a second feature parameter characterizing the data void rate, and a third feature parameter characterizing the cost-effectiveness ratio of mode switching. The first feature parameter is calculated based on the first counting parameter and the second counting parameter. The second feature parameter is calculated based on the third counting parameter and the total number of pages in the waste recycling source block. The third feature parameter is calculated based on the estimated total time required to complete this waste recycling using the first mode and the second mode, as well as the mode switching overhead.

4. The method according to claim 1, characterized in that, The step of determining the reading mode for this garbage collection based on the decision value and the preset baseline includes: In response to the decision value being greater than the preset baseline, the reading mode for this garbage collection is determined to be the first mode; In response to the decision value being less than or equal to the preset baseline, the reading mode for this garbage collection is determined to be the second mode.

5. The method according to claim 1, characterized in that, The step of determining the reading mode for this garbage collection based on the decision value and the preset baseline includes: The real-time status of the storage device is obtained, and the preset baseline is dynamically adjusted according to the real-time status to obtain a dynamic baseline. The reading mode is determined based on the decision value and the dynamic baseline; The real-time status includes a wear factor related to the average number of erases of the memory module, a capacity factor related to the proportion of available space, and a quality of service factor related to the depth of the host command queue.

6. The method according to claim 1, characterized in that, Before obtaining a decision value based on the quantification parameters according to a preset decision model, the method further includes: Based on the distribution information of the effective data, the category of the at least one waste recycling source block is determined, the category includes a first category that is clearly suitable for the first mode, a second category that is clearly suitable for the second mode, and a third category whose mode is yet to be determined; The reading mode determination based on the decision value and the preset baseline is performed on the garbage recycling source blocks belonging to the third category.

7. The method according to claim 6, characterized in that, The determination of the category of the at least one waste recycling source block based on the distribution information of the valid data includes: Before data migration is performed after the waste recycling source block is identified, the identified at least one waste recycling source block is quickly screened based on the quantification parameters or lightweight features extracted from the distribution information through pre-configured judgment rules or simple models to determine the category of the at least one waste recycling source block. During the execution phase of the garbage collection mechanism, a predetermined reading mode is directly used for the garbage collection source blocks of the first and second types; For the third type of waste recycling source block, the reading mode for this waste recycling is determined based on the decision value and the preset baseline.

8. The method according to claim 1, characterized in that, The method further includes: The read mode for this garbage collection is determined based on the current load status of the storage device.

9. The method according to claim 8, characterized in that, The method further includes: In response to the current load state being either the first state or the second state, the preset baseline is lowered or the weights used to calculate the decision value are adjusted. In response to the current load state being the third state, the preset baseline is raised; The first state is an emergency garbage collection state, the second state is a high-performance state, and the third state is an idle / background state.

10. The method according to claim 1, characterized in that, The process of obtaining a decision value based on a preset decision model and the quantification parameters includes: The decision-making model is a cost calculation model; Based on the distribution information, the total time required to complete this waste collection using the first mode and the second mode is estimated respectively. Based on the estimated total time, a decision value representing the relative time advantage of the first mode is calculated.

11. The method according to claim 10, characterized in that, The estimated total time required to complete this waste collection using the first mode and the second mode respectively includes: Obtain the average time cost of reading operations for executing the first mode and the second mode of garbage collection once, and the number of reading operations required if the first mode and the second mode are used for this garbage collection. The total time for the first mode and the total time for the second mode are calculated based on the average time overhead and the number of read operations, respectively.

12. The method according to claim 1, characterized in that, The storage device comprises multiple chips, and the method further includes: In response to the fact that the garbage collection source blocks are distributed across different grains, read mode decisions for each garbage collection source block are executed in parallel.

13. The method according to claim 12, characterized in that, The parallel execution of the read mode decision for each of the garbage collection source blocks includes: Generate preliminary pattern suggestions for each waste recycling source block; In response to the consistent mode recommendation of the garbage collection source block, concurrent reading is performed on each garbage collection source block using the read mode corresponding to the mode recommendation; In response to the inconsistent mode recommendations for the aforementioned waste recycling source blocks, a collaborative solution is determined.

14. The method according to claim 13, characterized in that, The collaborative scheme includes accepting mode switching overhead, executing different read modes sequentially, or uniformly using a single read mode.

15. The method according to claim 1, characterized in that, The method further includes: Regularly collect performance data on garbage collection execution, fine-tune the weighting coefficients used to calculate the decision value, the preset baseline, and / or update the historical record database.

16. A storage device, characterized in that, include: A connection interface for electrically connecting to a host system; The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple physical pages; as well as The memory controller includes an error checking and correction circuit, a buffer memory, and a memory control circuit, and is electrically connected to the connection interface and the memory module; The memory controller is configured to perform the memory control method as described in any one of claims 1 to 15.

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