Three-dimensional stacked memory and redundancy repair method
By employing a parallel testing-serial testing and repair method, the problems of low yield and high hardware area overhead caused by memory cell failures in three-dimensional stacked memory were solved, achieving efficient fault repair and hardware savings.
Patent Information
- Application Number
- CN202511350686.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-19
- Publication Date
- 2026-02-03
AI Technical Summary
Traditional 3D stacked memory suffers from low wafer stacking yield and large hardware area overhead due to memory cell failures. Existing repair methods are inefficient and have excessive hardware overhead.
It adopts a parallel testing-serial testing and repair process, and through the collaborative work of the built-in self-test module and the built-in redundancy analysis module, it can achieve rapid fault screening and accurate repair of memory chips, and share the redundancy analysis module to save hardware space.
It improves wafer stacking yield for 3D stacked memory, reduces hardware area overhead, and enhances testing speed and repair efficiency.
Smart Images
Figure CN121459906A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of integrated circuit design, and in particular relates to a three-dimensional stacked memory and a redundancy repair method. Background Technology
[0002] Today, many applications require high bandwidth, such as high-performance computing (HPC), Ethernet, and graphics processing units (GPUs). Furthermore, the accumulation of big data, innovation in theoretical algorithms, increased computing power, and the evolution of network infrastructure have led to another revolutionary advancement in the artificial intelligence industry, which has been accumulating expertise for over half a century. AI research and applications have entered a new stage of development. With the active promotion of governments and industries, AI technology is making rapid progress in large-scale industrial applications. AI computing involves a large number of process parameters, requiring enormous storage capacity, high bandwidth, low latency memory access capabilities, and rich and flexible connections between computing units and storage devices.
[0003] With the development of integrated circuits, traditional Dynamic Random Access Memory (DRAM) can no longer meet performance requirements. Many applications demand miniaturization, high speed, high bandwidth, and low power consumption from DRAM. As Moore's Law gradually becomes obsolete, adopting advanced packaging technologies to increase chip performance while reducing size and power consumption has become a new trend. Among these technologies, 3D stacked memory involves stacking multiple chips in 3D and interconnecting them through through-silicon vias (TSVs). This shortens the interconnect lines between chips, achieving high speed, low power consumption, and small area requirements. However, during the fabrication process, memory cell failures may occur due to process limitations, causing the stacked chips to malfunction, resulting in low yield, and the hardware area overhead of the memory also needs to be reduced. Summary of the Invention
[0004] The purpose of this application is to provide a three-dimensional stacked memory and a redundancy repair method, which aims to solve the problems of low wafer stacking yield and large hardware area overhead caused by memory cell failure in related technologies.
[0005] To address the aforementioned technical problems, a first aspect of this application provides a three-dimensional stacked memory, applied to a three-dimensional stacked memory, comprising:
[0006] A logic control chip and multiple memory chips, wherein the logic control chip includes:
[0007] Multiple built-in self-test modules are provided, each of which is connected to one of the memory chips via a connection channel, and the number of the built-in self-test modules corresponds to the number of the connection channels.
[0008] A built-in redundancy analysis module is included, which is electrically connected to multiple built-in self-test modules; wherein...
[0009] Multiple built-in self-test modules are configured to perform parallel tests on all memory chips and send the first fault information corresponding to the first memory chip obtained from the test to the built-in redundancy analysis module. The first memory chip is the first memory chip that is detected to have a fault.
[0010] The built-in redundancy analysis module is configured to generate a corresponding first redundancy repair strategy based on the received first fault information.
[0011] The built-in self-test module is also configured to determine a second memory chip based on the test results of the parallel test, wherein the second memory chip is a memory chip that has been detected to be faulty, excluding the first memory.
[0012] The built-in self-test module is also configured to perform serial tests on each of the second memory chips in sequence, and send the second fault information corresponding to the second memory chip obtained from the test to the built-in redundancy analysis module in sequence.
[0013] The built-in redundancy analysis module is also configured to generate corresponding second redundancy repair strategies based on the second fault information.
[0014] In one embodiment, the built-in self-test module includes a fault count register, which is configured to record a first fault count;
[0015] The built-in self-test module is also configured to:
[0016] Based on the first number of faults, all the second memory chips are sorted in descending order to obtain a fault repair sequence;
[0017] Each of the second memory chips is sequentially tested according to the fault repair sequence.
[0018] In one embodiment, the built-in self-test module is further configured to:
[0019] When performing serial testing on each of the second memory chips, the number of the second faults currently detected is recorded, and the number of the second faults is compared with the number of the first faults.
[0020] If the second fault count equals the first fault count, then the serial test of the currently faulty memory is completed.
[0021] In one embodiment, the built-in redundancy analysis module is further configured to:
[0022] Get currently available repair resources;
[0023] Determine whether the currently available repair resources meet the resource requirements of the first redundancy repair strategy or the second redundancy repair strategy;
[0024] If the resource requirements of the first redundancy repair strategy or the second redundancy repair strategy are not met, then subsequent testing will be stopped and the repair process will end.
[0025] In one embodiment, the built-in redundancy analysis module is further configured to:
[0026] The first redundancy repair strategy or the second redundancy repair strategy is sent to the corresponding first fault memory chip or the second fault memory chip for redundancy repair, and an analysis completion signal is sent to the built-in self-test module after the first redundancy repair strategy or the second redundancy repair strategy is sent.
[0027] The built-in self-test module is also configured to:
[0028] Upon receiving the analysis completion signal, increment the number of repaired faulty memory chips by one;
[0029] If the number of repaired faulty memory chips after the increase is different from the number of faulty memory chips, then the next faulty memory chip is tested, and the next fault information obtained from the test is sent to the built-in redundancy analysis module.
[0030] The built-in redundancy analysis module is also configured to:
[0031] The next redundancy repair strategy is generated based on the received next fault information, and the next redundancy repair strategy is sent to the corresponding memory chip for redundancy repair.
[0032] Once the next redundancy repair strategy is sent, an analysis completion signal is sent to the built-in self-test module.
[0033] A second aspect of this application provides a redundancy repair method applied to a three-dimensional stacked memory, the three-dimensional stacked memory including a logic control chip and multiple memory chips, the logic control chip including multiple built-in self-test modules and built-in redundancy analysis modules, the method comprising:
[0034] All memory chips are tested in parallel using multiple built-in self-test modules, and the first fault information corresponding to the first memory chip obtained from the test is sent to the built-in redundancy analysis module. The first memory chip is the first memory chip that is detected to have a fault.
[0035] The built-in redundancy analysis module is controlled to generate a corresponding first redundancy repair strategy based on the received first fault information;
[0036] The built-in self-test module is controlled to determine the second memory chip based on the test results of the parallel test. The second memory chip is the memory chip that was detected to be faulty, excluding the first memory chip.
[0037] Based on the built-in self-test module, each of the second memory chips is sequentially tested, and the second fault information corresponding to the second memory chip obtained from the test is sequentially sent to the built-in redundancy analysis module.
[0038] Based on the built-in redundancy analysis module, a corresponding second redundancy repair strategy is generated sequentially based on the second fault information.
[0039] The beneficial effects of this application embodiment compared with the prior art are: it provides a three-dimensional stacked memory and a redundancy repair method, and designs a repair process of "parallel testing-repair-serial testing and repair", which enables all built-in self-test modules in the logic chip to share a built-in redundancy analysis module, which can greatly save hardware area overhead, retain the number of built-in self-test modules while taking into account the test speed. Combined with the scheme of sharing repair units between layers, it can effectively improve the wafer stacking yield caused by memory unit failure. Attached Figure Description
[0040] To more clearly illustrate the related technologies or the technical solutions in the embodiments of this application, the drawings used in the description of the related technologies or the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application, and not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0041] Figure 1 A schematic diagram of a 3D stacked memory testing and redundancy repair architecture is provided for the first aspect of the embodiments of this application;
[0042] Figure 2 A flowchart illustrating a redundancy repair method provided as a second aspect of the embodiments of this application;
[0043] Figure 3 A detailed flowchart of a redundancy repair method provided for the second aspect of the embodiments of this application. Detailed Implementation
[0044] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0045] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0046] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.
[0048] Today, many applications require high bandwidth, such as high-performance computing (HPC), Ethernet, and graphics processing units (GPUs). Furthermore, the accumulation of big data, innovation in theoretical algorithms, increased computing power, and the evolution of network infrastructure have led to another revolutionary advancement in the artificial intelligence industry, which has been accumulating expertise for over half a century. AI research and applications have entered a new stage of development. With the active promotion of governments and industries, AI technology is making rapid progress in large-scale industrial applications. AI computing involves a large number of process parameters, requiring enormous storage capacity, high bandwidth, low latency memory access capabilities, and rich and flexible connections between computing units and storage devices.
[0049] With the development of integrated circuits, traditional dynamic random access memory (DRAM) can no longer meet performance requirements. Many applications demand miniaturization, high speed, high bandwidth, and low power consumption from DRAM. As Moore's Law gradually becomes obsolete, adopting advanced packaging technologies to increase chip performance while reducing size and power consumption has become a new trend. Among these technologies, 3D stacked memory involves stacking multiple chips in 3D and interconnecting them through through silicon vias (TSVs). This shortens the interconnect lines between chips, achieving the requirements of high speed, low power consumption, and small area.
[0050] However, during the fabrication process, memory cell failures may occur due to process limitations, causing the stacked chips to malfunction and resulting in low yield. Furthermore, current solutions primarily involve repairing each chip layer individually. If all layers can be repaired (the number of available repair cells ≥ the number of faulty cells), the stacked chips can function normally. In the testing and repair process, a 3D parallel testing and parallel repair method is commonly used to achieve the fastest repair speed. However, the current solution of repairing each chip layer individually has a drawback: if any layer cannot be repaired (the number of available repair cells < the number of faulty cells), the entire stacked chip will fail. Additionally, since parallel testing and parallel repair require n built-in self-test modules (BIST) and n built-in redundancy analysis modules (BIRA), where n equals the number of memory channels, this leads to the maximum area overhead.
[0051] Therefore, the related technologies suffer from problems such as low wafer stacking yield due to memory cell failures, and large hardware area overhead caused by existing repair methods.
[0052] The first aspect of this application provides a three-dimensional stacked memory, such as... Figure 1As shown in the architecture, the three-dimensional stacked memory includes a logic control chip and multiple memory chips. The logic control chip includes: multiple built-in self-test modules, each of which is connected to one of the memory chips via a connection channel, with the number of built-in self-test modules corresponding to the number of connection channels; and a built-in redundancy analysis module, which is electrically connected to each of the multiple built-in self-test modules. The multiple built-in self-test modules are configured to perform parallel testing on all memory chips and send the first fault information corresponding to the first memory chip detected during testing to the built-in redundancy analysis module. The first memory chip is the first memory chip detected to have a fault. The built-in redundancy analysis module is configured to generate a corresponding first redundancy repair strategy based on the received first fault information. The built-in self-test module is also configured to determine the second memory chip based on the test results of the parallel testing. The second memory chip is the memory chip detected to have a fault, excluding the first memory chip. The built-in self-test module is also configured to perform serial testing on each of the second memory chips and sequentially send the second fault information corresponding to the second memory chip detected during testing to the built-in redundancy analysis module. The built-in redundancy analysis module is also configured to sequentially generate a corresponding second redundancy repair strategy based on the second fault information.
[0053] Specifically, in this embodiment, the logic control chip includes a built-in redundancy analysis module and multiple built-in self-test modules. The built-in self-test modules are first configured to perform parallel tests on all memory chips in the three-dimensional stacked memory to quickly complete the initial fault screening. During the parallel testing process, when the first faulty memory chip is detected, the built-in self-test module sends the fault information corresponding to the faulty chip to the built-in redundancy analysis module. After receiving the fault information, the built-in redundancy analysis module generates a redundancy repair strategy suitable for the faulty chip based on the information, so as to achieve targeted repair of the first faulty chip. When the first fault is detected, its corresponding memory chip is selected as the memory chip to be repaired, so that after the parallel testing is completed, there is no need to consider which memory to select as the first object to be repaired, and the selection process occurs during the parallel testing process, saving process time.
[0054] After parallel testing is completed, the built-in self-test module is further configured to classify the remaining memory chips (excluding the first faulty chip) into faulty memory chips (i.e., chips with faults) and non-faulty memory chips (i.e., chips without detected faults) based on the parallel test results, thereby achieving fault classification of the memory chips. For the classified faulty memory chips, the built-in self-test module is further configured to perform serial tests on each faulty memory chip in a preset order to obtain more accurate fault information. After the serial test of each faulty memory chip is completed, its corresponding fault information is sent sequentially to the built-in redundancy analysis module. Accordingly, after receiving the fault information from each faulty memory chip, the built-in redundancy analysis module sequentially generates corresponding redundancy repair strategies based on this fault information to complete the redundancy repair of all faulty memory chips.
[0055] It is understood that, in some embodiments, in the serial testing and repair process, the process of sequential testing by the built-in self-test module and the process of sequential analysis by the built-in redundancy analysis module are coordinated with each other. After the testing and analysis of one fault register chip is completed, the next fault register chip is tested.
[0056] In some embodiments, the built-in self-test module includes a fault count register, which is configured to record a first fault count; the built-in self-test module is also configured to: sort all the second memory chips in descending order based on the first fault count to obtain a fault repair sequence; and perform serial tests on each of the second memory chips according to the fault repair sequence.
[0057] Specifically, in this embodiment, the built-in self-test module further includes a fault count register, which is configured to record the number of faults (defined as the first fault count) corresponding to each faulty memory chip during the parallel testing phase. This configuration enables the built-in self-test module to accurately obtain the fault severity information of each faulty memory chip, thereby optimizing the order of subsequent testing and repair.
[0058] Based on the first fault count recorded in the fault count register, the built-in self-test module is further configured to sort all faulty memory chips: specifically, the faulty memory chips are arranged in descending order of the first fault count (i.e., from most to least faulty), forming a fault repair sequence. The logic of using descending order is that memory chips with a larger number of faults are usually more likely to be unrepairable. Prioritizing their processing can identify unrepairable chips early, thereby avoiding subsequent ineffective testing and repair operations and improving overall process efficiency.
[0059] Furthermore, after obtaining the fault repair sequence, the built-in self-test module performs serial tests on each faulty memory chip sequentially according to the sequence. That is, it first performs serial testing on the faulty memory chip that is first in the fault repair sequence, and then performs serial testing on the next faulty memory chip in sequence, until all faulty memory chips have been tested. This orderly serial testing arrangement, combined with the priority ranking of the number of faults, makes the testing process more targeted and efficient.
[0060] Furthermore, it's worth noting that the fault count register in the built-in self-test module only stores the number of faults, not the specific fault information. The specific fault information needs to be acquired and stored by the built-in redundancy analysis module. Firstly, since there are many built-in self-test modules, setting up fault information storage functionality for each would result in significant hardware area overhead. However, this application's solution shares the built-in redundancy analysis module and employs a serial repair method, integrating the fault information acquisition and storage functionality into the built-in redundancy analysis module. This significantly saves hardware area and also explains why this application's solution performs serial testing before the serial repair process.
[0061] In some embodiments, the built-in self-test module is further configured to: when performing serial testing on each of the second memory chips, record the number of second faults currently detected and compare the number of second faults with the number of first faults; if the number of second faults is equal to the number of first faults, then complete the serial test on the currently faulty memory.
[0062] Specifically, in this embodiment, when the built-in self-test module performs serial testing on each faulty memory chip according to the fault repair sequence, it is further configured to record the number of faults detected in real time, defined as the second fault number. This second fault number is associated with the first fault number recorded in the fault number register (i.e., the number of faults of the corresponding faulty memory chip recorded in the parallel testing phase). The built-in self-test module compares the real-time acquired second fault number with the first fault number corresponding to the faulty memory chip. When the comparison result shows that the second fault number equals the first fault number, it indicates that the serial test has completely detected all faults of the faulty memory chip. At this time, the built-in self-test module completes the serial test of the current faulty memory chip and does not need to continue to execute subsequent redundant test steps. This configuration, by using the first fault number obtained in the parallel testing phase as a reference, avoids over-detection that may occur in the serial test. While ensuring the integrity of the fault information, it can effectively shorten the test time of a single faulty memory chip and further improve the efficiency of the entire test and repair process.
[0063] In some embodiments, the built-in redundancy analysis module is further configured to: obtain currently available repair resources; determine whether the currently available repair resources meet the resource requirements of the first redundancy repair strategy or the second redundancy repair strategy; if the resource requirements of the first redundancy repair strategy or the second redundancy repair strategy are not met, then stop subsequent testing and end the repair process.
[0064] Specifically, in this embodiment, the built-in redundancy analysis module is first configured to obtain currently available repair resources. This resource information comes from the redundancy resource data reported by each memory chip in the three-dimensional stacked memory, covering key resource information such as redundant rows and columns that can be repaired. It is understood that the BIRA module in this application is shared by the BIST module. Similarly, the redundant resources in this application are inter-layer shared repair units, equivalent to an entire resource pool, with a single BIRA allocating repair resources. Compared to schemes where each layer can only use its own repair units, this offers greater flexibility and achieves the highest repair rate.
[0065] Based on the currently available repair resources, the built-in redundancy analysis module further determines whether these resources can meet the resource requirements of its generated redundancy repair strategy. Specifically, it determines whether the quantity and type of existing redundant resources are sufficient to cover the repair needs of the corresponding faulty memory chip. If the determination shows that the currently available repair resources cannot meet the resource requirements of the redundancy repair strategy, it means that the faulty memory chip is no longer repairable. In this case, the built-in redundancy analysis module is configured to immediately trigger a termination mechanism: stopping all subsequent testing and repair operations on other faulty memory chips and ending the entire repair process. By performing resource feasibility verification before repair execution, unrepairable scenarios can be identified early, avoiding further testing and analysis of unrepairable chips, thereby significantly reducing ineffective resource investment and improving the overall efficiency of logic control chips in testing and repairing 3D stacked memory.
[0066] In some embodiments, the built-in redundancy analysis module is further configured to: send a first redundancy repair strategy or a second redundancy repair strategy to the corresponding first faulty memory chip or second faulty memory chip for redundancy repair, and send an analysis completion signal to the built-in self-test module after the first redundancy repair strategy or the second redundancy repair strategy is sent; the built-in self-test module is further configured to: after receiving the analysis completion signal, increment the number of repaired faulty memory chips by one; if the incremented number of repaired faulty memory chips is different from the number of faulty memory chips, test the next faulty memory chip, and send the next fault information obtained from the test to the built-in redundancy analysis module; the built-in redundancy analysis module is further configured to: generate the next redundancy repair strategy based on the received next fault information, and send the next redundancy repair strategy to the corresponding memory chip for redundancy repair; after the next redundancy repair strategy is sent, send an analysis completion signal to the built-in self-test module.
[0067] Specifically, after generating a redundancy repair strategy for a specific faulty memory chip, the built-in redundancy analysis module is configured to send this strategy to the corresponding faulty memory chip to guide it in performing redundancy repair operations. Once the redundancy repair strategy has been fully sent to the target chip, the built-in redundancy analysis module sends an analysis completion signal to the corresponding built-in self-test module. This signal informs the built-in self-test module that the repair strategy for the current faulty memory chip has been delivered and subsequent processes can proceed.
[0068] After receiving the analysis completion signal, the built-in self-test module is configured to update the number of repaired faulty memory chips by incrementing the count to record the current number of repaired faulty chips. Subsequently, the built-in self-test module compares the updated number of repaired faulty memory chips with the "total number of faulty memory chips obtained after parallel testing" in the above scheme. If the two values differ, it indicates that there are still unrepaired faulty memory chips. In this case, the built-in self-test module will initiate a serial test for the next faulty memory chip according to the fault repair sequence in the above scheme, and after the test is completed, send the corresponding fault information of that chip to the built-in redundancy analysis module.
[0069] Correspondingly, after receiving the fault information of the next faulty memory chip, the built-in redundancy analysis module is configured to generate a new redundancy repair strategy suitable for that chip based on the information, and send the strategy to the corresponding faulty memory chip for repair. After the next redundancy repair strategy is sent, the built-in redundancy analysis module sends an analysis completion signal to the built-in self-test module again, triggering the re-execution of the above process until the number of repaired faulty memory chips matches the total number of faulty memory chips (all faulty chips have been repaired) or the termination condition in the above scheme is triggered.
[0070] Through signal interaction and process loops between the above modules, the logic control chip can perform orderly and sequential repairs of faulty memory chips, ensuring the continuity and integrity of the testing and repair process, and adapting to the multi-level repair requirements of three-dimensional stacked memory.
[0071] In some embodiments, the built-in self-test module further includes: a test vector generator configured to generate test data; a test address generator configured to generate a test address for sending test data; and a comparator configured to compare test response data with expected response data to detect faults.
[0072] Specifically, the test vector generator is configured to generate test data for testing the storage function of memory chips. This test data is generated according to a preset test algorithm and can cover a variety of operating scenarios of memory chips, ensuring that potential storage faults, such as data read / write errors and storage cell failures, can be effectively exposed.
[0073] The test address generator works in conjunction with the test vector generator to generate the test address for sending the aforementioned test data. This test address corresponds to the location of the memory cell to be tested within the memory chip, ensuring that the test data generated by the test vector generator can be accurately written to the specified memory area of the memory chip.
[0074] The comparator performs the core fault detection function. It is configured to receive the test response data returned by the memory chip during the testing process, that is, the data read after the test data is written, and compare this test response data with the preset expected response data, that is, the original data or theoretically correct data when the test data was written. If the two match, it indicates that the corresponding memory cell is working normally; if there is a difference, it is determined that the memory cell is faulty.
[0075] In some embodiments, the built-in redundancy analysis module includes: a counter configured to record available redundant rows / columns in the redundancy repair resources; a fault storage content addressable memory configured to record fault information corresponding to the current memory chip to be repaired; a controller configured to allocate any available redundant rows / columns in the redundancy repair resources based on the fault information stored in the fault storage content addressable memory using a preset allocation algorithm, and generate a corresponding redundancy repair strategy; and a repair register configured to store the redundancy repair strategy and send the redundancy repair strategy to the current memory chip to be repaired.
[0076] Specifically, the counter is configured to record available redundant rows and columns of redundant repair resources. This information comes from the redundant resource data reported by each memory chip in the 3D stacked memory. By statistically analyzing and storing this data, the counter ensures that the controller can monitor the total amount and distribution of resources currently available for repair in real time.
[0077] The Fault Content Addressable Memory (CAM) is configured to record fault information corresponding to the memory chip currently under repair. This fault information, including key data such as the number of faults and their location, is sent by the built-in self-test module after parallel or serial testing. The CAM's high-speed storage and retrieval capabilities ensure that the controller can quickly obtain the fault details of the chip under repair.
[0078] The controller, as the core processing unit of the built-in redundancy analysis module, is configured to allocate any available redundant rows or columns from the redundant repair resources based on the fault information of the memory chip to be repaired stored in the fault storage CAM, combined with the available redundant rows / columns recorded by the counter. This algorithm can select the optimal combination of redundant resources according to the fault type and distribution, and finally generate a targeted redundancy repair strategy.
[0079] The repair register is configured to receive the redundancy repair strategy generated by the memory controller and sends this strategy to the memory chip currently being repaired when needed. Through the temporary storage and transmission control of the repair register, it is ensured that the redundancy repair strategy is accurately and completely delivered to the target chip.
[0080] Figure 2 A flowchart illustrating a redundancy repair method provided in the second aspect of an embodiment of this application is shown. The redundancy repair method is applied to a three-dimensional stacked memory, which includes a logic control chip. The logic control chip includes a built-in redundancy analysis module and multiple built-in self-test modules. The method includes the following steps 201 to 205.
[0081] Step 201: The built-in self-test module performs parallel tests on all memory chips and sends the fault information corresponding to the first faulty memory chip obtained from the test to the built-in redundancy analysis module.
[0082] Step 202: The built-in redundancy analysis module generates a corresponding redundancy repair strategy based on the fault information of the first faulty memory chip received.
[0083] Step 203: The built-in self-test module divides the remaining memory chips into faulty memory chips and non-faulty memory chips based on the parallel test results.
[0084] Step 204: The built-in self-test module performs serial tests on each faulty memory chip in sequence, and sends the fault information corresponding to the faulty memory chip obtained from the test to the built-in redundancy analysis module in sequence.
[0085] Step 205: The built-in redundancy analysis module generates corresponding redundancy repair strategies based on the fault information of the received faulty memory chip.
[0086] In some embodiments, the built-in self-test module includes a fault count register for recording a first fault count. The method further includes: controlling the built-in self-test module to sort all the second memory chips in descending order based on the first fault count to obtain a fault repair sequence; and controlling the built-in self-test module to perform serial tests on each of the second memory chips according to the fault repair sequence.
[0087] In some embodiments, the method further includes: when performing serial testing on each second memory chip, controlling the built-in self-test module to record the number of currently detected second faults and comparing the number of second faults with the number of first faults; if the number of second faults is equal to the number of first faults, controlling the built-in self-test module to complete the serial test on the currently faulty memory.
[0088] In some embodiments, the method further includes: obtaining currently available repair resources based on the built-in redundancy analysis module; determining whether the currently available repair resources meet the resource requirements of the first redundancy repair strategy or the second redundancy repair strategy based on the built-in redundancy analysis module; if the resource requirements of the first redundancy repair strategy or the second redundancy repair strategy are not met, controlling the built-in redundancy analysis module to stop subsequent tests and end the repair process.
[0089] In some embodiments, the method further includes: sending a first redundancy repair strategy or a second redundancy repair strategy to the corresponding first faulty memory chip or second faulty memory chip for redundancy repair based on the built-in redundancy analysis module, and sending an analysis completion signal to the built-in self-test module after the first redundancy repair strategy or the second redundancy repair strategy is sent; after receiving the analysis completion signal, incrementing the number of repaired faulty memory chips by one based on the built-in self-test module; if the incremented number of repaired faulty memory chips is different from the number of faulty memory chips, testing the next faulty memory chip and sending the next fault information obtained from the test to the built-in redundancy analysis module; generating a next redundancy repair strategy based on the received next fault information based on the built-in redundancy analysis module, sending the next redundancy repair strategy to the corresponding memory chip for redundancy repair, and sending an analysis completion signal to the built-in self-test module after the next redundancy repair strategy is sent.
[0090] It is understandable that each step in the redundancy repair method has been explained in the corresponding module mentioned above, and will not be repeated here.
[0091] Figure 3This document provides a detailed flowchart of a redundancy repair process for a second aspect of an embodiment of this application, illustrating the entire redundancy repair process. In general, the process begins by identifying repairable resources in all chips, followed by a parallel testing phase to repair the first faulty memory. Then, a serial testing and repair phase is initiated to test and repair the remaining faulty memories sequentially.
[0092] In detail, all BIST modules of the logic control chip start synchronously and perform parallel tests on all core DRAM chips. If the first faulty memory chip is detected, the fault information of the chip is immediately transmitted to the BIRA module. After the memory chip has been tested, a repair strategy is generated based on the statistically available redundant resources. The strategy is sent to the faulty chip through the repair register to complete the repair.
[0093] For the remaining faulty chips discovered during parallel testing, in such cases... Figure 3 In the illustrated embodiment, the numbering and recording start from i=0. The BIST module does not immediately transmit complete fault information, but only records the number of faults of each chip through the fault count register. As shown in the figure, the number of Memory i errors = the number of Memory i errors + 1. After the parallel test is completed, the BIST module divides all chips into faulty memory chips and fault-free memory chips according to the test results. Fault-free chips directly exit the subsequent process, while faulty chips enter the serial test and repair stage.
[0094] The BIST module first arranges the faulty memory chips in descending order of fault count based on the first fault count recorded in the fault count register, forming a fault repair sequence. The BIST module then initiates serial testing on the faulty chips sequentially according to the sequence, sending the fault information obtained from the tests to BIRA. During the test, the module records the number of faults detected in real time, i.e., the second fault count, and continuously compares the second fault count with the first fault count. If the two are equal, it indicates that all faults of the chip have been completely detected, and the serial testing of the chip is immediately stopped to avoid redundant operations. Figure 3 In one implementation, whenever the BIST module sends an error message to the BIRA module, it will set the previously recorded Memory i error count to Memory i error count - 1, until the error count is 0.
[0095] After the serial test stops, the BIRA module calls the updated available redundant resources in the counter to determine whether the current resources meet the repair requirements:
[0096] If the repairable resources do not meet the requirements, the test and repair branch will be terminated immediately, and the entire process will end (due to the failure of the 3D stacked memory as a single chip is unrepairable).
[0097] If the repairable resources meet the requirements, the BIRA module generates a corresponding repair strategy and sends it to the faulty chip through the repair register to complete the repair, while updating the available redundant resources in the counter.
[0098] After the repair is completed, the BIST module determines whether the number of repaired faulty chips is equal to the total number of faulty memory chips: if they are not equal, it returns to the step of testing the next faulty chip according to the fault repair sequence and repeats the serial test-repair logic; if they are equal, it means that all faulty chips have been repaired and the process terminates normally.
[0099] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0100] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0101] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A three-dimensional stacked memory, characterized in that, include: A logic control chip and multiple memory chips, wherein the logic control chip includes: Multiple built-in self-test modules are provided, each of which is connected to one of the memory chips via a connection channel, and the number of the built-in self-test modules corresponds to the number of the connection channels. A built-in redundancy analysis module is included, which is electrically connected to multiple built-in self-test modules; wherein... Multiple built-in self-test modules are configured to perform parallel tests on all memory chips and send the first fault information corresponding to the first memory chip obtained from the test to the built-in redundancy analysis module. The first memory chip is the first memory chip that is detected to have a fault. The built-in redundancy analysis module is configured to generate a corresponding first redundancy repair strategy based on the received first fault information. The built-in self-test module is also configured to determine a second memory chip based on the test results of the parallel test, wherein the second memory chip is a memory chip that has been detected to be faulty, excluding the first memory. The built-in self-test module is also configured to perform serial tests on each of the second memory chips in sequence, and send the second fault information corresponding to the second memory chip obtained from the test to the built-in redundancy analysis module in sequence. The built-in redundancy analysis module is also configured to generate corresponding second redundancy repair strategies based on the second fault information.
2. The three-dimensional stacked memory as described in claim 1, characterized in that, The built-in self-test module includes a fault count register, which is configured to record a first fault count; The built-in self-test module is also configured to: Based on the first number of faults, all the second memory chips are sorted in descending order to obtain a fault repair sequence; Each of the second memory chips is sequentially tested according to the fault repair sequence.
3. The three-dimensional stacked memory as described in claim 2, characterized in that, The built-in self-test module is also configured to: When performing serial testing on each of the second memory chips, the number of the second faults currently detected is recorded, and the number of the second faults is compared with the number of the first faults. If the second fault count equals the first fault count, then the serial test of the currently faulty memory is completed.
4. The three-dimensional stacked memory as described in claim 1, characterized in that, The built-in redundancy analysis module is also configured to: Get currently available repair resources; Determine whether the currently available repair resources meet the resource requirements of the first redundancy repair strategy or the second redundancy repair strategy; If the resource requirements of the first redundancy repair strategy or the second redundancy repair strategy are not met, then subsequent testing will be stopped and the repair process will end.
5. The three-dimensional stacked memory as described in claim 1, characterized in that, The built-in redundancy analysis module is also configured to: The first redundancy repair strategy or the second redundancy repair strategy is sent to the corresponding first fault memory chip or the second fault memory chip for redundancy repair, and an analysis completion signal is sent to the built-in self-test module after the first redundancy repair strategy or the second redundancy repair strategy is sent. The built-in self-test module is also configured to: Upon receiving the analysis completion signal, increment the number of repaired faulty memory chips by one; If the number of repaired faulty memory chips after the increase is different from the number of faulty memory chips, then the next faulty memory chip is tested, and the next fault information obtained from the test is sent to the built-in redundancy analysis module. The built-in redundancy analysis module is also configured to: The next redundancy repair strategy is generated based on the received next fault information, and the next redundancy repair strategy is sent to the corresponding memory chip for redundancy repair. Once the next redundancy repair strategy is sent, an analysis completion signal is sent to the built-in self-test module.
6. A redundancy repair method, characterized in that, Applied to a three-dimensional stacked memory, the three-dimensional stacked memory includes a logic control chip and multiple memory chips, the logic control chip including multiple built-in self-test modules and built-in redundancy analysis modules, the method includes: All memory chips are tested in parallel using multiple built-in self-test modules, and the first fault information corresponding to the first memory chip obtained from the test is sent to the built-in redundancy analysis module. The first memory chip is the first memory chip that is detected to have a fault. The built-in redundancy analysis module is controlled to generate a corresponding first redundancy repair strategy based on the received first fault information; The built-in self-test module is controlled to determine the second memory chip based on the test results of the parallel test. The second memory chip is the memory chip that was detected to be faulty, excluding the first memory chip. Based on the built-in self-test module, each of the second memory chips is sequentially tested, and the second fault information corresponding to the second memory chip obtained from the test is sequentially sent to the built-in redundancy analysis module. Based on the built-in redundancy analysis module, a corresponding second redundancy repair strategy is generated sequentially based on the second fault information.
7. The redundancy repair method as described in claim 6, characterized in that, The built-in self-test module includes a fault count register, which is used to record a first fault count. The method further includes: The built-in self-test module is controlled to sort all the second memory chips in descending order based on the first number of faults to obtain a fault repair sequence. The built-in self-test module is controlled to perform serial tests on each of the second memory chips according to the fault repair sequence.
8. The redundancy repair method as described in claim 7, characterized in that, Also includes: When performing serial testing on each of the second memory chips, the built-in self-test module is controlled to record the number of second faults currently detected and compare the number of second faults with the number of first faults. If the second number of faults is equal to the first number of faults, then the built-in self-test module is controlled to complete the serial test of the currently faulty memory.
9. The redundancy repair method as described in claim 6, characterized in that, Also includes: The currently available repair resources are obtained based on the built-in redundancy analysis module. Based on the built-in redundancy analysis module, it is determined whether the currently available repair resources meet the resource requirements of the first redundancy repair strategy or the second redundancy repair strategy; If the resource requirements of the first redundancy repair strategy or the second redundancy repair strategy are not met, the built-in redundancy analysis module is controlled to stop subsequent tests and end the repair process.
10. The redundancy repair method as described in claim 6, characterized in that, Also includes: Based on the built-in redundancy analysis module, the first redundancy repair strategy or the second redundancy repair strategy is sent to the corresponding first fault memory chip or the second fault memory chip for redundancy repair, and after the first redundancy repair strategy or the second redundancy repair strategy is sent, an analysis completion signal is sent to the built-in self-test module. After receiving the analysis completion signal, the number of repaired faulty memory chips is incremented by one based on the built-in self-test module. If the number of repaired faulty memory chips after the increment is different from the number of faulty memory chips, the next faulty memory chip is tested, and the next fault information obtained from the test is sent to the built-in redundancy analysis module. Based on the received next fault information, the built-in redundancy analysis module generates the next redundancy repair strategy and sends the next redundancy repair strategy to the corresponding memory chip for redundancy repair. After the next redundancy repair strategy is sent, an analysis completion signal is sent to the built-in self-test module.