Data comparison method, memory device and memory controller thereof
By using IMS units in memory for population testing, the problem of low data alignment efficiency in genome sequence analysis is solved, realizing an efficient data alignment method that reduces data movement and improves performance.
Patent Information
- Application Number
- CN202510611681.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-05-06
- Filing Date
- 2025-05-13
- Publication Date
- 2026-02-03
AI Technical Summary
In existing genome sequence analysis, the large amount of data movement between flash memory and DRAM caused by data alignment methods has become a bottleneck for performance improvement, affecting data alignment efficiency.
An in-memory search (IMS) unit is used to perform group testing on candidate matching input data. Combined with a pre-screening filter and a group test decoder, data movement is reduced and matching efficiency is improved.
By performing data alignment in memory, the performance bottleneck caused by data migration is reduced, the amount of data movement is significantly reduced, energy efficiency is improved, and the speed of genome sequence analysis is increased.
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Figure CN121459937A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a data comparison method, a memory device, and its memory controller. Background Technology
[0002] Genome sequencing is the process of decoding and interpreting an organism's DNA, providing crucial insights for a wide range of biological and medical applications. Next-Generation Sequencing (NGS) enables high-throughput sequencing, but requires significant computation to reconstruct the complete sequence from the fragmented reads.
[0003] Figure 1 This diagram illustrates the comparison of a sample fragment to a reference sequence. (Example) Figure 1 As shown, by comparing a sample fragment to a reference sequence, it can be determined whether the sample fragment matches the reference sequence.
[0004] Based on current genome sequence analysis, the sample fragments and reference subsequences stored in flash memory are pre-sorted and loaded into dynamic random access memory (DRAM). Furthermore, the controller performs sequence alignment to confirm whether the sample fragments are identical to the reference subsequences.
[0005] Figure 2 This shows a schematic diagram of comparing the sorted sample fragments with the reference sequence. The sample fragments and the reference sequence can be sorted offline beforehand, from smallest to largest. Because the sample fragments and the reference sequence have been sorted, this means: (1) A i >A j With B i >B j , i>j (i and j are positive integers), A represents the sample segment, and B represents the reference sequence. (2) In A i >B k If A holds true j >A i Then for all s≦k (where s and k are positive integers), A j >B S .
[0006] exist Figure 2 In the middle, at t=0, after comparison, A i >B s-2 At t=1, after comparison, A i >B s-1 At t=2, after comparison, A i =B s That is, A i Matched by B s Because A iSince A has already been matched, the next step is to match A. i+1 Because A i >B s-1 B s-2 This implies that A i+1 >B s-1 B s-2 Therefore, at t=3, when comparing A... i+1 At that time, A can be performed. i+1 With B s The comparison can be performed without performing A. i+1 For B s-1 With B s-2 The comparison.
[0007] However, this existing comparison method inevitably involves a large amount of data movement between flash memory (which stores sample fragments and reference sequences) and DRAM, and this large amount of data movement may become a bottleneck for performance improvement.
[0008] Therefore, improving the performance of data alignment methods that require large amounts of data, such as genome sequence analysis, is one of the industry's key areas of focus. Summary of the Invention
[0009] According to a first aspect of the present invention, a data comparison method is proposed for use in a memory system. The data comparison method includes: performing a pre-screening operation on multiple input data stored in multiple storage cells to pre-screen multiple candidate matching input data and multiple first non-matching input data from the input data; and performing a group test on the candidate matching input data by multiple in-memory search (IMS) units to compare the candidate matching input data with multiple reference data stored in the IMS units to generate a matching result, thereby separating multiple matching input data and a second non-matching input data from the candidate matching input data, wherein the matching result indicates information about the matching input data that matches the reference data, while the second non-matching input data does not match the reference data.
[0010] According to a second aspect of the invention, an in-memory search (IMS) apparatus is provided, comprising: a plurality of IMS memory blocks storing a plurality of reference data; an accumulator coupled to the IMS memory blocks; a selection bit vector generation unit for generating a selection bit vector for selecting a plurality of target IMS memory blocks from the IMS memory blocks, the target IMS memory blocks comparing the reference data with the plurality of input data to generate a plurality of IMS alignment results, the accumulator accumulating the IMS alignment results generated by the target IMS memory blocks; and a checking unit for comparing the selection bit vector with the IMS alignment results to generate an alignment result for identifying a mismatched input data from the input data, wherein the mismatched input data is not matched with the reference data.
[0011] According to a third aspect of the invention, a memory controller is provided, comprising: a control unit coupled to and controlling a plurality of storage cells and a plurality of in-memory search (IMS) devices. The control unit comprises: a search unit; a pre-screening filter coupled to the control unit; and a group of test decoders coupled to the IMS units, wherein the pre-screening filter performs a pre-screening operation on multiple input data stored in the storage units to pre-screen multiple candidate matching input data and multiple first non-matching input data from the input data; the IMS units perform group testing on the candidate matching input data to compare the candidate matching input data with multiple reference data stored in the IMS units to generate a matching result, thereby separating multiple matching input data and a second non-matching input data from the candidate matching input data, wherein the matching result indicates information about the matching input data that matches the reference data, while the second non-matching input data does not match the reference data; and the IMS units send multiple group test results to the group test decoders to obtain a group test decoding result, which is used to identify or indicate the second non-matching input data.
[0012] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description
[0013] Figure 1 This diagram illustrates the comparison of a sample fragment with a reference sequence.
[0014] Figure 2 This diagram illustrates the alignment of sorted sample fragments with a reference sequence.
[0015] Figure 3A functional block diagram of a memory system according to an embodiment of the present invention is shown.
[0016] Figure 4 This illustrates a data comparison method according to an embodiment of the present invention.
[0017] Figure 5 An architecture diagram according to an embodiment of the present invention is shown to illustrate data comparison.
[0018] Figure 6 This diagram illustrates the conversion of data into a binary vector according to an embodiment of the present invention.
[0019] Figure 7 This diagram shows the circuit architecture of an IMS unit according to an embodiment of the present invention.
[0020] Figure 8 This diagram illustrates the operation of an IMS unit according to an embodiment of the present invention.
[0021] Figure 9 A schematic diagram showing IMS operation according to an embodiment of the present invention is displayed.
[0022] Figure 10 This diagram illustrates the generation of the test matrix and the selection of the bit vector in one embodiment of the present invention.
[0023] Figure 11 This diagram illustrates how a mismatched input data is identified from the group test decoding results according to an embodiment of the present invention.
[0024] Explanation of reference numerals in the attached figures:
[0025] A i A i+1 Sample fragment
[0026] B S-2 ~B S+1 Reference sequence
[0027] 300: Memory System
[0028] 340: DRAM
[0029] 350: Host
[0030] 310: Memory controller
[0031] 320: Storage unit
[0032] 330: IMS (In-Memory Search) Unit
[0033] CH1-CHN: Channel
[0034] 311_1-311_N: Flash memory controller
[0035] 313_1-313_N: Pre-screening filters
[0036] 315: Group Test Decoder (GTD)
[0037] 405: Pre-screening operation
[0038] 410: Candidate Matching Input Data
[0039] 420: First mismatched input data
[0040] 430: Match input data
[0041] 440: Second mismatched input data
[0042] 415: Group Test
[0043] 510-560: Steps
[0044] 610, 620: Calculations
[0045] 615, 625: Binary vectors
[0046] 710: IMS memory block
[0047] 720: Page Buffer
[0048] 730: Accumulator
[0049] 740: Word line driver
[0050] 750: Select bit vector generation unit
[0051] 760: Test Matrix Unit
[0052] 770: Inspection Unit
[0053] 410_1~410_4: Candidate matching input data
[0054] 810: Select bit vector
[0055] 820: IMS Results
[0056] 840 and 850: Arithmetic Units
[0057] 910: SSL Switch
[0058] 920: IMS Unit
[0059] 1010: Adder
[0060] 1015: Buffer
[0061] AV: Cumulative Value
[0062] 1020: Multiplexer
[0063] 1030: First-In-First-Out (FIFO) Buffer
[0064] AV_0-AV_2: bits
[0065] RID: Column Identifier
[0066] TM: Test Matrix
[0067] S: Group test results Detailed Implementation
[0068] The technical terms used in this specification are based on common terminology in the field. Where this specification provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions provided in this specification. Each embodiment of this disclosure has one or more technical features. Where feasible, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.
[0069] Figure 3 A functional block diagram of a memory system according to an embodiment of the present invention is shown. Figure 3 As shown, a memory system 300 according to an embodiment of the present invention is coupled to a DRAM 340 and a host 350. The memory system 300 includes a memory controller 310, a plurality of storage cells 320, and a plurality of IMS (in-memory search) units 330. The memory controller 310 is coupled to these storage cells 320 and these IMS units 330 via a plurality of channels CH1-CHN (N being a positive integer). In a possible embodiment of the present invention, these storage cells 320 and these IMS units 330 are, for example, but not limited to, NAND flash memory. These storage cells 320 store a plurality of input data (e.g., but not limited to, sample fragments). These IMS units 330 store a plurality of reference data (e.g., but not limited to, reference sequences).
[0070] The memory controller 310 includes multiple flash memory controllers (also known as control units) 311_1-311_N, multiple pre-seeding filters 313_1-313_N, and a group test decoder (GTD) 315.
[0071] These flash memory controllers 311_1-311_N are coupled to these storage cells 320, these IMS cells 330 and these pre-screening filters 313_1-313_N. These flash memory controllers 311_1-311_N control these storage cells 320 and these IMS cells 330.
[0072] These pre-filters 313_1-313_N pre-filter the input data stored in these storage units 320 to identify the input data that matches these reference data in advance.
[0073] The group test decoder 315 is coupled to the IMS units 330 via the flash memory controllers 311_1-311_N to decode the group test results transmitted from the IMS units 330 and transmit the decoded results to the host 350. In another possible embodiment of the invention, the group test decoder 315 may be located within the NAND flash memory (such as storage unit 320), which is also within the spirit of the invention.
[0074] Figure 4 This illustrates a data comparison method according to an embodiment of the present invention, which can be applied to... Figure 3 The memory system 300.
[0075] like Figure 4 As shown, these pre-screening filters 313_1-313_N perform a pre-screening operation 405 on the input data stored in these storage units 320. By performing a matching test on these input data, they identify input data that are highly likely to match these reference data in advance. After pre-screening, the input data that passes the matching test is considered to be highly likely to match these reference data and is called candidate matching input data 410, while the input data that fails the matching test is called first non-matching input data 420. The reference data stored in these IMS units 330 are unique and will not be repeated. That is, after pre-screening, the input data is classified into candidate matching input data 410 and first non-matching input data 420, wherein candidate matching input data 410 passes the matching test, while first non-matching input data 420 fails the matching test.
[0076] The first mismatched input data 420 is sent to the host 350 for alignment processing. For example, but not limited to, when performing genome sequence analysis, alignment processing can add sample fragments that do not match the reference sequence (such as the first mismatched input data 420) to the reference sequence.
[0077] The candidate matching input data 410 is further subjected to a group test 415 by the IMS unit 330 to match the candidate matching input data 410 with these reference data. After the group test, the candidate matching input data 410 that matches these reference data are referred to as matching input data 430, while the candidate matching input data 410 that does not match these reference data are referred to as second non-matching input data 440. That is, after the group test, the candidate matching input data 410 is classified into matching input data 430 and second non-matching input data 440, where matching input data 430 matches the reference data, and second non-matching input data 440 does not match the reference data.
[0078] The matching results are sent to host 350 for a location query. The matching results include information indicating which input data matches these reference data. In one possible embodiment of the invention, this information includes, for example, but not limited to, which bit lines of the storage block match the reference data.
[0079] Similarly, the second mismatched input data 440 is sent to the host 350 for alignment processing to align the sample fragments (such as the second mismatched input data 440) that do not match the reference sequence to the reference sequence.
[0080] Figure 5 A diagram illustrating an embodiment of the present invention is shown to explain data comparison in this embodiment. Figure 5 Applicable to Figure 3 The memory system 300. Please refer to it as well. Figure 4 and Figure 5 .
[0081] In step 510, the flash memory controllers 311_1-311_N read metadata and input data from the storage cells 320. Here, the metadata includes, but is not limited to, a reference placement scheme and a pre-seeding filter mask. "Reference placement scheme" and "pre-seeding filter mask" are technical terms specifically defined by the inventors in this application. "Reference placement scheme" refers to a table that records the exact location of the matching comparison results. "Pre-seeding filter mask" refers to a pre-seeding filter mask filter (e.g., ...). Figure 3 or Figure 5 The parameters required for a Bloom filter are shown below. For example, the parameters related to the pre-filter mask can be used as a filter vector of the pre-filter mask to filter out most of the mismatched input data as a Bloom filter.
[0082] In step 520, these pre-filters 313_1-313_N perform a pre-filtering operation 405 on the input data stored in these storage units 320 by performing a matching test on the input data to pre-identify input data that may highly match these reference data. The input data that passes the matching test after pre-filtering is referred to as candidate matching input data 410, while the input data that fails the matching test is referred to as first non-matching input data 420.
[0083] In step 530, the flash controllers 311_1-311_N send candidate matching input data 410 to the IMS units 330 for group testing, and send first mismatch input data 420 to the host 350 for alignment processing.
[0084] In step 540, the IMS units 330 perform a group test on the candidate matching input data 410 to match the candidate matching input data 410 with the reference data. After the group test, the candidate matching input data 410 that matches the reference data are referred to as matching input data 430, while the candidate matching input data 410 that does not match the reference data are referred to as second non-matching input data 440.
[0085] In step 550, the IMS units 330 send any mismatch check results (also known as group test results) from the group test to the group test decoder 315 via the flash memory controller to decode the group test results transmitted by the IMS units 330, and the group test decoder 315 generates the group test decoding result to identify or indicate the second mismatch input data 440.
[0086] In step 560, the group test decoder 315 sends the group test decoding result back to the flash memory controllers 311_1-311_N, so that the flash memory controllers 311_1-311_N can transmit the matching result and the second non-matching input data 440 to the host 350, wherein the matching result includes information indicating which input data matches the reference data.
[0087] Figure 6 This diagram illustrates the conversion of data into a binary vector according to an embodiment of the present invention. Figure 6As shown, a first operation 610 is performed on the input data to obtain a binary vector 615 of the input data. Similarly, a second operation 620 is performed on the reference data to obtain a binary vector 625 of the reference data. The first operation 610 on the input data and the second operation 620 on the reference data can be performed offline. The first operation 610 and the second operation 620 include, but are not limited to, hash functions and modulo functions.
[0088] In one embodiment of the present invention, the pre-screening operation is used to pre-identify input data that passes the matching test. Generally, if the binary vector 615 of the input data is equal to the binary vector 625 of the reference data, the input data is considered to have passed the matching test, meaning that the input data has a high probability of matching the reference data. As mentioned above, the input data that passes the matching test is called candidate matching input data (410). On the other hand, if the binary vector 615 of the input data is not equal to the binary vector 625 of the reference data, the input data fails the matching test, and the input data that fails the matching test is called the first non-matching input data (420). However, there may still be a low probability that the candidate matching input data is different (non-matching) from the reference data. That is, such a judgment result may still include a small number of false positive input data, that is, although the binary vector 615 is equal to the binary vector 625, the input data is actually different from the reference data. Such input data is called false positive input data.
[0089] The architecture of the IMS unit 330 in one embodiment of the present invention and the details of group testing will be described below.
[0090] Figure 7 This diagram shows a circuit architecture of an IMS unit 330 according to one embodiment of the present invention. In one possible embodiment, the IMS unit 330 may be a three-dimensional architecture, such as, but not limited to, a 3D NAND flash memory architecture or a 3D NOR flash memory architecture. Figure 7 As shown, the IMS unit 330 in one embodiment of the present invention includes: a plurality of IMS memory blocks 710, a page buffer 720, an accumulator 730, a word line driver 740, a selection bit vector generation unit 750, a test matrix unit 760, and a checking unit 770.
[0091] These IMS memory blocks 710 are used to store this reference data. Each IMS memory block 710 stores the same reference data.
[0092] Page buffer 720 is coupled to these IMS memory blocks 710 to sense IMS comparison results.
[0093] Accumulator 730 is coupled to these IMS memory blocks 710 to accumulate these IMS alignment results.
[0094] Word line drivers 740 are coupled to these IMS memory blocks 710 to input candidate matching input data 410 of the input data into these IMS memory blocks 710. In other possible embodiments of the invention, other search architectures that can access multiple input data simultaneously may also be employed, and the invention is not limited thereto.
[0095] The selection bit vector generation unit 750 generates a selection bit vector based on the test matrix to control whether these IMS memory blocks 710 are selected (activated) during the group test. That is, the selection bit vector is used to select these IMS memory blocks 710 to become multiple target IMS memory blocks 710, which are used to compare the reference data with multiple input data to generate multiple IMS alignment results. IMS memory blocks that are not selected will not be compared with the reference data and the input data.
[0096] The test matrix unit 760 is used to set the test matrix. In one embodiment of the present invention, the test matrix can be generated using a lookup table method or an ASIC (Application-Specific Integrated Circuit).
[0097] The checking unit 770 is coupled to the accumulator 730 to compare these IMS alignment results with the selected bit vector. For example, but not limited to, the checking unit 770 compares the checksum of these IMS alignment results with the checksum of the selected bit vector.
[0098] Therefore, it is possible to determine whether the candidate matching input data 410 matches these reference data.
[0099] Figure 8 This diagram illustrates the operation of an IMS unit 330 according to an embodiment of the present invention. Figure 8 As shown, the selection bit vector 810 controls whether these IMS memory blocks 710 are selected (activated) during the group test. These IMS memory blocks 710 respectively receive candidate matching input data 410_1 to 410_4.
[0100] After IMS, these IMS memory blocks 710 output IMS results 820 (i.e., matching results) for the candidate matching input data 410_1 to 410_4, respectively. That is, for the selected (activated) IMS memory block 710, if any candidate matching input data 410 matches the reference data of the IMS memory block 710, then the IMS memory block 710 outputs a first IMS result (e.g., but not limited to logic 1); and if none of the candidate matching input data 410 matches the reference data of the IMS memory block 710, then the IMS memory block 710 outputs a second IMS result (e.g., but not limited to logic 0).
[0101] The selected bit vector 810 and the IMS result 820 are processed by operation units 840 and 850 respectively to obtain the checksum of the selected bit vector 810 and the checksum of the IMS result 820. The checking unit 770 compares whether the checksum of the IMS result 820 matches the checksum of the selected bit vector 810. If the checksum of the IMS result 820 matches the checksum of the selected bit vector 810, the checking unit 770 outputs a first group test result S (e.g., but not limited to logic 1); and if the checksum of the IMS result 820 does not match the checksum of the selected bit vector 810, the checking unit 770 outputs a second group test result S (e.g., but not limited to logic 0). The group test result S is sent by the checking unit 770 to GTD 315.
[0102] Figure 9 A schematic diagram illustrating IMS operation according to an embodiment of the present invention is shown. For example... Figure 9 As shown, individual bits of these selection bit vectors 810 are used as string select line (SSL) input signals to control whether these IMS memory blocks 710 are selected (activated) during the group test. That is, a first selection bit of these selection bit vectors 810 is input to the SSL switch 910 of a first IMS memory block 710 to control whether the first IMS memory block 710 is selected (activated) during the group test. For example, when the first selection bit is logic 1, the SSL switch 910 of the first IMS memory block is turned on, so the first IMS memory block 710 is selected (activated) during the group test; and when the first selection bit is logic 0, the SSL switch 910 of the first IMS memory block 710 is turned off, so the first IMS memory block 710 is not selected (not activated) during the group test.
[0103] When the first IMS memory block 710 is selected, the plurality of IMS cells 920 of the first IMS memory block 710 output induced currents to the page buffer 720. The page buffer 720 generates an IMS result 820 based on these induced currents.
[0104] Figure 10 This diagram illustrates the generation of the test matrix and the selection of the bit vector in one embodiment of the present invention. Figure 10 The components are located within the IMS unit 330. Figure 10 One possible example of the test matrix is shown, but it is understood that the invention is not limited thereto. Initially, the accumulated value AV temporarily stored in buffer 1015 is, for example, but not limited to, 000. After each cycle, adder 1010 adds the accumulated value AV to an accumulated reference value (for example, but not limited to, 1) to produce an updated accumulated value AV. Buffer 1015 is coupled to adder 1010.
[0105] The accumulated value AV in buffer 1015 is output to multiplexer 1020. Multiplexer 1020 is coupled to buffer 1015. Multiplexer 1020 selects one bit from the accumulated value AV based on the row ID (RID) to output to first-in-first-out (FIFO) buffer 1030. For example, when row ID (RID) = 2, multiplexer 1020 selects bit AV_2 from the accumulated value AV to output to FIFO buffer 1030; when row ID (RID) = 1, multiplexer 1020 selects bit AV_1 from the accumulated value AV to output to FIFO buffer 1030; and when row ID (RID) = 0, multiplexer 1020 selects bit AV_0 from the accumulated value AV to output to FIFO buffer 1030.
[0106] The first-in-first-out (FIFO) buffer 1030 is coupled to the multiplexer 1020. The FIFO buffer 1030 temporarily stores the selection bits output by the multiplexer 1020 and treats them as the selection bit vector 810.
[0107] The details of generating the selection bit vector 810 will now be explained. It is assumed here that the column identifier RID=2, but it should be understood that the invention is not limited thereto.
[0108] During the first cycle, the accumulated value AV is 000. The multiplexer 1020 selects bit AV_2 (=0) from the multiple bits of the accumulated value AV to output to the first-in-first-out buffer 1030. Therefore, the first bit of the selected bit vector 810 is 0.
[0109] During the second cycle, the accumulated value AV is 001. The multiplexer 1020 selects bit AV_2 (=0) from the multiple bits of the accumulated value AV to output to the first-in-first-out buffer 1030. Therefore, the second bit of the selected bit vector 810 is 0.
[0110] During the third cycle, the accumulated value AV is 010. The multiplexer 1020 selects bit AV_2 (=0) from the multiple bits of the accumulated value AV to output to the first-in-first-out buffer 1030. Therefore, the third bit of the selected bit vector 810 is 0.
[0111] During the 4th cycle, the accumulated value AV is 011. The multiplexer 1020 selects bit AV_2 (=0) from the multiple bits of the accumulated value AV to output to the first-in-first-out buffer 1030. Therefore, the fourth bit of the selected bit vector 810 is 0.
[0112] In the 5th cycle, the accumulated value AV is 100. The multiplexer 1020 selects bit AV_2 (=1) from the multiple bits of the accumulated value AV to output to the first-in-first-out buffer 1030. Therefore, the fifth bit of the bit vector 810 is selected as 1.
[0113] At the 6th cycle, the accumulated value AV is 101. The multiplexer 1020 selects bit AV_2 (=1) from the multiple bits of the accumulated value AV to output to the first-in-first-out buffer 1030. Therefore, the sixth bit of the bit vector 810 is selected as 1.
[0114] At the 7th cycle, the accumulated value AV is 110. The multiplexer 1020 selects bit AV_2 (=1) from the multiple bits of the accumulated value AV to output to the first-in-first-out buffer 1030. Therefore, the seventh bit of the bit vector 810 is selected as 1.
[0115] At the 8th cycle, the accumulated value AV is 111. The multiplexer 1020 selects bit AV_2 (=1) from the multiple bits of the accumulated value AV to output to the first-in-first-out buffer 1030. Therefore, the eighth bit of the bit vector 810 is selected as 1.
[0116] Therefore, the resulting selection bit vector 810 is 00001111.
[0117] After each comparison round (i.e., each group test), the checking unit 770 generates a 1-bit comparison result S and sends it to the GTD 315. The number of comparison rounds required to find mismatched input data depends on the number of input data. For example, when the number of input data is N (N is the number of samples), at least log(N) comparison rounds are required to find mismatched input data.
[0118] Figure 11This diagram illustrates how mismatched input data is identified from the group test decoding results according to an embodiment of the present invention. Figure 11 As shown, assuming the sample size is 8, after 3 group tests, 3 group test results S can be obtained. Assuming these 3 group test results S = 110, then according to the test matrix TM, GTD 315 can decode that the 7th input data (i.e., the 7th sample) does not match the reference data. GTD 315 can then send the group test decoding result (indicating that the 7th input data (i.e., the 7th sample) does not match the reference data) to host 350. Host 350 performs alignment processing based on this, and then aligns the 7th input data (i.e., the 7th sample) that does not match the reference data to the reference data (reference sequence).
[0119] As described above, in one embodiment of the present invention, performing matching detection within the memory eliminates the need for externally loading reference sequences, thereby reducing the performance bottleneck caused by large-scale data migration. Furthermore, in one embodiment of the present invention, using group testing technology can significantly reduce the amount of data movement and improve energy efficiency.
[0120] In one embodiment of the invention, swarm testing is applied to accelerate the precise match filtering process, thereby speeding up genome sequence analysis.
[0121] The data comparison method of this invention can be applied to a variety of fields, such as, but not limited to, keyword comparison of spam, detection of inherited diseases, and gene alignment.
[0122] The data comparison method of this invention can reduce the number of samples in group testing and further improve data comparison efficiency.
[0123] The foregoing primarily describes the solutions provided in the embodiments of this application from the perspective of the memory controller. It is understood that, to achieve the above functions, the memory controller may include corresponding hardware structures and / or software modules that perform the functions. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the embodiments described in this specification, this application can be implemented in hardware or firmware form. Whether the functionality is executed in hardware or firmware form depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the functions described in each specific application, but such implementations should not be considered beyond the scope of this application.
[0124] In one embodiment of this application, the memory controller can also be divided into functional modules based on the aforementioned method examples. For example, it can be divided according to each corresponding function to obtain each functional module, or two or more functions can be integrated into one processing module. It should be noted that the division into modules in the embodiments of this application is merely an example and represents a logical functional division. In actual implementation, other division methods can be used. The present invention is not limited thereto.
[0125] While the invention may describe many specific details, these should not be construed as limiting the scope of the claimed invention, but rather as descriptions of the characteristics of particular embodiments. In this description, certain features described in the context of a single embodiment may also be implemented in combination in that single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, while features may initially be described as functioning in certain combinations, or even initially described as such combinations, in some cases one or more features may be removed from that combination, and the described combination may be for a sub-combination or a variation thereof. Similarly, while operations are depicted in the figures as being performed in a specific order, this should not be construed as requiring these operations to be performed in the specific order or sequence shown, or that all depicted operations must be performed to achieve the desired result.
[0126] Although the above embodiments of the present invention only disclose some examples and implementations, changes, modifications, and enhancements can be made to the examples, implementations, and other implementations based on the disclosed content.
[0127] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
Claims
1. A data comparison method applied to a memory system, the data comparison method comprising: A pre-filtering operation is performed on multiple input data stored in multiple storage units to pre-filter out multiple candidate matching input data and multiple first non-matching input data from these input data; as well as Multiple in-memory search (IMS) units perform a group test on these candidate matching input data to compare these candidate matching input data with multiple reference data stored in these IMS units to generate a matching result, thereby separating multiple matching input data and a second non-matching input data from these candidate matching input data, wherein the matching result indicates information about the matching input data that matches the reference data, while the second non-matching input data does not match the reference data.
2. The data comparison method according to claim 1, wherein, These candidate matching input data match these reference data, while these first non-matching input data do not match these reference data; These first mismatched input data are sent to the host for alignment processing; The matching result is sent to the host for location lookup. as well as The second mismatched input data is sent to the host for alignment processing.
3. The data comparison method according to claim 1 further includes: Multiple control units read multiple metadata and these input data from these storage units.
4. The data comparison method according to claim 3 further includes: These control units send the candidate matching input data to these IMS units for group testing, and send the first mismatch input data to the host for alignment processing.
5. An in-memory search (IMS) device, comprising: Multiple IMS memory blocks store multiple reference data; An accumulator is coupled to these IMS memory blocks; A selection bit vector generation unit is used to generate a selection bit vector for selecting multiple target IMS memory blocks from these IMS memory blocks. These target IMS memory blocks compare these reference data with multiple input data to generate multiple IMS alignment results. The accumulator accumulates these IMS alignment results generated by these target IMS memory blocks. as well as A checking unit is used to compare the selected bit vector with these IMS alignment results to generate an alignment result, which is used to find a mismatched input data from these input data, wherein the mismatched input data does not match these reference data.
6. The memory search device according to claim 5, further comprising: A test matrix unit is used to set a test matrix, and the selection bit vector generation unit generates the selection bit vector based on the test matrix.
7. The memory search device according to claim 5, wherein, Multiple bits of the selection bit vector are used as a series of selection line input signals to control whether these IMS memory blocks are selected as these target IMS memory blocks in a group of tests.
8. A memory controller, comprising: A control unit is coupled to and controls multiple storage units and multiple in-memory search (IMS) units; A pre-screening filter is coupled to the control unit; as well as A group of test decoders are coupled to these IMS units. in, The pre-filter performs a pre-filtering operation on multiple input data stored in these storage units to pre-filter multiple candidate matching input data and multiple first non-matching input data from these input data; These IMS units perform a group test on the candidate matching input data to compare the candidate matching input data with multiple reference data stored in these IMS units to generate a matching result, thereby separating multiple matching input data and a second non-matching input data from the candidate matching input data. The matching result indicates information about the matching input data that matches the reference data, while the second non-matching input data does not match the reference data. These IMS units send multiple group test results to the group test decoder to obtain a group test decoding result, which is used to identify or indicate the second mismatched input data.
9. The memory controller according to claim 8, wherein, These candidate matching input data match these reference data, while these first non-matching input data do not match these reference data; These first mismatched input data are sent to the host for alignment processing; The matching result is sent to the host for location lookup. as well as The second mismatched input data is sent to the host for alignment processing.
10. The memory controller according to claim 8, wherein: The control unit reads multiple metadata from these storage units along with these input data.