Amplifier, integrator and modulator based on inverter structure

Abstract

The invention discloses an amplifier based on an inverter structure, an integrator and a modulator, and the amplifier comprises an inverter body which is used for amplifying an input signal when the amplifier is in an amplification stage; the bias unit is used for providing bias current for the phase inverter body when the amplifier is in the zero setting stage and establishing stable bias voltage on the phase inverter body; the zeroing storage unit is used for storing the bias voltage when the amplifier is in the zeroing stage and maintaining the stability of the bias voltage when the amplifier is in the amplification stage, so that the inverter body has a stable working point in the amplification stage; and the switching unit is used for controlling the working states of the bias unit, the zeroing storage unit and the inverter body through non-overlapping clock signals, so that the amplifier is switched between a zeroing stage and an amplifying stage. According to the invention, the problems of uncontrollable bias voltage, low gain and noise caused by mismatch of transistors of a traditional inverter amplifier are solved, and the inverter amplifier has the advantages of high zero setting speed, stable working point, low power consumption and the like.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an amplifier, integrator, and modulator based on an inverter structure. Background Technology

[0002] Incremental Delta-Sigma ADCs (IADCs) are one of the ideal ADC architecture choices for high-precision analog-to-digital (AD) conversion of signals generated by focal plane arrays such as CMOS and CCD image sensors. In recent years, the traditional CMOS operational amplifiers used in the analog signal integrators of the architecture have been replaced with inverter-based circuit structures, further reducing their power consumption and area, making IADCs more attractive in focal plane array readout circuit applications.

[0003] In practical applications of IADC based on inverter amplifiers, the classic dual CMOS transistor inverter has three problems, which makes it rarely used directly in circuit design: First, due to the uncontrolled bias voltage, it has poor resistance to process-voltage-temperature variation (PVT) and unstable operation. Second, the gain provided by the amplifier structure is low and cannot meet the requirements of AD conversion with 12-bit and above precision. Third, because the transistor fabrication size cannot be guaranteed to be completely consistent, the DC operating point of all amplifiers of the same specification on the chip is not uniform ("mismatch"), which introduces fixed-mode noise and reduces the quality of digitized images. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide an amplifier, integrator and modulator based on inverter structure that can break through the application bottleneck of traditional classic inverters.

[0005] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is to provide an amplifier based on an inverter structure, comprising: The inverter body is used to amplify the input signal when the amplifier is in the amplification stage; The bias unit is used to provide bias current to the inverter body when the amplifier is in the zero-adjustment stage, and to establish a stable bias voltage in the inverter body. The zero-adjustment storage unit is used to store the bias voltage of the inverter body when the amplifier is in the zero-adjustment stage, and to maintain the stability of the bias voltage when the amplifier is in the amplification stage, so that the inverter body has a stable operating point in the amplification stage. The switching unit is used to control the working state of the bias unit, the zero-adjustment storage unit and the inverter body through a non-overlapping clock signal, so that the amplifier switches between the zero-adjustment stage and the amplification stage, thereby achieving isolation between the zero-adjustment stage and the amplification stage.

[0006] Furthermore, the inverter body includes a first PMOS transistor 101 and a first NMOS transistor 102; the gate of the first PMOS transistor 101 serves as the first input terminal of the inverter body and is electrically connected to the first output terminal of the zero-adjustment memory unit, the source of the first PMOS transistor 101 is connected to a power supply, and the drain of the first PMOS transistor 101 is electrically connected to the first terminal of the switching unit; the gate of the first NMOS transistor 102 serves as the second input terminal of the inverter body and is electrically connected to the second output terminal of the zero-adjustment memory unit, the source of the first NMOS transistor 102 is grounded, and the drain of the first NMOS transistor 102 is electrically connected to the second terminal of the switching unit; the drain of the first PMOS transistor 101 or the drain of the first NMOS transistor 102 serves as the output terminal of the inverter body to output the amplified signal; The bias unit includes a second PMOS transistor 103 and a second NMOS transistor 104; the gate of the second PMOS transistor 103 serves as the first input terminal of the bias unit and is connected to an external bias voltage, the source of the second PMOS transistor 103 is connected to a power supply, and the drain of the second PMOS transistor 103 is electrically connected to the third terminal of the switching unit; the gate of the second NMOS transistor 104 serves as the second input terminal of the bias unit and is connected to an external bias voltage, the source of the second NMOS transistor 104 is grounded, and the drain of the second NMOS transistor 104 is electrically connected to the fourth terminal of the switching unit.

[0007] Furthermore, the zero-adjustment storage unit includes a first capacitor 111 and a second capacitor 112; the first plate of the first capacitor 111 and the first plate of the second capacitor 112 are electrically connected as the input terminal of the zero-adjustment storage unit, inputting the common-mode voltage of the amplifier during the zero-adjustment stage and the signal to be amplified during the amplification stage; the second plate of the first capacitor 111 serves as the first output terminal of the zero-adjustment storage unit and is electrically connected to the gate of the first PMOS transistor 101, and the second plate of the second capacitor 112 serves as the second output terminal of the zero-adjustment storage unit and is electrically connected to the gate of the first NMOS transistor 102.

[0008] Furthermore, the switching unit includes a first switch 121, a second switch 122, a third switch 123, a fourth switch 124, and a fifth switch 125; the first terminal of the first switch 121 is electrically connected to the first terminal of the third switch 123, serving as the first terminal of the switching unit and electrically connected to the drain of the first PMOS transistor 101; the second terminal of the first switch 121 is electrically connected to the gate of the first PMOS transistor 101; the first terminal of the second switch 122 is electrically connected to the second terminal of the third switch 123, serving as the second terminal of the switching unit and electrically connected to the gate of the first NMOS transistor 101. The drain of the OS transistor 102 is electrically connected, and the second terminal of the second switch 122 is electrically connected to the gate of the first NMOS transistor 102; the first terminal of the fourth switch 124 is electrically connected to the second terminal of the third switch 123, and the second terminal of the fourth switch 124 serves as the third terminal of the switching unit and is electrically connected to the drain of the second PMOS transistor 103; the first terminal of the fifth switch 125 is electrically connected to the first terminal of the third switch 123, and the second terminal of the fifth switch 125 serves as the fourth terminal of the switching unit and is electrically connected to the drain of the second NMOS transistor 104.

[0009] Furthermore, the inverter body also includes a third PMOS transistor 202 and a third NMOS transistor 203; the switching unit also includes a sixth switch 221, a seventh switch 222, an eighth switch 223, and a ninth switch 224; the source of the third PMOS transistor 202 is electrically connected to the drain of the first PMOS transistor 101, the drain of the third PMOS transistor 202 is electrically connected to the first terminal of the third switch 123, and the gate of the third PMOS transistor 202 is electrically connected to the second terminal of the sixth switch 221; the first terminal of the sixth switch 221 is electrically connected to the gate of the first PMOS transistor 101, and the sixth switch 221... The second terminal of switch 1 is electrically connected to the first terminal of the seventh switch 222, and the second terminal of the seventh switch 222 is grounded; the source of the third NMOS transistor 203 is electrically connected to the drain of the first NMOS transistor 102, the drain of the third NMOS transistor 203 is electrically connected to the second terminal of the third switch 123, and the gate of the third NMOS transistor 203 is electrically connected to the second terminal of the ninth switch 224; the first terminal of the ninth switch 224 is electrically connected to the gate of the first NMOS transistor 102, the second terminal of the ninth switch 224 is electrically connected to the first terminal of the eighth switch 223, and the second terminal of the eighth switch 223 is connected to a power supply.

[0010] Furthermore, the inverter body also includes a fourth PMOS transistor 301 and a fourth NMOS transistor 304; the switching unit also includes a tenth switch 321, an eleventh switch 322, a twelfth switch 323, and a thirteenth switch 324; the source of the fourth PMOS transistor 301 is connected to a power supply, the drain of the fourth PMOS transistor 301 is electrically connected to the source of the first PMOS transistor 101, and the gate of the fourth PMOS transistor 301 is electrically connected to the first terminal of the tenth switch 321 and the first terminal of the twelfth switch 323, respectively. The second terminal is grounded, and the second terminal of the twelfth switch 323 is electrically connected to the gate of the first PMOS transistor 101; the source of the fourth NMOS transistor 304 is grounded, the drain of the fourth NMOS transistor 304 is electrically connected to the source of the first NMOS transistor 102, the gate of the fourth NMOS transistor 304 is electrically connected to the first terminal of the eleventh switch 322 and the first terminal of the thirteenth switch 324 respectively, the second terminal of the eleventh switch 322 is connected to the power supply, and the second terminal of the thirteenth switch 324 is electrically connected to the gate of the first NMOS transistor 102.

[0011] Furthermore, the inverter body also includes a fifth PMOS transistor 401 and a fifth NMOS transistor 402; the switching unit also includes a fourteenth switch 422 and a fifteenth switch 423; the source of the fifth PMOS transistor 401 is connected to a power supply, the gate of the fifth PMOS transistor 401 is electrically connected to the second plate of the first capacitor 111, and the drain of the fifth PMOS transistor 401 is electrically connected to the first terminal of the third switch 123; the source of the fifth NMOS transistor 402 is grounded, and the gate of the fifth NMOS transistor 402... The drain of the fifth NMOS transistor 402 is electrically connected to the second plate of the second capacitor 112, and the drain of the fifth NMOS transistor 402 is electrically connected to the second terminal of the third switch 123; the first terminal of the fourteenth switch 422 is electrically connected to the first terminal of the third switch 123; the second terminal of the fourteenth switch 422 is electrically connected to the drain of the first PMOS transistor 101; the first terminal of the fifteenth switch 423 is electrically connected to the second terminal of the third switch 123, and the second terminal of the fifteenth switch 423 is electrically connected to the drain of the first NMOS transistor 102.

[0012] Furthermore, the inverter body also includes a sixth PMOS transistor 503 and a sixth NMOS transistor 504; the switching unit also includes a sixteenth switch 524 and a seventeenth switch 525; the source of the sixth PMOS transistor 503 is connected to a power supply, the gate of the sixth PMOS transistor 503 is electrically connected to the gate of the first PMOS transistor 101, the drain of the sixth PMOS transistor 503 is electrically connected to the second terminal of the sixteenth switch 524, and the first terminal of the sixteenth switch 524 is electrically connected to the first terminal of the third switch 123; the source of the sixth NMOS transistor 504 is grounded, the gate of the sixth NMOS transistor 504 is electrically connected to the gate of the first NMOS transistor 102, the drain of the sixth NMOS transistor 504 is electrically connected to the second terminal of the seventeenth switch 525, and the first terminal of the seventeenth switch 525 is electrically connected to the second terminal of the third switch 123.

[0013] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide an integrator, including the amplifier based on the inverter structure.

[0014] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is to provide a modulator, including the amplifier based on the inverter structure.

[0015] The amplifier, integrator, and modulator based on the inverter structure of the present invention have at least the following beneficial effects: The present invention stores the inverter bias voltage during the zero-adjustment stage through a zero-adjustment storage unit, and, in conjunction with precise timing control of a non-overlapping clock, achieves physical isolation between the zero-adjustment stage and the amplification stage. After the bias voltage storage is completed, by disconnecting the relevant switches and closing the third switch, it ensures that the inverter operating point during the amplification stage is completely maintained by the zero-adjustment storage unit and is not affected by PVT fluctuations. By adding biases to the two transistors in the inverter body respectively, the high-impedance wire network nodes of the inverter are avoided from participating in the zero-adjustment process, thereby significantly improving the zero-adjustment speed, which is beneficial to improving the working stability of the integrator in the IADC, and thus improving the IADC performance and resistance to PVT changes. By precisely controlling the non-overlapping clock to actively establish and store a stable bias voltage during the zero-adjustment stage, the high-impedance state of the inverter body input terminal and the mismatch and accuracy degradation caused by the slow establishment of bias by leakage current during the zero-adjustment stage are eliminated, ensuring... The amplifier exhibits a highly stable operating point during the amplification phase, suppressing mismatch noise. Furthermore, due to the stable and consistent operating point, the inverter itself can achieve higher open-loop gain during amplification, adapting to low supply voltages. The input external bias voltage terminals in the bias unit are not directly connected to any switch, preventing significant charging and discharging of the input external bias voltage network during switching operations, thus maintaining stability. This is particularly suitable for applications with harsh input bias voltage driven load environments, such as focal plane array readout circuits. By further splitting the transistors within the inverter body before biasing, the supply current remains consistent across all driving clock phases while the current bias remains constant during the amplification phase, further reducing power consumption. The amplifier's fast and stable zeroing and amplification characteristics directly improve the dynamic range, conversion accuracy, and energy efficiency of the integrator and modulator containing this amplifier, demonstrating significant engineering application value. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a structural block diagram of an embodiment of the amplifier based on the inverter structure of the present invention.

[0017] Figure 2 This is a circuit diagram of one embodiment of the amplifier based on the inverter structure of the present invention.

[0018] Figure 3 The timing waveform diagram is for non-overlapping clock signals.

[0019] Figure 4This is a circuit diagram of another embodiment of the amplifier based on the inverter structure of the present invention.

[0020] Figure 5 This is a circuit diagram of another embodiment of the amplifier based on the inverter structure of the present invention.

[0021] Figure 6 This is a circuit diagram of another embodiment of the amplifier based on the inverter structure of the present invention.

[0022] Figure 7 This is a circuit diagram of another embodiment of the amplifier based on the inverter structure of the present invention.

[0023] Figure 8 This is a circuit diagram of one embodiment of the integrator of the present invention.

[0024] Figure 9 for Figure 8 The diagram shows the operation of the integrator's input and output terminals under non-overlapping clock drive.

[0025] Figure 10 This is a circuit diagram of one embodiment of the modulator of the present invention.

[0026] Figure 11 for Figure 10 The diagram shows a typical working schematic of the modulator. Detailed Implementation

[0027] The invention will now be further described with reference to the accompanying drawings.

[0028] The inverter-based amplifier of this invention can be applied to applications such as incremental analog-to-digital converters (IADCs) that require integrators driven by non-overlapping clock signals. Used as an amplifier within an integrator, it operates in two states: a zero-adjustment phase and an amplification phase. The switching between these states is controlled by a non-overlapping clock signal. This non-overlapping clock signal includes a zero-adjustment phase (hereinafter referred to as the first phase) and an amplification phase (hereinafter referred to as the second phase). There is a delay between the high-level transition of the zero-adjustment phase and the high-level transition of the amplification phase, and the two phases do not overlap in time.

[0029] Please see Figures 1 to 3The amplifier A based on an inverter structure of the present invention includes an inverter body 1, a bias unit 2, a zero-adjustment storage unit 3, and a switching unit 4. The inverter body 1 amplifies the input signal when the amplifier is in the amplification phase. The bias unit 2 provides bias current to the inverter body 1 when the amplifier is in the zero-adjustment phase, establishing a stable bias voltage in the inverter body 1. The zero-adjustment storage unit 3 stores the bias voltage of the inverter body 1 when the amplifier is in the zero-adjustment phase and maintains the stability of the bias voltage when the amplifier is in the amplification phase, ensuring a stable operating point for the inverter body 1 during the amplification phase. The switching unit 4 controls the operating states of the bias unit 2, the zero-adjustment storage unit 3, and the inverter body 1 through a non-overlapping clock signal, switching the amplifier between the zero-adjustment phase and the amplification phase, thus achieving isolation between the zero-adjustment phase and the amplification phase.

[0030] The inverter body 1 includes a first PMOS transistor 101 and a first NMOS transistor 102. The gate of the first PMOS transistor 101 serves as the first input terminal of the inverter body 1 and is electrically connected to the first output terminal of the zero-adjustment memory unit 3. The source of the first PMOS transistor 101 is connected to a power supply, and the drain of the first PMOS transistor 101 is electrically connected to the first terminal of the switching unit 4. The gate of the first NMOS transistor 102 serves as the second input terminal of the inverter body 1 and is electrically connected to the second output terminal of the zero-adjustment memory unit 3. The source of the first NMOS transistor 102 is grounded, and the drain of the first NMOS transistor 102 is electrically connected to the second terminal of the switching unit 4. The drain of either the first PMOS transistor 101 or the drain of the first NMOS transistor 102 serves as the output terminal of the inverter body 1, outputting an amplified signal. In this embodiment, either the drain connection network 134 of the first NMOS transistor 102 or the drain connection network 135 of the first PMOS transistor 101 can serve as the output terminal of the inverter body 1, outputting an amplified signal during the amplification stage.

[0031] The bias unit 2 includes a second PMOS transistor 103 and a second NMOS transistor 104. The gate of the second PMOS transistor 103 serves as the first input terminal 132 of the bias unit 2, which is connected to an external bias voltage. The source of the second PMOS transistor 103 is connected to a power supply, and the drain of the second PMOS transistor 103 is electrically connected to the third terminal of the switching unit 4. The gate of the second NMOS transistor 104 serves as the second input terminal 133 of the bias unit 2, which is connected to an external bias voltage. The source of the second NMOS transistor 104 is grounded, and the drain of the second NMOS transistor 104 is electrically connected to the fourth terminal of the switching unit 4.

[0032] The zero-adjustment storage unit 3 includes a first capacitor 111 and a second capacitor 112. The first plate of the first capacitor 111 is electrically connected to the first plate of the second capacitor 112, serving as the input terminal 131 of the zero-adjustment storage unit 3. During the zero-adjustment phase, it inputs the common-mode voltage of the amplifier; during the amplification phase, it inputs the signal to be amplified. The second plate of the first capacitor 111 serves as the first output terminal of the zero-adjustment storage unit 3 and is electrically connected to the gate of the first PMOS transistor 101. The second plate of the second capacitor 112 serves as the second output terminal of the zero-adjustment storage unit 3 and is electrically connected to the gate of the first NMOS transistor 102.

[0033] The switching unit 4 includes a first switch 121, a second switch 122, a third switch 123, a fourth switch 124, and a fifth switch 125. The first terminal of the first switch 121 is electrically connected to the first terminal of the third switch 123, serving as the first terminal of the switching unit 4 and electrically connected to the drain of the first PMOS transistor 101. The second terminal of the first switch 121 is electrically connected to the gate of the first PMOS transistor 101. The first terminal of the second switch 122 is electrically connected to the second terminal of the third switch 123, serving as the second terminal of the switching unit 4 and electrically connected to the drain of the first NMOS transistor 102. The second terminal of the second switch 122 is electrically connected to the gate of the first NMOS transistor 102. The first terminal of the fourth switch 124 is electrically connected to the second terminal of the third switch 123, and the second terminal of the fourth switch 124 serves as the third terminal of the switching unit 4 and is electrically connected to the drain of the second PMOS transistor 103. The first terminal of the fifth switch 125 is electrically connected to the first terminal of the third switch 123, and the second terminal of the fifth switch 125 serves as the fourth terminal of the switching unit 4 and is electrically connected to the drain of the second NMOS transistor 104. All switches in the switching unit 4 are controlled by a non-overlapping clock signal (hereinafter referred to as the clock). The first switch 121, the second switch 122, the fourth switch 124, and the fifth switch 125 are closed when the first phase φ1 of the clock is high and open when it is low. The third switch 123 is closed when the first delay phase φ1 of the clock is low. 1D When the voltage level is high, the circuit is open; when the voltage level is low, the circuit is closed (equivalent to switch 123 at φ). 1D_BAR Disconnect when φ is low. 1D_BAR When the signal is high, the circuit is closed; the following text is affected by φ. 1D_BAR The same applies to the controller. After φ1 goes low, φ 1D It will maintain a high level for a short period of time. This crucial delay is to ensure that after φ1 is turned off, all switches controlled by φ1 are completely disconnected, and the high level is maintained. 1D Only when the controlled switch can it operate; this safety interval ensures the stability of phase switching. Additionally, Figure 3 φ in 1D_BAR It is φ 1DThe inverted signal, φ 1D_BAR The level state and φ 1D Conversely, when φ 1D When it is high, φ 1D_BAR A low level indicates a low voltage level, and vice versa.

[0034] In this embodiment, the operation of amplifier A based on the inverter structure is as follows: First, the clock enters the first phase φ1. The input terminal 131 of the zero-adjustment storage unit 3 inputs the common-mode voltage of the amplifier. The first switch 121, the second switch 122, the fourth switch 124, and the fifth switch 125 are closed, and the third switch 123 is opened. The second NMOS transistor 104 provides bias current to the first PMOS transistor 101. The bias voltage of the first PMOS transistor 101 formed by feedback falls on its gate, and the zero-adjustment information is stored in the first capacitor 111. The second PMOS transistor 103 provides bias current to the first NMOS transistor 102. The bias voltage of the first NMOS transistor 102 formed by feedback falls on its gate, and the zero-adjustment information is stored in the second capacitor 112. When the first phase φ1 ends and zeroing is completed, firstly, the first switch 121, the second switch 122, the fourth switch 124, and the fifth switch 125 are disconnected, cutting off the connection between the second PMOS transistor 103 and the first NMOS transistor 102, and the connection between the second NMOS transistor 104 and the first PMOS transistor 101. The gate bias voltage obtained by the first PMOS transistor 101 is maintained on the second plate of the first capacitor 111, and the gate bias voltage obtained by the first NMOS transistor 102 is maintained on the second plate of the second capacitor 112. Then, the third switch 123 is closed, connecting the drains of the first PMOS transistor 101 and the first NMOS transistor 102, forming a dual-transistor inverter with a stable bias voltage and eliminating mismatch. Then, a valid signal to be amplified is input at the input terminal 131 of the zeroing storage unit 3 during the second phase φ2 of the clock, and the amplified output signal is obtained at the output terminal of the inverter body 1. After the second phase φ2 ends, the first phase φ1 is entered again to perform the above bias zeroing operation, and so on as needed. During the above process, the first input terminal 132 and the second input terminal 133 of the bias unit 2 are each input with their respective bias voltages, which remain unchanged. The operating characteristics of this amplifier mean that when it consumes 2I current in the second phase, it will consume 4I current in the first phase. Therefore, the average operating current of this amplifier is about 3I.

[0035] To reduce power consumption, as a preferred implementation method, please refer to... Figure 4 ,exist Figure 2The amplifier structure shown is further improved as follows: the inverter body is further provided with a third PMOS transistor 202 and a third NMOS transistor 203, and the switching unit 4 is further provided with a sixth switch 221, a seventh switch 222, an eighth switch 223, and a ninth switch 224. The source of the third PMOS transistor 202 is electrically connected to the drain of the first PMOS transistor 101, the drain of the third PMOS transistor 202 is electrically connected to the first terminal of the third switch 123, and the gate of the third PMOS transistor 202 is electrically connected to the second terminal of the sixth switch 221. The first terminal of the sixth switch 221 is electrically connected to the gate of the first PMOS transistor 101, the second terminal of the sixth switch 221 is electrically connected to the first terminal of the seventh switch 222, and the second terminal of the seventh switch 222 is grounded. The source of the third NMOS transistor 203 is electrically connected to the drain of the first NMOS transistor 102, the drain of the third NMOS transistor 203 is electrically connected to the second terminal of the third switch 123, and the gate of the third NMOS transistor 203 is electrically connected to the second terminal of the ninth switch 224. The first terminal of the ninth switch 224 is electrically connected to the gate of the first NMOS transistor 102, the second terminal of the ninth switch 224 is electrically connected to the first terminal of the eighth switch 223, and the second terminal of the eighth switch 223 is connected to a power supply. In this embodiment, either the drain connection network 244 of the third NMOS transistor 203 or the drain connection network 245 of the third PMOS transistor 202 can serve as the output terminal of the inverter body 1 to output the amplified signal during the amplification stage.

[0036] In this embodiment, the operation of the amplifier based on the inverter structure is as follows: First, the clock enters the first phase φ1, and the input terminal 131 of the zero-adjustment storage unit 3 inputs the common-mode voltage of the amplifier. The first switch 121, the second switch 122, the fourth switch 124, the fifth switch 125, the sixth switch 221, and the ninth switch 224 are closed, while the third switch 123, the seventh switch 222, and the eighth switch 223 are open. The second NMOS transistor 104 provides a bias current of value I to the first PMOS transistor 101 and the third PMOS transistor 202. The feedback-formed bias voltages of the first PMOS transistor 101 and the third PMOS transistor 202 fall on their respective gates, and the zero-adjustment information is stored in the first capacitor 111. At this time, the gate voltage of the first PMOS transistor 101... The gates of the first NMOS transistor 101 and the third NMOS transistor 202 are connected to the same network, so the width-to-length ratio of the first NMOS transistor 101 can be regarded as half of the actual physical ratio (the length becomes twice). The second NMOS transistor 103 provides a bias current of I to the third NMOS transistor 203 and the first NMOS transistor 102. The bias voltages of the third NMOS transistor 203 and the first NMOS transistor 102 formed by feedback fall on their respective gates, and the zero-adjustment information is stored in the second capacitor 112. At this time, the gates of the third NMOS transistor 203 and the first NMOS transistor 102 are connected to the same network, so the width-to-length ratio of the first NMOS transistor 102 can be regarded as half of the actual physical ratio. When the first phase ends and zeroing is completed, firstly disconnect the first switch 121, the second switch 122, the fourth switch 124, the fifth switch 125, the sixth switch 221, and the ninth switch 224. Disconnect the second PMOS transistor 103 from the third NMOS transistor 203 and the first NMOS transistor 102. Simultaneously disconnect the second NMOS transistor 104 from the first PMOS transistor 101 and the third PMOS transistor 202. Maintain the gate bias voltage acquired by the first PMOS transistor 101 on the second plate of the first capacitor 111, and maintain the gate bias voltage acquired by the first NMOS transistor 102 on the second plate of the first capacitor 111. On the second electrode of the second capacitor 112; then close the third switch 123, the seventh switch 222, and the eighth switch 223, connecting the drain of the third PMOS transistor 202 and the drain of the third NMOS transistor 203, and ground the gate of the third PMOS transistor 202 and connect the gate of the third NMOS transistor 203 to the power supply, making the third PMOS transistor 202 and the third NMOS transistor 203 into closed-state switching transistors. Thus, the drains of the first PMOS transistor 101 and the first NMOS transistor 102 can be considered directly connected, forming a dual-transistor inverter with a stable bias voltage and eliminating part of the mismatch. Since the gate bias voltages obtained by the first PMOS transistor 101 and the first NMOS transistor 102 do not change during the above process, but the equivalent width-to-length ratio increases to twice that at the beginning of the phase after the first phase φ1 ends, the current flowing through the two transistors becomes 2I after the inverter is formed.Then, a valid signal to be amplified is input to the input terminal 131 of the zero-adjustment storage unit 3 at the second phase φ2 of the clock, and the amplified output signal is obtained at the output terminal of the inverter body 1. After the second phase φ2 ends, the first phase φ1 is entered to perform the above-mentioned bias zero-adjustment operation, and so on as needed. During the above process, the first input terminal 132 and the second input terminal 133 of the bias unit 2 are input with their respective appropriate bias voltages, which remain unchanged at all times; the current flowing through the amplifier as a whole remains constant at 2I.

[0037] To optimize the output signal swing, as a preferred embodiment, the switching unit 4 further includes an eighteenth switch 230 and a nineteenth switch 231. The first terminal of the eighteenth switch 230 is electrically connected to the source of the third PMOS transistor 202, and the second terminal of the eighteenth switch 230 is electrically connected to the drain of the third PMOS transistor 202. The first terminal of the nineteenth switch 231 is electrically connected to the source of the third NMOS transistor 203, and the second terminal of the nineteenth switch 231 is electrically connected to the drain of the third NMOS transistor 203. Both switches are controlled by a non-overlapping clock, and both are in the first clock delay phase φ. 1D The circuit is closed when the voltage level is low and open when the voltage level is high. During the above operation, the eighteenth switch 230 and the nineteenth switch 231 operate in the same way as the third switch 123, the seventh switch 222 and the eighth switch 223. By shorting the source and drain of the third PMOS transistor 202 and the third NMOS transistor 203, the influence of their source-drain voltage drop on the DC operating point voltage of the first PMOS transistor 101 and the first NMOS transistor 102 is eliminated, thus providing a more complete upper limit of the output signal swing for the circuit in the second phase φ2 signal amplification stage.

[0038] To reduce energy consumption, as a preferred implementation method, please refer to... Figure 5 ,exist Figure 2The amplifier structure shown is further improved as follows: the inverter body 1 is further provided with a fourth PMOS transistor 301 and a fourth NMOS transistor 304; the switching unit 4 is further provided with a tenth switch 321, an eleventh switch 322, a twelfth switch 323, and a thirteenth switch 324. The source of the fourth PMOS transistor 301 is connected to a power supply, the drain of the fourth PMOS transistor 301 is electrically connected to the source of the first PMOS transistor 101, the gate of the fourth PMOS transistor 301 is electrically connected to the first terminal of the tenth switch 321 and the first terminal of the twelfth switch 323, the second terminal of the tenth switch 321 is grounded, and the second terminal of the twelfth switch 323 is electrically connected to the gate of the first PMOS transistor 101. The source of the fourth NMOS transistor 304 is grounded, and its drain is electrically connected to the source of the first NMOS transistor 102. The gate of the fourth NMOS transistor 304 is electrically connected to the first terminal of the eleventh switch 322 and the first terminal of the thirteenth switch 324, respectively. The second terminal of the eleventh switch 322 is connected to a power supply, and the second terminal of the thirteenth switch 324 is electrically connected to the gate of the first NMOS transistor 102. In this embodiment, either the drain connection network 344 of the first NMOS transistor 102 or the drain connection network 345 of the first PMOS transistor 101 can serve as the output terminal of the inverter body 1, outputting the amplified signal during the amplification stage.

[0039] In this embodiment, the operation of the amplifier based on the inverter structure is as follows: First, the clock enters the first phase φ1, and the input terminal 131 of the zero-adjustment storage unit 3 inputs the common-mode voltage of the amplifier. The first switch 121, the second switch 122, the fourth switch 124, the fifth switch 125, the twelfth switch 323, and the thirteenth switch 324 are closed, while the third switch, the tenth switch 321, and the eleventh switch 322 are open. The second NMOS transistor 104 provides a bias current of I to the first PMOS transistor 101 and the fourth PMOS transistor 301. The feedback-formed bias voltages of the first PMOS transistor 101 and the fourth PMOS transistor 301 fall on their respective gates, and the zero-adjustment information is stored in the first capacitor 111. At this time, the first PMOS transistor 101... The gate of the first PMOS transistor 101 is connected to the same network as the gate of the fourth PMOS transistor 301. The width-to-length ratio of the first PMOS transistor 101 can be regarded as half of the actual physical ratio (the length becomes twice). The second PMOS transistor 103 provides a bias current of I to the first NMOS transistor 102 and the fourth NMOS transistor 304. The bias voltages of the first NMOS transistor 102 and the fourth NMOS transistor 304 formed by feedback fall on their respective gates, and the zero-adjustment information is stored in the second capacitor 112. At this time, the gate of the first NMOS transistor 102 and the gate of the fourth NMOS transistor 304 are connected to the same network. The width-to-length ratio of the first NMOS transistor 102 can be regarded as half of the actual physical ratio. When the first phase ends and zeroing is completed, firstly disconnect the first switch 121, the second switch 122, the fourth switch 124, the fifth switch 125, the twelfth switch 323, and the thirteenth switch 324. Disconnect the second PMOS transistor 103 from the first NMOS transistor 102 and the fourth NMOS transistor 304, and simultaneously disconnect the second NMOS transistor 104 from the first PMOS transistor 101 and the fourth PMOS transistor 301. Maintain the gate bias voltage obtained by the first PMOS transistor 101 on the second plate of the first capacitor 111, and maintain the gate bias voltage obtained by the first NMOS transistor 102 on the second plate of the first capacitor 111. The voltage is maintained on the second plate of the second capacitor 112; then the third switch 123, the tenth switch 321 and the eleventh switch 322 are closed to connect the drain of the first PMOS transistor 101 and the drain of the first NMOS transistor 102, and the gate of the PMOS transistor 301 is grounded and the gate of the NMOS transistor 304 is connected to the power supply, so that the fourth PMOS transistor 301 and the fourth NMOS transistor 304 become closed switching transistors. Thus, a dual-transistor inverter composed of the first PMOS transistor 101 and the first NMOS transistor 102 is formed with a stable bias voltage and to eliminate part of the mismatch.Since the gate bias voltages of the first PMOS transistor 101 and the first NMOS transistor 102 theoretically do not change during the above process, but the equivalent width-to-length ratio increases to twice that at the beginning of the phase after the first phase φ1 ends, the current flowing through the two transistors after forming the inverter should theoretically be 2I (in reality, the fourth PMOS transistor 301 and the fourth NMOS transistor 304 still contain a small amount of resistance after being in the closed switching state, causing the gate-source voltage drop of the first PMOS transistor 101 and the first NMOS transistor 102 to decrease compared to the previous stage, thus causing the actual current flowing through the inverter to be slightly less than 2I). Then, in the second phase φ2 of the clock, a valid signal to be amplified is input at the input terminal 131 of the zero-adjustment storage unit 3, and the amplified output signal is obtained at the output terminal of the inverter body 1; after the second phase φ2 ends, the first phase φ1 is entered again to perform the above bias zero-adjustment operation, and so on as needed. During the above process, the first input terminal 132 and the second input terminal 133 of the bias unit 2 are each input with their respective bias voltages, which remain constant; the overall current through the amplifier is always maintained at a level of about 2I.

[0040] To optimize the output signal driving capability, as a preferred embodiment, the switching unit 4 further includes a twentieth switch 330 and a twenty-first switch 331. The first terminal of the twentieth switch 330 is electrically connected to the drain of the fourth PMOS transistor 301, and the second terminal of the twentieth switch 330 is connected to a power supply. The first terminal of the twenty-first switch 331 is electrically connected to the drain of the fourth NMOS transistor 304, and the second terminal of the twenty-first switch 331 is grounded. Both switches are controlled by a non-overlapping clock, and both operate at the first clock delay phase φ. 1D The circuit is closed when the voltage level is low and open when the voltage level is high. During the above operation, the twentieth switch 330, the twenty-first switch 331, the third switch, the tenth switch 321, and the eleventh switch 322 operate in unison. By directly connecting the sources of the first PMOS transistor 101 and the first NMOS transistor 102 to the power supply / ground, their gate-source voltage drop is increased to restore the inverter current value, thus providing the circuit with a more complete output signal driving capability during the second phase φ2 signal amplification stage.

[0041] To reduce energy consumption, as a preferred implementation method, please refer to... Figure 6 ,exist Figure 2The amplifier structure shown is further improved as follows: the inverter body 1 further includes a fifth PMOS transistor 401 and a fifth NMOS transistor 402; the switching unit 4 further includes a fourteenth switch 422 and a fifteenth switch 423. The source of the fifth PMOS transistor 401 is connected to the power supply, the gate of the fifth PMOS transistor 401 is electrically connected to the second plate of the first capacitor 111, and the drain of the fifth PMOS transistor 401 is electrically connected to the first terminal of the third switch 123. The source of the fifth NMOS transistor 402 is grounded, the gate of the fifth NMOS transistor 402 is electrically connected to the second plate of the second capacitor 112, and the drain of the fifth NMOS transistor 402 is electrically connected to the second terminal of the third switch 123; the first terminal of the fourteenth switch 422 is electrically connected to the first terminal of the third switch 123. The second terminal of the fourteenth switch 422 is electrically connected to the drain of the first PMOS transistor 101; the first terminal of the fifteenth switch 423 is electrically connected to the second terminal of the third switch 123, and the second terminal of the fifteenth switch 423 is electrically connected to the drain of the first NMOS transistor 102. In this embodiment, the drain connection network 444 of the fifth NMOS transistor 402 or the drain connection network 445 of the fifth PMOS transistor 401 can both serve as the output terminal of the inverter body 1 to output the amplified signal during the amplification stage.

[0042] In this embodiment, the operation of the amplifier based on the inverter structure is as follows: First, the clock enters the first phase φ1. The input terminal 131 of the zero-adjustment storage unit 3 inputs the common-mode voltage of the amplifier. The first switch 121, the second switch 122, the fourth switch 124, and the fifth switch 125 are closed, while the third switch 123, the fourteenth switch 422, and the fifteenth switch 423 are opened. The second NMOS transistor 104 provides a bias current of value I to the first PMOS transistor 101. The bias voltage of the first PMOS transistor 101 formed by feedback falls on itself and the gate of the fifth PMOS transistor 401, and the zero-adjustment information is stored in the first capacitor 111. The second PMOS transistor 103 provides a bias current of value I to the first NMOS transistor 102. The bias voltage of the first NMOS transistor 102 formed by feedback falls on itself and the gate of the fifth NMOS transistor 402, and the zero-adjustment information is stored in the second capacitor 112. At this time, the drains of the fifth PMOS transistor 401 and the fifth NMOS transistor 402 are both floating, so although there is a gate bias voltage provided, no bias current is generated. When the first phase ends and zeroing is completed, firstly disconnect the first switch 121, the second switch 122, the fourth switch 124, and the fifth switch 125, disconnect the connection between the second PMOS transistor 103 and the first NMOS transistor 102, and simultaneously disconnect the connection between the second NMOS transistor 104 and the first PMOS transistor 101. The gate bias voltages obtained by the fifth PMOS transistor 401 and the first PMOS transistor 101 are maintained on the second plate of the first capacitor 111, and the gate bias voltages obtained by the fifth NMOS transistor 402 and the first NMOS transistor 102 are maintained on the second plate of the second capacitor 112. Then close the third switch 123 and the tenth switch 125. Four switches 422 and fifteenth switch 423 connect the drains of the first PMOS transistor 101, the first NMOS transistor 102, the fifth PMOS transistor 401, and the fifth NMOS transistor 402 to the same network, forming a dual-transistor inverter with a stable bias voltage and partial mismatch elimination (the fifth PMOS transistor 401 and the first PMOS transistor 101 are connected in parallel and can be regarded as a single PMOS transistor with a width-to-length ratio twice that of the fifth PMOS transistor 401 or the first PMOS transistor 101; the same applies to the NMOS transistors 402 and 102). At this time, each of these four transistors carries a current of I, so the current flowing through the inverter as a whole is 2I. Then, a valid signal to be amplified is input at the input terminal 131 of the zero-adjustment storage unit 3 during the second phase φ2 of the clock, and the amplified output signal is obtained at the output terminal of the inverter body 1; after the second phase φ2 ends, the first phase φ1 is entered to perform the above-mentioned bias zero-adjustment operation, and so on as needed in a cyclical manner. During the above process, the first input terminal 132 and the second input terminal 133 of the bias unit 2 are each input with their respective bias voltages, which remain constant; the overall current through the amplifier remains constant at 2I.

[0043] To reduce energy consumption, as a preferred implementation method, please refer to... Figure 7 ,exist Figure 2 The amplifier structure shown is further improved as follows: the inverter body 1 further includes a sixth PMOS transistor 503 and a sixth NMOS transistor 504; the switching unit 4 further includes a sixteenth switch 524 and a seventeenth switch 525. The source of the sixth PMOS transistor 503 is connected to the power supply, the gate of the sixth PMOS transistor 503 is electrically connected to the gate of the first PMOS transistor 101, the drain of the sixth PMOS transistor 503 is electrically connected to the second terminal of the sixteenth switch 524, and the first terminal of the sixteenth switch 524 is electrically connected to the first terminal of the third switch 123. The source of the sixth NMOS transistor 504 is grounded, the gate of the sixth NMOS transistor 504 is electrically connected to the gate of the first NMOS transistor 102, the drain of the sixth NMOS transistor 504 is electrically connected to the second terminal of the seventeenth switch 525, and the first terminal of the seventeenth switch 525 is electrically connected to the second terminal of the third switch 123. In this embodiment, either the drain connection network 544 of the first NMOS transistor 102 or the drain connection network 545 of the first PMOS transistor 101 can be used as the output terminal of the inverter body 1 to output the amplified signal during the amplification stage.

[0044] In this embodiment, the operation of the amplifier based on the inverter structure is as follows: First, the clock enters the first phase φ1. The input terminal 131 of the zero-adjustment storage unit 3 inputs the common-mode voltage of the amplifier. The first switch 121, the second switch 122, the fourth switch 124, and the fifth switch 125 are closed, while the third switch 123, the sixteenth switch 524, and the seventeenth switch 525 are opened. The second NMOS transistor 104 provides a bias current of value I to the first PMOS transistor 101. The bias voltage of the first PMOS transistor 101 formed by feedback falls on itself and the gate of the sixth PMOS transistor 503, and the zero-adjustment information is stored in the first capacitor 111. The second PMOS transistor 103 provides a bias current of value I to the first NMOS transistor 102. The bias voltage of the first NMOS transistor 102 formed by feedback falls on itself and the gate of the sixth NMOS transistor 504, and the zero-adjustment information is stored in the second capacitor 112. At this time, the drains of the sixth PMOS transistor 503 and the sixth NMOS transistor 504 are both floating, so although there is a gate bias voltage provided, no bias current is generated. When the first phase ends and zeroing is completed, firstly disconnect the first switch 121, the second switch 122, the fourth switch 124, and the fifth switch 125. Simultaneously disconnect the second PMOS transistor 103 from the first NMOS transistor 102, and disconnect the second NMOS transistor 104 from the first PMOS transistor 101. The gate bias voltages obtained by the first PMOS transistor 101 and the sixth PMOS transistor 103 are maintained on the second plate of the first capacitor 111, and the gate bias voltages obtained by the first NMOS transistor 102 and the sixth NMOS transistor 504 are maintained on the second plate of the second capacitor 112. Then close the third switch 123 and the sixteenth PMOS transistor 125. Switches 524 and 17th switch 525 connect the drains of the first PMOS transistor 101, the first NMOS transistor 102, the sixth PMOS transistor 503, and the sixth NMOS transistor 504 to the same network, forming a dual-transistor inverter with a stable bias voltage and eliminating some mismatch (the first PMOS transistor 101 and the sixth PMOS transistor 503 are connected in parallel and can be regarded as a single PMOS transistor with a width-to-length ratio twice that of the first PMOS transistor 101 or the sixth PMOS transistor 503; the same applies to the NMOS transistors 102 and 504). At this time, each of these four transistors carries a current of I, so the current flowing through the inverter as a whole is 2I. Then, a valid signal to be amplified is input at the input terminal 131 of the clock phase 2, located in the zero-adjustment storage unit 3, and the amplified output signal is obtained at the output terminal of the inverter body 1; after the second phase φ2 ends, the first phase φ1 is entered to perform the above-mentioned bias zero-adjustment operation, and so on as needed in a cyclical manner. During the above process, the first input terminal 132 and the second input terminal 133 of the bias unit 2 are each input with their respective bias voltages, which remain constant; the overall current through the amplifier remains constant at 2I.

[0045] The present invention also provides an integrator, including any of the inverter-based amplifiers described in the above embodiments. Of course, the integrator also includes a sampling capacitor C. S With integrating capacitor C I Please see. Figure 8 For ease of explanation, this embodiment uses the following... Figure 2 The amplifier A shown is based on an inverter structure, and the sampling capacitor C is... S With integrating capacitor C I The capacitance values ​​are equal, and the switches in the diagram are all closed when their respective control timing is high and open when the control timing is low.

[0046] Please see Figure 9 The waveform in the figure shows Figure 8 The diagram illustrates the operation of the key input and output terminals of the integrator under non-overlapping clock driving. Generally, the integrator samples the signal in the first phase φ1 of the same clock cycle and stores the sampled information in the sampling capacitor C. S Simultaneously, the amplifier in the integrator is zeroed, the integrator outputs the integral in the second phase φ2, and the continuous integration information is stored in the integrating capacitor C. I In this waveform, the integrator performs a reset in the first clock cycle. When RST is high, the integrating capacitor C... I When short-circuited, the integrator output at the second phase φ2 of the clock is approximately equal to the integrator's common-mode voltage V. CM The voltage value; in the second and third clock cycles, the integrator is demonstrated to integrate and output a higher voltage, V. in The received input level is higher than V CM Then, the level value of the integrator output in the second phase φ2 of the clock gradually increases, and the increment of each output compared to the previous output is equal to (V in -V CM The values ​​are equal; in the fourth and fifth clock cycles, the integrator is demonstrated to integrate the output to a lower voltage, V. in The received input level is lower than V CM Therefore, the output level of the integrator in the second clock phase φ2 gradually decreases in the same manner. However, in the first clock phase φ1 of all clock cycles, due to the output V... out It is only connected to the gate and drain network of the first NMOS transistor 102 in the amplifier A based on the inverter structure, so it continuously outputs the bias voltage of the first NMOS transistor 102.

[0047] Please see Figure 10The present invention also provides a modulator, which is a classic second-order Delta-Sigma modulator for IADC, and is a CIFF with no input signal feedforward and a single-ended analog signal input architecture. In the figure, amplifiers 701 and 702 in the first and second order integrators can use any of the inverter-based amplifiers described in the above embodiments. In the first-order integrator amplifier, the switch is controlled by the first phase of the clock or by the first phase φ1 and φ2 of the global clock. 1D_BAR The control in the second-order integrator amplifier is controlled by the first phase of the clock or by the second phase φ2 and φ3 of the global clock. 2D_BAR Control; 703 is a dynamic comparator, in the signal φ 2_EVAL The circuit compares the signal values ​​at its positive and negative input terminals with the rising edge of the signal and outputs a high or low digital signal level. In this circuit schematic, all switches close when their respective control timing is high and open when it is low.

[0048] Please see Figure 11 The waveform in the figure shows Figure 10 The diagram illustrates the typical operation of the modulator. Unlike a typical Delta-Sigma ADC, an IADC only accepts DC-level input and follows a pattern of (initial reset) - first level sampling, conversion - reset - second level sampling, conversion - reset... From a timing perspective, an IADC can be considered a Nyquist ADC. In the diagram, after the first reset, the modulator receives and modulates an input level higher than the modulator's common-mode voltage. After the second reset, it receives and modulates an input level lower than the modulator's common-mode voltage. During this period, the qualitative output waveforms of the first and second-order integrator amplifiers are shown as "Network 757" and "Network 758" in the diagram. The signal modulation generates a digitized waveform, which will be further processed by secondary digital filters to generate the final digitized sampled signal value.

[0049] The amplifier in this design was successfully applied to an integrator and a Delta-Sigma modulator in an incremental analog-to-digital converter (IADC), verifying its reliability in a real-world system. Its fast and stable zero-adjustment and amplification characteristics directly improve the dynamic range, conversion accuracy, and energy efficiency of the integrator and even the entire IADC, demonstrating significant engineering application value.

[0050] This invention stores the inverter bias voltage during the zero-adjustment phase using a zero-adjustment storage unit, and, in conjunction with precise timing control using a non-overlapping clock, achieves physical isolation between the zero-adjustment and amplification phases. After storing the bias voltage, by disconnecting the relevant switches and closing the third switch, it ensures that the inverter operating point during the amplification phase is entirely maintained by the zero-adjustment storage unit and is unaffected by PVT fluctuations. By adding biases to the two transistors in the inverter body, the high-impedance network nodes of the inverter are prevented from participating in the zero-adjustment process, thereby significantly improving the zero-adjustment speed. This is beneficial for improving the stability of the integrator in the IADC, and thus improving the IADC performance and its resistance to PVT variations. By precisely controlling the zero-adjustment phase with a non-overlapping clock, a stable bias voltage is actively established and stored, eliminating the high-impedance state at the inverter input and the slow bias establishment due to leakage current during the zero-adjustment phase. The mismatch and accuracy degradation issues introduced by this design ensure a highly stable operating point for the amplifier during the amplification stage, suppressing mismatch noise. Furthermore, by providing a stable and consistent operating point, the inverter itself can achieve higher open-loop gain during the amplification stage, adapting to low supply voltages. The input external bias voltage terminals in the bias unit are not directly connected to any switch, and the switching action in the switching unit does not cause significant charging and discharging of the input external bias voltage network, which helps maintain its stability. This is particularly suitable for applications with harsh input bias voltage driven load environments, such as focal plane array readout circuits. By further splitting the transistors in the inverter body before biasing, the supply current can remain consistent across all driving clock phases while the current bias remains constant during the amplification stage, further reducing power consumption.

[0051] The above description merely illustrates preferred embodiments of the present invention and is quite specific and detailed; however, it should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the appended claims.

Claims

1. An amplifier based on an inverter structure, characterized in that, include: The inverter body is used to amplify the input signal when the amplifier is in the amplification phase; The bias unit is used to provide bias current to the inverter body when the amplifier is in the zero-adjustment stage, and to establish a stable bias voltage in the inverter body. The zero-adjustment storage unit is used to store the bias voltage of the inverter body when the amplifier is in the zero-adjustment stage, and to maintain the stability of the bias voltage when the amplifier is in the amplification stage, so that the inverter body has a stable operating point in the amplification stage. The switching unit is used to control the working state of the bias unit, the zero-adjustment storage unit and the inverter body through a non-overlapping clock signal, so that the amplifier switches between the zero-adjustment stage and the amplification stage, thereby achieving isolation between the zero-adjustment stage and the amplification stage.

2. The amplifier based on the inverter structure as described in claim 1, characterized in that: The inverter body includes a first PMOS transistor 101 and a first NMOS transistor 102; the gate of the first PMOS transistor 101 serves as the first input terminal of the inverter body and is electrically connected to the first output terminal of the zero-adjustment memory unit; the source of the first PMOS transistor 101 is connected to a power supply; and the drain of the first PMOS transistor 101 is electrically connected to the first terminal of the switching unit. The gate of the first NMOS transistor 102 serves as the second input terminal of the inverter body and is electrically connected to the second output terminal of the zero-adjustment memory unit; the source of the first NMOS transistor 102 is grounded; and the drain of the first NMOS transistor 102 is electrically connected to the second terminal of the switching unit. The drain of either the first PMOS transistor 101 or the drain of the first NMOS transistor 102 serves as the output terminal of the inverter body, outputting an amplified signal. The bias unit includes a second PMOS transistor 103 and a second NMOS transistor 104; the gate of the second PMOS transistor 103 serves as the first input terminal of the bias unit and is connected to an external bias voltage, the source of the second PMOS transistor 103 is connected to a power supply, and the drain of the second PMOS transistor 103 is electrically connected to the third terminal of the switching unit; the gate of the second NMOS transistor 104 serves as the second input terminal of the bias unit and is connected to an external bias voltage, the source of the second NMOS transistor 104 is grounded, and the drain of the second NMOS transistor 104 is electrically connected to the fourth terminal of the switching unit.

3. The amplifier based on the inverter structure as described in claim 2, characterized in that: The zero-adjustment storage unit includes a first capacitor 111 and a second capacitor 112. The first plate of the first capacitor 111 and the first plate of the second capacitor 112 are electrically connected and serve as the input terminal of the zero-adjustment storage unit. During the zero-adjustment stage, the common-mode voltage of the amplifier is input, and during the amplification stage, the signal to be amplified is input. The second plate of the first capacitor 111 serves as the first output terminal of the zero-adjustment storage unit and is electrically connected to the gate of the first PMOS transistor 101. The second plate of the second capacitor 112 serves as the second output terminal of the zero-adjustment storage unit and is electrically connected to the gate of the first NMOS transistor 102.

4. The amplifier based on the inverter structure as described in claim 3, characterized in that: The switching unit includes a first switch 121, a second switch 122, a third switch 123, a fourth switch 124, and a fifth switch 125. The first terminal of the first switch 121 is electrically connected to the first terminal of the third switch 123, serving as the first terminal of the switching unit and electrically connected to the drain of the first PMOS transistor 101. The second terminal of the first switch 121 is electrically connected to the gate of the first PMOS transistor 101. The first terminal of the second switch 122 is electrically connected to the second terminal of the third switch 123, serving as the second terminal of the switching unit and electrically connected to the first NMOS transistor 101. The drain of transistor 102 is electrically connected, and the second terminal of the second switch 122 is electrically connected to the gate of the first NMOS transistor 102; the first terminal of the fourth switch 124 is electrically connected to the second terminal of the third switch 123, and the second terminal of the fourth switch 124 serves as the third terminal of the switching unit and is electrically connected to the drain of the second PMOS transistor 103; the first terminal of the fifth switch 125 is electrically connected to the first terminal of the third switch 123, and the second terminal of the fifth switch 125 serves as the fourth terminal of the switching unit and is electrically connected to the drain of the second NMOS transistor 104.

5. The amplifier based on the inverter structure as described in claim 4, characterized in that: The inverter body further includes a third PMOS transistor 202 and a third NMOS transistor 203; the switching unit further includes a sixth switch 221, a seventh switch 222, an eighth switch 223, and a ninth switch 224; the source of the third PMOS transistor 202 is electrically connected to the drain of the first PMOS transistor 101, the drain of the third PMOS transistor 202 is electrically connected to the first terminal of the third switch 123, and the gate of the third PMOS transistor 202 is electrically connected to the second terminal of the sixth switch 221; the first terminal of the sixth switch 221 is electrically connected to the gate of the first PMOS transistor 101, and the ninth switch 224 is electrically connected to the gate of the first PMOS transistor 101. The second terminal of the seventh switch 222 is electrically connected to the first terminal of the seventh switch 222, and the second terminal of the seventh switch 222 is grounded; the source of the third NMOS transistor 203 is electrically connected to the drain of the first NMOS transistor 102, the drain of the third NMOS transistor 203 is electrically connected to the second terminal of the third switch 123, and the gate of the third NMOS transistor 203 is electrically connected to the second terminal of the ninth switch 224; the first terminal of the ninth switch 224 is electrically connected to the gate of the first NMOS transistor 102, the second terminal of the ninth switch 224 is electrically connected to the first terminal of the eighth switch 223, and the second terminal of the eighth switch 223 is connected to a power supply.

6. The amplifier based on the inverter structure as described in claim 4, characterized in that: The inverter body further includes a fourth PMOS transistor 301 and a fourth NMOS transistor 304; the switching unit further includes a tenth switch 321, an eleventh switch 322, a twelfth switch 323, and a thirteenth switch 324; the source of the fourth PMOS transistor 301 is connected to a power supply, the drain of the fourth PMOS transistor 301 is electrically connected to the source of the first PMOS transistor 101, and the gate of the fourth PMOS transistor 301 is electrically connected to the first terminal of the tenth switch 321 and the first terminal of the twelfth switch 323, respectively. The second terminal of the twelfth switch 323 is grounded, and the second terminal of the twelfth switch 323 is electrically connected to the gate of the first PMOS transistor 101. The source of the fourth NMOS transistor 304 is grounded, and the drain of the fourth NMOS transistor 304 is electrically connected to the source of the first NMOS transistor 102. The gate of the fourth NMOS transistor 304 is electrically connected to the first terminal of the eleventh switch 322 and the first terminal of the thirteenth switch 324, respectively. The second terminal of the eleventh switch 322 is connected to a power supply, and the second terminal of the thirteenth switch 324 is electrically connected to the gate of the first NMOS transistor 102.

7. The amplifier based on the inverter structure as described in claim 4, characterized in that: The inverter body further includes a fifth PMOS transistor 401 and a fifth NMOS transistor 402; the switching unit further includes a fourteenth switch 422 and a fifteenth switch 423; the source of the fifth PMOS transistor 401 is connected to a power supply, the gate of the fifth PMOS transistor 401 is electrically connected to the second plate of the first capacitor 111, and the drain of the fifth PMOS transistor 401 is electrically connected to the first terminal of the third switch 123; the source of the fifth NMOS transistor 402 is grounded, the gate of the fifth NMOS transistor 402 is electrically connected to the second plate of the second capacitor 112, and the drain of the fifth NMOS transistor 402 is electrically connected to the second terminal of the third switch 123; the first terminal of the fourteenth switch 422 is electrically connected to the first terminal of the third switch 123; the second terminal of the fourteenth switch 422 is electrically connected to the drain of the first PMOS transistor 101; the first terminal of the fifteenth switch 423 is electrically connected to the second terminal of the third switch 123, and the second terminal of the fifteenth switch 423 is electrically connected to the drain of the first NMOS transistor 102.

8. The amplifier based on the inverter structure as described in claim 4, characterized in that: The inverter body further includes a sixth PMOS transistor 503 and a sixth NMOS transistor 504; the switching unit further includes a sixteenth switch 524 and a seventeenth switch 525; the source of the sixth PMOS transistor 503 is connected to a power supply, the gate of the sixth PMOS transistor 503 is electrically connected to the gate of the first PMOS transistor 101, the drain of the sixth PMOS transistor 503 is electrically connected to the second terminal of the sixteenth switch 524, and the first terminal of the sixteenth switch 524 is electrically connected to the first terminal of the third switch 123; the source of the sixth NMOS transistor 504 is grounded, the gate of the sixth NMOS transistor 504 is electrically connected to the gate of the first NMOS transistor 102, the drain of the sixth NMOS transistor 504 is electrically connected to the second terminal of the seventeenth switch 525, and the first terminal of the seventeenth switch 525 is electrically connected to the second terminal of the third switch 123.

9. An integrator, characterized in that: The amplifier includes an inverter-based structure as described in any one of claims 1 to 8.

10. A modulator, characterized in that: The amplifier includes an inverter-based structure as described in any one of claims 1 to 8.

Images