Ka wave band high-efficiency power amplifier based on GaAs technology

Abstract

The invention discloses a ka wave band high-efficiency power amplifier based on a GaAs technology. A circuit comprises an input stage tube core, a driving stage tube core, an output stage tube core, an output stage second harmonic suppression network, an inter-stage matching network, an output matching network, a grid electrode biasing circuit, a drain electrode biasing circuit and a stabilizing resistor. The input matching network adopts a T-shaped matching network structure, and the inter-stage matching circuit adopts a matching network combining an LC series structure and a T-shaped structure, so that the working bandwidth of the circuit is further improved, and the area of the power amplifier is reduced; the output efficiency of the whole power amplifier is improved by introducing a second harmonic suppression network at the output end by adopting a second harmonic suppression technology. According to the invention, based on the 0.15 [mu] m GaAs pHEMT technology, a three-stage cascade amplification and power distribution synthesis structure is adopted to realize that the output saturation power is greater than or equal to 29.5 dBm and the power additional efficiency is greater than or equal to 34% in the working frequency band of 34-38GHz, and the power amplifier has the advantages of high stability, high power additional efficiency, high saturation output power, wide working frequency band and the like.

Description

TECHNICAL FIELD

[0001] The application relates to the field of radio frequency power amplifiers, in particular to a GaAs process-based high-efficiency power amplifier in a ka band. BACKGROUND

[0002] In the link architecture of a Ka band (26.5-40GHz) communication system, a power amplifier is in a core position of a radio frequency front end, and the performance of the power amplifier directly determines the signal coverage range, transmission reliability and communication quality of the system. At present, a GaAs-based Ka band power amplifier has been applied on a large scale in multiple key fields. In the field of communications, in the radio frequency unit of a 5G Ka band base station, a power amplifier based on a GaAs pHEMT process has become a mainstream configuration, and Ka band base station products of global mainstream communication equipment manufacturers all adopt the scheme. Although the GaAs-based Ka band power amplifier has been widely applied, with the evolution of communication technology to 6G and the expansion of Ka band application scenarios, the existing scheme still has three core bottlenecks: 1. insufficient power efficiency; 2. contradiction between linearity and bandwidth; and 3. to be improved in integration and reliability. Therefore, it is of urgent technical necessity and application value to develop a new type of Ka band GaAs power amplifier with high efficiency, high linearity and high integration. SUMMARY

[0003] The application provides a 0.15um GaAs pHEMT process-based high-efficiency power amplifier in a ka band, which realizes high-power output in a three-stage cascading and power combining manner. A secondary harmonic suppression technology is adopted in an output stage matching network, and a secondary harmonic suppression network structure is designed. The secondary harmonic suppression network structure adopts a quarter-wave microstrip line as a bias network and is combined with multi-stage reactance matching to form an output end matching network, so that the secondary harmonic is connected to the ground, and the harmonic energy is avoided from being reflected and consumed in the circuit. A T-shaped matching network structure is used in an input matching network, and an LC series structure and a T-shaped structure are combined in an inter-stage matching network to adapt to normal operation in a wide frequency band. One die is used as an amplification stage in an input stage, two dies are used for two-way cluster power distribution to the next stage in a driving stage, four dies are used for four-way cluster power synthesis to two-way synthesis to one-way to output in an output stage, and power synthesis is realized. The application realizes three-stage amplification at 34GHz-38GHz, the output power is greater than or equal to 29.5dBm, and the power added efficiency is greater than or equal to 34%.

[0004] The overall circuit of the high-efficiency power amplifier in the ka band is as shown in Figure 1As shown, the capacitor C1 is used as a direct current isolation capacitor of the signal input terminal, to isolate direct current and avoid mutual interference of static working points. The microstrip line TL1, the microstrip line TL2 and the grounding capacitor C2 in the circuit constitute the input matching network. The first port of the capacitor C1 is connected to the radio frequency signal input terminal RFIN, the second port of the capacitor C1 is connected to the first port of the microstrip line TL1, the second port of the microstrip line TL1 is connected to the first port of the microstrip line TL2 and the first port of the capacitor C2, the second port of the capacitor C2 is connected to the ground, and the second port of the microstrip line TL2 is connected to the first port of the microstrip line TL101 and the first port of the microstrip line TL3. The second port of the microstrip line TL101 is connected to the first port of the grounding capacitor C101 and the input stage gate end bias voltage VGS1, to form an input stage gate end bias circuit. The second port of the microstrip line TL3 is connected to the 1 port of the input stage die M1, to connect the input matching network, the input stage bias circuit and M1 together, so as to better realize impedance matching.

[0005] The second port of the microstrip line TL4 is connected with the first port of the microstrip line TL102 and the first port of the microstrip line TL5, the microstrip line TL102 and the ground capacitor C102 constitute a drain bias circuit of the input stage die M1, the second port of the microstrip line TL102 is connected with the first port of the ground capacitor C102 and the drain end input voltage VDS1 to ensure that the input stage die M1 can work normally. The microstrip line TL5 and the capacitor C3 constitute an LC series matching network, the second port of the microstrip line TL5 is connected with the first port of the capacitor C3, the second port of the capacitor C3 is connected with the first port of the microstrip line TL6 and the second port of the microstrip line TL7, the capacitor C3 is used for isolating direct current and avoiding mutual influence of static working points. The first port of the microstrip line TL6 is connected with the first port of the microstrip line TL7 and the first port of the capacitor C3, the second port of the microstrip line TL6 is connected with the first port of the ground capacitor C4 and the first port of the microstrip line TL8, the microstrip line TL6, the ground capacitor C4 and the microstrip line TL7 constitute a T-type matching network, the microstrip line TL5, the capacitor C3, the microstrip line TL6, the ground capacitor C4 and the microstrip line TL8 constitute the inter-stage matching network adopting the LC series structure and the T-type structure, and impedance matching between the load end of the input stage die M1 and the source end of the driving stage die M2 is realized. The second port of the microstrip line TL8 is connected with the first port of the microstrip line TL103 and the first port of the microstrip line TL10, the second port of the microstrip line TL103 is connected with the first port of the ground capacitor C103 and the gate bias voltage VGS2_1 of the driving stage die M2, the microstrip line TL103 and the ground capacitor C103 constitute a gate bias circuit of the driving stage die M2, and the voltage VGS2_1 provides a static working point for the driving stage die M2. The second port of the microstrip line TL10 is connected with the first port of the resistor R1 and the first port of the microstrip line TL12, the second port of the microstrip line TL12 is connected with the first port of the driving stage die M2; the first port of the microstrip line TL7 is connected with the second port of the capacitor C3 and the first port of the microstrip line TL6, the second port of the microstrip line TL7 is connected with the first port of the ground capacitor C5 and the first port of the microstrip line TL9, the microstrip line TL7, the ground capacitor C5 and the microstrip line TL9 constitute a T-type matching network, the microstrip line TL5, the capacitor C3, the microstrip line TL7, the ground capacitor C5 and the microstrip line TL9 constitute the inter-stage matching network adopting the LC series structure and the T-type structure, and impedance matching between the load end of the input stage die M1 and the source end of the driving stage die M3 is realized.The second port of the microstrip line TL9 is connected to the first port of the microstrip line TL104 and the first port of the microstrip line TL11, the second port of the microstrip line TL104 is connected to the first port of the ground capacitor C104 and the gate input voltage VGS2_2 of the driving stage die M3, the microstrip line TL104 and the ground capacitor C104 constitute the gate bias circuit of the driving stage die M3, and the voltage VGS2_2 provides a static working point for the driving stage die M3. The second port of the microstrip line TL11 is connected to the second port of the resistor R1 and the first port of the microstrip line TL13, the second port of the microstrip line TL13 is connected to the 1 port of the driving stage die M3; the T-shaped matching network composed of the microstrip line TL6, the ground capacitor C4 and the microstrip line TL8 is exactly the same as the T-shaped matching network composed of the microstrip line TL7, the ground capacitor C5 and the microstrip line TL9. The gate bias circuit composed of the microstrip line TL103 and the ground capacitor C103 is exactly the same as the gate bias circuit composed of the microstrip line TL104 and the ground capacitor C104; the connection structure composed of the microstrip line TL10 and the microstrip line TL12 is exactly the same as the connection structure composed of the microstrip line TL11 and the microstrip line TL13; the driving stage die M2 and the driving stage die M3 are exactly the same in size, and constitute two-way cluster output to the next stage, and the gate bias voltage VGS2_1 is exactly the same as the gate bias voltage VGS2_2.

[0006] The second port of the microstrip line TL14 is connected to the first port of the microstrip line TL105 and the first port of the microstrip line TL16; the second port of the microstrip line TL105 is connected to the first port of the ground capacitor C105 and the drain bias voltage VDS2_1 of the driving stage die M2, the microstrip line TL105 and the ground capacitor C105 constitute the drain bias circuit of the driving stage die M2, and the drain bias voltage VDS2_1 provides a static working point for the drain of the driving stage die M2. The second port of the microstrip line TL16 is connected to the first port of the capacitor C6, which serves as a direct-current isolation capacitor between the driving stage and the output stage to avoid mutual interference of static working points. The second port of the capacitor C6 is connected to the first port of the microstrip line TL107 and the first port of the microstrip line TL18, the second port of the microstrip line TL107 is connected to the first port of the ground capacitor C107 and the gate bias voltage VGS3_1, the microstrip line TL107 and the ground capacitor C107 constitute the gate bias circuit of the output stage die M4 and M5, and the gate bias voltage VGS3_1 provides a static working point for the output stage die M4 and M5. The second port of the microstrip line TL18 is connected to the first port of the microstrip line TL20 and the first port of the microstrip line TL21, the second port of the microstrip line TL20 is connected to the first port of the ground capacitor C8 and the first port of the microstrip line TL24, and the second port of the microstrip line TL24 is connected to the first port of the resistor R2 and the 1 port of the output stage die M4. The first port of the microstrip line TL21 is connected to the second port of the microstrip line TL18 and the first port of the microstrip line TL20, the second port of the microstrip line TL21 is connected to the first port of the ground capacitor C9 and the first port of the microstrip line TL25, and the second port of the microstrip line TL25 is connected to the second port of the resistor R2 and the 1 port of the output stage die M5. The microstrip line TL20, the ground capacitor C8 and the microstrip line TL24 constitute a T-type matching network, the microstrip line TL21, the ground capacitor C9 and the microstrip line TL25 constitute a T-type matching network, and the T-type matching network composed of the microstrip line TL20, the ground capacitor C8 and the microstrip line TL24 is symmetrical and identical in parameters to the T-type matching network composed of the microstrip line TL21, the ground capacitor C9 and the microstrip line TL25.The microstrip line TL16, the capacitor C6, the microstrip line TL18, the microstrip line TL20, the ground capacitor C8 and the microstrip line constitute the LC series structure and the T-shaped structure combined interstage matching network, realizing impedance matching of the driving stage die M2 load end and the output stage die M4 source end; the microstrip line TL16, the capacitor C6, the microstrip line TL18, the microstrip line TL21, the ground capacitor C9 and the microstrip line TL25 constitute the LC series structure and the T-shaped structure combined interstage matching network, realizing impedance matching of the driving stage die M2 load end and the output stage die M5 source end; the first port of the resistor R2 is connected with a port of the output stage die M4, the second port of the resistor R2 is connected with a port of the output stage die M5, and the resistor R2 is connected with M4 and M5 to prevent circuit oscillation and improve the stability of the circuit.

[0007] The second port of the microstrip line TL15 is connected with the first port of the microstrip line TL106 and the first port of the microstrip line TL17, the second port of the microstrip line TL106 is connected with the first port of the ground capacitor C106 and the drain bias voltage VDS2_2, the microstrip line TL106 and the ground capacitor C106 constitute the drain bias voltage of the driving stage die M3, and the drain bias voltage VDS2_2 provides a static working point for the driving stage die M3. The second port of the microstrip line TL17 is connected with the first port of the capacitor C7, the capacitor C7 is used as a direct current blocking capacitor of the driving stage and the output stage, and avoids mutual influence of the static working points, the second port of the capacitor C7 is connected with the first port of the microstrip line TL108 and the first port of the microstrip line TL19, the second port of the microstrip line TL108 is connected with the first port of the ground capacitor C108 and the gate bias voltage VGS3_2, the microstrip line TL108 and the ground capacitor C108 constitute the gate bias circuit of the output stage die M6 and M7, and the gate bias voltage VGS3_2 provides a static working point for the output stage die M6 and M7. The second port of the microstrip line TL19 is connected with the first port of the microstrip line TL22 and the first port of the microstrip line TL23, the second port of the microstrip line TL22 is connected with the first port of the ground capacitor C10 and the first port of the microstrip line TL26, the second port of the microstrip line TL26 is connected with the first port of the capacitor R3 and the 1 port of the output stage die M6; the microstrip line TL22, the ground capacitor C10 and the microstrip line TL26 constitute a T-type matching network. The first port of the microstrip line TL23 is connected with the second port of the microstrip line TL19 and the first port of the microstrip line TL22, the second port of the microstrip line TL23 is connected with the first port of the ground capacitor C11 and the first port of the microstrip line TL27, the second port of the microstrip line TL27 is connected with the second port of the resistor R3 and the 1 port of the output stage die M7; the microstrip line TL23, the ground capacitor C11 and the microstrip line TL27 constitute a T-type matching network. The resistor R3 is connected with the M6 and M7 to prevent circuit oscillation and improve circuit stability; the T-type matching network composed of the microstrip line TL22, the ground capacitor C10 and the microstrip line TL26 is symmetrical with the T-type matching network composed of the microstrip line TL23, the ground capacitor C11 and the microstrip line TL27, and the parameters are completely same. The microstrip line TL17, the capacitor C7, the microstrip line TL19, the microstrip line TL22, the ground capacitor C10 and the microstrip line TL26 constitute an inter-stage matching network combining the LC series structure and the T-type structure, and realize impedance matching between the load end of the driving stage die M3 and the source of the output stage die M6.The microstrip line TL17, the capacitor C7, the microstrip line TL19, the microstrip line TL23, the ground capacitor C11 and the microstrip line TL27 constitute the inter-stage matching network combining the LC series structure and the T-shaped structure, and realize impedance matching of the load end of the driving stage die M3 and the source end of the output stage die M7. The drain bias network composed of the microstrip line TL105 and the ground capacitor is completely symmetrical and has the same parameters as the drain bias circuit composed of the microstrip line TL106 and the ground capacitor C106; the drain bias voltage VDS2_1 has the same parameters as the drain bias voltage VDS2_1. The microstrip line TL16, the capacitor C6, the microstrip line TL18, the microstrip line TL20, the ground capacitor C8, the microstrip line TL24, the microstrip line TL21, the ground capacitor C9 and the microstrip line TL25 constitute the inter-stage matching network combining the LC series structure and the T-shaped structure, which is completely symmetrical and has the same parameters as the inter-stage matching network combining the LC series structure and the T-shaped structure composed of the microstrip line TL17, the capacitor C7, the microstrip line TL19, the microstrip line TL22, the ground capacitor C10, the microstrip line TL26, the microstrip line TL23, the ground capacitor C11 and the microstrip line TL27. The gate bias circuit composed of the microstrip line TL107 and the ground capacitor C107 is completely symmetrical and has the same parameters as the gate bias circuit composed of the microstrip line TL108 and the ground capacitor C108; the gate bias voltage VGS3_1 has the same parameters as the gate bias voltage VGS3_2; the resistance R2 has the same parameters as the resistance R3; the output stage dies M4, M5, M6 and M7 have the same parameters and constitute the four-way cluster output.

[0008] The 2-port of the output stage die M4 is connected to the first port of the resistance R4 and the first port of the microstrip line TL28, and the 3-port is grounded. The second port of the microstrip line TL28 is connected to the ground capacitor C12 and the first port of the microstrip line TL32, and the microstrip line TL28, the ground capacitor C12 and the microstrip line TL32 constitute a T-shaped matching network. The second port of the microstrip line TL32 is connected to the first port of the microstrip line TL109, the second port of the microstrip line TL33 and the first port of the TL36, the second port of the microstrip line TL36 is connected to the first port of the ground capacitor C16 and the first port of the microstrip line TL38, the second port of the microstrip line TL38 is connected to the first port of the ground capacitor C18 and the first port of the capacitor C19; the second port of the capacitor C19 is connected to the RFOUT. The second port of the microstrip line TL109 is connected to the first port of the ground capacitor C109 and the drain bias voltage VDS3_1, and the microstrip line TL109 and the ground capacitor C109 constitute the quarter-wavelength microstrip line bias network circuit of the output stage dies M4 and M5, the drain bias voltage VDS3_1 provides a static operating point for the output stage die, and ensures the normal operation of the circuit.

[0009] The second port of the output stage die M5 is connected to the second port of the resistor R4 and the first port of the microstrip line TL29, and the 3-port is grounded. The second port of the microstrip line TL29 is connected to the first port of the grounded capacitor C13 and the first port of the microstrip line TL33, and the second port of the microstrip line TL33 is connected to the second port of the TL32, the first port of the microstrip line T109 and the first port of the microstrip line TL36. The microstrip line TL29, the grounded capacitor C13 and the microstrip line TL33 constitute a T-type matching network, and the T-type matching network constituted by the microstrip line TL28, the grounded capacitor C12 and the microstrip line TL32 is symmetrical and completely identical in parameters to the T-type matching network constituted by the microstrip line TL29, the grounded capacitor C13 and the microstrip line TL33. The T-type matching network constituted by the microstrip line TL28, the grounded capacitor C12 and the microstrip line TL32, the T-type matching network constituted by the microstrip line TL29, the grounded capacitor C13 and the microstrip line TL33, the quarter-wave microstrip line biasing network constituted by the microstrip line T109 and the grounded capacitor C109, and the reactance matching network constituted by the microstrip line TL36, the grounded capacitor C16, the microstrip line TL38 and the grounded capacitor C18 together constitute the output terminal matching network which is composed of the quarter-wave microstrip line biasing network and the multi-stage reactance matching network.

[0010] The 2-port of the output stage die M6 is connected to the first port of the resistor R5 and the first port of the microstrip line TL30, and the 3-port is grounded. The second port of the microstrip line TL30 is connected to the first port of the grounded capacitor C14 and the first port of the microstrip line TL34, and the microstrip line TL30, the grounded capacitor C14 and the microstrip line TL34 constitute a T-type matching network. The second port of the microstrip line TL34 is connected to the first port of the microstrip line TL110, the first port of the microstrip line TL35 and the first port of the microstrip line TL37, the second port of the microstrip line TL37 is connected to the first port of the grounded capacitor C17 and the first port of the microstrip line TL38, and the second port of the microstrip line TL38 is connected to the first port of the grounded capacitor C18 and the first port of the capacitor C19.

[0011] The second port of the 2-port connection resistor R5 of the output stage die M7 is connected to the first port of the microstrip line TL31, and the 3-port is connected to ground. The second port of the microstrip line TL31 is connected to the first port of the ground capacitor C15 and the first port of the microstrip line TL35, and the microstrip line TL31, the ground capacitor C15 and the microstrip line TL35 constitute a T-type matching network. The second port of the microstrip line TL35 is connected to the first port of the microstrip line TL110, the second port of the microstrip line TL34 and the first port of the microstrip line TL35; the second port of the microstrip line TL110 is connected to the first port of the ground capacitor C110 and the drain bias voltage VDS3_2. The microstrip line TL110 and the ground capacitor C110 constitute the quarter-wave microstrip line bias network circuit of the output stage die M6, M7, and the drain bias voltage VDS3_2 provides a static operating point for the output stage die M6, M7. The T-type matching network composed of the microstrip line TL30, the ground capacitor C14 and the microstrip line TL34 is completely symmetrical and has the same parameters as the T-type matching network composed of the microstrip line TL31, the ground capacitor C15 and the microstrip line TL35. The T-type matching network composed of the microstrip line TL30, the ground capacitor C14 and the microstrip line TL34, the T-type matching network composed of the microstrip line TL31, the ground capacitor C15 and the microstrip line TL35, the quarter-wave microstrip line bias network circuit composed of the microstrip line TL110 and the ground capacitor C110, and the reactive matching network composed of the microstrip line TL37, the ground capacitor C17, the microstrip line TL38 and the ground capacitor C18 together constitute the output terminal supporting network composed of the quarter-wave microstrip line bias network and the multi-stage reactive matching. The T-type matching network composed of the microstrip line TL28, the ground capacitor C12 and the microstrip line TL32, the T-type matching network composed of the microstrip line TL29, the ground capacitor C13 and the microstrip line TL33, the quarter-wave microstrip line bias network circuit composed of the microstrip line TL109 and the ground capacitor C109, and the reactive matching network composed of the microstrip line TL36, the ground capacitor C16, the microstrip line TL38 and the ground capacitor C18 together constitute the output terminal supporting network composed of the quarter-wave microstrip line bias network and the multi-stage reactive matching, which is completely the same as the T-type matching network composed of the microstrip line TL30, the ground capacitor C14 and the microstrip line TL34, the T-type matching network composed of the microstrip line TL31, the ground capacitor C15 and the microstrip line TL35, the quarter-wave microstrip line bias network circuit composed of the microstrip line TL110 and the ground capacitor C110, and the reactive matching network composed of the microstrip line TL37, the ground capacitor C17, the microstrip line TL38 and the ground capacitor C18.The drain bias voltage VDS3_1 is completely same as the drain bias voltage VDS3_2, the resistance R4 is completely same as the resistance R5, the first port of the resistance R4 is connected with the 2 port of the output stage die M4, the second port of the resistance R4 is connected with the 2 port of the output stage die M5, which prevents the circuit from oscillation; the first port of the resistance R5 is connected with the 2 port of the output stage die M6, the second port of the resistance R5 is connected with the 2 port of the output stage die M7, which prevents the circuit from oscillation. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 It is the whole circuit diagram of the application;

[0013] Figure 2 It is the circuit layout of the application;

[0014] Figure 3 It is the simulation result comparison chart of the power added efficiency of the application before and after the output end supporting network which combines the bias network of the quarter wavelength microstrip line and the multi-stage reactance matching;

[0015] Figure 4 It is the simulation result chart of the small signal S parameter of the application;

[0016] Figure 5 It is the simulation result chart of the power added efficiency of the application;

[0017] Figure 6 It is the simulation result chart of the saturated output power of the application;

[0018] Figure 7 It is the simulation result chart of the stability of the application. DETAILED DESCRIPTION

[0019] The technical scheme of the application will be described in detail below with the embodiments and the drawings, so as to obtain better understanding.

[0020] Figure 1As shown, the embodiment adopts a structure of three-stage cascade power distribution, the radio frequency input signal RFIN is given to 15dBm, and the gate length of the input stage die M1 is selected as 2*75um. The technical index reaches a saturated power output of >=29.5dBm, a power added efficiency output of >=34%, and a small signal gain of >=20dB. The output saturated power of the input stage die M1 is distributed to the input ends of the drive stage dies M2 and M3 through the inter-stage matching network of the LC series structure and T structure combined by the microstrip line TL4, the microstrip line TL5, the capacitor C3, the microstrip line TL6, the grounding capacitor C4 and the microstrip line TL8, and the inter-stage matching network of the LC series structure and T structure combined by the microstrip line TL4, the microstrip line TL5, the capacitor C3, the microstrip line TL7, the grounding capacitor C5 and the microstrip line TL9, so as to realize effective impedance matching between the input stage and the drive stage and improve the performance. The inter-stage matching network of the LC series structure and T structure combined by the microstrip line TL4, the microstrip line TL5, the capacitor C3, the microstrip line TL6, the grounding capacitor C4 and the microstrip line TL8, and the inter-stage matching network of the LC series structure and T structure combined by the microstrip line TL4, the microstrip line TL5, the capacitor C3, the microstrip line TL7, the grounding capacitor C5 and the microstrip line TL9 are symmetrical and have the same parameters. Since a plurality of devices are used in the application, the connecting network composed of the microstrip line TL10, the resistor R3, the microstrip line TL12, the microstrip line TL11 and the microstrip line TL12 is used to reduce the oscillation generated by the drive stage and improve the stability of the circuit. Considering the area and performance requirements, the drive stage dies M2 and M3 have a certain driving amplification capacity, so the gate length of the drive stage dies M2 and M3 is selected as 4*75um. The output stage die has sufficient output saturated output power capacity, and the gate length of the four output stage dies M4, M5, M6 and M7 is selected as 6*75um. In order to have a saturated power output of >=29.5dBm, the drive stage adopts two dies for two-way cluster power distribution, and the output stage adopts four dies for four-way cluster power synthesis. The saturated output power of the drive stage die M2 is distributed to the input ends of the output stage dies M4 and M5 through the inter-stage matching network of the LC series structure and T structure combined by the microstrip line TL14, the microstrip line TL16, the capacitor C6, the microstrip line TL18, the microstrip line TL20, the grounding capacitor C8 and the microstrip line, and the inter-stage matching network of the LC series structure and T structure combined by the microstrip line TL14, the microstrip line TL16, the capacitor C6, the microstrip line TL18, the microstrip line TL21, the grounding capacitor C9 and the microstrip line TL25, so as to realize effective impedance matching between the drive stage and the output stage and improve the performance of the power amplifier of the application.The microstrip line TL14, the microstrip line TL16, the capacitor C6, the microstrip line TL18, the microstrip line TL20, the grounding capacitor C8 and the microstrip line constitute the LC series structure and T structure combined inter-stage matching network, and the microstrip line TL14, the microstrip line TL16, the capacitor C6, the microstrip line TL18, the microstrip line TL21, the grounding capacitor C9 and the microstrip line TL25 constitute the LC series structure and T structure combined inter-stage matching network which are symmetrical and have the same parameters. The driving stage die M3 is connected to the input ends of the output stage dies M6 and M5 through the LC series structure and T structure combined inter-stage matching network constituted by the microstrip line TL15, the microstrip line TL17, the capacitor C7, the microstrip line TL19, the microstrip line TL22, the grounding capacitor C10 and the microstrip line TL26, and the LC series structure and T structure combined inter-stage matching network constituted by the microstrip line TL15, the microstrip line TL17, the capacitor C7, the microstrip line TL19, the microstrip line TL23, the grounding capacitor C11 and the microstrip line TL27, so that the driving stage and the output stage are effectively impedance matched, and the performance of the power amplifier is improved. The LC series structure and T structure combined inter-stage matching network constituted by the microstrip line TL15, the microstrip line TL17, the capacitor C7, the microstrip line TL19, the microstrip line TL22, the grounding capacitor C10 and the microstrip line TL26 and the LC series structure and T structure combined inter-stage matching network constituted by the microstrip line TL15, the microstrip line TL17, the capacitor C7, the microstrip line TL19, the microstrip line TL23, the grounding capacitor C11 and the microstrip line TL27 are symmetrical and have the same parameters. In order to prevent circuit oscillation, the resistor R2 is connected to the 1 port of the output stage dies M4 and M5, and the resistor R3 is connected to the 1 port of the output stage dies M6 and M7, so that the stability of the circuit is improved. The output power of the output stage dies M4 and M5 is combined into one path through the T type matching network constituted by the microstrip line TL28, the grounding capacitor C12 and the microstrip line TL32 and the T type matching network constituted by the microstrip line TL29, the grounding capacitor C13 and the microstrip line T33, and then is transmitted to the quarter wavelength microstrip line formed by the microstrip line TL109, the grounding capacitor C109, the microstrip line TL36 and the grounding capacitor C16 to form a bias network and a multi-stage reactance matching network, so as to constitute an output end matching network. The output power of the output stage dies M6 and M7 is combined into one path through the T type matching network constituted by the microstrip line TL30, the grounding capacitor C14 and the microstrip line TL34 and the T type matching network constituted by the microstrip line TL31, the grounding capacitor C15 and the microstrip line T35, and then is transmitted to the quarter wavelength microstrip line formed by the microstrip line TL110, the grounding capacitor C110, the microstrip line TL37 and the grounding capacitor C17 to form a bias network and a multi-stage reactance matching network, so as to constitute an output end matching network.The output dies M4 and M5 and the output dies M6 and M7 are combined by a two-way quarter wavelength microstrip line to form a bias network and a multi-stage reactance matching network, and the output end matching network is combined to form a saturated output power, which is output to the radio frequency signal output end RFOUT through the reactance matching network formed by the microstrip line TL38, the grounding capacitor C18 and the capacitor C19. Figure 3 As shown in the figure, the power added efficiency PAE_1 of the output end matching network before the output end matching network of the application is combined is only ≥ 31% in the working frequency band of 34GHz-38GHz, and the minimum value of the power added efficiency PAE_2 after the output end matching network is combined can reach 35%, which is about 12.9% higher. Figure 4 As shown in the figure, the input reflection coefficient S(1,1) of the application is ≤-10dB, the output reflection coefficient S(2,2) is ≤-10dB, the small signal gain S(2,1) is between 20dB and 22dB, and the gain flatness is ≤2. Figure 5 As shown in the figure, the power added efficiency PAE_layout of the application is ≥ 34%. Figure 6 As shown in the figure, the saturated output power of the application is ≥ 29.5dBm.

Claims

1. A high-efficiency power amplifier based on GaAs technology in the Ka-band, comprising capacitors C1-C19 and C101-C110, microstrip lines TL1-TL38 and TL101-TL110, input stage die M1, driver stage dies M2 and M3, and output stage dies M4, M5, M6, and M7; characterized in that: The first port of C1 is connected to the RF signal input terminal RFIN. The second port of C1 is connected to the first port of TL1. The second port of TL1 is connected to the first port of TL2 and the first port of C2. The second port of C2 is grounded. The second port of TL2 is connected to the first ports of TL101 and TL3. The second port of TL101 and the first port of C101 are connected to the gate bias voltage VGS1 of M1. The second port of C101 is grounded. The second port of TL3 is connected to port 1 of M1. Port 2 of M1 is connected to the first port of TL4. Port 3 of M1 is grounded. The second port of TL4 is connected to the first ports of TL102 and TL5. The second ports of TL102 and the first port of C102 are connected to the drain bias voltage VDS1 of M1. The second port of C102 is grounded. The second port of TL5 is connected to the first port of C3. The second port of C3 is connected to the first ports of TL6 and TL7. The second port of TL6 is connected to the first port of C4 and the first port of TL8. The second port of C4 is grounded. The second port of TL8 is connected to the first ports of TL103 and TL10. The second port of TL103 and the first port of C103 are connected to the gate bias voltage VGS2_1 of M2. The second port of C103 is grounded. The second port of TL10 is connected to the first port of resistor R1 and the first port of TL12. The second port of TL12 is connected to port 1 of M2. The second port of TL7 is connected to the first port of C5 and the first port of TL9. The second port of TL9 is connected to the first ports of TL104 and TL11. The second port of TL104 and the first port of C104 are connected to the gate bias voltage VGS2_2 of M3. The second port of C104 is grounded. The second port of TL11 is connected to the second port of resistor R1 and the first port of TL13. The second port of TL13 is connected to port 1 of M3. Port 2 of M2 is connected to the first port of TL14, and port 3 of M2 is grounded; the second port of TL14 is connected to the first ports of TL105 and TL16; the second port of TL105 and the first port of C105 are connected to the drain bias voltage VDS2_1 of M2, and the second port of C105 is grounded; the second port of TL16 is connected to the first port of C6, the second port of C6 is connected to the first ports of TL107 and TL18, the second port of TL107 and the first port of C107 are connected to the gate bias voltage VGS3_1 of M4 and M5, and the second port of C107 is grounded; the second port of TL18 is connected to the first ports of TL20 and TL21, the second port of TL20 is connected to the first port of C8 and the first port of TL24, the second port of C8 is grounded, the second port of TL24 is connected to the first port of resistor R2 and port 1 of M4; the second port of TL21 is connected to the first port of C9 and the first port of TL25, the second port of C9 is grounded, and the second port of TL25 is connected to the second port of resistor R2 and port 1 of M5; Port 2 of M3 is connected to the first port of TL15, and port 3 of M3 is grounded. Port 2 of TL15 is connected to the first ports of TL106 and TL17. Port 2 of TL106 and port 1 of C106 are connected to the drain bias voltage VDS2_2 of M3, and port 2 of C106 is grounded. Port 2 of TL17 is connected to the first port of C7. Port 2 of C7 is connected to the first ports of TL108 and TL19. Port 2 of TL108 and port 1 of C108 are connected to the gate bias voltage VGS3_2 of M6 and M7, and port 2 of C108 is grounded. Port 2 of TL19 is connected to the first ports of TL22 and TL23. Port 2 of TL22 is connected to the first ports of C10 and TL26. Port 2 of C10 is grounded. Port 2 of TL26 is connected to the first port of resistor R3 and port 1 of M6. Port 2 of TL23 is connected to the first port of C11 and the first port of TL27. Port 2 of C11 is grounded. Port 2 of TL27 is connected to the second port of resistor R3 and port 1 of M7. Port 2 of M4 is connected to the first port of resistor R4 and the first port of TL28, and port 3 of M4 is grounded; port 2 of TL28 is connected to the first port of C12 and the first port of TL32, and port 2 of C12 is grounded; port 2 of M5 is connected to the second port of resistor R4 and the first port of TL29, and port 3 of M5 is grounded; port 2 of TL29 is connected to the first port of C13 and the first port of TL33, and port 2 of C13 is grounded. The second port of TL32, the second port of TL33, the first port of TL109, and the first port of TL36 are interconnected. The second port of TL109 and the first port of C109 are connected to the drain bias voltage VDS3_1 of M4 and M5, and the second port of C109 is grounded. The second port of TL36 is connected to the first port of C16 and the first port of TL38, and the second port of C16 is grounded. Port 2 of M6 is connected to the first port of resistor R5 and the first port of TL30, and port 3 of M6 is grounded; port 2 of TL30 is connected to the first port of C14 and the first port of TL34, and port 2 of C14 is grounded; port 2 of M7 is connected to the second port of resistor R5 and the first port of TL31, and port 3 of M7 is grounded; port 2 of TL31 is connected to the first port of C15 and the first port of TL35, and port 2 of C15 is grounded. The second port of TL34, the second port of TL35, the first port of TL110, and the first port of TL37 are interconnected. The second port of TL110 and the first port of C110 are connected to the drain bias voltage VDS3_2 of M6 and M7, and the second port of C110 is grounded. The second port of TL37 is connected to the first port of C17 and the first port of TL38, and the second port of C17 is grounded. The second port of TL38 is connected to the first port of C18 and C19. The second port of C18 is grounded, and the second port of C19 is connected to the RF signal output terminal RFOUT.

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