Adaptive elimination method for fixed clock frequency division stray in ADC (Analog to Digital Converter) acquired data
By generating a phase- and amplitude-adjustable DDS signal within the FPGA, and using product and subtraction operations to eliminate fixed clock frequency division spurious signals, the problem of ADC performance degradation caused by poor digital-to-analog isolation is solved. This achieves adaptive elimination of fixed clock frequency division spurious signals, thereby improving the ADC's SFDR and SNR performance.
Patent Information
- Application Number
- CN202511522677.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-23
- Publication Date
- 2026-02-03
AI Technical Summary
In communication, radar, and electronic countermeasures systems, the fixed clock frequency division spurious emissions caused by poor digital-to-analog isolation affect the SFDR and SNR performance of ADCs, which are difficult to effectively handle with existing technologies.
An adaptive method within the FPGA is employed, which generates a DDS signal with adjustable phase and amplitude, multiplies and sums it with the input fixed-clock frequency-divided spurious signal, adjusts the DDS signal to match the frequency and phase of the spurious signal, and then performs subtraction to eliminate it.
Without increasing the area of the ADC's peripheral circuitry, this method effectively eliminates fixed clock frequency division spurious signals, simplifies the processing circuitry, adapts to ADC operation under different sampling clocks, and improves ADC performance.
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Figure CN121461981A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of communication, radar, and electronic countermeasures, and in particular to an adaptive method for eliminating fixed clock frequency division spurious signals in ADC acquisition data. Background Technology
[0002] In communication, radar, and electronic countermeasures systems, with increasingly stringent requirements for cost, size, power consumption, and bandwidth, direct RF sampling is finding wider application scenarios. The continuous increase in sampling frequency and data rate of ADC converters necessitates higher requirements for digital-to-analog isolation. Factors affecting ADC performance include system noise, spurious signals, and harmonics. The first two factors, with their random frequency, amplitude, and phase characteristics, cannot be accurately located and processed in the post-stage of a high-speed ADC and must be addressed through system design and PCB layout. Fixed-clock spurious signals, however, are correlated with the sampling clock and can be processed digitally in the post-sampling stage of the ADC. For example, if a high-speed ADC uses a clock frequency of fs / D (where fs is the sampling frequency and D is a fixed integer) in the digital domain, and the ADC's digital-to-analog power ground is not effectively isolated, this digital clock will couple to the analog domain to some extent, generating fixed-clock spurious signals during ADC sampling that affect the ADC's SFDR and SNR performance. Summary of the Invention
[0003] This invention provides an adaptive elimination method for fixed clock division spurious signals in ADC acquisition data, which solves the problem of fixed clock division spurious signals caused by poor digital-to-analog isolation in high-speed ADCs. The elimination process can be performed within the FPGA without increasing the area of the ADC peripheral circuit, thus simplifying the processing circuit. In software radio, the ADC sampling frequency changes with the application environment, and the fixed clock division spurious signals need to be eliminated adaptively according to the change in sampling rate.
[0004] This invention is achieved using the following technical solution: An adaptive method for eliminating fixed clock division spurious signals in ADC acquisition data includes the following steps: Step S1: Generate a system DDS signal with adjustable phase and amplitude; Step S2: Multiply the system DDS signal with the input fixed clock frequency division spurious signal, and sum them up at a certain number of sample points; Step S3: Calculate the amplitude and phase of the input fixed clock frequency division spurious signal using the summation result, adjust the system DDS signal to a new DDS signal with the same frequency, amplitude and phase as the fixed clock frequency division spurious signal, and eliminate the spurious signal by subtracting the new DDS signal from the input fixed clock frequency division spurious signal.
[0005] Specifically, the system DDS signal generated in step S1 is at the same frequency as the input fixed clock frequency-divided spurious signal, as expressed as: .
[0006] Specifically, the frequency of the input fixed clock frequency-divided spurious signal is set to fs / D, the period is T=D / fs, and the signal is represented as: .
[0007] Specifically, the product operation of the system DDS signal and the input fixed clock frequency-divided spurious signal in step S2 is expressed as follows: .
[0008] Specifically, the amplitude calculation of the input fixed clock frequency division spurious signal in step S3 includes: Perform the product operation on the result Integrating over 10 periods, we obtain: ; when and When in phase, that is , =1, s(t) is the maximum value. , is represented as: ; Obtain the fixed clock frequency division spurious signal The amplitude value is: .
[0009] Specifically, the new DDS signal in step S3 is represented as follows: .
[0010] Specifically, the subtraction elimination in step S3 is represented as follows: Divide the input fixed clock frequency spurious signal Subtract the adjusted new DDS signal The ADC data obtained after eliminating fixed clock frequency division spurious signals is as follows: ; A value of 0 indicates that the input fixed clock frequency division spurious signal has been eliminated.
[0011] Specifically, it also includes: when using an FPGA to perform the adaptive elimination process of steps S1 to S3, converting the serial ADC data into parallel ADC data.
[0012] The beneficial effects of this invention are as follows: It employs an adaptive approach, allowing the high-speed ADC to operate under different sampling clocks. The frequency and phase of the fixed clock spurious signal are related to the sampling rate, and the amplitude of the fixed clock spurious signal can vary randomly, resulting in a wide range of applications. Using digital processing, it can be implemented using an FPGA, simplifying the hardware structure of the ADC's peripheral circuitry. This method effectively eliminates the fixed clock spurious signal (fs / D, where fs is the sampling rate and D is a fixed integer) generated during ADC sampling due to poor digital-to-analog isolation. The adaptive function allows the ADC to operate under sampling clocks of different frequencies. The frequency and phase of the fixed clock spurious signal are related to the sampling rate, and the amplitude of the fixed clock spurious signal varies randomly. Attached Figure Description
[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0014] Figure 1 This is a schematic diagram of the fixed clock frequency division spurious elimination process in an embodiment of the present invention; Figure 2 This is a schematic diagram of the fixed clock frequency division spurious elimination process using FPGA in this embodiment; Figure 3 This is a schematic diagram of the adaptive system clock processing flow in this embodiment; Figure 4 This is the timing diagram for the fixed clock frequency division spurious elimination FPGA module in this embodiment. Detailed Implementation
[0015] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0016] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0017] The following is in conjunction with the appendix Figures 1-4 The following describes some embodiments of the present invention in detail. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0018] This invention proposes an adaptive elimination method for fixed clock frequency division spurious signals in ADC acquisition data. The method employs a Direct Current Distribution (DDS) to multiply the fixed clock frequency division spurious signals, and uses the accumulated result of the multiplication to determine the phase and amplitude of the spurious signals. A DDS signal with the same frequency, amplitude, and phase as the spurious signals is generated. The DDS signal is then subtracted from the spurious signals to eliminate them. Since the fixed clock frequency division spurious signals are correlated with the sampling clock, using fs / D as the system's operating clock allows for adjustment of the operating clock according to changes in the sampling rate, thus enabling adaptive elimination of fixed clock frequency division spurious signals even when the sampling clock changes. In a preferred embodiment, the method specifically includes the following steps: Step S1: Generate a system DDS signal with adjustable phase and amplitude; Step S2: Multiply the system DDS signal with the input fixed clock frequency division spurious signal, and sum them up at a certain number of sample points; Step S3: Calculate the amplitude and phase of the input fixed clock frequency division spurious signal using the summation result, adjust the system DDS signal to a new DDS signal with the same frequency, amplitude and phase as the fixed clock frequency division spurious signal, and eliminate the spurious signal by subtracting the new DDS signal from the input fixed clock frequency division spurious signal.
[0019] In this embodiment, it is assumed that the frequency of the input fixed-clock spurious signal is fs / D, and the period is T=D / fs. The fixed-clock spurious signal is represented by f(t), and its function is: .
[0020] The system generates a DDS signal with the same frequency as f(t), whose function is: .
[0021] Multiplying the input fixed-clock spurious signal with the DDS signal yields the following result: = = = Perform on y(t) Integrating over a period of time, we have: When f(t) and h(t) are in phase ( )hour, =1, s(t) is the maximum value. ,but: .
[0022] Therefore, the magnitude of f(t) can be deduced as follows: .
[0023] Adjusting the amplitude and phase of the DDS signal to match the frequency-divided spurious signal of the input fixed clock is expressed as: ; Subtract the adjusted DDS signal from the input fixed clock frequency division spurious signal f(t). We can obtain: = =0 Therefore, it can be concluded that the input fixed clock frequency division spurious signal has been eliminated.
[0024] This fixed clock frequency division spurious cancellation method is applicable to situations where the system has spurious signals at a fixed frequency of fs / D (where fs is the sampling frequency and D is a fixed integer), but the bandwidth of the useful signal must not fall on the fixed frequency of fs / D.
[0025] The following are some specific examples for illustration: Example 1: Fixed Clock Frequency Division Spurious Elimination like Figure 1 As shown, f(n) is the input fixed-clock spurious signal, and h(n) is the DDS signal generated by the system, whose initial phase is adjustable from 0 to 256 (0°~360°). The fixed-clock spurious signal is copied into two paths, one of which is multiplied by the fixed-clock spurious signal (104), and the result of the multiplication is y(n). y(n) is then processed... Accumulate (106), the accumulated output is s(n), if s(n) is greater than the accumulated value of the current record. If the value is large (108), then the current value of s(n) will be assigned to... (110). The initial phase of the DDS signal is accumulated and scanned (102), and the above multiplication, summation, judgment and assignment are repeated. After the phase of the DDS has traversed from 0 to 256 (112), the following is obtained: From the peak value and the initial phase value of DDS at the peak value, the amplitude A of the fixed clock frequency division spurious signal can be calculated. , The DDS signal at the peak value is in phase with the fixed-clock spurious signal (114). The other fixed-clock spurious signal is subtracted from the DDS signal whose phase and amplitude have been adjusted (118) to obtain the ADC data f_out(n) after eliminating the fixed-clock spurious signal.
[0026] Example 2: Fixed Clock Spurious Elimination Using FPGA High-speed ADCs with direct RF sampling widely adopt high-speed serial interfaces, with sampling rates exceeding 1 GSPS. FPGAs cannot process at such high rates. If FPGAs are required to process the data according to the adaptive elimination method of this invention, the serial ADC data must be converted into parallel ADC data to reduce the processing speed of the FPGA.
[0027] In this embodiment, the block diagram for fixed clock division spurious cancellation processing using FPGA is shown below. Figure 2 As shown, serial data is converted into four parallel data streams, namely f(n), f(n-1), f(n-2), and f(n-3), which are four parallel ADC signal inputs. Simultaneously, the system generates four DDS signals with default initial phases of 0°, 90°, 180°, and 240°. The four parallel data streams are multiplied by the four DDS signals (204). The results of these four multiplications are then summed. The sums of the four sums are added pairwise to obtain a single accumulated result s(n) (206). If s(n) is greater than the currently recorded accumulated value... If the value is large (208), then the current value of s(n) will be assigned to... (210). The initial phases of the four DDS signals are accumulated and scanned (202), and the above multiplication, summation, judgment and assignment are repeated. After the phase of the DDS has traversed from 0 to 256 (212), the following is obtained: From the peak value and the initial phase value of DDS at the peak value, the amplitude A of the fixed clock frequency division spurious signal can be calculated. , The peak DDS signal is in phase with the fixed-clock spurious signal (214). The fixed-clock spurious data of the 4 parallel ADCs are subtracted from the 4 DDS signals with adjusted phase and amplitude (218), and finally the 4 parallel ADC signal data f_out(n), f_out(n-1), f_out(n-2), and f_out(n-3) after fixed-clock spurious cancellation are output.
[0028] In one embodiment, such as Figure 3As shown, the D-division of the ADC sampling clock is used as the adaptive working clock of the system, with a frequency of fs / D (302). This working clock serves as the global clock to drive data transmission (304), DDS detection signal generation (306), accumulator unit (308), amplitude and phase calculation unit (310), DDS cancellation signal generation (312), and output data transmission. The output frequency of the generated DDS detection signal is fs / D, and the frequency of the input fixed clock division spurious signal is also fs / D. When the ADC sampling rate fs changes, the frequency of the fixed clock division spurious signal and the output frequency of the DDS detection signal will also change accordingly. However, the relative values of the frequencies of the fixed clock division spurious signal and the DDS detection signal are fixed, thus enabling the adaptive processing of the fixed clock division spurious signal.
[0029] Timing of FPGA processing, such as Figure 4 adc_din[0]~adc_din[3] are the 4-channel parallel ADC data of the input module, clk is the module working clock, which is fixed at fs / 4, corr_start is the calibration start signal input, dou_sel is the output calibration signal enable, rstn is the module reset input, corr_over is the calibration completion signal, and dou[0]~dout[3] are the 4-channel parallel ADC data output. The system starts self-calibration upon power-up. The ADC input is empty, that is, no useful signal is input, only the generated fixed clock frequency division spurious signal is retained. The system inputs a low-level reset signal rstn, and each sub-circuit module is initialized. When corr_start is detected to be high, the calibration process is executed according to the fixed clock frequency division spurious data of adc_din[0]~adc_din[3]. When corr_over outputs a high level, it indicates that the calibration is complete. When dou_sel is high, dou[0]~dout[3] outputs data that has eliminated the fixed clock frequency division spurious signal. At this time, the ADC can input a useful signal.
[0030] For the foregoing embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to this application.
[0031] The above embodiments describe the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Modifications and variations made by those skilled in the art without departing from the spirit and scope of the invention should be within the protection scope of the appended claims.
Claims
1. An adaptive method for eliminating fixed clock frequency division spurious signals in ADC acquisition data, characterized in that, Includes the following steps: Step S1: Generate a system DDS signal with adjustable phase and amplitude; Step S2: Multiply the system DDS signal with the input fixed clock frequency division spurious signal, and sum them up at a certain number of sample points; Step S3: Calculate the amplitude and phase of the input fixed clock frequency division spurious signal using the summation result, adjust the system DDS signal to a new DDS signal with the same frequency, amplitude and phase as the fixed clock frequency division spurious signal, and eliminate the spurious signal by subtracting the new DDS signal from the input fixed clock frequency division spurious signal.
2. The adaptive elimination method for fixed clock division spurious signals in ADC acquisition data as described in claim 1, characterized in that, The system DDS signal generated in step S1 has the same frequency as the input fixed clock frequency-divided spurious signal, which is expressed as: .
3. The adaptive elimination method for fixed clock division spurious signals in ADC acquisition data as described in claim 2, characterized in that, The frequency of the input fixed clock frequency-divided spurious signal is set to fs / D, and the period is T=D / fs. The signal is represented as follows: .
4. The adaptive elimination method for fixed clock division spurious signals in ADC acquisition data as described in claim 3, characterized in that, The product operation of the system DDS signal and the input fixed clock frequency division spurious signal in step S2 is expressed as follows: 。 5. The adaptive elimination method for fixed clock division spurious signals in ADC acquisition data as described in claim 4, characterized in that, The amplitude calculation of the input fixed clock frequency division spurious signal in step S3 specifically includes: Perform the product operation on the result Integrating over 10 periods, we obtain: ； when and When in phase, that is , =1, s(t) is the maximum value. , is represented as: ； Obtain the fixed clock frequency division spurious signal The amplitude value is: .
6. The adaptive elimination method for fixed clock division spurious signals in ADC acquisition data as described in claim 5, characterized in that, The new DDS signal in step S3 is represented as follows: 。 7. The adaptive elimination method for fixed clock division spurious signals in ADC acquisition data as described in claim 6, characterized in that, The subtraction elimination in step S3 is represented as follows: Divide the input fixed clock frequency spurious signal Subtract the adjusted new DDS signal The ADC data obtained after eliminating fixed clock frequency division spurious signals is as follows: ； A value of 0 indicates that the input fixed clock frequency division spurious signal has been eliminated.
8. The adaptive elimination method for fixed clock division spurious signals in ADC acquisition data as described in claim 1, characterized in that, Also includes: When using an FPGA to perform the adaptive elimination process in steps S1 to S3, the serial ADC data is converted into parallel ADC data.