Double-comparator SAR ADC background calibration method based on variable step LMS algorithm

Abstract

The invention discloses a dual-comparator SAR ADC background calibration method based on a variable step LMS algorithm, and the method comprises the steps: designing an input signal, and collecting an output code; obtaining a first statistical result based on the starting sequence of the control comparator and the lowest bit of the output code; determining a calibration direction according to the first statistical result and calculating a statistical result error; calibrating the offset voltage of the comparator according to the calculated calibration direction and the statistical result error by adopting a variable-step LMS algorithm; after error compensation is carried out according to the calibrated voltage, an output code is collected again and used for updating the first statistical result; and repeating the steps until the cycle index reaches the maximum cycle requirement. According to the invention, no extra clock is introduced, the calibration direction is determined on the basis of the original dual-comparator structure by counting the starting sequence of the dual comparators and counting the last comparison result of the comparators, the error is minimized as much as possible by adopting the variable step LMS algorithm, and the performance of the DC-SAR ADC is improved.

Description

Technical Field

[0001] This invention belongs to the field of digital-to-analog converters and relates to digital-to-analog converter calibration technology, specifically to a background calibration method for a dual comparator SAR ADC based on the variable step-size LMS algorithm. Background Technology

[0002] In recent years, with the continuous development of communication technology and high-speed serial interface technology, the requirements for high-speed analog-to-digital converters (ADCs) have become increasingly stringent. Among them, dual-comparator successive approximation analog-to-digital converters (DC-SAR ADCs) are widely used due to their characteristics such as no operational amplifiers, low power consumption, and fast conversion speed.

[0003] In a DC-SAR ADC, two comparators operate alternately; while one comparator is performing a comparison, the other is reset. Compared to a single-comparator SAR ADC, a DC-SAR ADC avoids the impact of comparator reset time on the ADC's conversion rate.

[0004] However, DC-SAR ADCs are affected by the relative misalignment between the two comparators, which can severely degrade the ADC's performance and directly affect the conversion accuracy of the digital-to-analog converter. Summary of the Invention

[0005] Purpose of the invention: To overcome the shortcomings of the existing technology, a background calibration method for dual comparator SAR ADC based on variable step size LMS algorithm is provided. This method does not introduce an additional clock. On the original dual comparator structure, the calibration direction is determined by statistical analysis of the turn-on sequence of the dual comparators and the statistical analysis of the last comparison result of the comparators. The variable step size LMS algorithm is used to minimize the error as much as possible, thereby improving the performance of DC-SAR ADC.

[0006] Technical Solution: To achieve the above objectives, this invention provides a background calibration method for a dual-comparator SAR ADC based on the variable step-size LMS algorithm, comprising the following steps:

[0007] S1: Design the input signal, acquire the output encoding;

[0008] S2: Based on the enabling order of the control comparator and the least significant bit of the output code, the first statistical result is obtained;

[0009] S3: Determine the calibration direction based on the first statistical result and calculate the statistical result error;

[0010] S4: The comparator offset voltage is calibrated using the variable step size LMS algorithm based on the calculated calibration direction and statistical error.

[0011] S5: After error compensation based on the calibrated voltage, the output code is collected again to update the first statistical result;

[0012] S6: Repeat steps S1 to S5 until the maximum number of iterations is reached.

[0013] Furthermore, the input signal designed in step S1 is

[0014]

[0015] Among them, V in V represents the input signal. offset V represents the offset in the input signal. amplitude The input signal's original amplitude is represented by f, the input signal's frequency is represented by f, and the input signal's time vector is represented by t.

[0016] Furthermore, in step S2, a set of random signals is used to control the turn-on order of the comparators to ensure that the two comparators have the same probability of turning on first during the measurement of a set of input signals. The value of the least significant bit of the output code is statistically analyzed and corresponds to the corresponding turn-on comparator to obtain the first statistical result.

[0017] Furthermore, in step S3, when the number of ADC bits is N, N is an even number. Assume that the offset voltages of comparator 1 and comparator 2 are x1 and x2 respectively, where x1>x2; p1(1) is obtained according to the first statistical result. N偶 and p2(1) N偶 The two parameters are the probability that the comparison result of the Nth (N≥2) bit is 1 when the comparator is 1 for the first time and the probability that the comparison result of the Nth (N≥2) bit is 1 when the comparator is 2 for the first time.

[0018] Furthermore, the method for determining the calibration direction in step S3 includes:

[0019] According to p1(1) N偶 and p2(1) N偶 Perform the following calculations:

[0020]

[0021] Among them, let =C, then the above formula is updated to:

[0022]

[0023] Where C>0 when N≥2 and N is even, and since x1 is greater than x2, therefore Δp (1-2)>0; This indicates that the probability of comparator 2 participating in the Nth comparison and determining the least significant bit as 1 is greater than the probability of comparator 1 participating in the Nth comparison and determining the least significant bit as 1; similarly, when N is odd, it is...

[0024]

[0025] Where C>0 when N≥2 and N is odd, and since x1 is greater than x2, therefore Δp (1-2) <0; This indicates that the probability of comparator 1 participating in the Nth comparison and determining LSB as 1 is less than the probability of comparator 2 participating in the Nth comparison and determining LSB as 1.

[0026] Based on the analysis of these two cases, it can be seen that when N is even, x1 and x2 are not the same. If x1 is greater than x2, then P1(1) N >P2(1) N If x1 is less than x2, then P1(1) N <P2(1) N When N is odd, if x1 is greater than x2, then P1(1) N <P2(1) N If x1 is less than x2, then P1(1) N >P2(1) N Thus, the calibration direction for mismatch is obtained.

[0027] Furthermore, in step S4, a nonlinear step size adjustment method is used to dynamically adjust the comparator offset voltage. The designed step size adjustment factor formula is as follows:

[0028]

[0029] Where a, b, and c are user-defined parameters; e(n) represents the error. Parameter a plays a decisive role in adjusting the step size; a larger value of a results in a larger step size, thus improving the algorithm's convergence speed. Meanwhile, the values ​​of parameters b and c significantly affect the shape of the step size factor function graph. When a and b are fixed, a larger c results in a larger change in the step size factor. When a and c are fixed, b has little effect on the change in the step size factor, but it can be observed that a smaller b results in a larger change in the step size factor, allowing for fine-tuning of the step size factor's variation.

[0030] Furthermore, the error compensation method in step S5 based on the calibrated voltage is as follows:

[0031] By controlling the activation order of the two comparators with a random signal, and statistically analyzing the last comparison result of the comparators over a period of time, the error function e is calculated. N for

[0032]

[0033] Among them, e N The error is represented by P1(1), which is then approached to 0 using the LMS algorithm. N P2(1) N These are the expected values ​​of comparator 1 and comparator 2 respectively for the Nth bit over a certain period of time, where the result is 1; when e N When e is greater than 0, comparator 1 is negatively compensated, and comparator 2 is positively compensated; when e N When the value is less than 0, comparator 1 is positively compensated and comparator 2 is negatively compensated.

[0034] Furthermore, the update formula for the first statistical result in step S5 is:

[0035]

[0036] Where φ is the adjustment step size for the comparator offset voltage.

[0037] Beneficial effects: Compared with the prior art, this invention first sets a certain range of input signals to continuously input to the DC-SAR ADC. During this process, the first statistical result is obtained based on the least significant bit of the output code and the comparator activation order during statistical comparison, thereby determining the calibration direction. The variable step size LMS algorithm is used to perform background calibration of the DC-SAR ADC, effectively accelerating the calibration speed and improving the calibration accuracy. After verification, the method of this invention can be better applied to the relative offset calibration of dual comparators in DC-SAR ADC. The calibration speed is fast and does not occupy an additional clock cycle during the calibration process. After calibration, the impact of the offset voltage between the two comparators on the accuracy of the analog-to-digital converter output result is significantly reduced, effectively improving the effective number of bits of the analog-to-digital converter. Attached Figure Description

[0038] Figure 1 This is a schematic flowchart of the calibration method of the present invention;

[0039] Figure 2 This is a basic structural diagram of a dual-comparator SAR ADC;

[0040] Figure 3 This is a diagram illustrating the ideal conversion process of a 3-bit dual comparator SAR ADC.

[0041] Figure 4 For offset voltage simulation model;

[0042] Figure 5 Error analysis chart;

[0043] Figure 6 A graph showing the influence of each parameter on u(n);

[0044] Figure 7 The curve represents the change of the linear scaling factor.

[0045] Figure 8 A comparison of the function graphs of the nonlinear adjustment factor and the linear scaling factor;

[0046] Figure 9 A comparison chart of calibration results from Experiment 1;

[0047] Figure 10 This is a comparison chart of the calibration results for Experiment 2;

[0048] Figure 11 This is a comparison chart of the calibration results for Experiment 3. Detailed Implementation

[0049] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. After reading this invention, any modifications of the invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.

[0050] Example 1:

[0051] like Figure 1 As shown, this embodiment provides a background calibration method for a dual-comparator SAR ADC based on the variable step-size LMS algorithm, including the following steps:

[0052] S1: Design the input signal, acquire the output encoding;

[0053] The designed input signal is

[0054]

[0055] Among them, V in V represents the input signal. offset V represents the offset in the input signal. amplitude The input signal's original amplitude is represented by f, the input signal's frequency is represented by f, and the input signal's time vector is represented by t.

[0056] S2: The turn-on order of the comparators is controlled by a set of random signals to ensure that the two comparators have the same probability of turning on first during the measurement of a set of input signals. The value of the least significant bit of the output code is counted and corresponds to the corresponding turn-on comparator to obtain the first statistical result.

[0057] S3: Determine the calibration direction based on the first statistical result and calculate the statistical result error;

[0058] When the ADC bit depth is N, N is an even number. Assume that the offset voltages of comparator 1 and comparator 2 are x1 and x2 respectively, where x1>x2; according to the first statistical result, p1(1) is obtained. N偶 and p2(1) N偶 The two parameters are the probability that the comparison result of the Nth (N≥2) bit is 1 when the comparator is 1 for the first time and the probability that the comparison result of the Nth (N≥2) bit is 1 when the comparator is 2 for the first time.

[0059] Methods for determining the calibration direction include:

[0060] According to p1(1) N偶 and p2(1) N偶 Perform the following calculations:

[0061]

[0062] Among them, let =C, then the above formula is updated to:

[0063]

[0064] Where C>0 when N≥2 and N is even, and since x1 is greater than x2, therefore Δp (1-2) >0; This indicates that the probability of comparator 2 participating in the Nth comparison and determining the least significant bit as 1 is greater than the probability of comparator 1 participating in the Nth comparison and determining the least significant bit as 1; similarly, when N is odd, it is...

[0065]

[0066] Where C>0 when N≥2 and N is odd, and since x1 is greater than x2, therefore Δp (1-2) <0; This indicates that the probability of comparator 1 participating in the Nth comparison and determining LSB as 1 is less than the probability of comparator 2 participating in the Nth comparison and determining LSB as 1.

[0067] Based on the analysis of these two cases, it can be seen that when N is even, x1 and x2 are not the same. If x1 is greater than x2, then P1(1) N >P2(1) N If x1 is less than x2, then P1(1) N <P2(1) N When N is odd, if x1 is greater than x2, then P1(1) N <P2(1) N If x1 is less than x2, then P1(1) N >P2(1) N Thus, the calibration direction for mismatch is obtained.

[0068] S4: The comparator offset voltage is calibrated using the variable step size LMS algorithm based on the calculated calibration direction and statistical error.

[0069] A nonlinear step size adjustment method is used to dynamically adjust the comparator offset voltage. The formula for the designed step size adjustment factor is as follows:

[0070]

[0071] Where a, b, and c are user-defined parameters; e(n) represents the error. Parameter a plays a decisive role in adjusting the step size; a larger value of a results in a larger step size, thus improving the algorithm's convergence speed. Meanwhile, the values ​​of parameters b and c significantly affect the shape of the step size factor function graph. When a and b are fixed, a larger c results in a larger change in the step size factor. When a and c are fixed, b has little effect on the change in the step size factor, but it can be observed that a smaller b results in a larger change in the step size factor, allowing for fine-tuning of the step size factor's variation.

[0072] S5: After error compensation based on the calibrated voltage, the output code is collected again to update the first statistical result;

[0073] The update formula for the first statistical result is:

[0074]

[0075] Where φ is the adjustment step size for the comparator offset voltage.

[0076] S6: Repeat steps S1 to S5 until the maximum number of iterations is reached.

[0077] Example 2:

[0078] like Figure 1 As shown, this embodiment provides a background calibration method for a dual-comparator SAR ADC based on the variable step-size LMS algorithm, including the following steps:

[0079] 1) Design the input signal and acquire the output encoding:

[0080] The input signal used in this embodiment is

[0081]

[0082] The input signal is a sinusoidal signal with an amplitude range of 0.05V-3.95V.

[0083] 2) The turn-on order of the comparators is controlled by a set of random signals to ensure that the two comparators have the same probability of turning on first during the measurement of a set of input signals. The value of the least significant bit of the output code is statistically analyzed and corresponds to the corresponding turn-on comparator to obtain the first statistical result.

[0084] 3) Determine the calibration direction based on the first statistical result and calculate the statistical result error:

[0085] In this embodiment, the basic structure of the dual-comparator SAR ADC is as follows: Figure 2 As shown in the figure. It mainly includes a sample-and-hold circuit (S / H), a digital-to-analog converter, dual comparators, an asynchronous clock and SAR logic module, a digital error correction circuit, and a decoding output unit.

[0086] Input voltage V in First, the sample-and-hold function is completed via the S / H module, and then the data is simultaneously fed into the non-inverting inputs of COMP1 and COMP2. Under the control of the asynchronous clock and SAR logic, the DAC generates a successive approximation analog voltage and inputs it to the inverting inputs of the two comparators. The two comparators operate alternately under the control of clocks clk1 and clk2. The two comparators integrate calibration circuits to compensate for comparator offset. The asynchronous clock and SAR logic module generates the control signal and clock signal for the DAC based on the comparison process, and finally, the decoder unit outputs the converted digital code.

[0087] This embodiment uses a 3-bit dual comparator SAR ADC as an example for analysis, with a reference voltage V. ref =8V, 1LSB=1V. In Figure 3 The diagram illustrates the ideal conversion process where neither comparator exhibits offset. The voltage to be converted is 5.3V. Figure 3 Comparator 1 and Comparator 2 compare the values ​​sequentially, and the final output code value is 101, where the offset voltage V of the two comparators is... os =0V.

[0088] In actual conversion processes, since the inherent characteristics of the two comparators cannot be perfectly unified, relative offset is unavoidable when the two comparators operate alternately. During simulation, the offset voltage of the comparators can be replaced by a voltage source. The offset voltage simulation model is as follows: Figure 4 As shown. The comparator is an ideal comparator, and the offset voltage is supplied by an additional voltage source V. os1 and V os2 The replacement represents the offset voltages of comparator 1 and comparator 2, respectively.

[0089] When the comparator has an offset voltage, comparing the DAC's conversion voltage with the hold circuit's output voltage can lead to a decision error. This is especially true when the conversion voltage is 5.3V. os1 =-0.5V, Vos2 When the voltage is +0.8V, the error analysis is as follows: Figure 5 As shown.

[0090] Figure 5 In (a), the first comparison is performed by comparator 1. During the second comparison, the decision voltage shifts down due to the offset voltage of +0.8V in comparator 2, resulting in an error in the comparison result of comparator 2. Figure 5 In (b), the first comparison is performed by comparator 2, and the second comparison is performed by comparator 1. Although comparator 1 has an offset voltage of -0.5V, which causes the decision voltage to shift upward, it will not lead to a decision error, so comparator 1 can output the correct result. It can be seen that the correctness of the output result of the dual comparator type SAR ADC is not only related to the offset voltage of the comparators, but also to the turn-on sequence of the comparators.

[0091] Assuming the voltage quantization range is 0-V ref The decision voltage for each comparison is

[0092]

[0093] In this context, we assume the offset of comparator 1 is x1, and the offset of comparator 2 is x2. The input voltage is u. Assume that comparator 1 is the first comparator to be turned on. If...

[0094]

[0095] The comparison result is 0 if the result is 0 otherwise, and the voltage across the DAC is 1 in both cases.

[0096]

[0097] The second comparison activates comparator 2. Based on the range in ε1, four scenarios will occur after comparator 2 completes the comparison. At this point, the voltage on the DAC will be...

[0098]

[0099] The third comparison activates comparator 1. Based on the range in ε2, comparator 1 will have eight possible outcomes after the comparison. At this point, the voltage on the DAC will be...

[0100]

[0101] In the fourth comparison, comparator 2 is enabled. Based on the above summary, the probability that comparator 2 determines 1 in the fourth comparison is:

[0102]

[0103] Based on this pattern, when the first comparator is comparator 1, the probability that the comparison result of the Nth (N≥2)th bit is 1 is:

[0104]

[0105] Where i=1 when N is even and i=0 when N is odd; floor(·) is the floor function, and the calculated value is the largest integer not greater than (·). When the comparator that is first turned on is comparator 2, the probability that the comparison result of the Nth (N≥2)th bit is 1 is:

[0106]

[0107] To determine the calibration direction, we discuss two cases: when N is even and when it is odd. When N is even, assuming x1 is greater than x2, we can obtain the following from the two formulas above:

[0108]

[0109] Substitution

[0110]

[0111] Among them, let If it equals C, then the above formula is updated to:

[0112]

[0113] Where C>0 when N≥2 and N is even, and since x1 is greater than x2, therefore Δp (1-2) >0. This indicates that the probability of comparator 2 participating in the Nth comparison and determining LSB as 1 is greater than the probability of comparator 1 participating in the Nth comparison and determining LSB as 1. Similarly, when N is odd...

[0114]

[0115] Where C>0 when N≥2 and N is odd, and since x1 is greater than x2, therefore Δp (1-2) <0. This indicates that the probability of comparator 1 participating in the Nth comparison and determining LSB as 1 is less than the probability of comparator 2 participating in the Nth comparison and determining LSB as 1. Based on the analysis of these two cases, it can be seen that when N is even, if x1 and x2 are different, and x1 is greater than x2, then P1(1) N >P2(1) N If x1 is less than x2, then P1(1) N <P2(1) N When N is odd, if x1 is greater than x2, then P1(1) N <P2(1) NIf x1 is less than x2, then P1(1) N >P2(1) N Based on this conclusion, the calibration direction for misalignment can be obtained.

[0116] 4) The comparator offset voltage is calibrated using the variable step size LMS algorithm based on the calculated calibration direction and statistical error results:

[0117] A nonlinear step size adjustment method is used to dynamically adjust the comparator offset voltage. The formula for the designed step size adjustment factor is as follows:

[0118]

[0119] Where a, b, and c are user-defined parameters; e(n) is the error.

[0120] This paper explores the influence of custom parameters a, b, and c on the step size adjustment factor u(n) in the above formula, such as... Figure 6 As shown. In Figure 6 In (a), the curves show the variation of u(n) with e(n) when a=1, b=0.5 are fixed, and c takes values ​​of 2, 4, 6, and 8 respectively. Figure 6 In (b), with b=0.5 and c=4 fixed, the curves showing the variation of u(n) with e(n) when a takes values ​​of 2, 4, 6, and 8 respectively. Figure 6 In (c), the curves of u(n) as a function of e(n) are given when a=1 and c=3 are fixed, and b takes values ​​of 0.1, 1, 1.5 and 2 respectively.

[0121] Analysis of these three parameters reveals that parameter 'a' plays a decisive role in adjusting the step size. A larger value for 'a' results in a larger step size, thereby improving the algorithm's convergence speed. Meanwhile, the values ​​of parameters 'b' and 'c' significantly influence the shape of the step size factor function graph. When 'a' and 'b' are fixed, a larger 'c' results in a larger change in the step size factor. When 'a' and 'c' are fixed, 'b' has little effect on the change in the step size factor, but a smaller 'b' results in a larger change in the step size factor, allowing for fine-tuning of the step size factor's variation. Therefore, when addressing practical engineering needs, it is necessary to rationally select the values ​​of parameters 'a', 'b', and 'c'.

[0122] 5) After error compensation based on the calibrated voltage, the output code is collected again to update the first statistical result:

[0123] By controlling the activation order of the two comparators with a random signal, and statistically analyzing the last comparison result of the comparators over a period of time, the error function e is calculated. N for

[0124]

[0125] Among them, e N The error is represented by P1(1), which can be brought close to 0 using the LMS algorithm. N P2(1) N These represent the expected values ​​of comparator 1 and comparator 2 for the Nth bit over a given period of time, where the comparison result is 1.

[0126] When the above formula is greater than 0, comparator 1 is negatively compensated and comparator 2 is positively compensated; when the above formula is less than 0, comparator 1 is positively compensated and comparator 2 is negatively compensated. Therefore, the update formula for the offset voltage is:

[0127]

[0128] Where φ is the adjustment step size for the comparator offset voltage.

[0129] To demonstrate the correlation between calibration direction and comparator relative misalignment, this embodiment uses a 12-bit ADC as an example for verification, as follows:

[0130] According to the formula:

[0131]

[0132] When the comparator initially enabled is comparator 1, the probability of the 12th comparison determining a value of 1 is:

[0133]

[0134] At this point, comparator 2 participates in the 12th comparison. According to the formula:

[0135]

[0136] When the comparator used for the first time is comparator 2, the probability of the 12th comparison being a 1 is:

[0137]

[0138] At this point, comparator 1 participates in the 12th comparison. In both of the above cases, the calculated probability range is...

[0139]

[0140]

[0141] In practical applications, x1 and x2 are less than or equal to Solving the above equation yields:

[0142]

[0143] Generalizing to N digits, the relationship between x1 and x2 is:

[0144]

[0145] Where N is the number of bits in the ADC, i=1 when N is even and i=0 when N is odd; floor(·) is the floor function, and the calculated value is the largest integer not greater than (·). When x1 and x2 satisfy the relationship in the above formula, the probability of the comparator's Nth comparison being judged as 1 is correlated only by adjusting the magnitude of the comparator offset voltage.

[0146] 6) Repeat the above steps until the maximum number of iterations is reached.

[0147] Example 3:

[0148] To verify the effectiveness and results of the method of the present invention, the following experiments and results analysis were conducted in this embodiment:

[0149] The experimental computer was equipped with an Intel(R) Core i7-8750H CPU @ 2.5GHz and 16GB of RAM; the operating system was Windows 11, and the programming environment was MATLAB R2021b. To verify the performance improvement brought by the method of this invention, a comparison was made between fixed-step LMS and variable-step LMS based on linear scaling factors. The ADC model used in this invention is a 12-bit single-ended DC-SAR ADC with an input range of 0-4V.

[0150] By calculating the probability of the Nth bit being identified as 1 under two different turn-on sequences of the comparator, when there is no relative misalignment between the two comparators, the probability of the Nth bit being identified as 1 should be 0 in both cases. Therefore, the difference in the probability of the Nth bit being identified as 1 under the two conditions can be used as a scaling factor to adjust the step size of the offset voltage. The scaling factor is calculated using the following formula:

[0151]

[0152] Where u is the scaling factor, e N Indicates the error. The curve showing the change of the linear scaling factor u is as follows: Figure 7 As shown, the scaling factor u and the error e N The comparator offset voltage adjustment formula is linear and is as follows:

[0153]

[0154] Where φ is the compensation voltage for the comparator, V ref Here, |φ| represents the reference voltage of the ADC, and N represents the number of bits in the ADC. The adjustment of the compensation voltage depends on the currently calculated scaling factor u; the larger |φ| is, the larger the compensation voltage, and the smaller |φ| is, the smaller the compensation voltage.

[0155] In the variable step-size LMS algorithm used in this invention, the step size is adjusted using a nonlinear adjustment factor. The formula for the designed nonlinear adjustment factor is as follows:

[0156]

[0157] The function graphs of the nonlinear adjustment factor and the linear scaling factor are compared, for example... Figure 8 As shown, when |e(n)| is larger, the variable step size factor has a greater adjustment capability and accelerates the convergence speed. As |e(n)| decreases, the variable step size factor has a smaller adjustment capability and maintains stable adjustment.

[0158] The method of this invention was compared with fixed-step LMS and variable-step LMS based on linear scaling factor, respectively. The number of cycles was 100, and calibration was stopped when the number of cycles reached 100. Among them, the fixed-step LMS used a step size of 0.7mV for adjustment.

[0159] The offset voltage of comparator 1 is set to -8.87679mV, the offset voltage of comparator 2 is set to 58.7679mV, and the offset amount is 67.64469mV.

[0160] The comparative experimental results of the method of this invention, fixed step size LMS, and variable step size LMS based on linear scaling factor in Experiment 1 are as follows: Figure 9 As shown, (a) is the calibration result of fixed step size LMS, (b) is the calibration result of linear scaling factor variable step size LMS, and (c) is the calibration result of the algorithm of the present invention. It can be seen that the method of the present invention can eliminate the relative offset between comparators in 28 cycles; the linear scaling factor variable step size LMS algorithm can basically eliminate the relative offset voltage between the two comparators in 43 cycles, but the compensation voltage is unstable during the elimination process; the calibration tends to be stable in 46 cycles using the fixed step size LMS algorithm, but the relative offset voltage always exists after calibration because the offset voltage is compensated by a fixed step size.

[0161] In Experiment 2, the offset voltage of comparator 1 was set to 8.87679mV, and the offset voltage of comparator 2 was set to 5.87679mV, with an offset of 3mV, for comparison. The comparison results are as follows. Figure 10 As shown, (a) is the calibration result of fixed step size LMS, (b) is the calibration result of linear scaling factor variable step size LMS, and (c) is the calibration result of the algorithm of the present invention. It can be seen that, under the relative misalignment condition, the method of the present invention is basically consistent with other comparison methods in terms of convergence speed, and all converge at the end of the 4th cycle. However, the algorithm of the present invention is more stable in adjusting the relative misalignment voltage of the comparator than the fixed step size LMS algorithm and the linear scaling factor variable step size LMS algorithm.

[0162] In Experiment 3, the offset voltage of comparator 1 was set to -88.7679mV, and the offset voltage of comparator 2 was set to 58.7679mV, with a total offset of 147.5358mV. The comparison results are as follows: Figure 11 As shown, (a) is the calibration result of fixed step size LMS, (b) is the calibration result of linear scaling factor variable step size LMS, and (c) is the calibration result of the algorithm of the present invention. It can be seen that the algorithm of the present invention can eliminate the relative offset between comparators in 55 cycles; the linear scaling factor variable step size LMS algorithm can basically eliminate the relative offset voltage between the two comparators in 83 cycles; and the calibration tends to be stable in 95 cycles using the fixed step size LMS algorithm.

[0163] Based on the above experimental results, it can be seen that the method of the present invention does not introduce additional clock cycles during the offset calibration of the 12-bit DC-SAR ADC comparator and can eliminate the relative offset between the two comparators in a relatively small number of cycles.

Claims

1. A background calibration method for a dual-comparator SAR ADC based on a variable step-size LMS algorithm, characterized in that, Includes the following steps: S1: Design the input signal, acquire the output encoding; S2: Based on the enabling order of the control comparator and the least significant bit of the output code, the first statistical result is obtained; S3: Determine the calibration direction based on the first statistical result and calculate the statistical result error; S4: The comparator offset voltage is calibrated using the variable step size LMS algorithm based on the calculated calibration direction and statistical error. S5: After error compensation based on the calibrated voltage, the output code is collected again to update the first statistical result; S6: Repeat steps S1 to S5 until the maximum number of iterations is reached.

2. The background calibration method for a dual-comparator SAR ADC based on the variable step-size LMS algorithm according to claim 1, characterized in that, The input signal designed in step S1 is ； Among them, V in V represents the input signal. offset V represents the offset in the input signal. amplitude The input signal's original amplitude is represented by f, the input signal's frequency is represented by f, and the input signal's time vector is represented by t.

3. The background calibration method for a dual-comparator SAR ADC based on the variable step-size LMS algorithm according to claim 2, characterized in that, In step S2, a set of random signals is used to control the turn-on order of the comparators, ensuring that the two comparators have the same probability of turning on first during the measurement of a set of input signals. The value of the least significant bit of the output code is statistically analyzed and corresponds to the corresponding turn-on comparator to obtain the first statistical result.

4. The background calibration method for a dual-comparator SAR ADC based on the variable step-size LMS algorithm according to claim 3, characterized in that, In step S3, when the number of ADC bits is N, N is an even number. Assume that the offset voltages of comparator 1 and comparator 2 are x1 and x2 respectively, where x1>x2; p1(1) is obtained according to the first statistical result. N偶 and p2(1) N偶 The two parameters are the probability that the Nth bit comparison result is 1 when the comparator is 1 for the first time and the probability that the Nth bit comparison result is 1 when the comparator is 2 for the first time.

5. A background calibration method for a dual-comparator SAR ADC based on a variable step-size LMS algorithm according to claim 4, characterized in that, The method for determining the calibration direction in step S3 includes: According to p1(1) N偶 and p2(1) N偶 Perform the following calculations: ； Among them, let =C, then the above formula is updated to: ； Where C>0 when N≥2 and N is even, and since x1 is greater than x2, therefore Δp (1-2) >0; This indicates that the probability of comparator 2 participating in the Nth comparison and determining the least significant bit as 1 is greater than the probability of comparator 1 participating in the Nth comparison and determining the least significant bit as 1; similarly, when N is odd, it is... ； Where C>0 when N≥2 and N is odd, and since x1 is greater than x2, therefore Δp (1-2) <0; This indicates that the probability of comparator 1 participating in the Nth comparison and determining LSB as 1 is less than the probability of comparator 2 participating in the Nth comparison and determining LSB as 1. Based on the analysis of these two cases, it can be seen that when N is even, x1 and x2 are not the same. If x1 is greater than x2, then P1(1) N >P2(1) N If x1 is less than x2, then P1(1) N <P2(1) N When N is odd, if x1 is greater than x2, then P1(1) N <P2(1) N If x1 is less than x2, then P1(1) N >P2(1) N Thus, the calibration direction for mismatch is obtained.

6. The background calibration method for a dual-comparator SAR ADC based on the variable step-size LMS algorithm according to claim 5, characterized in that, In step S4, a nonlinear step size adjustment method is used to dynamically adjust the comparator offset voltage. The designed step size adjustment factor formula is as follows: ； Where a, b, and c are user-defined parameters; e(n) is the error.

7. The background calibration method for a dual-comparator SAR ADC based on the variable step-size LMS algorithm according to claim 6, characterized in that, The error compensation method in step S5 based on the calibrated voltage is as follows: By controlling the activation order of the two comparators with a random signal, and statistically analyzing the last comparison result of the comparators over a period of time, the error function e is calculated. N for ； Among them, e N The error is represented by P1(1), which is then approached to 0 using the LMS algorithm. N P2(1) N These are the expected values ​​of comparator 1 and comparator 2 respectively for the Nth bit over a certain period of time, where the result is 1; when e N When e is greater than 0, comparator 1 is negatively compensated, and comparator 2 is positively compensated; when e N When the value is less than 0, comparator 1 is positively compensated and comparator 2 is negatively compensated.

8. The background calibration method for a dual-comparator SAR ADC based on the variable step-size LMS algorithm according to claim 7, characterized in that, The update formula for the first statistical result in step S5 is: ； Where φ is the adjustment step size for the comparator offset voltage.

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