Vertical nanowire memory device

Abstract

The invention discloses a vertical nanowire memory device, and relates to the technical field of semiconductors. The device is characterized in that the device is provided with a vertical nanowire channel structure composed of GaN, AlN and AlGaN materials, and the structure is specifically characterized in that a first channel is formed by an AlN and GaN heterojunction, and a second channel is formed by an AlN and AlGaN heterojunction. The two channels are sequentially distributed in the radial direction of the nanowire from inside to outside, and the performance of the device is improved by utilizing the high polarization charge density of the first channel and the wide band gap and high voltage resistance characteristics of the second channel respectively. The source electrode and the drain electrode are oppositely arranged in the vertical direction and are formed by stacking a metal layer and an oxide layer. The gate structure adopts a full-surrounding gate and sequentially comprises a ferroelectric AlScN layer and a gate conducting layer from inside to outside, the ferroelectric AlScN layer is in contact with the nanowire channel, and the gate conducting layer is formed by alternately depositing a gate and nitride. Enhanced polarization control and low leakage current are provided.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of semiconductor technology, in particular to a vertical nanowire memory device. BACKGROUND

[0002] Non-volatile memory technologies such as ferroelectric random access memory (FeRAM) and ferroelectric field effect transistor (FeFET) have great prospects due to their low power consumption, durability and cycle speed.

[0003] Perovskite ferroelectrics and the hafnium oxide system established in 2009 have been extensively studied for this purpose. However, the compatibility of perovskite oxides with complementary metal oxide semiconductor (CMOS) technology is limited, as its harsh high-temperature deposition process poses a major challenge to device integration.

[0004] Although significant improvements have been made based on hafnium-based technology, its limited remanent polarization and significant wake-up and fatigue behavior still limit their widespread applicability. Most existing FeFETs have limited thermal stability, with reliable operation typically below 150°C, making them unsuitable for high-temperature environments such as avionics, space exploration and energy harvesting.

[0005] However, aluminum scandium nitride (Al1−xScxN) has emerged as a promising candidate for ferroelectric applications. Fichtner et al. discovered in 2019 that Al1−xScxN is ferroelectric, with a remnant polarization exceeding 100 μC / cm2, and a coercive field decreasing with increasing Sc content. Wolff et al. further confirmed its ferroelectric properties using STEM imaging, demonstrating a clear atomic-scale polarization reversal between Al (metallic) and N polarity.

[0006] These findings have triggered a wave of research aimed at optimizing material performance, including alloying with scandium, thin film thickness, and reducing leakage current.

[0007] By using AlGaN and GaN high electron mobility transistors (HEMTs) to develop the potential of GaN, the transistor has extremely low on-resistance due to the spontaneous existence of two-dimensional electron gas (2DEG).

[0008] Ultra-wide bandgap (UWBG) semiconductors such as diamond, cubic BN, Ga2O3 and AlN have recently received widespread attention for their potential in high-voltage, high-frequency electronics and deep ultraviolet optoelectronics, thanks to their wider bandgaps compared to traditional wide bandgap (WBG) materials such as GaN and SiC.

[0009] AlGaN stands out due to its tunable bandgap, depending on the aluminum composition. This unique property, combined with its ability to support 2DEG and higher critical electric field, makes AlGaN a special channel material. It provides significant advantages for power electronics devices by offering key breakdown enhancement features that gallium nitride channel HEMTs cannot achieve, resulting in superior performance in the next generation of devices. SUMMARY

[0010] The present application aims to provide a vertical nanowire memory device to solve the problems raised in the prior art.

[0011] To achieve the above-mentioned purpose, the present application provides the following technical solution: a vertical nanowire memory device; The device includes a nanowire channel structure, a source, a drain, and a gate structure. The source and drain are arranged opposite to each other in the vertical direction, with a vertical nanowire channel in between. In the working process, the source and drain act as current access channels. The source and drain are formed by stacking metal layers and oxide layers on top of each other. The metal layer provides low resistance contact, and the oxide layer acts as an insulating and barrier layer. In the working process, this stacked structure optimizes carrier injection and extraction, reduces leakage current, and improves the read-write efficiency and data retention capability of the memory.

[0012] The nanowire channel is a double heterojunction composed of GaN, AlN, and AlGaN materials. In the working process, the vertical nanowire channel serves as a carrier transport path, and the double heterojunction design enhances carrier and mobility. The nanowire channel structure specifically includes a first channel composed of AlN and GaN heterostructures, which utilizes the high two-dimensional electron gas density of the AlN and GaN heterojunction for high-speed carrier transport, and a second channel composed of AlN and AlGaN heterostructures, which utilizes the wide bandgap characteristics of the AlN and AlGaN heterojunction to improve breakdown voltage and stability.

[0013] The first channel and the second channel are distributed from the inside to the outside in the radial direction of the nanowire, specifically: GaN, AlN, and AlGaN. This radial layered structure provides high electron mobility in the inner layer GaN, isolation as a barrier in the middle AlN layer, and high field bearing in the outer AlGaN layer, ensuring the reliability and efficiency of the device under high voltage operation.

[0014] The AlN and GaN heterojunction provides high polarization-induced charge density, the AlN and AlGaN heterojunction bears high critical electric field by virtue of the wide band gap characteristic of AlGaN, in the working process, the high polarization charge density reduces the on-resistance and improves the switching speed; the wide band gap characteristic enables the device to work at high voltage without breakdown, and adapts to high-power storage.

[0015] The gate structure surrounds the nanowire channel structure and is located between the source and the drain, in the working process, the gate structure controls the conduction state of the channel through an electric field to realize the switching operation of the memory.

[0016] The gate structure is a full-surrounding gate structure, the full-surrounding gate structure enables the gate electric field to uniformly control the entire channel, and sequentially comprises a ferroelectric AlScN layer and a gate conductive layer from inside to outside, the ferroelectric AlScN layer serves as a storage medium and realizes data storage through polarization reversal; in the working process, the gate voltage changes the ferroelectric polarization state, thereby modulating the channel conductivity and completing data writing and erasing.

[0017] The ferroelectric AlScN layer is in contact with the nanowire channel structure, and the gate conductive layer is in contact with the ferroelectric AlScN layer, in the working process, the gate voltage directly acts on the ferroelectric layer to quickly induce polarization change, thereby realizing low-power and high-speed data operation.

[0018] The gate conductive layer is formed by alternately depositing a gate and a nitride, and the alternately deposited structure enhances the conductivity and thermal stability of the gate, in the working process, the gate layer provides uniform electric field distribution, and the nitride layer serves as a diffusion barrier to ensure the durability of the device under long-term operation.

[0019] Compared with the prior art, the present application has the following beneficial effects: 1. Computing performance: the core of the present application lies in that the ferroelectric AlScN material is used as the gate dielectric. The material has switchable polarization characteristics and can realize non-volatile data storage. Meanwhile, it is compatible with the GaN platform and has a thermal stability of up to 1100 DEG C, providing a high-performance and high-reliability alternative solution for ferroelectric perovskite (PZT) and hafnium-zirconium oxide (HZO), the combination of such ferroelectric characteristics and vertical transistors is suitable for dense multiply-accumulate (MAC) operations in memory computing. The ferroelectric polarization state can be controlled by the gate voltage, and the computing operation can be directly completed in the storage unit, reducing the data transfer between the processor and the memory, and improving the computing energy efficiency and speed. 2. Dual-channel electron transport: This invention employs a dual heterojunction channel structure of AlN and GaN, and AlN and AlGaN. The AlN and GaN heterojunction generates a high-density two-dimensional electron gas (2DEG), providing extremely high polarization-induced charge density and electron mobility, ensuring that the device has low on-resistance and high switching speed, laying the foundation for high-speed operation. The AlN and AlGaN heterojunction utilizes the wide bandgap characteristics of AlGaN, enabling the device to withstand higher critical electric fields and drain voltages, enhancing the device's voltage withstand capability and power handling capability. The two channels are integrated radially from the inside out, working together to achieve an optimized combination of performance, while taking into account the advantages of high speed and high voltage operation. Attached Figure Description

[0020] Fig. 1 This is a cross-sectional view of a transistor used in a vertical nanowire memory device according to the present invention; Fig. 2 This is a schematic diagram of the vertical drain-source channel of the present invention applied to a vertical nanowire memory device; Fig. 3 This is a schematic diagram illustrating the alternating deposition of a gate layer and a nitride layer in a vertical nanowire memory device according to the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Example: Figs. 1-3 As shown, the present invention provides a technical solution, a vertical nanowire memory device; the device is a dual-channel ferroelectric transistor, and its core working principle is: by applying a voltage pulse to the gate (1005), the polarization direction of the ferroelectric material AlScN (1004) is changed, thereby permanently modulating the conduction state of two two-dimensional electron gas (2DEG) channels (formed by AlN and GaN, AlN and AlGaN heterostructures); The device includes a nanowire channel structure, a source, a drain, and a gate structure; The source and drain are arranged opposite each other in the vertical direction, with a vertical nanowire channel constructed in the middle. In the working process, the source and drain serve as current inlet and outlet channels. The source and drain are formed by stacking metal and oxide layers, with the metal layers providing low-resistance contacts and the oxide layers serving as insulation and barrier layers. During operation, this stacked structure optimizes carrier injection and extraction, reduces leakage current, and improves memory read / write efficiency and data retention.

[0023] The nanowire channel is a double heterojunction composed of GaN, AlN and AlGaN materials. In the working process, the vertical nanowire channel serves as the carrier transport path, and the double heterojunction design enhances the carrier and mobility. The nanowire channel structure is specifically as follows: a first channel is formed by AlN and GaN heterostructures, which utilizes the AlN and GaN heterojunction to generate a high two-dimensional electron gas density for high-speed carrier transport; and a second channel is formed by AlN and AlGaN heterostructures, which utilizes the wide bandgap characteristics of the AlN and AlGaN heterojunctions to improve breakdown voltage and stability.

[0024] The first and second channels are distributed radially from the inside to the outside of the nanowire, specifically GaN, AlN, and AlGaN. In operation, this radially layered structure provides high electron mobility for the inner GaN layer, acts as a potential barrier for isolation, and withstands a high electric field for the outer AlGaN layer, ensuring the reliability and efficiency of the device under high voltage operation.

[0025] The AlN and GaN heterojunction provides a high polarization-induced charge density. The AlN and AlGaN heterojunction utilize the wide bandgap characteristics of AlGaN to withstand a high critical electric field. During operation, the high polarization charge density reduces the on-resistance and improves the switching speed. The wide bandgap characteristics enable the device to operate at high voltages without breakdown, making it suitable for high-power storage.

[0026] The gate structure surrounds the nanowire channel structure and is located between the source and drain. During operation, the gate structure controls the channel conductivity state through an electric field to realize the switching operation of the memory.

[0027] The gate structure is a fully encircling gate structure, which enables the gate electric field to uniformly control the entire channel. From the inside out, it includes: a ferroelectric AlScN layer and a gate conductive layer. The ferroelectric AlScN layer serves as a storage medium, and data storage is achieved through polarization reversal. During operation, a gate voltage is applied to change the ferroelectric polarization state, thereby modulating the channel conductivity and completing the writing and erasing of data.

[0028] The ferroelectric AlScN layer is in contact with the nanowire channel structure, and the gate conductive layer is in contact with the ferroelectric AlScN layer. During the operation, the gate voltage is directly applied to the ferroelectric layer, which quickly induces polarization changes, thereby achieving low-power and high-speed data operation.

[0029] The gate conductive layer is formed by alternating deposition of the gate and nitride layers. This alternating deposition structure enhances the conductivity and thermal stability of the gate. During operation, the gate layer provides a uniform electric field distribution, while the nitride layer acts as a diffusion barrier, ensuring device durability under long-term operation.

[0030] Example: Definition of storage state (write operation): Writing to state "1": A +5V positive voltage pulse is applied to the gate (1005), which causes the polarization direction of the ferroelectric AlScN layer (1004) to be downward. This polarization state induces a high concentration of two-dimensional electron gas (2DEG) in the underlying GaN and AlGaN channels, reducing the channel resistance. This low-resistance state is defined as storing logic "1". Writing to state "0": A negative voltage pulse of -5V is applied to the gate (1005), which causes the polarization direction of the ferroelectric AlScN layer (1004) to be upward. This polarization state depletes the two-dimensional electron gas in the channel, significantly increasing the channel resistance. This high-resistance state is defined as storing logic "0". Because AlScN has excellent ferroelectric remanent polarization and thermal stability, the two polarization states mentioned above can be maintained for a long time after power failure, thus achieving non-volatile storage.

[0031] Reading from storage state (read operation): A read voltage of +0.2V is applied between the source and drain. This voltage is much lower than the coercive voltage of ferroelectric reversal to ensure that the read operation does not change the stored state. The channel current flowing from the drain to the source is measured. If the stored state is "1" (low resistance state), a large channel current will be measured. If the stored state is "0" (high resistance state), a very small channel current (almost off) will be measured. This current signal is compared with a reference value by a sense amplifier to determine whether the stored logic value is "1" or "0".

[0032] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A vertical nanowire memory device, characterized in that: The device includes a nanowire channel structure, a source, a drain, and a gate structure; The source and drain are arranged opposite each other in the vertical direction, with a vertical nanowire channel constructed in the middle. The nanowire channel is a double heterojunction composed of GaN, AlN and AlGaN materials; The gate structure surrounds the nanowire channel structure and is located between the source and drain.

2. The vertical nanowire memory device according to claim 1, characterized in that: The nanowire channel structure is specifically composed of a first channel formed by AlN and GaN heterostructures, and a second channel formed by AlN and AlGaN heterostructures.

3. A vertical nanowire memory device according to claim 2, characterized in that: The first channel and the second channel are distributed from the inside to the outside in the radial direction of the nanowire, specifically GaN, AlN, and AlGaN from the inside to the outside.

4. A vertical nanowire memory device according to claim 2, characterized in that: The AlN and GaN heterojunction provides a high polarization-induced charge density, and the AlN and AlGaN heterojunction utilizes the wide bandgap characteristics of AlGaN to withstand a high critical electric field.

5. A vertical nanowire memory device according to claim 1, characterized in that: The gate structure is a fully encircling gate structure, which includes, from the inside out: a ferroelectric AlScN layer and a gate conductive layer.

6. A vertical nanowire memory device according to claim 5, characterized in that: The ferroelectric AlScN layer is in direct contact with the nanowire channel structure, and the gate conductive layer is in direct contact with the ferroelectric AlScN layer.

7. A vertical nanowire memory device according to claim 5, characterized in that: The gate conductive layer is formed by alternating deposition of gate and nitride.

8. A vertical nanowire memory device according to claim 1, characterized in that: The source and drain are formed by stacking metal layers and oxide layers one on top of the other.

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