Thermal shutter for electrostatic discharge clamp and method of manufacturing the same

Abstract

The invention relates to a thermal turn-off for an electrostatic discharge clamp and a method of manufacturing the same. An apparatus (200) is disclosed herein. The apparatus comprises: a first power rail (202); a second power rail (204); an electrical protection component (214) conductively coupled between the first power rail and the second power rail, the electrical protection component configured to monitor a voltage characteristic of the power rails to detect an electrical event; and a thermal protection component (216) conductively coupled between the power rails and to the electrical protection component, the thermal protection component including a temperature sensitive transistor (Q1) configured to vary an electrical characteristic of the electrical protection component in response to a temperature change of the device.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically to electrostatic overstress circuits in semiconductor devices. Background Technology

[0002] Integrated circuits (ICs) can be severely damaged by electrostatic overstress (EOS) events, which include electrostatic discharge (ESD) events. Sources of EOS events include discharges from the human body, metallic objects, and electrical events. During an EOS event, voltage and / or current spikes may occur in the IC. The rise time of these current and / or voltage spikes may be shorter than expected, often causing higher-than-normal stress on the IC. Rapid charging or discharging of voltage and / or current from the IC often stresses it. This stress often degrades and / or damages the IC's components. ESD circuitry is coupled to the IC to mitigate the stress and damage caused by voltage and / or current spikes in the IC. Summary of the Invention

[0003] This document discloses an apparatus comprising a first power rail; a second power rail; an electrical protection component conductively coupled between the first and second power rails, the electrical protection component being configured to monitor the voltage characteristics of the power rails to detect electrical events; and a thermal protection component conductively coupled between the power rails and conductively coupled to the electrical protection component, the thermal protection component including a temperature-sensitive transistor configured to change the electrical characteristics of the electrical protection component in response to temperature changes in the apparatus.

[0004] This document also discloses a device comprising a power rail, a reference rail, an ESD protection component, and a thermal protection component, the ESD protection component being conductively coupled to the power rail and the reference rail. The thermal protection component includes a first transistor and a bipolar junction transistor (BJT), the first transistor including a first gate terminal conductively coupled to the reference rail. The BJT includes: a base conductively coupled to the first transistor; a collector configured to provide a control signal to a control terminal of the ESD protection component; and an emitter conductively coupled to the reference rail, wherein the BJT is configured to change the control signal in response to temperature changes in the device.

[0005] This document also discloses a method for manufacturing an integrated circuit, comprising: forming an ESD protection circuit on or above a substrate, the ESD protection circuit being configured to operate in response to a transient electrical event on a power rail; and forming a thermal protection circuit on or above the substrate, the thermal protection circuit being connected to a control terminal of the ESD protection circuit, wherein the thermal protection circuit includes a temperature-sensitive component configured to modulate a control voltage at the control terminal in response to a temperature change of the integrated circuit.

[0006] Unless otherwise expressly indicated herein, the foregoing features and elements can be combined in any combination without exclusivity. The operation of these features and elements, and the disclosed examples, will become more apparent from the following description and accompanying drawings. Attached Figure Description

[0007] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale. While the drawings illustrate various examples employing the principles described herein, they do not limit the scope of the claims.

[0008] Figure 1 Functional diagrams of circuits based on various examples are shown.

[0009] Figure 2 It shows according to Figure 1 Functional diagrams and schematic diagrams of circuits for various examples associated with them.

[0010] Figure 3 It shows according to Figure 1 Functional diagrams and schematic diagrams of circuits for various examples associated with them.

[0011] Figure 4A and 4B It shows according to Figure 2 The diagram illustrates the function of the circuit and the circuit and voltage characteristics of various examples associated with it.

[0012] Figure 5A and 5B It shows according to Figure 3 The diagram illustrates the function of the circuit and the circuit and voltage characteristics of various examples associated with it.

[0013] Figure 6 It shows according to Figure 2 and 3 The diagram shows the schematic diagram and the flowchart of the method for forming an integrated circuit in various related examples.

[0014] Figure 7 It shows Figure 2 A schematic diagram and timing diagrams of various components of various instances associated with it.

[0015] Figure 8 It shows Figure 3 A schematic diagram and timing diagrams of various components of various instances associated with it. Detailed Implementation

[0016] The following detailed description is presented for illustrative and not restrictive purposes. Benefits, advantages, and / or solutions to problems may be described with reference to various examples. Detailed descriptions utilize various examples and refer to the accompanying drawings illustrating the various examples described herein. The diagrams, descriptions, and examples are described in sufficient detail to practice this disclosure. It should be understood that the connecting lines shown in the various diagrams are intended to represent exemplary functional relationships and / or physical couplings between various elements, but other relationships and / or couplings are possible while remaining within the scope of this disclosure. It should be further understood that the various diagrams may not be drawn to scale in order to simplify and clarify the detailed description herein. Furthermore, it should be understood that the descriptions and examples contained herein may permit the practice of other examples using logical, chemical, and / or mechanical variations without departing from the spirit and scope of this disclosure. For example, the steps described in the method and process description may be performed in a different order, additional process steps may be added, and / or process steps may be removed, while remaining within the scope of this disclosure.

[0017] Any reference to a singular item and / or instance may include multiple items and / or instances, and any reference to more than one item and / or instance may include a singular item and / or instance. Similarly, unless otherwise stated, a reference to “a / an” or “described” may include one or more of the referenced items. Any reference to the words and / or phrases of connection, coupling, fixing, attachment, or similar terms may include partial, complete, temporary, removable, permanent, or other connection options. Any reference to the phrase of contact may include minimal contact or reduced contact. All scopes used herein may include the upper and lower limits of the scopes disclosed herein, including ratio limits. The stated values ​​may include at least the variations expected within the field of practice of this disclosure and will be understood and accepted as values ​​included within 10% of the stated values. Similarly, the use of “approximately,” “about,” “substantially,” or other similar terms indicates a quantity that is close to the stated value and still achieves the stated or desired result and / or performs the stated or desired function, and may refer to a quantity within 10% of the stated value.

[0018] The detailed description of the accompanying drawings and symbols includes reference numerals that may be repeated across multiple instances. The repetition of reference numerals is intended for simplicity and clarity of description and is not intended to establish or define a relationship between the different instances described herein. The examples and descriptions provided herein are intended to be exemplary and are not intended to limit the scope of the claims. For example, the use of terms such as “above” and “over” may indicate that a first feature is formed in direct contact with a second feature, or may indicate a relationship where there is no direct contact between the first and second features, such as the formation of an additional feature between the first and second features.

[0019] Spatial relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used herein for ease of discussion and are not intended to limit the orientation of various components, systems, devices, apparatuses, or other features. Therefore, it should be understood and appreciated that the use of spatial relative terms for different orientation practices remains within the scope of this disclosure.

[0020] Rate-triggered ESD clamps or circuits can inadvertently turn on during rapid supply rail ramp-up (e.g., an ESD event), leading to EOS (Electronic Optical Array) failure. Some such ESD clamps incorporate high-voltage transistors, such as extended-drain (DE) nMOS (DENMOS) transistors. The EOS immunity of an ESD clamp can be improved by designing the high-voltage transistors to have a high safe operating area (SOA) tolerance within the operating voltage. That is, high-voltage transistors may be too large for the intended purpose of providing high SOA tolerance in applications. However, some high-voltage transistors have a reduced SOA at high temperatures (e.g., above approximately 150°C).

[0021] This document discloses systems and methods for protecting ESD clamps from fault voltages when operating at high temperatures. In various instances, the described systems and methods provide circuit-based solutions for protecting ESD clamps. In various instances, a thermal shutdown component is included as part of the ESD clamp. In various instances, the thermal shutdown component modifies the electrical characteristics (e.g., gate voltage) of the ESD clamp in response to an increase in the temperature of the ESD clamp. In various instances, the thermal shutdown component improves the fault voltage of the ESD clamp by reducing the gate drive of the high-voltage transistor in response to operation at high temperatures.

[0022] In various instances, thermal shutdown components can be used to reduce leakage current through ESD clamps, which may be caused by operation at high temperatures (e.g., about 175°C to about 225°C). In various instances, by incorporating thermal shutdown components, high-power transistors can be smaller than otherwise possible. That is, when thermal shutdown components are present, high-power transistors can have a smaller SOA and are therefore physically smaller.

[0023] In various instances, the thermal shutdown component includes a pull-down circuit conductively coupled to the gate terminal of a high-voltage transistor. In various instances, the pull-down circuit includes a bipolar transistor, such as an NPN bipolar junction transistor (BJT). In various instances, the pull-down circuit is configured to weakly pull down the gate voltage of the high-voltage transistor at room temperature (“RT”, e.g., about 27°C), but to more strongly turn on at high temperatures (e.g., about 175°C to about 225°C). In various instances, such operation tends to reduce the effective gate bias on the high-voltage transistor at high temperatures, thus increasing the fault voltage of the high-power transistor.

[0024] Throughout this disclosure, various concepts will be referenced, such as voltage, temperature, time frame, and physical size. It should be understood that these design parameters, operating ranges, and applications associated with each of the mentioned concepts are intended to be illustrative and not limiting. Among the various instances, references may be made to normal temperature, room temperature, and high temperature. These references are intended for descriptive purposes, as the temperature ranges constituting high or normal may be specific to design choices or intended applications. The descriptions and examples contained in this disclosure may be adapted to the specific integrated circuit being designed while remaining within the scope of this disclosure.

[0025] Now for reference Figure 1 Functional diagrams of circuit 100 are shown according to various embodiments of this disclosure. Circuit 100 includes a first pad 102, a second pad 104, an ESD protection circuit 106, a load 108, a first power rail 110, and a second power rail 112. In various embodiments, the first power rail 110 may be configured to provide a positive voltage, a negative voltage, or ground. In various embodiments, the second power rail 112 may be configured to provide a positive voltage, a negative voltage, or ground. For ease of discussion and simplicity, the first power rail 110 will be referred to as having a higher voltage, sometimes referred to as V. dd And the second power rail 112 will be referred to as having a lower voltage, sometimes referred to as V. ss In various instances, load 108 may be a circuit or other component powered by the potential difference between the first power rail 110 and the second power rail 112. ESD protection circuit 106 provides ESD or EOS protection for load 108. As shown, ESD protection circuit 106 is conductively coupled to the first power rail 110, the second power rail 112, and load 108.

[0026] ESD protection circuit 106 further includes protection circuit 114 and thermal protection circuit 116. Protection circuit 114 and similar protection circuits are sometimes referred to herein as an actFET cell, but are not limited thereto. Additional aspects of the actFET cell are described in U.S. Patent No. 8,804,290, which is incorporated herein by reference in its entirety.

[0027] Both the actFET cell 114 and the thermal protection circuit 116 are electrically coupled to a first power rail 110 and a second power rail 112. The actFET cell 114 is configured to protect the load 108 from EOS events (including ESD events). The thermal protection circuit 116 is configured to protect the actFET cell 114 and more broadly the ESD protection circuit 106 from the adverse effects of temperature increases in the ESD protection circuit 106. The thermal protection circuit 116 is electrically coupled to the actFET cell 114 via a control line 118. In various embodiments, the thermal protection circuit 116 may send a signal to the actFET cell 114 in response to the temperature of the ESD protection circuit 106 (including the thermal protection circuit 116 and the actFET cell 114) exceeding a predetermined threshold temperature.

[0028] During operation, initially through the first gasket 102 and the second gasket 104 (e.g., the first gasket 102 is in V...) dd (And the second pad 104 is grounded) applies power ("energizing") to the circuit 100. In this type of operation, the expected voltage and / or current increases at a known rate. Under normal conditions, the ESD protection circuit 106 does not affect the voltage and / or current between the first power rail 110 and the second power rail 112, and the load 108 subsequently operates as expected.

[0029] During rapid transient events such as ESD events, abnormal power-on events, and / or power supply noise, the voltage and / or current on the first power rail 110 can increase or spike at a rate much higher than normal over a short period of time. During such rapid transient events, the ESD protection circuit 106 can be activated and configured to shunt current from the first power rail 110 to the second power rail 112 to rapidly reduce the magnitude of the voltage spike, thus minimizing wear and / or damage to the load 108. However, when operating at elevated temperatures, as may occur in industrial or automotive settings, the SOA of the high-voltage transistor in the actFET cell 114 can decrease. Therefore, increased temperatures can lead to wear and / or damage to components of the ESD protection circuit 106 containing the actFET cell 114. Thermal protection circuit 116 can be configured to respond to this temperature rise and adjust the operation of actFET cell 114 via control line 118 to reduce and / or minimize the effects of the increased temperature and avoid damage to ESD protection circuit 106 containing actFET cell 114. Specifically, thermal protection circuit 116 is configured to reduce the turn-on sensitivity of actFET cell 114 at high temperatures, thereby partially disabling ESD protection circuit 106 at high temperatures. For simplicity, the function of ESD protection circuit 106 will be described below with respect to ESD events, but it should be understood that other fast transient events are within the scope of this disclosure.

[0030] Now for reference Figure 2 Based on various embodiments of this disclosure, a schematic diagram of circuit 200 is shown. Circuit 200 includes components similar to those described above. Figure 1 The circuit 100 described herein contains similar components, including a first pad 202, a second pad 204, an ESD protection circuit 206, a load 208, a first power rail 210, a second power rail 212, an actFET cell 214, a thermal protection circuit 216, and a control line 218, which may not be described again below. In various instances, circuit 200 may be particularly effective in mitigating problems associated with rapid voltage change EOS events at elevated operating temperatures. Additional details regarding the operation of the actFET cell 214 and the thermal protection circuit 216 will be described below, according to various examples. It should be understood that the configuration of the actFET cell 214 and the thermal protection circuit 216 may differ from those shown and described below, while remaining within the scope of this disclosure.

[0031] The actFET cell 214 includes a first transistor M1, a second transistor M2, a first resistor R1, and a second resistor R2 interconnected as shown. The first transistor M1 includes a first gate terminal 220, a first drain terminal 222, a first body terminal 223, and a first source terminal 224. In various embodiments, the first transistor M1 may be a metal-oxide-semiconductor field-effect transistor (MOSFET), a power MOSFET, an insulated-gate bipolar transistor (IGBT), a laterally diffused MOSFET (LDMOS), a complementary MOSFET (CMOS), a drain-extended MOSFET (DEMOS), or another type of transistor. That is, the first transistor M1 may be designed to handle large currents, such as those associated with ESD events. In various embodiments, the first transistor M1 may be a high-voltage transistor. In various embodiments, the SOA of the first transistor M1 may decrease with increasing temperature due to the inherent physical effects of temperature on the transistor's constituent materials. Typically, the physical size of the first transistor M1 is SOA-dependent, allowing transistors with lower SOA to be larger to provide a desired predetermined fault voltage, while transistors with higher SOA can be smaller for the same fault voltage. Therefore, in various instances, the SOA and physical dimensions can be selected based on the intended application. The SOA of a semiconductor device (e.g., the first transistor M1) defines the voltage and current conditions under which the semiconductor device can operate without damage. In some high-voltage transistors (e.g., IGBTs), the SOA tends to decrease significantly at temperatures above RT (e.g., above about 27°C).

[0032] In various embodiments, the second transistor M2 includes a second gate terminal 226, a second drain terminal 228, a second body terminal 229, and a second source terminal 230. In various embodiments, the second transistor M2 may be a field-effect transistor (FET), a MOSFET, or another type of transistor. In various embodiments, the second transistor M2 may be designed to handle a lower current than the first transistor M1. In various embodiments, the second transistor M2 may be a high-voltage transistor having a maximum voltage lower than the first transistor M1. Furthermore, the second transistor M2 forms a source follower circuit with the first transistor M1. This allows the first transistor M1 to be biased at a higher voltage for a longer period of time than would otherwise be possible. Therefore, and in various embodiments, the second transistor M2 may be physically smaller than the first transistor M1.

[0033] Thermal protection circuit 216 includes a third transistor M3, a bipolar junction transistor (BJT) Q1, a third resistor R3, a fourth resistor R4, and a fifth resistor R5 interconnected as shown. The third transistor M3 includes a third gate terminal 232, a third drain terminal 234, a third body terminal 235, and a third source terminal 236. In various embodiments, the second transistor M2 and the third transistor M3 may be nominally identical examples of the same components, such as FETs, MOSFETs, or other transistors. In various embodiments, the third transistor M3 may be the same size as the second transistor M2 or a different size (e.g., smaller or larger). The relatively smaller size of the third transistor M3 compared to transistor M1 helps to reduce the area of ​​thermal protection circuit 216. BJT Q1 includes a base 238, a collector 240, and an emitter 242. Figure 2 As shown, the first transistor M1, the second transistor M2, and the third transistor M3 are n-type MOSFET (NMOS) transistors. In various instances, depending on the intended application, the first transistor M1, the second transistor M2, and / or the third transistor M3 may be p-type MOSFET (PMOS) transistors.

[0034] like Figure 2As shown, and relative to the actFET cell 214, the second gate terminal 226 is electrically coupled to the second resistor R2 and the collector 240 via control line 218. The second drain terminal 228 is electrically coupled to the first power rail 210. The second body terminal 229 is electrically coupled to the first body terminal 223, the first source terminal 224, and the second power rail 212. The second source terminal 230 is electrically coupled to the first gate terminal 220 and the first resistor R1. The first gate terminal 220 is electrically coupled to the second source terminal 230 and the first resistor R1. The first drain terminal 222 is electrically coupled to the first power rail 210. The first body terminal 223 is electrically coupled to the second body terminal 229, the first source terminal 224, and the second power rail 212. The first source terminal 224 is electrically coupled to the first body terminal 223 and the second power rail 212. The first end of the first resistor R1 is conductively coupled to the first gate terminal 220 and the second source terminal 230, and the second end of the first resistor R1 is conductively coupled to the first power rail 210. The first end of the second resistor R2 is conductively coupled to the second gate terminal 226 and the collector 240, and the second end of the second resistor R2 is conductively coupled to the first power rail 210. Although this is one embodiment of the actFET cell 214, it should be understood that other rate-triggered circuit embodiments have been considered and are within the scope of this disclosure. In various other instances, the first body terminal 223 and / or the second body terminal 229 may be conductively coupled to the first power rail 210, the second power rail 212, and / or other power rails and / or ground rail, as well as other electrical components.

[0035] like Figure 2As shown, and relative to the thermal protection circuit 216, the third gate terminal 232 is conductively coupled to the third resistor R3. The third drain terminal 234 is conductively coupled to the fourth resistor R4. The third body terminal 235 is conductively coupled to the third source terminal 236, the base 238, and the fifth resistor R5. The third source terminal 236 is conductively coupled to the third body terminal 235, the base 238, and the fifth resistor R5. The base 238 is conductively coupled to the third body terminal 235, the third source terminal 236, and the fifth resistor R5. The collector 240 is conductively coupled to the second gate terminal 226 and the second resistor R2 via the control line 218. The emitter 242 is conductively coupled to the second power rail 212. The first end of the third resistor R3 is conductively coupled to the third gate terminal 232, and the second end of the third resistor R3 is conductively coupled to the second power rail 212. The first end of the fourth resistor R4 is conductively coupled to the third drain terminal 234, and the second end of the fourth resistor R4 is conductively coupled to the first power rail 210. The first end of the fifth resistor R5 is conductively coupled to the third body terminal 235, the third source terminal 236, and the base 238, and the second end of the fifth resistor R5 is conductively coupled to the second power rail 212. While this is one embodiment of the thermal protection circuit 216, it should be understood that other configurations are possible while remaining within the scope of this disclosure. In various other instances, the third body terminal 235 may be conductively coupled to the first power rail 210 and the second power rail 212, and / or other power rails and / or the ground rail, as well as other electrical components. In various other instances, the base 238 of Q1 may be conductively coupled to other components and / or may be part of a different circuit layout while remaining within the scope of this disclosure.

[0036] continue Figure 2 As previously mentioned, the actFET unit 214 provides ESD protection for the ESD protection circuit 206, and the thermal protection circuit 216 provides thermal protection for the ESD protection circuit 206. As previously stated, in various instances, the second transistor M2 affects the bias voltage of the first transistor M1. As will be described in more detail below, during an ESD event, the second transistor M2 first turns on, causing a voltage drop across the first resistor R1, thereby turning on the first transistor M1.

[0037] There is a capacitance C between the second gate terminal 226 and the second drain terminal 228. gd1 Resistors R2 and C gd1 V at the second gate terminal 226 dd The high-pass filter. During an ESD event, the voltage at the second gate terminal 226 of the first transistor M1 is determined by the second resistor R2 and the capacitor C. gd1Upward pumping. When the voltage is pumped upward, the second transistor M2 provides current through the first resistor R1 to turn on the first transistor M1. Once turned on, the first transistor M1 provides a path for shunting the current associated with the ESD event from the first power rail 210 to the second power rail 212. That is, during the sharp voltage rise on the first power rail 210 caused by the ESD event, the capacitor C... gd1 Charging causes the voltage at the second gate terminal 226 to exceed the threshold voltage of the second transistor M2, thereby turning on the second transistor M2. In response to the second transistor M2 turning on, current flows through the second transistor M2 from the first power rail 210 to the second power rail 212, and more specifically, from the second drain terminal 228 to the second source terminal 230. During such ESD events, the voltage at the first gate terminal 220 is generated by the first resistor R1, which causes the first transistor M1 to turn on when the voltage at the first gate terminal 220 exceeds the threshold voltage of the first transistor M1. Once the first transistor M1 is turned on, the actFET cell 214 then shunts current through the first transistor M1 from the first power rail 210 to the second power rail 212, and more specifically, from the first drain terminal 222 to the first source terminal 224. As previously described, the ESD protection circuit will have an operating environment with ambient temperature depending on the implementation. The operating temperature of the ESD protection circuit 206 will reflect the ambient temperature and will also be affected by power dissipation during an ESD event, as the first transistor M1 shunts current between the first power rail 210 and the second power rail 212. This power dissipation can increase the operating temperature of the actFET cell 214, and particularly the operating temperature of the first transistor M1.

[0038] To prevent damage to the ESD protection circuit 206 due to a decrease in the fault voltage of the first transistor M1 caused by increased temperature, the thermal protection circuit 216 provides thermal shutdown capability to the ESD protection circuit 206. That is, as the operating temperature of the IC increases, the thermal protection circuit 216 provides a signal to the actFET cell 214 via control line 218 to reduce the operating voltage of the actFET cell 214 by decreasing the voltage at the second gate terminal 226. This often protects the actFET cell 214 and, more specifically, the first transistor M1 from early-stage faults.

[0039] The operation of thermal protection circuit 216 is similar to that of actFET cell 214. During normal operation (e.g., when the IC is performing within design constraints), thermal protection circuit 216 is not active. During an ESD event, thermal protection circuit 216 is activated in a manner similar to that described above for actFET cell 214. That is, the third transistor M3 has a gate-drain capacitance C that charges in response to an ESD event between the third drain terminal 234 and the third gate terminal 232. gd2 The third transistor M3 is charged by the voltage on the first power rail 210, similar to the second transistor M2, thereby providing current through the fifth resistor R5 to turn on BJT Q1. At normal operating temperature (e.g., room temperature), BJT Q1 transfers a small amount of current or charge from the second resistor R2. The current transferred by BJT Q1 is small enough that the second transistor M2 continues to operate as described above. As the operating temperature increases, the gain current gain, or β, increases. Therefore, as the IC temperature rises (including the temperature of the thermal protection circuit 216), BJT Q1 has a higher pull-down strength and transfers more current from the second resistor R2, thereby effectively reducing the resistance between the second gate terminal 226 and the second power rail 212 (e.g., ground). This lower resistance, in turn, reduces the maximum gate voltage at the second gate terminal 226. By reducing the maximum gate voltage at the second gate terminal 226, the current through the first resistor R1 also decreases, thereby reducing the peak gate voltage at the first gate terminal 220 during voltage transient events. Therefore, it is anticipated that the maximum gate voltage at the first gate terminal 220 will be reduced during an ESD event to reduce or prevent damage to the actFET cell 214.

[0040] In various instances, the fourth resistor R4 of the thermal protection circuit 216 limits the gate voltage of the third transistor M3 (e.g., the third gate terminal 232) across ESD events at different slew rates and prevents overdrive and / or temperature insensitivity of the BJT Q1. That is, the fourth resistor R4 tends to reduce the sensitivity of the third transistor M3 to the voltage and / or current slew rate of the thermal protection circuit 216 to maintain the sensitivity of the third transistor M3 to temperature increases.

[0041] In various instances, the actFET cell 214 and the thermal protection circuit 216 may be a single integrated circuit. In some other instances, the actFET cell 214 and the thermal protection circuit 216 may be separate integrated circuits. In yet another instance, the separate circuits may be thermally coupled such that the operation of the thermal protection circuit 216 reflects the thermal environment of the actFET cell 214.

[0042] As described above, the thermal protection circuit 216 enables the actFET cell 214 to operate over a wider temperature range than otherwise described. As the operating temperature of the ESD protection circuit 206 increases, the shunt current provided by BJT Q1 is treated as a control signal provided by control line 218 that alters or modulates the operating characteristics of the actFET cell 214. Specifically, in various instances, the altered operating characteristics may include a lower peak gate voltage at the first gate terminal 220, a lower peak gate voltage at the second gate terminal 226, and / or a reduced peak current flowing through the second resistor R2. Therefore, as the operating temperature of the ESD protection circuit 206 rises, the thermal protection circuit 216 draws a higher current from the actFET cell 214, thereby reducing the gate voltages of the first transistor M1 and the second transistor M2 to reduce the sensitivity of the first transistor M1 to higher temperatures.

[0043] Now for reference Figure 3 A schematic diagram of circuit 300 is shown based on various alternative embodiments of this disclosure. Circuit 300 includes components similar to those described above. Figure 2 The circuit 200 described above contains components similar to those in the circuit 200 described above, including a first pad 302, a second pad 304, an ESD protection circuit 306, a load 308, a first power rail 310, a second power rail 312, an actFET cell 314, a thermal protection circuit 316, and a control line 318, which may not be described again below. The actFET cell 314 contains components similar to those described above. Figure 2 Similar to the actFET cell 214 described above, this assembly includes a first transistor M11, a second transistor M22, a first resistor R11, a second resistor R22, a first gate terminal 320, a first drain terminal 322, a first body terminal 323, a first source terminal 324, a second gate terminal 326, a second drain terminal 328, a second body terminal 329, and a second source terminal 330, which may not be described again below. While this is one embodiment of the actFET cell 214, it should be understood that other rate-triggered circuit embodiments have been considered and are within the scope of this disclosure. In various other instances, the first body terminal 323 and / or the second body terminal 329 may be electrically coupled to a first power rail 310, a second power rail 312, and / or other power rails and / or a ground rail, as well as other electrical components. The thermal protection circuit 316 includes components similar to those described above. Figure 2Similar components to the thermal protection circuit 216 described herein include a third transistor M33, a BJTQ11, a third resistor R33, a fourth resistor R44, a fifth resistor R55, a third gate terminal 332, a third drain terminal 334, a third body terminal 335, a third source terminal 336, a base 338, a collector 340, and an emitter 342, which may not be described again below. While this is one embodiment of the thermal protection circuit 216, it should be understood that other configurations are possible while maintaining the scope of this disclosure. In various other instances, the third body terminal 335 may be electrically coupled to a first power rail 310, a second power rail 312, and / or other power rails and / or a ground rail, as well as other electrical components.

[0044] In various examples, circuit 300 differs from circuit 200 in that collector 340 is electrically coupled to first gate terminal 320, second source terminal 330, and first resistor R11 via control line 318. This connection via control line 318 allows ESD protection circuit 306 to have lower leakage current than ESD protection circuit 206.

[0045] During normal or static operation (e.g., without an ESD event), the leakage current of low-power transistors, such as the second transistor M22, tends to be greater at higher temperatures. The leakage current through the second transistor M22 in response to an increase in IC temperature can result in a larger voltage at the first gate terminal 320, thus causing the first transistor M11 to be partially turned on. Turning on the first transistor M11 in this manner allows current to flow through it from the first power rail 310 to the second power rail 312. This current path can be from the V-shaped line coupled to the first pad 302 and the second pad 304. dd A source (such as a battery) consumes energy, thereby potentially shortening the operating life of a device in which circuit 300 is part and / or potentially heating circuit 300, as well as producing other effects.

[0046] Thermal protection circuit 316 reduces leakage current through actFET cell 314, which would otherwise occur at elevated operating temperatures. At this point, control line 318, and more specifically conductively coupled to collector 340 of first gate terminal 320, reduces the gate bias of first transistor M11, thereby reducing drain-to-source conductivity of first transistor M11. As the temperature of circuit 300 increases (whether during an ESD event or even during normal operation), leakage current through first transistor M11, second transistor M22, and third transistor M33 may increase. The increase in leakage current through second transistor M22 generates a positive voltage across first resistor R11 at first gate terminal 320 of first transistor M11. As the voltage at first gate terminal 320 increases, first transistor M11 turns on, allowing more current to leak through it. Similarly, the increase in leakage current through third transistor M33 generates a positive voltage across fifth resistor R55 at base 338 of BJT Q11. As the voltage at base 338 increases at higher temperatures, BJT Q11 allows a larger current to flow between collector 340 and emitter 342, thus shunting a portion of the leakage current from the second transistor M22 to ground (via control line 318) and reducing the voltage at the first gate terminal 320. The reduced voltage at the first gate terminal 320 decreases and / or eliminates the leakage current through the first transistor M11.

[0047] Therefore, the thermal protection circuit 316 enables the reduction or prevention of leakage current through the actFET cell 314 at elevated operating temperatures. The absorb current via the control line 318 is considered a control signal provided by the thermal protection circuit 316 to alter or modulate the operating characteristics of the actFET cell 314. Specifically, in various embodiments, the control line 318, and more specifically conductively coupled to the collector 340 of the first gate terminal 320, allows the thermal protection circuit 316 to reduce the gate bias of the first transistor M11 to reduce leakage current through the actFET cell 314 as temperature increases.

[0048] Now for reference Figure 4A and 4B The graph shows the operating voltage (V) of an ESD protection circuit in which the high-voltage transistor is implemented as an IGBT at two different temperatures. dd -V ss ) and the characteristics of current (VI). Figure 4AA first graph 400 is shown illustrating the VI characteristics of a baseline ESD protection circuit, exemplified, for example, by an actFET cell 214 without thermal protection circuitry 216. The first graph 400 has a voltage axis 402 (e.g., x-axis), a current axis 404 (e.g., y-axis), a first line 406, and a second line 408. The first line 406 and the second line 408 end at different maximum temperatures representing different fault voltages of the corresponding transistors. The first line 406 contains multiple points illustrating the VI characteristics of the baseline ESD protection circuit operating at approximately RT (e.g., approximately 27°C). The second line 408 contains multiple points illustrating the VI characteristics of the baseline ESD protection circuit operating at temperatures consistent with operation in industrial or automotive environments (e.g., approximately 200°C, non-limitingly referred to as "hot"). The first line 406 (RT) represents a first fault voltage, and the second line 408 (hot) represents a second, lower fault voltage. The difference between the first fault voltage and the second fault voltage represents, for example, a baseline example of the reduction in the fault voltage of the actFET of actFET cell 214 when it is not protected by thermal protection circuitry.

[0049] Figure 4B A second graph 420 is shown, illustrating the VI characteristics of a thermally protected ESD protection circuit exemplified by an ESD protection circuit 206 comprising both an actFET cell 214 and a thermal protection circuit 216. The second graph 420 has a voltage axis 422 (e.g., x-axis), a current axis 424 (e.g., y-axis), a first line 426, and a second line 428. Voltage axes 402 and 422 have the same scale. The first line 426 contains multiple points representing the VI characteristics of the thermally protected ESD protection circuit operating at RT, while the second line 428 contains multiple points representing the VI characteristics of the thermally protected ESD protection circuit operating at approximately 200°C. As previously mentioned, the first line 426 and the second line 428 terminate at different maximum temperatures representing different fault voltages of the corresponding thermally protected ESD protection circuits. The first line 426 shows a first fault voltage similar to (slightly larger than) the first fault voltage of the first line 406 (the unprotected actFET cell at RT). However, the second line 428 exhibits a second, lower fault voltage, which is relatively close to the fault voltage of the first line 426 and significantly greater than the fault voltage of the second line 408 (the unheated actFET). The larger fault voltage of the second line 428 represents a significant improvement in the expected reliability of the ESD protection circuit, which includes the thermal protection circuit illustrated by thermal protection circuit 216.

[0050] Now for reference Figure 5A and 5B The graph shows the VI characteristics of a circuit containing, for example, an actFET exemplified by actFET cell 314, as the analog leakage current varies with the operating voltage. Figure 5AA first graph 500 is shown, having a voltage axis 502 (e.g., x-axis), a leakage current axis 504 (e.g., y-axis), a first line 506, and a second line 508. The first graph 500 shows the leakage current as a function of the actFET's operating voltage when operating at RT. The first line 506 shows the VI characteristics of the actFET in an ESD protection circuit without thermal shutdown. The second line 508 shows the VI characteristics of an ESD protection circuit that includes the actFET and a thermal protection circuit exemplified by thermal protection circuit 316, interconnected with the actFET via a control line, for example, a control line 318 in ESD protection circuit 306. As shown by lines 506 and 508, the leakage current of the ESD protection circuit including the thermal protection circuit increases only slightly with increasing operating voltage at RT.

[0051] Figure 5B This is a second graph 520 with a voltage axis 522 (e.g., x-axis), a leakage current axis 524 (e.g., y-axis), a first line 526, and a second line 528. The voltage axis 522 has the same scaling as the voltage axis 502, and the leakage current axis 524 has the same scaling as the leakage current axis 504. The second graph 520 shows the leakage current characteristics of ESD protection circuits operating at 200°C with and without thermal protection circuitry (first line 526) and with thermal protection circuitry (second line 528). The leakage currents of both circuits are greater than those shown in the first graph 500, except near the top of the voltage range shown. However, the second line 528 shows that the leakage current of the ESD protection circuit with thermal protection circuitry is up to 20% smaller than the leakage current of the unprotected actFET shown by the first line 526. Therefore, in implementations where leakage current is a concern (e.g., low-power or battery-powered devices), thermal protection circuitry can provide a significant increase in operating life.

[0052] Now for reference Figure 6 According to various embodiments of this disclosure, a flowchart of a method 600 for forming an ESD circuit including protection circuitry and thermal shutdown circuitry is shown. In various embodiments, method 600 may be used to form ESD protection circuitry 206 and / or ESD protection circuitry 306. At step 602, an ESD protection circuit is formed on a semiconductor substrate. The ESD protection circuit is configured to shunt current from a first power rail to a second power rail in the event of an ESD event. At step 604, a thermal protection circuit is formed on the substrate. The thermal protection circuit is electrically coupled to the ESD protection circuit, and the thermal protection circuit includes a temperature-sensitive component configured to change the electrical characteristics of the ESD protection circuit in response to temperature changes.

[0053] Now for reference Figure 7Based on various examples of this disclosure, a timing diagram 700 for an ESD protection circuit is shown. Timing diagram 700 is relative to the above... Figure 2 The illustration of the operation of the described ESD protection circuit 206 is for illustrative and descriptive purposes only. That is, the timing diagram 700 is simplified for clarity. Therefore, it should be understood that the timing diagram 700 may not fully represent the subject electrical signals, as they may occur in actual installations. Instead, the timing diagram 700 shows the relative timing of different events occurring in the ESD protection circuit 206 in response to an ESD event.

[0054] The timing diagram 700 has a time axis 702 (e.g., the x-axis) and a y-axis 704 that qualitatively reflects the magnitude of key device parameters such as voltage, current, or temperature. At time t0, the ESD protection circuit has a relatively constant initial operating temperature and reflects the operating conditions of the device to which the ESD protection circuit is a part. For example, in automotive or industrial implementations, the initial operating temperature may be 200°C or higher.

[0055] At time t1, as part of a transient event such as an ESD event, the power supply voltage (e.g., the first power rail 210) increases to a first voltage. As previously described, both the gate voltage of the second transistor M2 and the gate voltage of the third transistor M3 are charged by the power supply voltage transient, thereby turning on the second transistor M2 and the third transistor M3. The current from the second transistor M2 generates a gate voltage at the first transistor M1, thereby turning on the first transistor M1 to shunt current between the power rails of the ESD protection circuit. Additionally, the current from the third transistor M3 supplies power to the control terminal (e.g., the base) of the BJT Q1, thereby turning on the BJT Q1.

[0056] At time t2, the circuit temperature may begin to increase. Any increase above the initial operating temperature will depend on the length and magnitude of the ESD event, and therefore on the power dissipated by transistor M1. At time t3, in response to the increased temperature, BJT Q1 draws more current. At time t4, the increased current drawn by BJT Q1 causes a voltage drop at the second transistor M2, which in turn causes a voltage drop at the first transistor M1, as previously discussed. The voltage drop at the first transistor M1 protects it from damage caused by high voltage at higher temperatures (e.g., greater than about 175°C), for example by ensuring that the first transistor M1 remains within its SOA. At time t4, the temperature reaches a steady state, and the current drawn by BJT Q1 remains stable. At time t6, the transient event ends with the supply voltage returning to its original state. The first transistor M1, the second transistor M2, the third transistor M3, and BJT Q1 each turn off in response to the supply voltage drop.

[0057] Now for reference Figure 8 Based on various examples of this disclosure, a timing diagram 800 for an ESD circuit is shown. Timing diagram 800 is as described above relative to... Figure 3 The illustration of the operation of the described ESD protection circuit 306 is for illustrative and descriptive purposes only, similar to the one above. Figure 7 Timing diagram 700 is described in the diagram. Timing diagram 800 illustrates a similar concept to timing diagram 700, incorporating the voltage, current, and temperature of ESD circuitry (e.g., ESD protection circuitry 106 and ESD protection circuitry 306) that vary over time. Timing diagram 800 includes components similar to those in timing diagram 700, including a time axis 802 (e.g., x-axis) and a y-axis 804, the value of which may vary depending on the component. At time t0, the ESD protection circuitry has a relatively constant initial operating temperature and reflects the operating conditions of the device to which the ESD protection circuitry is a component.

[0058] At time t1, as part of a transient event such as a power-on event, the power supply voltage (e.g., the first power rail 310) increases to a first voltage. The first transistor M11, the second transistor M22, and the third transistor M33 behave similarly to those described above in response to the transient event. At time t2, the first transistor M11, the second transistor M22, and the third transistor M33 each turn off in response to a stable power-on state. At time t3, the circuit temperature begins to increase. Due to current leakage through the second transistor M22, the increased temperature causes an increase in the voltage at the gate of the first transistor M11. Additionally, as described above, the current through BJT Q11 increases in response to the increased temperature. At time t4, the gate voltage of the first transistor M11 begins to decrease in response to the increased current through BJT Q11. At time t5, the temperature reaches a steady state, the current drawn by BJT Q1 remains stable, and the gate voltage of the first transistor M11 remains stable, thereby minimizing current leakage through the first transistor M11. At time t6, the power supply voltage returns to its original state (e.g., power off). The first transistor M11 turns off, BJT Q11 turns off, and the temperature begins to decrease.

[0059] Therefore, the circuits and methods disclosed herein provide an ESD circuit comprising a protection component and a thermal shutdown component for protecting the circuit from ESD events. In various embodiments disclosed herein, the thermal shutdown component protects the ESD circuit from damage caused by high temperatures by modifying the electrical characteristics (e.g., gate voltage) of the protection component in response to an increase in temperature. In various embodiments disclosed herein, the thermal shutdown component reduces current leakage caused by the higher operating temperature of the ESD circuit by modifying the electrical characteristics (e.g., gate voltage) of the protection component in response to an increase in temperature.

[0060] Finally, it should be understood that any of the concepts described above may be used alone or in combination with any or all of the other concepts described above. Although various examples have been disclosed and described, it should be understood, recognized, and / or anticipated that certain modifications will fall within the scope of this disclosure. Therefore, the description is not intended to be exhaustive or to limit the principles described or illustrated herein to any precise form. In light of the foregoing teachings, many modifications and variations are possible.

Claims

1. An apparatus comprising: First power rail; Second power rail; An electrical protection component, conductively coupled between a first power rail and a second power rail, is configured to monitor the voltage characteristics of the first power rail to detect electrical events. as well as A thermal protection component, electrically coupled between the power rails and electrically coupled to the electrical protection component, the thermal protection component including a temperature-sensitive transistor configured to change the electrical characteristics of the electrical protection component in response to temperature changes in the device.

2. The device of claim 1, wherein the temperature-sensitive component is a bipolar junction transistor (BJT).

3. The apparatus of claim 1, wherein the electrical characteristic is the fault voltage of the electrical protection component.

4. The apparatus of claim 1, wherein the electrical characteristic is the bias voltage at the control terminal of the electrical protection component.

5. The apparatus of claim 2, wherein the BJT comprises: The base, which is electrically coupled to the first power rail; The collector, which is conductively coupled to the control terminal of the electrical protection component; and The emitter is electrically coupled to the second power rail.

6. The apparatus of claim 5, wherein the thermal protection component further comprises: A first transistor has a first gate terminal, a first source / drain terminal, and a second source / drain terminal, the second source / drain terminal being electrically coupled to the base of the BJT; A first resistor, which is electrically coupled between the first power rail and the first source / drain terminal of the first transistor; A second resistor is conductively coupled between the first gate terminal of the first transistor and the second power rail. as well as A third resistor is conductively coupled between the node connecting the base of the BJT and the second source / drain terminal of the first transistor and the second power rail.

7. The apparatus of claim 6, wherein the first transistor is a laterally diffused metal-oxide-semiconductor LDMOS field-effect transistor.

8. The apparatus of claim 5, wherein the electrical protection component comprises: A first transistor having a first gate terminal; and The second transistor has a second gate terminal, wherein the collector of the BJT is electrically coupled to the first gate terminal of the first transistor to modulate the voltage at the second gate terminal in response to the temperature change of the device.

9. The apparatus of claim 5, wherein the electrical protection component comprises: A first transistor having a first gate terminal; and A second transistor having a second gate terminal, wherein the collector of the BJT is conductively coupled to the second gate terminal of the second transistor to change the bias voltage of the second transistor in response to the temperature change of the device.

10. The apparatus of claim 1, wherein the monitored voltage characteristic of the first power rail is a voltage transient between the first power rail and the second power rail, and The electrical protection component is configured to discharge current associated with the voltage transient to the second power rail when the characteristics of the voltage transient differ from a predetermined value by a predetermined difference.

11. An apparatus comprising: Power rail; Reference rail; An electrostatic discharge (ESD) protection component, which is conductively coupled to the power rail and the reference rail; as well as Thermal protection components, comprising: A first transistor, comprising a first gate terminal conductively coupled to the reference rail; and A bipolar junction transistor (BJT) includes: The base, which is electrically coupled to the first transistor; The collector, configured to provide control signals to the control terminals of the ESD protection component; and An emitter, which is conductively coupled to the reference rail, wherein the BJT is configured to change the control signal in response to temperature changes in the device.

12. The apparatus of claim 11, wherein the ESD protection component includes a second transistor having a second gate terminal, and wherein the collector is conductively coupled to the second gate terminal to change the fault voltage of the ESD protection component in response to the temperature change of the apparatus.

13. The apparatus of claim 12, wherein the ESD protection component further comprises a third transistor having a third gate terminal, wherein the third gate terminal is conductively coupled to the second transistor, and wherein the fault voltage of the ESD protection component is the fault voltage of the third transistor.

14. The apparatus of claim 11, wherein the ESD protection component includes a second transistor having a second gate terminal, wherein the collector is conductively coupled to the second gate terminal to change the bias voltage of the second transistor in response to an increase in temperature of the apparatus.

15. The apparatus of claim 14, wherein the ESD protection component further comprises a third transistor conductively coupled to the second gate terminal of the second transistor, wherein the third transistor is configured to activate the second transistor in response to an ESD event on the power rail or the reference rail, and wherein the third transistor has a different threshold voltage than the second transistor.

16. The apparatus of claim 11, wherein the thermal protection component further comprises: A first resistor, which is electrically coupled between the power rail and the first transistor; A second resistor, electrically coupled between the reference rail and the first transistor; and A third resistor is conductively coupled between the first transistor, the base of the BJT, and the reference rail.

17. A method for manufacturing an integrated circuit, comprising: An electrostatic discharge (ESD) protection circuit is formed on or above a substrate, the ESD protection circuit being configured to operate in response to transient electrical events on the power rail. as well as A thermal protection circuit is formed on or above the substrate, the thermal protection circuit being connected to a control terminal of the ESD protection circuit, wherein the thermal protection circuit includes a temperature-sensitive component configured to modulate a control voltage at the control terminal in response to temperature changes of the integrated circuit.

18. The method of claim 17, further comprising: The formation of the thermal protection circuit on the substrate comprises: A first transistor is formed, which is conductively coupled between the power rail and the ground rail; and A bipolar junction transistor (BJT) is formed, which is conductively coupled between the first transistor and the ESD protection circuit.

19. The method of claim 18, wherein the formation of the ESD protection circuit on the substrate comprises forming a second transistor conductively coupled between the power rail and the ground rail and conductively coupled to the collector of the BJT.

20. The method of claim 17, wherein the formation of the temperature-sensitive component comprises forming a transistor selected from the group consisting of bipolar junction transistors (BJTs) and insulated gate bipolar transistors (IGBTs).

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