Electrostatic discharge protection device

Abstract

An electrostatic discharge protection device includes: a substrate; a first doped region of the first conductivity type on the substrate; a second doped region of the first conductivity type on the substrate; an epitaxial layer of a second conductivity type between the first doped region and the second doped region; a first diffusion region of the first conductivity type on the first doped region; a second diffusion region of a second conductivity type on the epitaxial layer; a third diffusion region of the first conductivity type on the second doped region; and a fourth diffusion region of the second conductivity type on the first doped region and spaced apart from the first diffusion region. The first diffusion region and the fourth diffusion region are electrically bonded.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0102959, filed on August 2, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present disclosure relates generally to electrostatic discharge protection devices, and more particularly, to electrostatic discharge protection devices for protecting integrated circuit devices from reverse electrostatic discharge (ESD) voltages. BACKGROUND

[0003] Semiconductor devices and / or integrated circuits can be sensitive to electrostatic discharge (ESD) pulses and / or can be particularly susceptible to physical damage by high voltages and / or currents generated by ESD pulses. As the size of semiconductor devices gradually decreases, the voltage that a semiconductor device can withstand without damage can also decrease. Accordingly, input / output terminals of semiconductor devices can often be provided with electrostatic discharge protection devices to protect the semiconductor devices from damage that can be caused by pulses.

[0004] Electrostatic discharge protection devices can be provided to relatively quickly and / or relatively safely remove and / or reduce ESD pulses having relatively high voltages and / or relatively high currents when the ESD pulses are applied to semiconductor devices. SUMMARY

[0005] One or more example embodiments of the present disclosure provide electrostatic discharge protection devices that are capable of protecting integrated circuit devices and the like from reverse electrostatic discharge (ESD) voltages having a relatively small size by including a fourth diffusion region electrically connected to a first diffusion region when compared to related electrostatic discharge protection devices.

[0006] According to an aspect of the present disclosure, an electrostatic discharge protection device includes a substrate; a first doped region of a first conductivity type on the substrate; a second doped region of the first conductivity type on the substrate; an epitaxial layer of a second conductivity type between the first doped region and the second doped region; a first diffusion region of the first conductivity type on the first doped region; a second diffusion region of the second conductivity type on the epitaxial layer; a third diffusion region of the first conductivity type on the second doped region; and a fourth diffusion region of the second conductivity type on the first doped region and spaced apart from the first diffusion region. The first diffusion region and the fourth diffusion region are electrically bonded.

[0007] According to an aspect of the disclosure, an electrostatic discharge protection device includes a substrate; a first doped region of a first conductivity type on the substrate; a second doped region of the first conductivity type on the substrate and spaced apart from the first doped region; an epitaxial layer of a second conductivity type between the first doped region and the second doped region; a first well region of the second conductivity type on the first doped region; a second well region of the first conductivity type on the first doped region and spaced apart from the first well region; a third well region of the second conductivity type on the epitaxial layer; a first diffusion region of the first conductivity type on the second well region; a second diffusion region of the second conductivity type on the third well region; a third diffusion region of the first conductivity type on the second doped region; and a fourth diffusion region on the first well region. The first diffusion region and the fourth diffusion region are electrically joined. A first doping concentration of the third well region is greater than a second doping concentration of the epitaxial layer.

[0008] According to an aspect of the disclosure, an electrostatic discharge protection device includes a substrate; a first doped region of a first conductivity type on the substrate; a second doped region of the first conductivity type on the substrate and spaced apart from the first doped region; an epitaxial layer of a second conductivity type between the first doped region and the second doped region; a first well region of the second conductivity type on the first doped region; a second well region of the first conductivity type on the first doped region and spaced apart from the first well region; a first drift region of the second conductivity type on the epitaxial layer; a third well region of the second conductivity type on the first drift region and forming a junction interface with the second well region; a first diffusion region of the first conductivity type on the second well region; a second diffusion region of the second conductivity type on the third well region; a third diffusion region of the first conductivity type on the second doped region; and a fourth diffusion region of the second conductivity type on the first well region. The first diffusion region and the fourth diffusion region are electrically joined. A first doping concentration of the first drift region is less than a second doping concentration of the third well region. The first doping concentration of the first drift region is greater than a third doping concentration of the epitaxial layer. A fourth doping concentration of the first well region is greater than the third doping concentration of the epitaxial layer.

[0009] According to embodiments, an electrostatic discharge protection device can protect an integrated circuit device or the like from a reverse ESD voltage having a small size.

[0010] Additional aspects can be set forth in part in the description that follows, and in part can be apparent from the description, and / or can be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other aspects, features, and advantages of certain embodiments of the disclosure can be more apparent from the following description taken in conjunction with the accompanying drawings.

[0012] Figure 1is a schematic circuit diagram showing a semiconductor device including a general electrostatic discharge protection device according to an embodiment.

[0013] Figure 2 is a top plan view showing an electrostatic discharge protection device according to an embodiment.

[0014] Figure 3 is a cross-sectional view taken along line A-A' of Figure 2 is a cross-sectional view taken along line A-A' of

[0015] Figure 4 is an enlarged cross-sectional view of region R1 of Figure 3 is an enlarged cross-sectional view of region R1 of

[0016] Figure 5 is an equivalent circuit diagram of an electrostatic discharge protection device according to an embodiment.

[0017] Figure 6 is a graph showing a voltage-current curve of an electrostatic discharge protection device according to an embodiment.

[0018] Figures 7 to 13 is a cross-sectional view corresponding to line A-A' of Figure 2 is a cross-sectional view corresponding to line A-A' of

[0019] Figure 14 is a block diagram showing a system including an electrostatic discharge protection device according to an embodiment. DETAILED DESCRIPTION

[0020] The present disclosure is described below with reference to drawings, in which embodiments of the present disclosure are illustrated. As those skilled in the art will appreciate, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0021] The accompanying drawings and the description are to be regarded as illustrative in nature and are not restrictive, and throughout the specification identical reference numerals can designate identical elements.

[0022] For better understanding and ease of description, the size and thickness of each constituent element in the drawings can be arbitrarily shown, but the following embodiments are not limited thereto. In the drawings, the thickness of layers and regions can be exaggerated for clarity. In the drawings, the thickness of some layers and regions can be exaggerated for ease of description.

[0023] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. Also, when an element is referred to as being "on" or "over" a reference element, the element can be disposed on or under the reference element, and the element can not necessarily be referred to as being disposed "on" or "over" the reference element in a direction opposite to the gravitational direction.

[0024] In addition, the words "comprise," "comprising," "contain," "containing," "include," "including," and "includes," and variations thereof, can be understood to imply the inclusion of a stated element or process but not the exclusion of any other elements or process.

[0025] In addition, the phrase "on plan" can represent a view from a position above the object (e.g., from the top), and the phrase "in section" can represent a view of a section of the object that can be vertically cut from the side.

[0026] As used herein, when an element or layer is referred to as "covering," "overlying," or "surrounding" another element or layer, the element or layer can cover at least a portion of the other element or layer, where the portion can include a part of the other element or can include the entire dimension (e.g., length, width, depth) of the other element. Similarly, when an element or layer is referred to as "penetrating" another element or layer, the element or layer can penetrate at least a portion of the other element or layer, where the portion can include a part of the other element or can include the entire dimension (e.g., length, width, depth) of the other element.

[0027] Reference throughout this disclosure to "one embodiment," "an embodiment," "example embodiment," or similar language can indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the solution. Thus, the phrases "in one embodiment," "in an embodiment," "in an example embodiment," and similar language throughout this disclosure can (but not necessarily) all refer to the same embodiment. The embodiments described herein are example embodiments, and thus the disclosure is not limited thereto and can be implemented in various other forms.

[0028] Embodiments herein can be described and in the drawings as blocks that perform one or more functions described. These blocks, which can be referred to herein as units or modules, etc., or by names such as device, logic, circuit, controller, counter, comparator, generator, converter, etc., can be physically implemented by analog and / or digital circuits comprising one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc.

[0029] In the present disclosure, the singular is intended to include one or more items, and is used interchangeably with "one or more". The term "a" or similar language is used when only one item is intended. For example, the term "processor" can mean a single processor or multiple processors. When a processor is described as performing an operation and the processor is referred to as performing an additional operation, the multiple operations can be performed by the single processor, or any one or combination of the multiple processors.

[0030] Hereinafter, referring to Figure 1 An electrostatic discharge protection device according to an embodiment is described.

[0031] Figure 1 is a schematic circuit diagram illustrating a semiconductor device including a general electrostatic discharge (ESD) protection device according to an embodiment.

[0032] Referring to Figure 1 , an electrostatic discharge protection device (DSL) 100 can be disposed between an input / output (I / O) terminal 10 (or referred to as I / O 10) and a ground terminal (GND) 20 to which a ground voltage is applied. An integrated circuit device (or integrated circuit) 500 can be protected from an unwanted electrostatic discharge pulse by the electrostatic discharge protection device 100.

[0033] For example, the electrostatic discharge protection device 100 can protect the integrated circuit device 500 connected to the I / O terminal 10 and the ground terminal 20 from an electrostatic discharge pulse. For example, a voltage higher or lower than a potential of the ground terminal 20 can be applied to the I / O terminal 10, and a generated electrostatic pulse can be discharged by the electrostatic discharge protection device 100. The integrated circuit device 500 can include various devices including electrical elements. Referring to Figures 2 to 13 An electrostatic discharge protection device 100 employable herein is illustrated and described.

[0034] Hereinafter, referring to Figure 2 and Figure 3 An electrostatic discharge protection device according to an embodiment is described.

[0035] Figure 2 is a top plan view illustrating an electrostatic discharge protection device according to an embodiment. Figure 3 is a sectional view taken along line A-A' of Figure 2 according to an embodiment.

[0036] First, referring to Figure 2 and Figure 3According to an embodiment, an electrostatic discharge (ESD) protection device 100 can include a substrate 110, a first doped region 131 and a second doped region 132 disposed on the substrate 110, a first epitaxial layer 121 disposed between the first doped region 131 and the second doped region 132, a first diffusion region 181 disposed on the first doped region 131, a second diffusion region 182 disposed on the first epitaxial layer 121, a third diffusion region 183 disposed on the second doped region 132, and a fourth diffusion region 184 disposed on the first doped region 131 and electrically connected to the first diffusion region 181.

[0037] The substrate 110 can be, for example, a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon germanium (Si-Ge) substrate. In one embodiment, the substrate 110 can be a substrate of a first conductivity type. For example, the first conductivity type can be a p (or P) type. However, the disclosure is not limited thereto, and the substrate 110 can be a substrate of a second conductivity type different from the first conductivity type. For example, the second conductivity type can be an n (or N) type.

[0038] The electrostatic discharge protection device 100 according to an embodiment can further include embedded layers (e.g., a first embedded layer 111 and a second embedded layer 112) disposed on the substrate 110.

[0039] The first embedded layer 111 and the second embedded layer 112 can be disposed on an upper surface of the substrate 110. In one embodiment, the first embedded layer 111 and the second embedded layer 112 can include the first embedded layer 111 and the second embedded layer 112 having different conductivity types. The first embedded layer 111 and the second embedded layer 112 can extend in a second direction (Y direction), however, the disclosure is not limited thereto. The second embedded layer 112 can be disposed between the first embedded layer 111. The second embedded layer 112 can be disposed on one side of the first embedded layer 111, however, the disclosure is not limited thereto, and the second embedded layer 112 can be surrounded by the first embedded layer 111.

[0040] The first embedded layer 111 and the second embedded layer 112 can include silicon (Si). The first embedded layer 111 can have a first conductive region of high doping. For example, the first embedded layer 111 can be a p++ type, and can have a higher impurity concentration than other doped regions. The doping concentration of the first embedded layer 111 can be greater than the doping concentration of the substrate 110. The second embedded layer 112 can have a second conductive region of high doping. For example, the second embedded layer 112 can be an N++ type, and can have a higher impurity concentration than other doped regions. The doping concentration of the second embedded layer 112 can be greater than the doping concentration of the substrate 110.

[0041] The doped regions can be provided on the first embedded layer 111 and the second embedded layer 112. For example, the electrostatic discharge protection device 100 according to an embodiment can include a first doped region 131 and a second doped region 132 which can be provided on the second embedded layer 112.

[0042] The first doped region 131 and the second doped region 132 can be provided on the substrate 110. The first doped region 131 and the second doped region 132 can be provided on the upper surface of the second embedded layer 112 on the substrate 110. The first doped region 131 and the second doped region 132 can extend in the second direction (Y direction) and can be spaced apart from each other in the first direction (X direction). The first doped region 131 and the second doped region 132 can include substantially similar and / or identical materials. The first doped region 131 and the second doped region 132 can have the same conductivity type. For example, the first doped region 131 and the second doped region 132 can be doped with a first conductivity type impurity (or a first conductive impurity) to have a first conductivity type. For example, the first conductivity type can be a p-type. The doping concentration of the first doped region 131 and the second doped region 132 can be less than the doping concentration of the second embedded layer 112. In one embodiment, the first doped region 131 and the second doped region 132 can be high voltage p-well (HVPW) regions.

[0043] The electrostatic discharge protection device 100 according to an embodiment can further include a third doped region 133 provided on the first embedded layer 111.

[0044] The third doped region 133 can extend in the second direction (Y direction) and can be spaced apart from the first doped region 131 and the second doped region 132 in the first direction (X direction). The first doped region 131 and the second doped region 132 can be spaced apart from each other by a predetermined interval. The third doped region 133 can include substantially similar and / or identical materials to the first doped region 131 and the second doped region 132, and the third doped region 133 can have the same conductivity type as the first doped region 131 and the second doped region 132. For example, the third doped region 133 can be doped with a first conductivity type impurity to be a first conductivity type. In this case, the doping concentration of the third doped region 133 can be substantially similar and / or identical to the doping concentration of the first doped region 131 and the doping concentration of the second doped region 132, however, the disclosure is not limited thereto.

[0045] An epitaxial layer (e.g., the first epitaxial layer 121 and the second epitaxial layer 122) can be disposed on the substrate 110. The first and second epitaxial layers 121 and 122 can be disposed on an upper surface of the second embedded layer 112 on the substrate 110. For example, the first and second epitaxial layers 121 and 122 can include the first epitaxial layer 121 disposed between the first doped region 131 and the second doped region 132 on the second embedded layer 112. As used herein, the first epitaxial layer 121 can denote an epitaxial layer disposed between the first doped region 131 and the second doped region 132.

[0046] The first epitaxial layer 121 can be disposed between the first doped region 131 and the second doped region 132. The first epitaxial layer 121 can extend in the second direction (Y direction), however, the present disclosure is not limited thereto. The first epitaxial layer 121 can be in contact with the first doped region 131 and the second doped region 132. For example, a side surface of the first epitaxial layer 121 can form a junction interface with a side surface of the first doped region 131 and a side surface of the second doped region 132. The first epitaxial layer 121 can have a predetermined width. For example, the first epitaxial layer 121 can have a first width (W1) extending in the first direction (X direction). Figure 4 A magnitude of a trigger voltage of the electrostatic discharge protection device 100 can be determined according to the first width (W1) of the first epitaxial layer 121 in the first direction (X direction). Figure 4 A magnitude of a trigger voltage of the electrostatic discharge protection device 100 can be determined according to the first width (W1) of the first epitaxial layer 121 in the first direction (X direction). Figures 4 to 6 A description thereof is provided.

[0047] The first epitaxial layer 121 can be disposed in the same layer as the first doped region 131 and the second doped region 132. For example, a lower surface of the first epitaxial layer 121 can be disposed at substantially similar and / or the same height as a lower surface of the first doped region 131 and a lower surface of the second doped region 132. That is, a distance from the lower surface of the first epitaxial layer 121 to an upper surface of the substrate 110 can be substantially similar and / or the same as a distance from the lower surface of the first doped region 131 and the lower surface of the second doped region 132 to the upper surface of the substrate 110.

[0048] The first epitaxial layer 121 can include a material substantially similar to and / or the same as the substrate 110 and / or the second embedded layer 112. For example, the first epitaxial layer 121 can include silicon (Si), however, the present disclosure is not limited thereto. The first epitaxial layer 121 can be doped with a second-conductivity-type impurity (or second-conductivity impurity) to have a second conductivity type. The second conductivity type can be n-type. At this time, a doping concentration of the first epitaxial layer 121 can be less than a doping concentration of the second embedded layer 112. Accordingly, when a depletion region is formed between the first doped region 131 having the first conductivity type and the first epitaxial layer 121 having the second conductivity type by a reverse bias state, a punch-through phenomenon can occur in which a depletion region formation reaches the second doped region 132.

[0049] In one embodiment, the first and second epitaxial layers 121 and 122 can further include a second epitaxial layer 122 disposed between the first doped region 131 and the third doped region 133 and between the second doped region 132 and the third doped region 133. As used herein, the second epitaxial layer 122 can denote an epitaxial layer disposed on the outside of the first doped region 131 and the second doped region 132, respectively. The second epitaxial layer 122 can include a material substantially similar to and / or the same as the first epitaxial layer 121. The second epitaxial layer 122 can have the same conductivity type as the first epitaxial layer 121. For example, the second epitaxial layer 122 can be doped with a second-conductivity impurity to have a second conductivity type. The second conductivity type can be n-type. In this case, a doping concentration of the second epitaxial layer 122 can be less than a doping concentration of the second embedded layer 112.

[0050] In one embodiment, diffusion regions (e.g., a first diffusion region 181, a second diffusion region 182, a third diffusion region 183, a fourth diffusion region 184, a fifth diffusion region 185, a sixth diffusion region 186, a seventh diffusion region 187, and an eighth diffusion region 188) can be disposed on the substrate 110. The first diffusion region 181 to the eighth diffusion region 188 can be disposed on the first embedded layer 111 and the second embedded layer 112 on the substrate 110. The first diffusion region 181 to the eighth diffusion region 188 can be directly disposed on an upper surface of a well region (e.g., a first well region 171, a second well region 172, a third well region 173, a fourth well region 174, a fifth well region 175, and a sixth well region 176), however, the present disclosure is not limited thereto. In one embodiment, the first diffusion region 181 to the eighth diffusion region 188 can extend in a second direction (Y direction) and / or can be spaced apart from each other in a first direction (X direction). The first diffusion region 181 to the eighth diffusion region 188 can be separated from each other by a separation layer STI and can be electrically blocked from each other. The first diffusion region 181 to the eighth diffusion region 188 can be disposed as a contact region.

[0051] For example, the electrostatic discharge protection device 100 according to the embodiment can include first to fourth diffusion regions 181 to 184.

[0052] The first diffusion region 181 can be disposed on the first doped region 131. The first diffusion region 181 can extend in the second direction (Y direction). The first diffusion region 181 can be doped with a first conductive type impurity to have a first conductive type. The first conductive type can be a p-type. For example, the first diffusion region 181 can have a p+ type, and can have a higher impurity concentration than the third well region 173. The doping concentration of the first diffusion region 181 can be greater than the doping concentration of the first doped region 131. In one embodiment, the first diffusion region 181 can configure an emitter node of a first transistor (e.g., the first transistor Q1) and a base node of a third transistor (e.g., the third transistor Q3) of the electrostatic discharge protection device 100 according to the embodiment. Figure 4 Figure 4

[0053] The second diffusion region 182 can be disposed on the first epitaxial layer 121. The second diffusion region 182 can extend in the second direction (Y direction), and can be spaced apart from the first diffusion region 181 in the first direction (X direction). The second diffusion region 182 can be doped with a second conductive impurity to have a second conductive type. The second conductive type can be an n-type. For example, the second diffusion region 182 can have an n+ type, and can have a higher impurity concentration than the third well region 173. The doping concentration of the second diffusion region 182 can be greater than the doping concentration of the first epitaxial layer 121. In one embodiment, the second diffusion region 182 can configure a base node of a first transistor (e.g., the first transistor Q1), a base node of a second transistor (e.g., the second transistor Q2), and a collector node of a third transistor (e.g., the third transistor Q3) of the electrostatic discharge protection device 100 according to the embodiment. Figure 4 Figure 4 Figure 4

[0054] The third diffusion region 183 can be disposed on the second doped region 132. The third diffusion region 183 can extend in the second direction (Y direction), and can be spaced apart from the first diffusion region 181 and the second diffusion region 182 in the first direction (X direction). In one embodiment, the third diffusion region 183 can configure a collector node of a first transistor (e.g., the first transistor Q1) and a collector node of a second transistor (e.g., the second transistor Q2) of the electrostatic discharge protection device 100 according to the embodiment. Figure 4 Figure 4 In one embodiment, the third diffusion region 183 can be electrically connected to the second connection wiring 320 via the third via hole 333. The second connection wiring 320 can be connected to a second electrode (e.g., the second electrode 220).​​​​​​Figure 3 or Figure 5 the second electrode E2) in the second diode DE1, and the second electrode (e.g., Figure 3 or Figure 5 the second electrode E2) in the second diode DE1 can be a cathode electrode connected to a ground node.

[0055] The third diffusion region 183 can be doped with a first-conductivity-type impurity to have a first conductivity type. The first conductivity type can be a p-type. For example, the third diffusion region 183 can have a p+ type, and can have a higher impurity concentration than the fourth well region 174. The doping concentration of the third diffusion region 183 can be greater than the doping concentration of the second doped region 132.

[0056] The fourth diffusion region 184 can be disposed on the first doped region 131. The fourth diffusion region 184 can extend in the second direction (Y direction), and can be spaced apart from the first to third diffusion regions 181 to 183 in the first direction (X direction). In one embodiment, the fourth diffusion region 184 can be disposed on one side of the first diffusion region 181. That is, the first diffusion region 181 can be disposed between the fourth diffusion region 184 and the second diffusion region 182.

[0057] The fourth diffusion region 184 can be doped with a second-conductivity-type impurity to have a second conductivity type. The second conductivity type can be an n-type. For example, the fourth diffusion region 184 can have an n+ type, and can have a higher impurity concentration than the first well region 171. The doping concentration of the fourth diffusion region 184 can be greater than the doping concentration of the first epitaxial layer 121.

[0058] In one embodiment, the fourth diffusion region 184 can configure an electrode of the first diode (e.g., the first diode DE1) of the electrostatic discharge protection device 100 and an emitter node of the third transistor (e.g., the third transistor Q3). In one embodiment, the fourth diffusion region 184 and the first diffusion region 181 can be electrically connected (or electrically bonded). For example, the fourth diffusion region 184 and the first diffusion region 181 can be electrically connected to each other by the first connection wiring 310, the second via 334 connecting the fourth diffusion region 184 and the first connection wiring 310, and the first via 331 connecting the first diffusion region 181 and the first connection wiring 310. The first connection wiring 310, the first via 331, and the second via 334 can include a conductive material. For example, the first connection wiring 310 can be connected to the first electrode (e.g., the first electrode E1) of the first diode DE1, and the first electrode can be an anode electrode that can receive an electrostatic discharge voltage. Figure 4 Figure 4 In one embodiment, the fourth diffusion region 184 can configure an electrode of the first diode (e.g., the first diode DE1) of the electrostatic discharge protection device 100 and an emitter node of the third transistor (e.g., the third transistor Q3). In one embodiment, the fourth diffusion region 184 and the first diffusion region 181 can be electrically connected (or electrically bonded). For example, the fourth diffusion region 184 and the first diffusion region 181 can be electrically connected to each other by the first connection wiring 310, the second via 334 connecting the fourth diffusion region 184 and the first connection wiring 310, and the first via 331 connecting the first diffusion region 181 and the first connection wiring 310. The first connection wiring 310, the first via 331, and the second via 334 can include a conductive material. For example, the first connection wiring 310 can be connected to the first electrode (e.g., the first electrode E1) of the first diode DE1, and the first electrode can be an anode electrode that can receive an electrostatic discharge voltage. Figure 3 Figure 5 In one embodiment, the fourth diffusion region 184 can configure an electrode of the first diode (e.g., the first diode DE1) of the electrostatic discharge protection device 100 and an emitter node of the third transistor (e.g., the third transistor Q3). In one embodiment, the fourth diffusion region 184 and the first diffusion region 181 can be electrically connected (or electrically bonded). For example, the fourth diffusion region 184 and the first diffusion region 181 can be electrically connected to each other by the first connection wiring 310, the second via 334 connecting the fourth diffusion region 184 and the first connection wiring 310, and the first via 331 connecting the first diffusion region 181 and the first connection wiring 310. The first connection wiring 310, the first via 331, and the second via 334 can include a conductive material. For example, the first connection wiring 310 can be connected to the first electrode (e.g., the first electrode E1) of the first diode DE1, and the first electrode can be an anode electrode that can receive an electrostatic discharge voltage.

[0059] ​​In one embodiment, a third width W3 of the fourth diffusion region 184 in the first direction (X direction) can be greater than a fourth width W4 of the first diffusion region 181 in the first direction (X direction), however, the disclosure is not limited thereto. Within the above range, a contact resistance between the first connection wiring 310 and the fourth diffusion region 184 can be reduced. In another embodiment, the third width W3 of the fourth diffusion region 184 in the first direction (X direction) can be equal to the fourth width W4 of the first diffusion region 181 in the first direction (X direction).

[0060] The electrostatic discharge protection device 100 according to the embodiment can further include fifth to eighth diffusion regions 185 to 188.

[0061] The fifth diffusion region 185 and the seventh diffusion region 187 can be disposed on the second epitaxial layer 122. The fifth diffusion region 185 can be disposed on one side of the fourth diffusion region 184, and the seventh diffusion region 187 can be disposed on one side of the third diffusion region 183. That is, the fourth diffusion region 184 can be disposed between the fifth diffusion region 185 and the first diffusion region 181, and the third diffusion region 183 can be disposed between the second diffusion region 182 and the seventh diffusion region 187. The fifth diffusion region 185 and the seventh diffusion region 187 can be doped with a second conductive impurity to have a second conductivity type. The second conductivity type can be an n-type. For example, the fifth diffusion region 185 and the seventh diffusion region 187 can have an n+ type, and can have a higher impurity concentration than the fifth well region 175. A doping concentration of the fifth diffusion region 185 and a doping concentration of the seventh diffusion region 187 can be higher than a doping concentration of the second epitaxial layer 122.

[0062] The sixth diffusion region 186 and the eighth diffusion region 188 can be disposed on the third doped region 133. The sixth diffusion region 186 can be disposed on one side of the fifth diffusion region 185, and the eighth diffusion region 188 can be disposed on one side of the seventh diffusion region 187. That is, the fifth diffusion region 185 can be disposed between the sixth diffusion region 186 and the fourth diffusion region 184, and the seventh diffusion region 187 can be disposed between the third diffusion region 183 and the eighth diffusion region 188. The sixth diffusion region 186 and the eighth diffusion region 188 can be doped with a first conductivity type impurity to have a first conductivity type.

[0063] The first conductivity type can be a p-type. For example, the sixth diffusion region 186 and the eighth diffusion region 188 can have a p+ type, and can have a higher impurity concentration than the third doped region 133.

[0064] The electrostatic discharge protection device 100 according to the embodiment can further include a separation layer STI disposed between the first to eighth diffusion regions 181 to 188.

[0065] An isolation layer STI can be disposed between the first to eighth diffusion regions 181 to 188. For example, the isolation layer STI can be disposed between the fourth diffusion region 184 and the first diffusion region 181, between the first diffusion region 181 and the second diffusion region 182, and between the second diffusion region 182 and the third diffusion region 183. Additionally, the isolation layer STI can be disposed between the fourth diffusion region 184 and the fifth diffusion region 185, between the fifth diffusion region 185 and the sixth diffusion region 186, between the third diffusion region 183 and the seventh diffusion region 187, and between the seventh diffusion region 187 and the eighth diffusion region 188. In one embodiment, the isolation layer STI can surround each of the first to eighth diffusion regions 181 to 188. The first to eighth diffusion regions 181 to 188 can be separated from each other by the isolation layer STI. Each of the first to eighth diffusion regions 181 to 188 can be electrically isolated from each other by the isolation layer STI. The isolation layer STI can be, but is not limited to, a field oxide layer or a shallow trench isolation (STI). For example, the isolation layer STI can include, but is not limited to, silicon oxide (SiO).

[0066] The electrostatic discharge protection device 100 according to an embodiment can include the first to sixth well regions 171 to 176 disposed between the first and second epitaxial layers 121 and 122 and the first to eighth diffusion regions 181 to 188 or between the first to third doped regions 131 to 133 and the first to eighth diffusion regions 181 to 188.

[0067] For example, the electrostatic discharge protection device 100 according to an embodiment can include the first well region 171 disposed between the first doped region 131 and the fourth diffusion region 184, the second well region 172 disposed between the first doped region 131 and the first diffusion region 181, the third well region 173 disposed between the first epitaxial layer 121 and the second diffusion region 182, and the fourth well region 174 disposed between the second doped region 132 and the third diffusion region 183.

[0068] The first well region 171 can be disposed under the fourth diffusion region 184. For example, the first well region 171 can be disposed directly under a lower surface of the fourth diffusion region 184. The first well region 171 can be in contact with the lower surface of the fourth diffusion region 184, however, the disclosure is not limited thereto. The first well region 171 can be disposed in the first doped region 131. The first well region 171 can be surrounded by the first doped region 131. A lower surface and a side surface of the first well region 171 can be in contact with the first doped region 131. The lower surface of the first well region 171 can be disposed at a higher level than a lower surface of the first doped region 131. That is, the lower surface of the first well region 171 can be disposed farther from the upper surface of the substrate 110 than the lower surface of the first doped region 131. The first well region 171 can be stacked in the third direction (Z direction) with the fourth diffusion region 184 and the isolation layer STI disposed on both sides of the fourth diffusion region 184 in the first direction (X direction). In one embodiment, the third direction (Z direction) can be a thickness direction of the substrate 110. A width of the first well region 171 in the first direction (X direction) can be greater than a width of the fourth diffusion region 184 in the first direction (X direction), however, the disclosure is not limited thereto.

[0069] In one embodiment, the first well region 171 can have a different conductivity type from the first doped region 131. For example, the first well region 171 can be doped with second conductive impurities to have a second conductivity type, and the first doped region 131 can be doped with first conductive impurities to have a first conductivity type. For example, the first conductivity type can be p-type, and the second conductivity type can be n-type. Accordingly, a PN junction can be formed at a junction interface of the first well region 171 and the first doped region 131, and thus can be used as a first diode (e.g., a first diode DE1) of the electrostatic discharge protection device 100 according to an embodiment. Reference is made to Figure 4 and Figure 4 and Figure 5 for a description thereof. The doping concentration of the first well region 171 can be higher than the doping concentration of the first epitaxial layer 121. The doping concentration of the first well region 171 can be lower than the doping concentration of the fourth diffusion region 184.

[0070] The second well region 172 can be disposed under the first diffusion region 181. For example, the second well region 172 can be disposed directly under a lower surface of the first diffusion region 181. The second well region 172 can be in contact with the lower surface of the first diffusion region 181, however, the disclosure is not limited thereto. The second well region 172 can be disposed on the first doped region 131. At least a portion of the second well region 172 can be surrounded by the first doped region 131. Additionally, the second well region 172 can be disposed on the first drift region 141. That is, at least a portion of the second well region 172 can be disposed on the first doped region 131, and a remaining portion of the second well region 172 can be disposed on the first drift region 141. However, the disclosure is not limited thereto, and the second well region 172 can not be disposed on the first drift region 141, and can be surrounded by the first doped region 131. A lower surface of the second well region 172 can be in contact with the first doped region 131 and the first drift region 141. The lower surface of the second well region 172 can be disposed at a higher level than a lower surface of the first doped region 131. That is, the lower surface of the second well region 172 can be disposed farther from the upper surface of the substrate 110 than the lower surface of the first doped region 131. The lower surface of the second well region 172 can be disposed at substantially similar and / or the same level as the lower surface of the first well region 171, however, the disclosure is not limited thereto.

[0071] The second well region 172 can be stacked in the third direction (Z direction) with the first diffusion region 181 and the isolation layer STI disposed on both sides of the first diffusion region 181 in the first direction (X direction). A width of the second well region 172 in the first direction (X direction) can be greater than a width of the first diffusion region 181 in the first direction (X direction), however, the disclosure is not limited thereto.

[0072] In one embodiment, the second well region 172 can be spaced apart from the first well region 171. The first doped region 131 can be disposed between the second well region 172 and the first well region 171. That is, the second well region 172 and the first well region 171 can be stacked with the first doped region 131 in a horizontal direction (e.g., the first direction (X direction) and / or the second direction (Y direction)). Side surfaces of the second well region 172 and the first well region 171 can be in contact with the first doped region 131, however, the disclosure is not limited thereto.

[0073] In one embodiment, the second well region 172 may have a different conductivity type than the first well region 171. The second well region 172 may also have the same conductivity type as the first diffusion region 181. For example, the second well region 172 may be doped with a first conductive impurity to have a first conductivity type, and the first well region 171 may be doped with a second conductive impurity to have a second conductivity type. For example, the first conductivity type may be p-type, and the second conductivity type may be n-type. The doping concentration of the second well region 172 may be higher than the doping concentration of the first doped region 131 and the doping concentration of the second doped region 132. The doping concentration of the second well region 172 may be lower than the doping concentration of the first diffusion region 181.

[0074] The third well region 173 may be disposed below the second diffusion region 182. For example, the third well region 173 may be disposed directly below the lower surface of the second diffusion region 182. The third well region 173 may be in contact with the lower surface of the second diffusion region 182; however, this disclosure is not limited thereto. The third well region 173 may be disposed on the first epitaxial layer 121. For example, the third well region 173 may be disposed on the first drift region 141, which is disposed on the first epitaxial layer 121. The third well region 173 may be spaced apart from the first epitaxial layer 121 in the third direction (Z direction); however, this disclosure is not limited thereto. The third well region 173 may be superimposed on the second diffusion region 182 and the isolation layers STI disposed on both sides of the second diffusion region 182 in the first direction (X direction) in the third direction (Z direction). The width of the third well region 173 in the first direction (X direction) may be greater than the width of the second diffusion region 182 in the first direction (X direction); however, this disclosure is not limited thereto.

[0075] In one embodiment, the side surface of the third well region 173 may contact the side surface of the second well region 172. Therefore, a PN junction can be formed at the junction interface between the third well region 173 and the second well region 172. Thus, the first transistor of the electrostatic discharge protection device 100 according to the embodiment (e.g., Figure 4 The trigger voltage of the first transistor Q1. (Refer to...) Figures 4 to 6 A detailed description is provided. However, this disclosure is not limited thereto, and the side surface of the third well region 173 may be spaced apart from the side surface of the second well region 172 in a first direction (X direction). The third well region 173 may have the same conductivity type as the second diffusion region 182. For example, the third well region 173 may be doped with a second conductive impurity to have a second conductivity type. The second conductivity type may be n-type. The doping concentration of the third well region 173 may be greater than the doping concentration of the first epitaxial layer 121. The doping concentration of the third well region 173 may be less than the doping concentration of the second diffusion region 182. Additionally, the doping concentration of the third well region 173 may be greater than the doping concentration of the first drift region 141.

[0076] The fourth well region 174 can be disposed under the third diffusion region 183. For example, the fourth well region 174 can be disposed directly under a lower surface of the third diffusion region 183. The fourth well region 174 can be in contact with the lower surface of the third diffusion region 183, however, the disclosure is not limited thereto. The fourth well region 174 can be disposed on the second doped region 132. At least a portion of the fourth well region 174 can be surrounded by the second doped region 132. Additionally, the fourth well region 174 can be disposed on the first drift region 141. That is, at least a portion of the fourth well region 174 can be disposed on the second doped region 132, and a remaining portion of the fourth well region 174 can be disposed on the first drift region 141. However, the disclosure is not limited thereto, and the fourth well region 174 can not be disposed on the first drift region 141, and can be surrounded by the second doped region 132. A lower surface of the fourth well region 174 can be in contact with the second doped region 132 and the first drift region 141. The lower surface of the fourth well region 174 can be disposed at a higher level than a lower surface of the second doped region 132. That is, the lower surface of the fourth well region 174 can be disposed farther from the upper surface of the substrate 110 than the lower surface of the second doped region 132. The lower surface of the fourth well region 174 can be disposed at substantially similar and / or the same level as the lower surfaces of the first to third well regions 171 to 173, however, the disclosure is not limited thereto.

[0077] The fourth well region 174 can be stacked in the third direction (Z direction) with the third diffusion region 183 and the isolation layer STI disposed on both sides of the third diffusion region 183 in the first direction (X direction). A width of the fourth well region 174 in the first direction (X direction) can be greater than a width of the third diffusion region 183 in the first direction (X direction), however, the disclosure is not limited thereto.

[0078] The fourth well region 174 can have the same conductivity type as the third diffusion region 183. For example, the fourth well region 174 can be doped with first conductivity type impurities to have the first conductivity type. The first conductivity type can be p-type. A doping concentration of the fourth well region 174 can be greater than a doping concentration of the first doped region 131 and a doping concentration of the second doped region 132. The doping concentration of the fourth well region 174 can be less than a doping concentration of the third diffusion region 183.

[0079] The electrostatic discharge protection device 100 according to an embodiment can further include a fifth well region 175 and a sixth well region 176.

[0080] The fifth well region 175 can be disposed between the fifth diffusion region 185 and the second epitaxial layer 122. The fifth well region 175 can be disposed below the fifth diffusion region 185. For example, the fifth well region 175 can be disposed directly below a lower surface of the fifth diffusion region 185. The fifth well region 175 can be in contact with the lower surface of the fifth diffusion region 185, however, the disclosure is not limited thereto. The fifth well region 175 can be disposed on the second epitaxial layer 122. For example, the fifth well region 175 can be disposed on the third drift region 143 disposed on the second epitaxial layer 122. The fifth well region 175 can be spaced apart from the second epitaxial layer 122 in the third direction (Z direction), however, the disclosure is not limited thereto.

[0081] The fifth well region 175 can have the same conductivity type as the fifth diffusion region 185. For example, the fifth well region 175 can be doped with second conductivity impurities to have a second conductivity type. The second conductivity type can be n-type. The doping concentration of the fifth well region 175 can be greater than the doping concentration of the second epitaxial layer 122. The doping concentration of the fifth well region 175 can be less than the doping concentration of the fifth diffusion region 185.

[0082] The sixth well region 176 can be disposed between the sixth diffusion region 186 and the third doped region 133. The sixth well region 176 can be disposed below the sixth diffusion region 186. For example, the sixth well region 176 can be disposed directly below a lower surface of the sixth diffusion region 186. The sixth well region 176 can be in contact with the lower surface of the sixth diffusion region 186, however, the disclosure is not limited thereto. The sixth well region 176 can be disposed on the third doped region 133. The sixth well region 176 can be disposed in the third doped region 133. The sixth well region 176 can be surrounded by the third doped region 133. A lower surface and a side surface of the sixth well region 176 can be in contact with the third doped region 133, however, the disclosure is not limited thereto.

[0083] The sixth well region 176 can have the same conductivity type as the sixth diffusion region 186. For example, the sixth well region 176 can be doped with first conductivity type impurities to have a first conductivity type. The first conductivity type can be p-type. The doping concentration of the sixth well region 176 can be greater than the doping concentration of the third doped region 133. The doping concentration of the sixth well region 176 can be less than the doping concentration of the sixth diffusion region 186.

[0084] The electrostatic discharge protection device 100 according to an embodiment can further include a first drift region 141 disposed between the first epitaxial layer 121 and the third well region 173.

[0085] The first drift region 141 can be disposed on the first epitaxial layer 121. For example, the first drift region 141 can be disposed directly above an upper surface of the first epitaxial layer 121, however, the present disclosure is not limited thereto. The first drift region 141 can be disposed between the first epitaxial layer 121 and the third well region 173, between the first epitaxial layer 121 and the fourth well region 174, and between the first epitaxial layer 121 and the second well region 172. That is, the first drift region 141 can be stacked in the third direction (Z direction) with the second well region 172 to the fourth well region 174. In one embodiment, the first drift region 141 can be at least partially stacked in the third direction (Z direction) with the second well region 172 and / or the fourth well region 174. The first drift region 141 can be in contact with the second well region 172 to the fourth well region 174. Additionally, the first drift region 141 can be disposed between the third well region 173 and the fourth well region 174. In one embodiment, the first drift region 141 can have a predetermined width. For example, the first drift region 141 can have a second width (e.g., W2 in FIG. 1) in the first direction (X direction). In one embodiment, the second width of the first drift region 141 in the first direction (X direction) can be greater than or equal to the first width (e.g., W1 in FIG. 1) of the first epitaxial layer 121 in the first direction (X direction), however, the present disclosure is not limited thereto. Within the above range, the magnitude of the second reverse trigger voltage of the second transistor (e.g., Q2 in FIG. 1) can be reduced. As used herein, the second reverse trigger voltage can denote a voltage for turning on the second transistor in a reverse direction. Figure 4 Figure 4 Figure 4

[0086] In one embodiment, the first drift region 141 can have the same conductivity type as the first epitaxial layer 121. For example, the first drift region 141 can be doped with second conductive impurities to have a second conductivity type. The second conductivity type can be an n-type. The doping concentration of the first drift region 141 can be greater than the doping concentration of the first epitaxial layer 121. The doping concentration of the first drift region 141 can be less than the doping concentration of the first well region 171 and the doping concentration of the third well region 173. Accordingly, when a depletion region is formed by a reverse bias state between the first doped region 131 having the first conductivity type and the first drift region 141 having the second conductivity type, a punch-through phenomenon can occur in which the depletion region formation reaches the second doped region 132.

[0087] The electrostatic discharge protection device 100 according to the embodiment can further include a third drift region 143 disposed between the second epitaxial layer 122 and the fifth well region 175.

[0088] ​​​A third drift region 143 can be disposed on the second epitaxial layer 122. The third drift region 143 can be surrounded by the second epitaxial layer 122. The third drift region 143 can surround the fifth well region 175. The third drift region 143 can have the same conductivity type as the fifth well region 175 and the second epitaxial layer 122. For example, the third drift region 143 can be doped with second conductive impurities to have a second conductivity type. The second conductivity type can be n-type. The doping concentration of the third drift region 143 can be greater than the doping concentration of the second epitaxial layer 122 and less than the doping concentration of the fifth well region 175, however, the disclosure is not limited thereto.

[0089] The electrostatic discharge protection device 100 according to the embodiment can further include a field plate 350 connected with each of the first connection wiring 310 and the second connection wiring 320. The field plate 350 can be disposed on the isolation layer STI. The field plate 350 can prevent the surrounding field from spreading.

[0090] Hereinafter, the electrostatic discharge protection device according to the embodiment is further described with reference to Figure 4 and Figure 5

[0091] Figure 4 is an enlarged sectional view of the region R1 of Figure 3 Figure 5 is an equivalent circuit diagram of the electrostatic discharge protection device according to the embodiment.

[0092] Further, the electrostatic discharge protection device 100 according to the embodiment can include a first transistor Q1, a second transistor Q2, a third transistor Q3, a first diode DE1, and a second diode DE2 with reference to Figure 4 , for example. The first to third transistors Q1 to Q3 can be and / or can include, but are not limited to, bipolar junction transistors (BJTs). For example, the first and second transistors Q1 and Q2 can be PNP bipolar junction transistors, and the third transistor Q3 can be an NPN bipolar junction transistor.

[0093] In one embodiment, the first diffusion region 181, the second well region 172, the third well region 173, the first drift region 141, the fourth well region 174, and the third diffusion region 183 can configure the first transistor Q1. For example, the first diffusion region 181 and the second well region 172 can form an emitter of the first transistor Q1, the third well region 173 and the first drift region 141 can form a base of the first transistor Q1, and the fourth well region 174 and the third diffusion region 183 can form a collector of the first transistor Q1.

[0094] ​​Additionally, the fourth diffusion region 184, the first well region 171, and the first doped region 131 can form a first diode DE1, and the first doped region 131, the first epitaxial layer 121, the first drift region 141, the second doped region 132, the fourth well region 174, and the third diffusion region 183 can form a second transistor Q2. For example, the first doped region 131 can form the emitter of the second transistor Q2, the first epitaxial layer 121 and the first drift region 141 can form the base of the second transistor Q2, and the second doped region 132, the fourth well region 174, and the third diffusion region 183 can form the collector of the second transistor Q2.

[0095] Additionally, the third diffusion region 183, the fourth well region 174, and the first drift region 141 can form a second diode DE2, and the first drift region 141, the third well region 173, the second well region 172, the first doped region 131, the first well region 171, and the fourth diffusion region 184 can form a third transistor Q3. For example, in one embodiment, the first drift region 141 and the third well region 173 can form the collector of the third transistor Q3, the second well region 172 and the first doped region 131 can form the base of the third transistor Q3, and the first well region 171 and the fourth diffusion region 184 can form the emitter of the third transistor Q3. In this case, the fourth diffusion region 184 and the first diffusion region 181 can be electrically connected via the first connection wiring 310. Furthermore, in another embodiment, the third diffusion region 183, the fourth well region 174, the first drift region 141, and the third well region 173 can form the collector of the third transistor Q3.

[0096] Further reference Figure 5 The electrostatic discharge protection device 100 according to an embodiment may include a first transistor Q1 to a third transistor Q3, a first diode DE1, and a second diode DE2. Additionally, the electrostatic discharge protection device 100 according to an embodiment may include a first electrode E1 and a second electrode E2. The first electrode E1 may be electrically connected to... Figure 4 The first connection wiring 310, and the first electrode E1 can be an anode electrode that receives an electrostatic discharge voltage. Additionally, the second electrode E2 can be electrically connected to... Figure 4 The second connection wiring 320, and the second electrode E2 can be a cathode electrode connected to the ground node.

[0097] In one embodiment, the first transistor Q1 to the third transistor Q3 are electrically connected to the first electrode E1 via the first node N1 and to the second electrode E2 via the second node N2. Additionally, the first diode DE1 is electrically connected between the first node N1 and the second transistor Q2, and the second diode DE2 is electrically connected between the third transistor Q3 and the second node N2.

[0098] Hereinafter, the operation of the electrostatic discharge protection device 100 according to an embodiment is described.

[0099] For better understanding and ease of description, hereinafter, when the ESD voltage applied to the first electrode E1 has a positive value, the ESD voltage can be referred to as a forward ESD voltage, and when the ESD voltage has a negative value, the ESD voltage can be referred to as a reverse ESD voltage.

[0100] In one embodiment, a ground voltage can be applied to the second electrode E2. That is, the forward ESD voltage can be greater than the ground voltage of the second electrode E2, and the reverse ESD voltage can be less than the voltage of the second electrode E2.

[0101] Referring to Figure 4 and Figure 5 , first, when the forward ESD voltage is applied through the first electrode E1, the potential of the first diffusion region 181 and the second well region 172 can rise (increase). Accordingly, the first transistor Q1 including the first diffusion region 181, the second well region 172, the third well region 173, the first drift region 141, the fourth well region 174, and the third diffusion region 183 can be turned on. In this case, when the forward ESD voltage is greater than a first forward trigger voltage of the first transistor Q1, the first transistor Q1 can be turned on. As used herein, the first forward trigger voltage can denote a voltage for the first transistor Q1 to be turned on in a forward direction. The first forward trigger voltage of the first transistor Q1 can have a predetermined value. For example, the first forward trigger voltage of the first transistor Q1 can be, but is not limited to, 12 volts (V) to 50 V.

[0102] When the first transistor Q1 is turned on, a current can flow from the second well region 172 through the third well region 173 to the fourth well region 174, and the forward ESD voltage applied through the first electrode E1 can be discharged to the second electrode E2 through the third diffusion region 183 and the second connection wiring 320.

[0103] In addition, when the forward ESD voltage is applied through the first electrode E1, the potential of the first well region 171 rises together since the first diffusion region 181 and the fourth diffusion region 184 are electrically connected through the first connection wiring 310. Accordingly, the first well region 171 and the first doped region 131 can be in a reverse bias state, thereby forming a depletion region. That is, the first diode DE1 can be cut off, and the second transistor Q2 can not be turned on.

[0104] When a forward ESD voltage is applied through the first electrode E1, the potential of the third well region 173 can become higher than the potential of the fourth well region 174. Accordingly, the fourth well region 174 and the third well region 173 can be in a reverse-biased state, thereby forming a depletion region. That is, the second diode DE2 can be off, and the third transistor Q3 can not be turned on.

[0105] When a reverse ESD voltage is applied through the first electrode E1, the potentials of the first diffusion region 181 and the second well region 172 decrease. Accordingly, the first transistor Q1 including the first diffusion region 181, the second well region 172, the third well region 173, the first drift region 141, the fourth well region 174, and the third diffusion region 183 can be turned on in a reverse direction. In this case, a reverse ESD voltage less than or equal to a predetermined value is required for the first transistor Q1 to be turned on in the reverse direction. That is, when the reverse ESD voltage is less than a first reverse trigger voltage of the first transistor Q1, the first transistor Q1 can be turned on. As used herein, the first reverse trigger voltage can denote a voltage for the first transistor Q1 to be turned on in the reverse direction. The first reverse trigger voltage of the first transistor Q1 can have a predetermined value. The magnitude of the first reverse trigger voltage can be substantially similar to and / or equal to the magnitude of the first forward trigger voltage. For example, the first reverse trigger voltage of the first transistor Q1 can be, but is not limited to, -12V to -50V.

[0106] In this case, a current can flow from the second well region 172 through the third well region 173 to the fourth well region 174, and the reverse ESD voltage applied through the first electrode E1 can be discharged to the second electrode E2 through the third diffusion region 183 and the second connection wiring 320.

[0107] In addition, when a reverse ESD voltage is applied through the first electrode E1, the potential of the first well region 171 decreases together since the first diffusion region 181 and the fourth diffusion region 184 are electrically connected through the first connection wiring 310. Accordingly, the potential of the first well region 171 can become lower than the potential of the first doped region 131, and the first diode DE1 can be turned on. Accordingly, the potential of the first doped region 131 can decrease.

[0108] The doping concentration of the first epitaxial layer 121 forming a base of the second transistor Q2 and / or the doping concentration of the first drift region 141 can be less than the doping concentration of the third well region 173 forming a base of the first transistor Q1. Accordingly, a punch-through phenomenon can occur within the first epitaxial layer 121 and / or the first drift region 141.

[0109] That is, when the potential of the first doped region 131 decreases, a reverse bias state can be formed between the first doped region 131 having the first conductivity type and the first epitaxial layer 121 having the second conductivity type and / or between the first doped region 131 and the first drift region 141 having the second conductivity type, thereby forming a depletion region. In this case, when the first epitaxial layer 121 and / or the first drift region 141 is doped at a low concentration, the depletion region can be formed up to the second doped region 132. Accordingly, a punch-through phenomenon in which a current flows from the first doped region 131 to the second doped region 132 can occur regardless of the potential of the base of the second transistor Q2.

[0110] Additionally, in one embodiment, the doping concentration of the first epitaxial layer 121 can be less than the doping concentration of the first drift region 141. Accordingly, in a range in which the first width W1 of the first epitaxial layer 121 in the first direction (X direction) is less than or equal to the second width W2 of the first drift region 141 in the first direction (X direction), a punch-through phenomenon in which a current flows through the first epitaxial layer 121 from the first doped region 131 to the second doped region 132 can occur more easily.

[0111] Additionally, in one embodiment, the second reverse trigger voltage of the second transistor Q2 can depend on the first width W1 of the first epitaxial layer 121 in the first direction (X direction) and the second width W2 of the first drift region 141 in the first direction (X direction). For example, as the first width W1 of the first epitaxial layer 121 in the first direction (X direction) and the second width W2 of the first drift region 141 in the first direction (X direction) decrease, the magnitude of the second reverse trigger voltage can decrease, and as the first width W1 of the first epitaxial layer 121 in the first direction (X direction) and the second width W2 of the first drift region 141 in the first direction (X direction) increase, the magnitude of the second reverse trigger voltage can increase. That is, the smaller the widths of the first epitaxial layer 121 and the first drift region 141, the more easily a punch-through phenomenon can occur.

[0112] In summary, when the first epitaxial layer 121 and / or the first drift region 141 is doped with a low concentration, the magnitude of the reverse ESD voltage for turning on the second transistor Q2 in the reverse direction can be reduced. Accordingly, when the reverse ESD voltage is applied to the first electrode E1, the second transistor Q2 can be turned on before the first transistor Q1 is turned on. The magnitude of the second reverse trigger voltage for turning on the second transistor Q2 in the reverse direction can be smaller than the magnitude of the first reverse trigger voltage for turning on the first transistor Q1 in the reverse direction. That is, even when the reverse ESD voltage having a magnitude smaller than the magnitude of the first reverse trigger voltage of the first transistor Q1 is applied to the first electrode E1, the electrostatic discharge protection device 100 according to the embodiment can turn on the second transistor Q2. For example, the second reverse trigger voltage can be, but is not limited to, -2.8 V to -8 V.

[0113] Additionally, when the reverse ESD voltage is applied through the first electrode E1, the potential of the first drift region 141 can decrease. Accordingly, the second diode DE2 including the first drift region 141 and the fourth well region 174 can be turned on. Additionally, when the reverse ESD voltage is applied through the first electrode E1, the third transistor Q3 can be turned on as the potential of the first well region 171 decreases. Accordingly, the current can be discharged from the first electrode E1 to the second electrode E2 through the fourth diffusion region 184, the first well region 171, the second well region 172, the third well region 173, the first drift region 141, the fourth well region 174, and the third diffusion region 183.

[0114] At this time, the third reverse trigger voltage of the third transistor Q3 can depend on the first distance D1 between the first well region 171 and the second well region 172. For example, as the first distance D1 between the first well region 171 and the second well region 172 decreases, the magnitude of the third reverse trigger voltage can increase, and as the first distance D1 between the first well region 171 and the second well region 172 increases, the magnitude of the third reverse trigger voltage can decrease. Accordingly, the first doped region 131 doped with a relatively low concentration can be disposed between the first well region 171 and the second well region 172.

[0115] Further referring to Figure 6 An electrostatic discharge protection device according to an embodiment is described.

[0116] Figure 6 is a graph showing a voltage-current curve of an electrostatic discharge protection device according to an embodiment.

[0117] Figure 6is a graph showing a trigger voltage of the electrostatic discharge protection device 100b according to the embodiment and a trigger voltage of the electrostatic discharge protection device 100a according to the comparative example. The comparative example shows the electrostatic discharge protection device 100a not including the first well region 171 and the fourth diffusion region 184, and the electrostatic discharge protection device 100b according to the embodiment includes the first well region 171 and the fourth diffusion region 184. Figures 1 to 5 That is, the electrostatic discharge protection device 100a according to the comparative example can mean a case where the first transistor Q1 of the embodiment is included and the second transistor Q2 and the third transistor Q3 are not included. Figures 1 to 5

[0118] Further referring to Figure 6 , the first forward trigger voltage of the electrostatic discharge protection device 100a according to the comparative example can be VTa_1, and the first reverse trigger voltage can be VTa_2. According to the embodiment, the second forward trigger voltage of the electrostatic discharge protection device 100b can be VTb_1, and the second reverse trigger voltage can be VTb_2. In one embodiment, the first forward trigger voltage VTa_1 of the electrostatic discharge protection device 100a according to the comparative example can be substantially similar and / or equal to the first forward trigger voltage of the first transistor Q1 of the embodiment. Figures 1 to 5 The first reverse trigger voltage VTa_2 of the electrostatic discharge protection device 100a according to the comparative example can be substantially similar and / or equal to the first reverse trigger voltage of the first transistor Q1 of the embodiment. Figures 1 to 5

[0119] As shown in the graph, it can be seen that the electrostatic discharge protection device 100a can operate at the first reverse trigger voltage VTa_2 having a relatively large magnitude when the second transistor Q2 and the third transistor Q3 are not included. Thus, the electrostatic discharge protection device 100a not including the second transistor Q2 and the third transistor Q3 can not be sufficient to protect the integrated circuit device (e.g., the integrated circuit device 500 in Figure 1 ) from the reverse ESD voltage having a small magnitude.

[0120] Alternatively, because the electrostatic discharge protection device 100b including the second transistor Q2 and the third transistor Q3 utilizes the punch-through phenomenon within the first epitaxial layer 121 and / or the first drift region 141, the electrostatic discharge protection device 100b can operate at the second reverse trigger voltage VTb_2 having a relatively small magnitude. Thus, the electrostatic discharge protection device 100b according to the embodiment can protect the integrated circuit device (e.g., the integrated circuit device 500 in Figure 1 ) from the reverse ESD voltage having a magnitude smaller than the magnitude of the first reverse trigger voltage VTa_2.

[0121] ​​Hereinafter, reference is made to Figures 7 to 13 An electrostatic discharge protection device according to some embodiments is described.

[0122] Figures 7 to 13 is a cross-sectional view corresponding to line A-A' of Figure 2 the electrostatic discharge protection device according to some embodiments.

[0123] Figures 7 to 13 Various modified examples of the electrostatic discharge protection device according to Figures 1 to 6 the embodiments shown in Figures 7 to 13 the embodiments shown in Figures 1 to 6 may be substantially similar in many respects to the embodiments shown in therefore their description can be omitted for brevity, and the differences are briefly described. Additionally, the same reference numerals are used for the same components as in the previous embodiments.

[0124] Figure 7 The electrostatic discharge protection device 100 according to some embodiments can further include a second drift region 142 disposed between the first doped region 131 and the first well region 171.

[0125] The second drift region 142 can be disposed on the first doped region 131. The second drift region 142 can be surrounded by the first doped region 131. The second drift region 142 can surround the first well region 171. The second drift region 142 can be spaced apart from the second well region 172 in the first direction (X direction), however, the present disclosure is not limited thereto. The second drift region 142 can be formed at substantially similar and / or the same depth as the first drift region 141. A lower surface of the second drift region 142 can be disposed at the same height as a lower surface of the first drift region 141. That is, a distance from the lower surface of the second drift region 142 to an upper surface of the substrate 110 can be substantially similar and / or the same as a distance from the lower surface of the first drift region 141 to the upper surface of the substrate 110.

[0126] The second drift region 142 can have the same conductivity type as the first well region 171 and the first epitaxial layer 121. For example, the second drift region 142 can be doped with second conductive impurities to have a second conductivity type. The second conductivity type can be n-type. A doping concentration of the second drift region 142 can be greater than a doping concentration of the first epitaxial layer 121, and can be less than a doping concentration of the first well region 171.

[0127] The electrostatic discharge protection device 100 according to some embodiments can not include the first well region 171. For example, as Figure 8As shown, according to some embodiments, the electrostatic discharge protection device 100 may include a second drift region 142 on a first doped region 131, and a fourth diffusion region 184 may be directly disposed above the upper surface of the second drift region 142. That is, the lower surface of the fourth diffusion region 184 may contact the upper surface of the second drift region 142. Even when Figure 8 In some embodiments, a PN junction may also be formed at the junction interface between a second drift region 142 having a second conductivity type and a first doped region 131 having a first conductivity type. The second drift region 142 and the first doped region 131 may form a first diode (e.g., Figure 5 The first diode DE1 in the middle.

[0128] Reference Figure 9 According to some embodiments, the electrostatic discharge protection device 100 may not include the first well region 171. For example, according to some embodiments, the fourth diffusion region 184 of the electrostatic discharge protection device 100 may be directly disposed above the upper surface of the first doped region 131. The lower surface of the fourth diffusion region 184 may be in contact with the upper surface of the first doped region 131.

[0129] Reference Figure 10 According to some embodiments, the first well region 171_1 of the electrostatic discharge protection device 100 may have a different conductivity type than the fourth diffusion region 184. For example, the first well region 171_1 may have the same conductivity type as the second well region 172 and / or the first doped region 131. The first well region 171_1 may be doped with a first conductivity type impurity to have the first conductivity type. The first conductivity type may be p-type. In this case, the doping concentration of the first well region 171_1 may be greater than the doping concentration of the first doped region 131. The first well region 171_1 and the second well region 172 may be spaced apart from each other, but are not limited thereto. The remaining description of the first well region 171_1 may be related to in many respects... Figures 1 to 6 The description of the first well region 171 is essentially the same, and therefore repeated descriptions can be omitted for the sake of brevity.

[0130] Reference Figure 11 According to some embodiments, the fourth diffusion region 184_1 of the electrostatic discharge protection device 100 may have the same conductivity type as the first doped region 131. That is, the fourth diffusion region 184_1 may have a different conductivity type than the first well region 171. For example, the fourth diffusion region 184_1 may be doped with a first conductivity type impurity to have the first conductivity type. The first conductivity type may be p-type. In this case, the doping concentration of the fourth diffusion region 184_1 may be greater than the doping concentration of the first doped region 131. The remaining description of the fourth diffusion region 184_1 may differ in many respects from... Figures 1 to 6The description of the fourth diffusion region 184 of the electrostatic discharge protection device 100 according to some embodiments is substantially similar, and thus repeated description can be omitted for brevity.

[0131] Referring to Figure 12 The fourth diffusion region 184 of the electrostatic discharge protection device 100 according to some embodiments can include a plurality of diffusion regions. For example, the fourth diffusion region 184 can include a first sub-diffusion region 184a and a second sub-diffusion region 184b spaced apart from each other in a first direction (X direction). The first sub-diffusion region 184a and the second sub-diffusion region 184b can be electrically connected to the first connection wiring 310. For example, the first sub-diffusion region 184a can be electrically connected to the first connection wiring 310 through the fifth via hole 336, and the second sub-diffusion region 184b can be electrically connected to the first connection wiring 310 through the sixth via hole 335. Accordingly, the first sub-diffusion region 184a and the second sub-diffusion region 184b can be electrically connected to the first diffusion region 181. Additionally, the first sub-diffusion region 184a can be electrically connected to the second sub-diffusion region 184b.

[0132] In some embodiments, the first sub-diffusion region 184a and the second sub-diffusion region 184b can have the same conductive type as the second diffusion region 182. The first sub-diffusion region 184a and the second sub-diffusion region 184b can have a different conductive type from the first doped region 131. For example, the first sub-diffusion region 184a and the second sub-diffusion region 184b can be doped with second conductive impurities to have a second conductive type. The second conductive type can be an n-type. In some embodiments, the first sub-diffusion region 184a and the second sub-diffusion region 184b can have the same conductive type, however, the disclosure is not limited thereto, and the first sub-diffusion region 184a and the second sub-diffusion region 184b can have different conductive types. The remaining description of each of the first sub-diffusion region 184a and the second sub-diffusion region 184b can be substantially similar in many aspects to the description of the first diffusion region 181 of the electrostatic discharge protection device 100 according to some embodiments. Figures 1 to 6 The description of the first diffusion region 181 of the electrostatic discharge protection device 100 according to some embodiments is substantially similar, and thus repeated description can be omitted for brevity.

[0133] Additionally, a plurality of first well regions 171 of the electrostatic discharge protection device 100 according to some embodiments can be provided. For example, the first well region 171 can include a first sub-well region 171a and a second sub-well region 171b spaced apart from each other in a first direction (X direction). The first sub-well region 171a can be provided between the first sub-diffusion region 184a and the first doped region 131, and the second sub-well region 171b can be provided between the second sub-diffusion region 184b and the first doped region 131. The first sub-well region 171a and the second sub-well region 171b can be spaced apart from each other in the first direction (X direction), however, the disclosure is not limited thereto.

[0134] In some embodiments, the first sub-well region 171a can have the same conductivity type as the first sub-diffusion region 184a, and the second sub-well region 171b can have the same conductivity type as the second sub-diffusion region 184b. For example, the first sub-well region 171a and the second sub-well region 171b can be doped with second-conductive impurities to have a second conductivity type. The second conductivity type can be n-type. The doping concentration of the first sub-well region 171a and the second sub-well region 171b can be less than the doping concentration of the first sub-diffusion region 184a and the second sub-diffusion region 184b, and can be less than the doping concentration of the first drift region 141 and the first epitaxial layer 121.

[0135] In Figure 12 which a case where the fourth diffusion region 184 is formed of two (2) diffusion regions is shown, but the number of the fourth diffusion region 184 and the number of the first well region 171 are not limited thereto. For example, there can be three (3) or more fourth diffusion regions 184 and first well regions 171.

[0136] Referring to Figure 13 , the second well region 172 and the third well region 173 of the electrostatic discharge protection device 100 according to some embodiments can be spaced apart from each other. For example, the second well region 172 and the third well region 173 can be spaced apart from each other in the first direction (X direction). In this case, the first drift region 141 can be disposed between the second well region 172 and the third well region 173.

[0137] Hereinafter, a system including an electrostatic discharge protection device according to an embodiment is described with reference to Figure 14 .

[0138] Figure 14 is a block diagram illustrating a system including an electrostatic discharge protection device according to an embodiment.

[0139] Referring to Figure 14 , the system 2000 can include a main processor 2100, a memory (e.g., a first memory 2200a and a second memory 2200b), and a storage device (e.g., a first storage device 2300a and a second storage device 2300b), and can further include one or more of an image capture device 2410, a user input device 2420, a sensor 2430, a communication device 2440, a display 2450, a speaker 2460, a power device 2470, and a connection interface 2480.

[0140] The main processor 2100 can control the overall operation of the system 2000, such as but not limited to, the operation of other components included in the system 2000. The main processor 2100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor.

[0141] The main processor 2100 can include one or more CPU cores 2110, and can further include a controller 2120 for controlling the first and second memories 2200a and 2200b and / or the first and second storage devices 2300a and 2300b. According to an embodiment, the main processor 2100 can further include an accelerator 2130, which can be a special-purpose circuit for high-speed data operations such as artificial intelligence (AI) data operations. The accelerator 2130 can include a graphics processor (GPU), a neural processor (NPU), and / or a data processor (DPU), and can be implemented as a chip physically separated from other components of the main processor 2100.

[0142] The first and second memories 2200a and 2200b can serve as main memory devices of the system 2000, and although the first and second memories 2200a and 2200b can include volatile memories such as static random access memories (SRAMs) and / or dynamic random access memories (DRAMs), the first and second memories 2200a and 2200b can further include non-volatile memories such as, but not limited to, flash memories, phase-change random access memories (PRAMs), resistive random access memories (RRAMs), etc. The first and second memories 2200a and 2200b can also be implemented in the same package as the main processor 2100.

[0143] The first and second storage devices 2300a and 2300b can serve as non-volatile storage devices that can store data regardless of whether power is supplied thereto, and can have a relatively large storage capacity when compared with the first and second memories 2200a and 2200b. The first and second storage devices 2300a and 2300b can include storage controllers (e.g., first and second storage controllers 2310a and 2310b) and non-volatile memories (NVMs) (e.g., first and second NVMs 2320a and 2320b) that store data under the control of the first and second storage controllers 2310a and 2310b. The first and second non-volatile memories 2320a and 2320b can include 2-dimensional (2D) structures and / or 3-dimensional (3D) V-NAND (vertical NAND) flash memories, and / or can include other types of non-volatile memories such as PRAMs and / or RRAMs.

[0144] The first storage 2300a and the second storage 2300b included in the system 2000 can be physically separated from the main processor 2100 and / or can be implemented in the same package within the main processor 2100. Also, the first storage 2300a and the second storage 2300b can take the form of a solid state device (SSD) or a memory card, and can be removably combined with other components of the system 2000 through an interface such as the connection interface 2480. The first storage 2300a and the second storage 2300b can be devices to which a standard protocol such as Universal Flash Storage (UFS), Embedded Multimedia Card (eMMC), or Non-Volatile Memory Express (NVMe) can be applied, however, the disclosure is not limited thereto, and the first storage 2300a and the second storage 2300b can be implemented using other protocols.

[0145] The image capture device 2410 can capture still images and / or moving images, and can include, without limitation, a camera, a camcorder, and / or a webcam.

[0146] The user input device 2420 can receive various types of data input from a user of the system 2000, and can include, without limitation, a touchpad, a keypad, a keyboard, a mouse, and / or a microphone.

[0147] The sensor 2430 can detect various types of physical quantities that can be obtained from the outside of the system 2000, and can convert the detected physical quantities into electrical signals. The sensor 2430 can include, without limitation, a temperature sensor, a pressure sensor, a light sensor, a position sensor, an acceleration sensor, a biological sensor, and / or a gyroscope sensor.

[0148] The communication device 2440 can transmit and / or receive signals between other devices outside the system 2000 according to various communication protocols. The communication device 2440 can be implemented to include an antenna, a transceiver, and / or a modem.

[0149] The display 2450 and the speaker 2460 can serve as output devices that can output visual information and / or audible information, respectively, to a user of the system 2000.

[0150] The power device 2470 can appropriately convert power supplied from a battery built in the system 2000 and / or from an external power source, and supply the power to each component of the system 2000. For example, the power device 2470 can include one or more power management integrated circuits (PMICs). The power device 2470 can include an ESD protection device as described with reference to Figures 1 to 13

[0151] ​The connection interface 2480 can provide a connection between the system 2000 and an external device, which can be connected to the system 2000 and can be able to transmit data to and / or receive data from the system 2000. The connection interface 2480 can be implemented by using various interface schemes such as, but not limited to, an advanced technology attachment (ATA), a serial ATA (SATA), an external SATA (e-SATA), a small computer small interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnect (PCI), a PCI express (PCIe), an NVMe, an IEEE 1394 (FireWire), a universal serial bus (USB), a secure digital (SD) card, a multimedia card (MMC), an eMMC, a UFS, an embedded universal flash storage (eUFS), and a compact flash (CF) card interface.

[0152] While the present disclosure has been described in connection with what is presently considered to be the actual embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. An electrostatic discharge protection device, comprising: Base; A first doped region of a first conductivity type is on the substrate; A second doped region of the first conductivity type is on the substrate; An epitaxial layer of the second conductivity type is located between the first doped region and the second doped region; A first diffusion region of a first conductivity type is located on a first doped region; A second diffusion region of the second conductivity type is located on the epitaxial layer; The third diffusion region of the first conductivity type is located on the second doped region; as well as A fourth diffusion region of the second conductivity type is located on and spaced apart from the first doped region. Among them, the first diffusion region and the fourth diffusion region are electrically combined.

2. The electrostatic discharge protection device according to claim 1, wherein, The first conductivity type is p-type, and The second conductivity type is n-type.

3. The electrostatic discharge protection device according to claim 1 further includes: The first well region is located between the fourth diffusion region and the first doped region. The first doping concentration in the first well region is greater than the second doping concentration in the epitaxial layer.

4. The electrostatic discharge protection device according to claim 3 further includes: The first drift region of the second conductivity type is located between the epitaxial layer and the second diffusion region. The third doping concentration in the first drift region is less than the first doping concentration in the first well region.

5. The electrostatic discharge protection device according to claim 4, wherein, The first width of the epitaxial layer is less than or equal to the second width of the first drift region.

6. The electrostatic discharge protection device according to claim 3 further includes: A second well region of a first conductivity type is located between the first doped region and the first diffused region; as well as The third well region of the second conductivity type is located between the epitaxial layer and the second diffusion region. The third doping concentration in the third well region is greater than the second doping concentration in the epitaxial layer.

7. The electrostatic discharge protection device according to claim 6, wherein, The side surface of the second well region is in contact with the side surface of the third well region.

8. The electrostatic discharge protection device according to claim 6, wherein, The fourth doping concentration in the first doped region is less than the fifth doping concentration in the second well region.

9. The electrostatic discharge protection device according to claim 6, wherein, The second well region is separated from the first well region.

10. The electrostatic discharge protection device according to claim 6, further comprising: The first drift region of the second conductivity type is located between the epitaxial layer and the third well region. The fourth doping concentration in the first drift region is less than the third doping concentration in the third well region.

11. The electrostatic discharge protection device according to claim 10, wherein, The fourth doping concentration in the first drift region is greater than the second doping concentration in the epitaxial layer.

12. The electrostatic discharge protection device according to claim 10, wherein, The first drift region overlaps at least partially with the second well region in the thickness direction of the substrate.

13. The electrostatic discharge protection device according to claim 1, further comprising: The second drift region of the second conductivity type is located between the first doped region and the fourth diffusion region. In this process, the first doping concentration in the second drift region is greater than the second doping concentration in the epitaxial layer.

14. The electrostatic discharge protection device according to claim 13, further comprising: The first well region is in contact with the second drift region and the fourth diffusion region. The first doping concentration in the second drift region is less than the third doping concentration in the first well region.

15. The electrostatic discharge protection device according to any one of claims 1 to 14, wherein, The first width of the fourth diffusion region is greater than or equal to the second width of the first diffusion region.

16. An electrostatic discharge protection device, comprising: Base; A first doped region of a first conductivity type is on the substrate; A second doped region of a first conductivity type is on the substrate and spaced apart from the first doped region; An epitaxial layer of the second conductivity type is located between the first doped region and the second doped region; The first well region of the second conductivity type is located on the first doped region; A second well region of a first conductivity type is located on the first doped region and spaced apart from the first well region; The third well region of the second conductivity type is on the epitaxial layer; A first diffusion region of a first conductivity type is located on a second well region; The second diffusion region of the second conductivity type is located in the third well region; The third diffusion region of the first conductivity type is located on the second doped region; as well as The fourth diffusion region is located on the first well region. Among them, the first diffusion region and the fourth diffusion region are electrically combined, and In this case, the first doping concentration in the third well region is greater than the second doping concentration in the epitaxial layer.

17. The electrostatic discharge protection device according to claim 16, wherein, The fourth diffusion region has a second conductivity type, and The third doping concentration in the fourth diffusion region is greater than the fourth doping concentration in the first well region.

18. The electrostatic discharge protection device according to claim 16, further comprising: The first drift region of the second conductivity type is located between the epitaxial layer and the third well region. Wherein, the third doping concentration in the first drift region is less than the first doping concentration in the third well region, and In this region, the third doping concentration in the first drift region is greater than the second doping concentration in the epitaxial layer.

19. The electrostatic discharge protection device according to claim 18, further comprising: The fourth well region of the first conductivity type is located on the second doped region. The first drift region overlaps at least partially with the fourth well region in the thickness direction of the substrate.

20. An electrostatic discharge protection device, comprising: Base; A first doped region of a first conductivity type is on the substrate; A second doped region of a first conductivity type is on the substrate and spaced apart from the first doped region; An epitaxial layer of the second conductivity type is located between the first doped region and the second doped region; The first well region of the second conductivity type is located on the first doped region; A second well region of a first conductivity type is located on the first doped region and spaced apart from the first well region; The first drift region of the second conductivity type is on the epitaxial layer; The third well region of the second conductivity type is located on the first drift region and forms a junction interface with the second well region; A first diffusion region of a first conductivity type is located on a second well region; The second diffusion region of the second conductivity type is located in the third well region; The third diffusion region of the first conductivity type is located on the second doped region; as well as The fourth diffusion region of the second conductivity type is located in the first well region. Among them, the first diffusion region and the fourth diffusion region are electrically combined. In this region, the first doping concentration in the first drift region is less than the second doping concentration in the third well region. Wherein, the first doping concentration in the first drift region is greater than the third doping concentration in the epitaxial layer, and In this case, the fourth doping concentration in the first well region is greater than the third doping concentration in the epitaxial layer.

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