ESD (Electro-Static Discharge) protection structure of three-dimensional integrated circuit and design and integration method thereof

Abstract

The invention discloses an ESD (Electro-Static Discharge) protection structure of a three-dimensional integrated circuit and a design and integration method of the ESD protection structure, the structure is constructed based on a standard cell library, the parasitic PN junction characteristics of phase inverter PMOS (P-channel Metal Oxide Semiconductor) and NMOS (N-channel Metal Oxide Semiconductor) devices in the standard cell library are utilized, on the premise of not introducing a new device or modifying a technological process, a Tap unit is matched to form an ESD path, and efficient ESD protection is realized. The structure provided by the invention has the capability of being completely embedded into the functional circuit layout, the layout area is absorbed by the functional unit, and the problem that the area of the ESD structure is limited due to miniature bonding pitch is obviously relieved. The scheme is particularly suitable for protection of CDM discharge risks in the bonding process of different core particles of a three-dimensional integrated circuit, has the advantages of being compact in layout, fast in trigger response, high in design mobility and the like, is adaptive to various advanced process nodes and high-density interconnection chip scenes, and provides an effective solution for improving the bonding yield of the 3D IC and the ESD robustness of a system.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit design, and in particular to an electrostatic discharge (ESD) protection structure suitable for three-dimensional integrated circuits (3DIC). Specifically, it is a parasitic PN junction type ESD protection structure that is compatible with standard cells, area-friendly, and suitable for cross-voltage domain CDM (Charged Device Model) protection. The invention also relates to its design and integration methods. Background Technology

[0002] As advanced process technologies evolve towards 3 nanometers and below, the traditional approach of relying on process scaling to improve chip performance is facing bottlenecks. Three-dimensional integrated circuit (3D-IC) technology, by stacking multiple functional chips vertically, significantly improves system integration, performance density, and energy efficiency, becoming a key implementation path for high-performance computing, artificial intelligence, and communication system chips. In this structure, high-speed data and power signal transmission is achieved between chips through interconnection methods such as microbumps (μbumps) and through-silicon vias (TSVs). With the continuous miniaturization of bonding pitch, the I / O density and interconnect bandwidth between 3D IC chips have increased significantly, but this has also brought new reliability challenges.

[0003] Electrostatic discharge (ESD) is a particularly prominent issue. During die-to-die bonding, the inconsistency in charge potential between different chips can trigger transient electrostatic shocks of the charge model (CDM) type. Without effective protection structures, this can easily lead to breakdown of the gate oxide layer at the receiver, causing irreversible physical damage. Traditional ESD protection schemes often use pull-up and pull-down diodes placed in the I / O area to create discharge paths to power and ground. However, these structures typically require dedicated layout areas, making them difficult to deploy in areas with limited bonding pitch. Furthermore, the long interconnection paths between these structures and the protected circuits increase series resistance and protection response delay, making it difficult to cope with the nanosecond-level high current surges of CDM in 3D IC scenarios.

[0004] Even more challenging is the fact that in high-density 3D IC chips, the area and parasitic capacitance overhead of traditional ESD protection cells are significant, creating a sharp conflict with the interconnect design goals of high-bandwidth interfaces. Therefore, the industry urgently needs a new ESD protection structure with ultra-small area, fast conduction capability, and the ability to be integrated into standard cells to meet the demands of future high-density interconnects between chips and cross-voltage domain interfaces. Summary of the Invention

[0005] Purpose of the invention: The purpose of this invention is to provide an area-friendly ESD protection structure compatible with standard cells, aiming to solve the problems of limited layout space, long protection path distance, and excessive overall area overhead caused by the bonding pitch in existing three-dimensional integrated circuit (3D IC) electrostatic discharge (ESD) protection designs.

[0006] Technical Solution: The present invention provides an ESD protection structure for a three-dimensional integrated circuit. The ESD protection structure includes at least one pair of PMOS and NMOS transistors derived from standard cells in a standard cell library. The parasitic PN junction structure of the PMOS and NMOS transistors is used to construct a discharge path and is integrated into the three-dimensional integrated circuit, comprising:

[0007] The parasitic PN junction discharge path in the pull-up direction: The source, drain and gate of the PMOS transistor are shorted and connected to the input / output port to form the anode of the P-type parasitic diode. Its cathode is connected to VDD through the N-type doped region of the Tap cell in the standard cell library, thereby forming the pull-up discharge path from I / O to VDD.

[0008] The parasitic PN junction discharge path in the pull-down direction: The source, drain and gate of the NMOS transistor are shorted and connected to the input / output port to form the cathode of the N-type parasitic diode. Its anode is connected to VSS through the P-type doped region of the Tap cell in the standard cell library, thereby forming a pull-down discharge path from VSS to I / O.

[0009] The standard unit loses its original logical function after structural reconstruction, and only retains the parasitic PN junction to provide a discharge path in electrostatic discharge events.

[0010] Optionally, the standard cell is an inverter from the standard cell library, and the PMOS transistor and NMOS transistor of the inverter are arranged symmetrically in the layout structure.

[0011] Optionally, the Tap cell is a cell in the standard cell library, and its layout size and process parameters are compatible and consistent with the standard cell.

[0012] Optionally, the ESD protection structure can be directly integrated into a standard cell array in the functional circuit area.

[0013] Optionally, the ESD protection structure is used to implement electrostatic discharge protection at signal interfaces in different power supply voltage domains.

[0014] Optionally, the ESD protection structure is deployed in the near-end region of the core input / output interface to rapidly discharge electrostatic energy during a CDM event through the ESD discharge path.

[0015] Optionally, the discharge capability of the ESD protection structure can be adjusted in the following ways to meet the requirements of different CDM discharge indicators:

[0016] (1) Select standard units of different sizes and driving capabilities;

[0017] (2) Multiple pairs of Tap cells are used and arranged laterally on both sides of the standard cell, and are respectively connected to the parasitic PN junction electrode of the PMOS or NMOS transistor to form a parallel discharge path.

[0018] (3) Optimize the metal interconnect layout inside the ESD protection structure, including the metal traces between the input / output electrodes and the standard cell and the two side Tap cells. The optimization method includes adjusting the trace width, metal layers and the number and distribution of vias.

[0019] Optionally, the P+ diffusion region of the PMOS transistor serves as the anode of the parasitic P-type diode, and the N-well is connected to the power supply terminal VDD through a Tap unit to form the cathode; the N+ diffusion region of the NMOS transistor serves as the cathode of the parasitic N-type diode, and the P substrate is connected to the ground terminal VSS through a Tap unit to form the anode.

[0020] The present invention also provides a three-dimensional integrated circuit chip, including at least one of the aforementioned ESD protection structures, wherein the ESD protection structure is used to implement bidirectional discharge protection function of the input / output ports under electrostatic discharge events.

[0021] The present invention also provides a design and integration method for the aforementioned ESD protection structure, comprising the following steps:

[0022] Select the target standard cell from the standard cell library;

[0023] Reconstruct the PMOS and NMOS transistors in the standard cell by shorting their source, drain, and gate.

[0024] The standard unit is combined with the Tap unit to form a parasitic PN junction discharge path in the pull-up and pull-down directions;

[0025] Embed the ESD protection structure into the standard cell array region of the three-dimensional integrated circuit;

[0026] Adjust the size of the standard cell, the density of the Tap cell, and the layout parameters of the metal interconnect according to the target CDM discharge index;

[0027] The ESD protection structure is deployed in the near-end region of the core input / output interface to enable rapid discharge of electrostatic energy in the event of a CDM (Continuous Discharge Damage).

[0028] This invention proposes a three-dimensional integrated circuit ESD protection structure compatible with standard cells. The ESD protection structure is composed of modified standard cells, preferably inverter standard cells. Their original logic functions are shielded or abandoned, and instead, the parasitic PN junctions of their internal PMOS transistors and NMOS transistors are used to form a discharge path, thereby achieving rapid release of electrostatic energy.

[0029] The inverter includes a pair of PMOS transistors and an NMOS transistor. This invention reconfigures their connection to form parasitic diode paths in two directions. The pull-up path of this structure is formed by the original PMOS transistor, whose source, drain, and gate are shorted in the metal layer and connected to the I / O node to be protected, forming the anode of the P-type parasitic diode. It is connected to VDD using the N-type doped region of the Tap cell in the standard cell library, forming the cathode. The pull-down path is provided by the original NMOS transistor, whose source, drain, and gate are shorted and connected to the I / O node to be protected, forming the cathode of the N-type parasitic diode. It is connected to VSS using the P-type doped region of the Tap cell in the standard cell library, forming the anode.

[0030] The ESD protection structure of this invention can be directly arranged within the core area of ​​the functional circuit and integrated closely with the protected device, no longer limited by the design requirements of traditional ESD cells being arranged in the bonding pitch. Furthermore, the structure does not rely on additional dedicated ESD devices, utilizing only the parasitic PN junction of the MOS device in the standard cell to achieve CDM discharge function, exhibiting good process compatibility and saving additional layout area.

[0031] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages and technical effects: (1) The ESD protection structure is directly integrated into the functional circuit, without the need to reserve a dedicated ESD unit in the bonding pitch, which greatly improves the design flexibility and layout density; (2) The distance between the ESD protection structure and the functional device is short, which significantly reduces the series resistance of the discharge path and improves the ESD protection efficiency, and is suitable for instantaneous high current impact under the CDM model; (3) Based on the existing logic units such as inverters, structural modifications are made without introducing additional device types, which helps to achieve high-performance ESD protection design without changing the existing digital design process; (4) The parasitic PN junction structure in the original standard unit is used to realize the bidirectional discharge path, avoiding the introduction of additional devices or metal interconnects, which significantly saves chip area. Attached Figure Description

[0032] Figure 1 This is a schematic cross-sectional view of a three-dimensional integrated circuit packaging structure;

[0033] Figure 2A top view showing the layout of traditional ESD protection structures near the chip bonding locations in a three-dimensional integrated circuit.

[0034] Figure 3 A cross-sectional view of the layout near the chip bonding location of a traditional ESD protection structure in a three-dimensional integrated circuit.

[0035] Figure 4 This is a schematic diagram of a traditional pull-up / pull-down diode ESD protection structure.

[0036] Figure 5 This is a schematic diagram illustrating the principle of the electrostatic discharge path based on parasitic PN proposed in this invention.

[0037] Figure 6 This is a schematic diagram of the cross-section of a standard unit inverter structure;

[0038] Figure 7 This is a schematic diagram of the cross-sectional structure of the parasitic PN junction forming the discharge path in the modified standard cell of the present invention.

[0039] Figure 8 This is a schematic diagram illustrating the application of the structure of this invention in cross-voltage domain CDM ESD protection.

[0040] Figure 9 The layout structure for standard cell inverters and Tap cells;

[0041] Figure 10 This is a complete standard unit layout of the ESD protection structure of the present invention;

[0042] Figure 11 This is a simulated IV characteristic curve of the VSS to I / O direction according to an embodiment of the present invention;

[0043] Figure 12 This is a simulation IV characteristic curve of the I / O to VDD direction in an embodiment of the present invention. Detailed Implementation

[0044] The technical solution of the present invention will be further described below with reference to the accompanying drawings. It should be understood that the embodiments described herein are only for illustrating the technical principles of the present invention and do not constitute a limitation on the scope of the invention. Without departing from the essential spirit of the present invention, those skilled in the art can make various equivalent modifications or substitutions based on this, all of which should be considered to fall within the protection scope of the present invention.

[0045] Figure 1 This is a schematic cross-sectional view of a three-dimensional integrated circuit packaging structure, such as... Figure 1As shown, a three-dimensional integrated circuit (3D IC) packaging structure achieves system-level integration by vertically stacking multiple functional chips. This structure includes an upper chip 110, a lower chip 120, a printed circuit board or packaging substrate 130, multiple microbumps (μ-bumps) 140, and through-silicon vias (TSVs) 150. The upper chip 110 is electrically interconnected with the lower chip 120 through the microbumps 140. The lower chip 120 contains the through-silicon vias 150 for transmitting signals and power in the vertical direction, thereby achieving interlayer interconnection between multiple chips. The lower chip 120 is further connected to the substrate 130 by soldering or other methods to achieve system-level external interconnection. This packaging form achieves high-density integration within a limited planar area and is widely used in high-performance computing, artificial intelligence, and mobile terminals. However, during the bonding and packaging process, due to factors such as external electric field and triboelectric charging, static charge easily accumulates inside the bare chip (such as the upper chip 110 and the lower chip 120). Electrostatic discharge (ESD) may occur at the moment of contact, which causes transient stress on the interface circuit and becomes a key factor affecting chip yield and device reliability.

[0046] Traditional ESD protection strategies often involve placing a pair of pull-up and pull-down diodes near the interface to discharge charge during electrostatic discharge events. For example... Figure 2 As shown, the ESD protection area is marked 210, surrounded by multiple through-silicon vias (TSVs) 220, 230, and 240, with a silicon substrate 250 below. Figure 3 As shown, the ESD protection device region 210 is located between two through-silicon vias 220 and 230, corresponding to Figure 2 The silicon substrate 250 beneath the diodes supports the entire structure. In traditional designs, ESD protection devices are typically placed near I / O or TSV interconnect regions, connected to the power supply (VDD) via pull-up paths and to ground (VSS) via pull-down paths to achieve bidirectional discharge protection. While this traditional protection method provides a discharge path in the event of an electrostatic discharge (ESD) event, the available space for the protection structure is significantly limited in three-dimensional integrated circuits due to the continuously decreasing bond pitch. Diode size and design rules also limit their embedding in high-density interconnect regions, thus reducing layout flexibility.

[0047] Figure 4The schematic diagram of a traditional pull-up / pull-down diode ESD protection structure is shown. This structure can be applied to the signal interconnection path between the transmitter (TX) and receiver (RX), which are electrically connected via through-silicon vias (TSVs). At the nodes of this signal path, two independent PN junction diodes are connected in parallel, one end of which is connected to the power supply (VDD) and the other to the ground (VSS), respectively, to form a discharge path in the pull-up and pull-down directions during an electrostatic discharge event. When electrostatic charge accumulates and generates a transient high voltage at the node, the forward-biased diode conducts, discharging the charge to VDD or VSS respectively, thereby achieving bidirectional discharge protection. This traditional solution is simple in structure and easy to implement, but it occupies a large area, making it difficult to meet the design requirements of modern 3D integrated circuits under high integration and high bandwidth conditions.

[0048] To address the aforementioned issues, this invention proposes an area-friendly ESD protection structure compatible with standard cells. This structure eliminates the need for new device types; it reconstructs the internal electrical connections by adjusting the metal interconnection of the inverters in the standard cells. This causes the cells to lose their original logic functions, retaining only the parasitic PN junction characteristics of PMOS and NMOS devices for forming electrostatic paths.

[0049] like Figure 5 The diagram illustrates the principle of the electrostatic discharge path based on a parasitic PN junction proposed in this invention. The transmitter (TX) and receiver (RX) are interconnected via through-silicon vias (TSVs). At the RX node, the source, drain, and gate of the PMOS and NMOS devices are shorted and connected to the power supply (VDD) and ground (VSS) respectively via tap cells, thus forming parasitic PN junction discharge paths in the pull-up and pull-down directions. When an electrostatic discharge event occurs, the parasitic PN junction is forward-triggered and turned on, forming a highly efficient bidirectional ESD protection mechanism.

[0050] like Figure 6 As shown, the cross-sectional structure of a conventional inverter in the standard cell library consists of a pair of PMOS transistors and an NMOS transistor. The PMOS transistor is located in an N-well, with its source and drain being P+ diffusion regions; the NMOS transistor is located in a P-substrate, with its source and drain being N+ diffusion regions. The PMOS source is connected to the power supply terminal VDD, and the NMOS source is connected to the ground terminal VSS. The drains of both transistors are connected to the output terminal VOUT, and their gates are connected to the input terminal VIN, thus forming a standard inverting logic functional unit.

[0051] like Figure 7The diagram shows the cross-sectional structure of the inverter modified according to this invention. By shorting the source, drain, and gate terminals of the PMOS and NMOS transistors and connecting them to the input / output node (I / O), the original logic inversion function is masked, retaining only the parasitic PN junction characteristics within the device to form an electrostatic discharge path. Specifically, the P+ diffusion region of the PMOS transistor serves as the anode of the parasitic P-type diode, and the N-well is connected to the power supply terminal VDD via a tap unit, forming the cathode. Similarly, the N+ diffusion region of the NMOS transistor serves as the cathode of the parasitic N-type diode, and the P-substrate is connected to the ground terminal VSS via a tap unit, forming the anode.

[0052] The Tap cell is a standard cell from a standard cell library. It is a fixed-contact structure used to establish an ohmic contact connection between the well region or substrate and a stable potential terminal (VDD or VSS). Specifically, the Tap cell is connected to the power supply VDD through an N+ doped region to fix the N-well potential and act as the cathode of the parasitic P-type diode; it is also connected to the ground terminal VSS through a P+ doped region to fix the substrate potential and act as the anode of the parasitic N-type diode. In this invention, the Tap cell serves as the electrode terminal of the parasitic PN junction, thus forming a complete ESD discharge path.

[0053] Thus, a P-type parasitic diode conduction path is formed between the input / output node (I / O) and VDD, and an N-type parasitic diode conduction path is formed between the I / O node and VSS. Together, they form a symmetrical bidirectional electrostatic discharge path. When an electrostatic discharge event occurs, the corresponding parasitic PN junction is forward-triggered and conducts, thereby rapidly discharging the charge to VDD or VSS, achieving bidirectional ESD protection.

[0054] The ESD protection structure of this invention can be directly embedded in the standard cell array region of a three-dimensional integrated circuit (3D IC), maintaining compatibility with other functional units in the circuit. The protection structure utilizes the parasitic PN structure of at least one pair of PMOS and NMOS transistors in the standard cell to construct a discharge path, including:

[0055] (1) Parasitic PN junction discharge path in the pull-up direction: The source, drain and gate of the PMOS transistor are shorted and connected to the input / output node to form the anode of the parasitic P-type diode; the N-type doped region of the Tap cell in the standard cell library is connected to VDD to form the cathode, thereby establishing the pull-up discharge path from I / O to VDD;

[0056] (2) Parasitic PN junction discharge path in the pull-down direction: The source, drain and gate of the NMOS transistor are shorted and connected to the input / output node to form the cathode of the parasitic N-type diode; the P-type doped region of the Tap cell in the standard cell library is connected to VSS to form the anode, thereby establishing the pull-down discharge path from VSS to I / O.

[0057] The reconstructed standard cell loses its original logical function, retaining only the parasitic PN junction structure to provide an electrostatic discharge path. The Tap cell is derived from the standard cell library and maintains compatibility and consistency with the inverter cell in terms of layout size and process parameters, ensuring the reusability of this structure in design migration and process integration.

[0058] During the bonding process of 3D integrated circuit (3D IC) chips, the unequal potentials of different chips may lead to electrostatic discharge (ESD) risks similar to CDM in cross-voltage domain scenarios, causing irreversible damage to the thin gate oxide layer or input circuit at the receiving end. To address this, the ESD protection structure proposed in this invention can be deployed in the near-end region of the input end of the receiving domain (RX Domain) to achieve rapid discharge of electrostatic charge during CDM discharge events, thereby suppressing transient impacts on the circuit caused by high voltage and high current.

[0059] like Figure 8 As shown, the transmitting domain 710 and the receiving domain 730 correspond to different voltage domains in the three-dimensional integrated circuit system, with their power supply terminals being VDD_TX / VSS_TX and VDD_RX / VSS_RX, respectively. The transmitting circuit 712 outputs a signal, which is transmitted to the input terminal of the receiving circuit 732 via interconnects, realizing cross-chip signal communication. To prevent the risk of discharge across voltage domains, this invention introduces an ESD protection structure 720 in the receiving domain 730.

[0060] The ESD protection structure 720 is a symmetrical pull-up and pull-down discharge structure based on a parasitic PN junction, internally composed of a modified standard cell inverter. The source, drain, and gate of the PMOS and NMOS transistors in this inverter are shorted and connected to the input / output node (I / O), and simultaneously connected to the power supply terminal VDD_RX and the ground terminal VSS_RX via tap cells. Thus, a P-type parasitic diode conduction path is formed between the I / O node and VDD_RX, and an N-type parasitic diode conduction path is formed between the I / O node and VSS_RX, together forming a symmetrical bidirectional ESD discharge path.

[0061] When an ESD event conforming to the CDM model occurs, if the instantaneous potential of the input node is higher than the power supply terminal, the P-type parasitic diode is forward-triggered and conducts, discharging the charge along the I / O to VDD_RX path; conversely, if the input node potential is lower than the ground terminal, the N-type parasitic diode conducts, discharging the charge along the VSS_RX to I / O path. This bidirectional symmetrical structure enables the shunting and clamping of transient charges on a nanosecond timescale, effectively reducing the electrical stress caused by cross-voltage domain discharge.

[0062] Furthermore, the transmit domain 710 and the receive domain 730 respectively correspond to Figure 1 The upper core 110 and lower core 120 shown, the ESD protection structure 720 corresponds to Figure 4 and Figure 6 The diagram shows a discharge unit based on a parasitic PN junction. By embedding this structure at the receiving end, cross-chip discharge can be suppressed without increasing the additional layout area, significantly improving the ESD robustness and chip bonding yield of the 3D integrated circuit system.

[0063] like Figure 9 This is a schematic diagram of the layout structure of a standard cell inverter and a tap cell, as shown below. Figure 10 This is a complete standard cell layout of the ESD protection structure reconstructed by metal interconnects according to the present invention. Inverter cell 820 and Tap cell 810 are both derived from the standard cell library, and their geometric boundaries and process layers remain unchanged. The layers in the figure are defined as follows:

[0064] M1 represents the first metal interconnect layer, used for power rails, signal lines, and inter-cell interconnection;

[0065] SP stands for P+ source / drain injection layer (P+ S / D Implant).

[0066] SN stands for N+ source / drain injection layer (N+ S / D Implant);

[0067] AA stands for Active Area, which defines the source / drain diffusion region of the device;

[0068] GT stands for Poly Gate.

[0069] NW stands for N-well, which provides the body region for PMOS transistors and isolates the substrate.

[0070] exist Figure 9In the inverter unit 820, there are PMOS located in NW and NMOS located in P substrate; its source / drain regions are injected by SP / SN and fall in AA, respectively, and polysilicon GT forms the gate; each source, drain and gate is connected to M1 through via (not separately marked in the figure); the tap unit 810 consists of NW Tap (connected to VDD) and P-sub Tap (connected to VSS), which are injected in AA through N+ / P+ to form ohmic contacts and fix the well / substrate potential.

[0071] like Figure 10 As shown, this invention, while maintaining cell layout compatibility, reconfigures the interconnects at the metal level. This shorts the source, drain, and gate terminals of the PMOS and NMOS transistors inside the inverter on M1 and unifies them to the input / output (I / O) node. This causes the inverter cell to lose its logic function, retaining only its parasitic PN junction characteristics. The two tap cells on either side are connected to the VDD and VSS power rails via M1, respectively, forming a pull-up parasitic diode path from I / O to VDD and a pull-down parasitic diode path from VSS to I / O. This establishes a symmetrical bidirectional ESD discharge path.

[0072] When an ESD event occurs, if the I / O potential is higher than VDD, the parasitic P-type diode formed by the PMOS body region and P+ diffusion (NW and SP / AA) is forward-biased, and the charge is discharged along I / O→VDD; conversely, when the I / O potential is lower than VSS, the parasitic N-type diode formed by the NMOS body region and N+ diffusion (P-sub and SN / AA) is forward-biased, and the charge is discharged along VSS→I / O, thereby achieving bidirectional rapid current shunting and clamping.

[0073] In terms of layout, the ESD protection structure can be embedded within a standard cell array of the functional circuit area. Tap cells 810 can be repeatedly arranged at array boundaries or periodic positions as needed to ensure potential uniformity between the well region and the substrate and improve the continuity of the ESD discharge path. When the structure contains multiple pairs of tap cells, the VDD / VSS terminals of each tap cell and the adjacent modified standard cell (i.e., the reconstructed ESD protection structure of the inverter cell 820) are interconnected via M1 to form a continuous power rail, thereby providing a low-resistance charge discharge path during discharge. To adapt to different ESD protection levels, designers can reduce the equivalent series resistance and inductance by adjusting cell size, increasing tap cell density, optimizing M1 linewidth and via count, etc., to achieve the required discharge capability.

[0074] Furthermore, Figure 11 and Figure 12Simulated I-V curves for both VSS to I / O and I / O to VDD directions of a specific embodiment of the present invention are presented. Simulation results show that the structure of the present invention begins to conduct at approximately 0.9V, exhibiting an I-V characteristic curve similar to that of a conventional pull-up / pull-down diode, verifying that the parasitic PN structure possesses effective discharge capability during electrostatic discharge (ESD) events. These results further demonstrate that the proposed structure can form a stable ESD discharge path in 3D IC scenarios, thereby meeting the system's ESD protection requirements.

[0075] The present invention discloses a three-dimensional integrated circuit chip, including at least one of the aforementioned ESD protection structures, for implementing bidirectional discharge protection function of input / output ports under CDM events.

[0076] This invention offers excellent scalability. Depending on different CDM protection specifications, designers can select different sizes of inverters and tap cells to adjust the on-resistance and parasitic capacitance of the discharge path, thereby adjusting its ESD protection capability. Furthermore, the structure of this invention can be fully embedded in a standard cell array within a functional circuit, with its layout area absorbed by the functional cells, unrestricted by external layout space. This provides a solution to the problem of traditional ESD structures being unable to be deployed due to reduced bond pitch.

[0077] The present invention also provides a design and integration method for the aforementioned ESD protection structure, comprising the following steps:

[0078] Select the target standard cell from the standard cell library;

[0079] Reconstruct the PMOS and NMOS transistors in the standard cell by shorting their source, drain, and gate.

[0080] The standard unit is combined with the Tap unit to form a parasitic PN junction discharge path in the pull-up and pull-down directions;

[0081] Embed the ESD protection structure into the standard cell array region of the three-dimensional integrated circuit;

[0082] Adjust the size of the standard cell, the density of the Tap cell, and the layout parameters of the metal interconnect according to the target CDM discharge index;

[0083] The ESD protection structure is deployed in the near-end region of the core input / output interface to enable rapid discharge of electrostatic energy in the event of a CDM (Continuous Discharge Damage).

[0084] In summary, this invention provides an area-friendly CDM ESD protection structure based on a standard cell library, suitable for 3D integrated circuit structures. This structure is built upon a standard cell library, utilizing the parasitic PN junction characteristics of the inverter PMOS and NMOS devices within the library. Without introducing new devices or modifying the process flow, it forms an electrostatic discharge path with the help of Tap cells, achieving efficient ESD protection. The proposed structure has the capability to fully embed functional circuit layouts, with its layout area absorbed by the functional cells, significantly alleviating the ESD structure area limitation problem caused by the miniaturization of bonding pitch. This solution is particularly suitable for protecting against CDM discharge risks during the bonding process of different chips in 3D integrated circuits. It possesses advantages such as simple structure, compact layout, strong process compatibility, fast trigger response, and strong design mobility. It is adaptable to various advanced process nodes and high-density interconnect chip scenarios, significantly reducing the risk of chip electrostatic failure and providing an effective solution for improving 3D IC bonding yield and system ESD robustness. It is particularly suitable for chip systems that place extremely high demands on the reliability and integration density of 3D ICs, such as artificial intelligence, data centers, and high-speed communications, providing a feasible ESD protection solution for future high-density, high-bandwidth interconnection between chips.

Claims

1. An ESD protection structure for a three-dimensional integrated circuit, characterized in that, The ESD protection structure includes at least one pair of PMOS and NMOS transistors derived from standard cells in a standard cell library. The parasitic PN junction structure of the PMOS and NMOS transistors is used to construct the discharge path and is integrated into the three-dimensional integrated circuit, including: The parasitic PN junction discharge path in the pull-up direction: The source, drain and gate of the PMOS transistor are shorted and connected to the input / output port to form the anode of the P-type parasitic diode. Its cathode is connected to VDD through the N-type doped region of the Tap cell in the standard cell library, thereby forming the pull-up discharge path from I / O to VDD. The parasitic PN junction discharge path in the pull-down direction: The source, drain and gate of the NMOS transistor are shorted and connected to the input / output port to form the cathode of the N-type parasitic diode. Its anode is connected to VSS through the P-type doped region of the Tap cell in the standard cell library, thereby forming a pull-down discharge path from VSS to I / O. The standard unit loses its original logical function after structural reconstruction, and only retains the parasitic PN junction to provide a discharge path in electrostatic discharge events.

2. The ESD protection structure for a three-dimensional integrated circuit according to claim 1, characterized in that, The standard cell is an inverter from the standard cell library, and the PMOS transistors and NMOS transistors of the inverter are arranged symmetrically in the layout structure.

3. The ESD protection structure for a three-dimensional integrated circuit according to claim 1, characterized in that, The Tap cell is a cell in the standard cell library, and its layout size and process parameters are compatible and consistent with the standard cell.

4. The ESD protection structure for a three-dimensional integrated circuit according to claim 1, characterized in that, The ESD protection structure can be directly integrated into a standard cell array in the functional circuit area.

5. The ESD protection structure for a three-dimensional integrated circuit according to claim 1, characterized in that, The ESD protection structure is used to implement electrostatic discharge protection at signal interfaces in different power supply voltage domains.

6. The ESD protection structure for a three-dimensional integrated circuit according to claim 1, characterized in that, The ESD protection structure is deployed in the near-end region of the chip input / output port to rapidly discharge electrostatic energy in the event of a CDM event through the ESD discharge path.

7. The ESD protection structure for a three-dimensional integrated circuit according to claim 1, characterized in that, The discharge capability of the ESD protection structure can be adjusted in the following ways to meet the requirements of different CDM discharge indicators: (1) Select standard units of different sizes and driving capabilities; (2) Multiple pairs of Tap cells are used and arranged laterally on both sides of the standard cell, and are respectively connected to the parasitic PN junction electrode of the PMOS or NMOS transistor to form a parallel discharge path. (3) Optimize the metal interconnect layout inside the ESD protection structure, including the metal traces between the input / output electrodes and the standard cell and the two side Tap cells. The optimization method includes adjusting the trace width, metal layers and the number and distribution of vias.

8. The ESD protection structure for a three-dimensional integrated circuit according to claim 1, characterized in that, The P+ diffusion region of the PMOS transistor serves as the anode of the parasitic P-type diode, and the N-well is connected to the power supply terminal VDD through a Tap unit to form the cathode; the N+ diffusion region of the NMOS transistor serves as the cathode of the parasitic N-type diode, and the P substrate is connected to the ground terminal VSS through a Tap unit to form the anode.

9. A three-dimensional integrated circuit chip, characterized in that, Includes at least one ESD protection structure as described in any one of claims 1 to 8, the ESD protection structure being used to implement bidirectional discharge protection function for input / output ports under electrostatic discharge events.

10. A design and integration method for an ESD protection structure according to any one of claims 1 to 8, characterized in that, Includes the following steps: Select the target standard cell from the standard cell library; Reconstruct the PMOS and NMOS transistors in the standard cell by shorting their source, drain, and gate. The standard unit is combined with the Tap unit to form a parasitic PN junction discharge path in the pull-up and pull-down directions; Embed the ESD protection structure into the standard cell array region of the three-dimensional integrated circuit; Adjust the size of the standard cell, the density of the Tap cell, and the layout parameters of the metal interconnect according to the target CDM discharge index; The ESD protection structure is deployed in the near-end region of the core input / output interface to enable rapid discharge of electrostatic energy in the event of a CDM (Continuous Discharge Damage).

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