Back contact cell and preparation method thereof, back contact laminated cell and photovoltaic module

Abstract

The invention relates to the technical field of photovoltaics, in particular to a back contact cell, a preparation method, a back contact laminated cell and a photovoltaic module. The preparation method comprises the following steps: firstly, depositing a tunneling oxide layer and an N-type doped layer on a first surface of a substrate, and detecting the contact resistance Rc1 of the deposited N-type doped layer; depositing a first mask layer, an intrinsic hydrogenated amorphous silicon layer and a P-type hydrogenated amorphous silicon layer on the first surface; then performing graphical processing, alkali etching and acid pickling on the first surface to remove the first mask layer, the intrinsic hydrogenated amorphous silicon layer and the P-type hydrogenated amorphous silicon layer on the N-type doped layer, and detecting the contact resistance Rc2 of the acid-pickled N-type doped layer; wherein Rc1 and Rc2 meet the condition that Rc2-Rc1 is larger than or equal to 0 omega and smaller than or equal to 30 omega, through protection of the first mask layer on the N-type doped layer, the surface characteristics of the deposited N-type doped layer and the surface characteristics of the acid-washed N-type doped layer are small in difference and even identical, series resistance can be reduced, filling factors can be improved, and therefore the finally-formed back contact battery has good photoelectric conversion efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic, in particular to a back contact cell, a preparation method thereof, a back contact stacked cell and a photovoltaic module. BACKGROUND

[0002] The back contact cell is one of the important development directions of high-performance cells, because the positive and negative electrodes are both placed on the back surface of the cell, eliminating the grid line shielding of the front surface of the cell, thereby significantly improving the utilization rate of incident light.

[0003] In the preparation process of the back contact cell, laser film opening is usually performed on the back surface of the cell to form a local contact area, so as to realize the ohmic contact between the electrode and the silicon substrate. When the laser acts on the passivation layer on the back surface of the cell, high temperature will cause part of the silicon material to melt instantaneously. If these molten silicon materials cannot be completely removed after the laser action ends, they will recondense and remain in the film opening area on the back surface of the cell, thereby affecting the ohmic contact effect between the electrode and the silicon substrate, and finally leading to the reduction of the electrical performance of the back contact cell. SUMMARY

[0004] Therefore, the present application provides a back contact cell, a preparation method thereof, a back contact stacked cell and a photovoltaic module, to solve the technical problem that the laser processing residues affect the ohmic contact in the prior art, leading to the reduction of the electrical performance of the back contact cell.

[0005] The present application provides a preparation method of a back contact cell, which comprises: providing a substrate having a first surface and a second surface oppositely arranged along a first direction, the first surface comprising an electron collection zone and a hole collection zone; sequentially depositing a tunneling oxide layer and an N-type doped layer on the first surface, the contact resistance of the N-type doped layer after deposition being Rc1; sequentially depositing a first mask layer, an intrinsic hydrogenated amorphous silicon layer and a P-type hydrogenated amorphous silicon layer on the first surface; and sequentially performing patterning treatment, alkali etching and acid washing on the electron collection zone to remove the first mask layer, the intrinsic hydrogenated amorphous silicon layer and the P-type hydrogenated amorphous silicon layer located on the N-type doped layer, the contact resistance of the N-type doped layer after acid washing being Rc2.

[0006] wherein Rc1 and Rc2 satisfy 0Ω≤Rc2-Rc1≤30Ω.

[0007] The beneficial effects of the embodiment are that, by protecting the N-type doped layer through the first mask layer, the surface characteristics of the N-type doped layer after acid washing are less different from, or even the same as, the surface characteristics of the N-type doped layer after deposition, which is conducive to reducing the series resistance and improving the fill factor, and thus the finally formed back contact cell has good photoelectric conversion efficiency. Moreover, the first mask layer can also reduce the possibility of light spots appearing on the surface of the N-type doped layer after the patterning process, which is not only conducive to ensuring the integrity of chemical passivation and field effect passivation to reduce the recombination rate of carriers in the electron collection region, thereby improving the open circuit voltage and optimizing the conversion efficiency, but also conducive to improving the uniformity of the reflection of long-wave photons in the back surface, thereby increasing the probability of secondary absorption of unabsorbed photons by the substrate, thereby reducing parasitic absorption and improving the short-circuit current.

[0008] In a possible implementation, after the step of sequentially depositing the first mask layer, the intrinsic hydrogenated amorphous silicon layer and the P-type hydrogenated amorphous silicon layer on the first surface, the preparation method further includes: depositing a second mask layer on the first surface.

[0009] In a possible implementation, in the first direction, the thickness of the first mask layer is H1, the thickness of the second mask layer is H2, and H1 and H2 satisfy H1≥H2, H1 further satisfies 50nm≤H1≤200nm, and H2 further satisfies 30nm≤H2≤50nm.

[0010] In a possible implementation, the material of the first mask layer and the second mask layer is silicon oxide, silicon nitride or silicon oxynitride.

[0011] In a possible implementation, the step of sequentially performing patterning, alkali etching and acid washing on the electron collection region to remove the first mask layer, the intrinsic hydrogenated amorphous silicon layer and the P-type hydrogenated amorphous silicon layer located on the N-type doped layer includes: performing patterning on the electron collection region by using a laser to remove the intrinsic hydrogenated amorphous silicon layer, the P-type hydrogenated amorphous silicon layer and the second mask layer located on the first mask layer.

[0012] performing alkali etching on the first surface by using an alkaline solution to clean the residues in the electron collection region located on the first mask layer.

[0013] performing acid washing on the first surface by using an acidic solution to remove the first mask layer in the electron collection region located on the N-type doped layer, and to remove the second mask layer in the hole collection region located on the P-type hydrogenated amorphous silicon layer.

[0014] In a possible implementation, the step of sequentially depositing the first mask layer, the intrinsic hydrogenated amorphous silicon layer and the P-type hydrogenated amorphous silicon layer on the first surface includes: depositing the first mask layer on the first surface.

[0015] The hole collection region is patterned by laser to remove the tunneling oxide layer, the N-type doped layer and the first mask layer on the substrate in the hole collection region.

[0016] The hole collection region is textured to form a textured structure, and the hole collection region is cleaned to remove the film layers on the substrate in the hole collection region.

[0017] An intrinsic hydrogenated amorphous silicon layer and a P-type hydrogenated amorphous silicon layer are sequentially deposited on the first surface.

[0018] In a possible implementation, after the step of patterning the hole collection region by laser to remove the tunneling oxide layer, the N-type doped layer and the first mask layer on the substrate in the hole collection region, the preparation method further comprises: The second surface is cleaned to remove the phosphosilicate glass and the N-type doped layer on the substrate.

[0019] The second surface and the hole collection region are simultaneously textured to form a textured structure on the corresponding surface of the substrate.

[0020] At least one passivation layer and at least one anti-reflection layer are sequentially deposited on the second surface.

[0021] The hole collection region is cleaned to remove the passivation layer and the anti-reflection layer on the substrate in the hole collection region.

[0022] An intrinsic hydrogenated amorphous silicon layer and a P-type hydrogenated amorphous silicon layer are sequentially deposited on the first surface.

[0023] In a possible implementation, after the step of sequentially patterning, alkali etching and acid washing the electron collection region to remove the first mask layer, the intrinsic hydrogenated amorphous silicon layer and the P-type hydrogenated amorphous silicon layer on the N-type doped layer, the preparation method further comprises: A transparent conductive layer is deposited on the first surface.

[0024] The transparent conductive layer is patterned or etched to form an isolation region between the electron collection region and the hole collection region.

[0025] A first electrode is printed on the electron collection region, and the first electrode is electrically connected to the N-type doped layer through the transparent conductive layer.

[0026] A second electrode is printed on the hole collection region, and the second electrode is electrically connected to the P-type hydrogenated amorphous silicon layer through the transparent conductive layer.

[0027] The application further provides a back contact cell made by any of the above preparation methods, the back contact cell comprising a substrate, a tunneling oxide layer, an N-type doped layer, an intrinsic hydrogenated amorphous silicon layer and a P-type hydrogenated amorphous silicon layer, a first surface of the substrate comprising an electron collection region and a hole collection region, the tunneling oxide layer and the N-type doped layer being sequentially stacked in the electron collection region, and the intrinsic hydrogenated amorphous silicon layer and the P-type hydrogenated amorphous silicon layer being sequentially stacked in the hole collection region.

[0028] wherein the series resistance of the back contact cell is Rs, and Rs satisfies 0.0006Ω≤Rs≤0.0014Ω.

[0029] The beneficial effects of the embodiment are that the tunneling oxide layer and the N-type doped layer can form a passivation contact structure of the electron collection region for collecting electrons, and the intrinsic hydrogenated amorphous silicon layer and the P-type hydrogenated amorphous silicon layer can form a passivation contact structure of the hole collection region for collecting holes, so that the design not only eliminates the shading area of the grid lines on the front surface of the cell to maximize the absorption of incident light, but also combines the characteristics of the tunneling passivation contact cell and the heterojunction cell on the back surface of the cell to improve the overall working performance of the back contact cell.

[0030] In addition, the N-type doped layer and the P-type hydrogenated amorphous silicon layer are protected by the mask layer during the preparation process, so that the surface characteristics of the N-type doped layer after acid washing are similar to or even the same as the surface characteristics of the N-type doped layer after deposition, and the surface characteristics of the P-type hydrogenated amorphous silicon layer after acid washing are similar to or even the same as the surface characteristics of the P-type hydrogenated amorphous silicon layer after deposition, so that the design is also conducive to improving the structural integrity of the N-type doped layer and the P-type hydrogenated amorphous silicon layer, so that both have initial electrical properties, which is conducive to reducing the series resistance of the finally formed back contact cell, and thus the back contact cell has good photoelectric conversion efficiency.

[0031] The application further provides a back contact stacked cell, the back contact stacked cell comprising a back contact bottom cell and a perovskite top cell, the perovskite top cell being electrically connected to the front surface of the back contact bottom cell, and the back contact bottom cell being the back contact cell described above.

[0032] The beneficial effect of the embodiment is that when the perovskite top cell and the back contact bottom cell are electrically connected on the front surface to form a back contact stacked cell, the solar spectrum can be used in different wave bands to improve the overall photoelectric conversion efficiency, that is, the perovskite top cell can absorb high-energy short-wavelength photons with a wide band gap to reduce light loss and improve open-circuit voltage, and the back contact bottom cell can absorb low-energy long-wavelength photons with a narrow band gap to reduce light-heat loss and improve current density, and the back contact bottom cell has a series resistance of the substrate, so that the photoelectric conversion efficiency of the back contact stacked cell can be improved through the synergistic effect of the perovskite top cell and the back contact bottom cell, and the back contact stacked cell has stable output effect under high current load, which is beneficial to improve the stability and reliability of the back contact stacked cell in the working process.

[0033] The application also provides a photovoltaic module, which comprises a cover plate, an encapsulation layer and at least one cell string, the cover plate is connected with the cell string through the encapsulation layer, and the cell string comprises a plurality of back contact cells or a plurality of back contact stacked cells as described above.

[0034] The beneficial effect of the embodiment is that the photovoltaic module using the back contact cell or the back contact stacked cell with extremely low series resistance can maximize the use of incident light to improve the photoelectric conversion efficiency, and can use a wider and thicker metal electrode on the back surface of the cell sheet layer, and further reduce the series resistance and improve the fill factor by optimizing the electrode layout and interconnection mode, thereby facilitating the improvement of the electrical performance of the photovoltaic module and improving the safety and reliability of the photovoltaic module in the working process.

[0035] It should be understood that the foregoing general description and the following detailed description are only exemplary and do not limit the application. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0037] Figure 1 is a partial sectional view of the substrate in one embodiment of the preparation method provided by the application; Figure 2 is a partial sectional view after forming a tunneling oxide layer, an N-type doped layer and a first mask layer in the preparation method provided by the application; Figure 3 is a partial sectional view after the first patterning treatment in the preparation method provided by the application; Figure 4Figure 1 is a partial cross-sectional view of a substrate after forming a passivation layer and an anti-reflective layer in the method of making provided herein; Figure 5 Figure 2 is a partial cross-sectional view of the substrate after forming an intrinsic hydrogenated amorphous silicon layer and a P-type hydrogenated amorphous silicon layer in the method of making provided herein; Figure 6 Figure 3 is a partial cross-sectional view of the substrate after forming a second masking layer in the method of making provided herein; Figure 7 Figure 4 is a partial cross-sectional view of the substrate after a second patterning process and alkali etching in the method of making provided herein; Figure 8 Figure 5 is a partial cross-sectional view of the substrate after acid washing in the method of making provided herein; Figure 9 Figure 6 is a partial cross-sectional view of the substrate after forming a transparent conductive layer in the method of making provided herein; Figure 10 Figure 7 is a partial cross-sectional view of a back contact cell in one embodiment of the method of making provided herein; Figure 11 Figure 8 is a schematic diagram of a structure of an N-type doped layer after a patterning process in the prior art; Figure 12 Figure 9 is a schematic diagram of a structure of an N-type doped layer after a patterning process in the method of making provided herein.

[0038] Legend of reference numerals: 1 - substrate; 11 - first surface; 111 - electron collection region; 112 - hole collection region; 113 - isolation region; 12 - second surface; 2 - tunneling oxide layer; 3 - N-type doped layer; 31 - light spot; 4 - intrinsic hydrogenated amorphous silicon layer; 5 - P-type hydrogenated amorphous silicon layer; 6 - transparent conductive layer; 7 - passivation layer; 8 - anti-reflective layer; 9 - electrode; 91 - first electrode; 92 - second electrode; 10 - masking layer; 101 - first masking layer; 102 - second masking layer.

[0039] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application. DETAILED DESCRIPTION

[0040] For a better understanding of the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the drawings.

[0041] It should be clear that the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0042] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0043] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0044] The embodiments of the present application provide a preparation method of a back contact battery, as shown in Figures 1-10 The preparation method comprises the following steps: A substrate 1 is provided, the substrate 1 has a first surface 11 and a second surface 12 oppositely arranged along a first direction x, and the first surface 11 comprises an electron collection region 111 and a hole collection region 112.

[0045] A tunneling oxide layer 2 and an N-type doped layer 3 are sequentially deposited on the first surface 11, and the contact resistance of the N-type doped layer 3 after deposition is Rc1.

[0046] A first mask layer 101, an intrinsic hydrogenated amorphous silicon layer 4 and a P-type hydrogenated amorphous silicon layer 5 are sequentially deposited on the first surface 11.

[0047] The electron collection region 111 is sequentially subjected to a patterning process, alkali etching and acid washing, so as to remove the first mask layer 101, the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5 located on the N-type doped layer 3, and the contact resistance of the N-type doped layer 3 after acid washing is Rc2.

[0048] The contact resistance Rc1 of the N-type doped layer 3 after deposition and the contact resistance Rc2 of the N-type doped layer 3 after pickling satisfy 0Ω≤Rc2-Rc1≤30Ω.

[0049] It should be noted that the substrate 1 can be doped with N-type elements, such as one or a combination of pentavalent elements such as phosphorus elements, arsenic elements, or antimony elements, and the substrate 1 can also be doped with P-type elements, such as one or a combination of trivalent elements such as boron elements, indium elements, or gallium elements. In the embodiments of the present application, the substrate 1 doped with N-type elements will be described. At the same time, the thickness direction of the back contact cell is defined as the first direction x, and the width direction of the back contact cell is defined as the second direction y, that is, the first direction x and the second direction y intersect and are perpendicular, the first surface 11 of the substrate 1 is defined as the back light surface of the back contact cell, and the second surface 12 of the substrate 1 is defined as the light receiving surface of the back contact cell, that is, the first surface 11 is not directly irradiated by sunlight, and the second surface 12 can be directly irradiated by sunlight.

[0050] In the embodiments of the present application, first, as shown in Figure 1 The provided substrate 1 can be subjected to polishing treatment, so that the topography of the first surface 11 and the second surface 12 is flat and smooth, which provides good working conditions for subsequent deposition process and patterning process, so as to form a film layer with high density and low defects and clear electronic collection area 111 and hole collection area 112 on the surface of the substrate 1, thereby facilitating to improve the passivation quality and electrical performance, and further improving the production yield of the back contact cell.

[0051] Among them, the electronic collection area 111 and the hole collection area 112 are arranged alternately along the second direction y.

[0052] Secondly, as shown in Figure 2 The tunneling oxide layer 2 and the N-type doped layer 3 are sequentially deposited on the first surface 11 of the substrate 1, at this time, the projections of the tunneling oxide layer 2 and the N-type doped layer 3 along the first direction x both cover the electronic collection area 111 and the hole collection area 112, and the contact resistance of the N-type doped layer 3 after deposition is Rc1.

[0053] Among them, the tunneling oxide layer 2 can suspend the dangling bond and form chemical passivation to reduce the recombination of electrons and holes, the N-type doped layer 3 can generate internal electric field and form field effect passivation to transport electrons and block holes, and through the synergistic effect of the two, a high-quality passivation effect can be formed, which is conducive to improving the open-circuit voltage and fill factor of the back contact cell. At the same time, after the deposition of the N-type doped layer 3 is completed, the contact resistance of the N-type doped layer 3 at this time is measured and recorded as Rc1, so as to be compared subsequently.

[0054] Then as shown in Figure 5As shown, a first mask layer 101, an intrinsic hydrogenated amorphous silicon layer 4, and a P-type hydrogenated amorphous silicon layer 5 are sequentially deposited on the first surface 11 of the substrate 1. At this time, the projections of the first mask layer 101, the intrinsic hydrogenated amorphous silicon layer 4, and the P-type hydrogenated amorphous silicon layer 5 along the first direction x all cover the electron collection region 111.

[0055] The first mask layer 101 can be an oxide layer, used to protect the N-type doped layer 3, so as to reduce the impact of the N-type doped layer 3 on the subsequent patterning process and improve the integrity of the N-type doped layer 3. The intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5 are mainly used to form a passivation contact structure in the hole collection region 112, so as to improve the passivation quality and electrical performance in the hole collection region 112.

[0056] Then as Figure 7 and Figure 8 As shown, the electron collection region 111 is sequentially patterned, etched with alkali, and acid-washed to remove the first mask layer 101, the intrinsic hydrogenated amorphous silicon layer 4, and the P-type hydrogenated amorphous silicon layer 5 covering the N-type doped layer 3. At this time, along the first direction x, the electron collection region 111 of the first surface 11 only includes the tunneling oxide layer 2 and the N-type doped layer 3, and the contact resistance of the acid-washed N-type doped layer 3 is Rc2.

[0057] Specifically, a laser can be used to pattern part or all of the electron collection region 111 to remove part or all of the P-type hydrogenated amorphous silicon layer 5 and the intrinsic hydrogenated amorphous silicon layer 4, providing working conditions for the subsequent reduction of the N-type doped layer 3 surface and the realization of ohmic contact. Furthermore, during the patterning process, laser parameters (such as power and scanning speed) can be adjusted so that the first mask layer 101 can act as an energy absorption layer, preventing laser energy from damaging the N-type doped layer 3 located beneath it. This helps to ensure the structural integrity and initial electrical properties of the N-type doped layer 3 (such as the contact resistance Rc1 of the deposited N-type doped layer 3).

[0058] After the patterning process is completed, the high temperature of the laser will not only vaporize the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5, but also produce a small amount of residue (i.e., molten silicon). The residue and the unvaporized intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5 can be completely removed by alkaline etching, so as to clean the surface of the first mask layer 101 and avoid the risk of poor ohmic contact caused by residues adhering to the surface of the subsequent N-type doped layer 3. This is beneficial to ensuring the electrical performance of the electron collection region 111.

[0059] After the alkali etching is completed, the first mask layer 101 can be removed by acid washing due to the low etching rate of the alkaline solution on the first mask layer 101, and at the same time, the etching residues, metal contaminants, and surface oxides and other impurities are cleaned away, and finally the clean N-type doped layer 3 surface is reduced, so as to increase the effective contact area of the subsequent ohmic contact, thereby reducing the contact resistance, improving the fill factor, and further optimizing the electrical performance of the electron collection area 111.

[0060] After the acid washing is completed, the contact resistance of the N-type doped layer 3 at this time is measured and recorded as Rc2, and compared with the previously measured Rc1, it is concluded that Rc1 and Rc2 satisfy 0Ω≤Rc2-Rc1≤30Ω, so that the contact resistance of the N-type doped layer 3 after acid washing and the contact resistance of the N-type doped layer 3 after deposition are relatively small or even equal, which guarantees the initial electrical performance of the N-type doped layer 3 to change as little as possible or remain unchanged, which is beneficial to reduce the series resistance of the electron collection area 111, thereby improving the fill factor and photoelectric conversion efficiency of the back contact cell.

[0061] Optionally, Rc2-Rc1 can be 0Ω, 1Ω, 2Ω, 3Ω, 4Ω, 5Ω, 6Ω, 7Ω, 8Ω, 9Ω, 10Ω, 11Ω, 12Ω, 13Ω, 14Ω, 15Ω, 16Ω, 17Ω, 18Ω, 19Ω, 20Ω, 21Ω, 22Ω, 23Ω, 24Ω, 25Ω, 26Ω, 27Ω, 28Ω, 29Ω, 30Ω, etc.

[0062] At the same time, as shown in Figure 11 and Figure 12 , the first mask layer 101 can also reduce the possibility of light spots 31 appearing on the surface of the N-type doped layer 3 after the patterning process, which not only helps to ensure the integrity of chemical passivation and field effect passivation to reduce the recombination rate of carriers in the electron collection area 111, thereby improving the open-circuit voltage and optimizing the conversion efficiency, but also helps to improve the uniformity of long-wave photon reflection in the backplane, thereby increasing the probability of secondary absorption of unabsorbed photons by the substrate 1, thereby reducing parasitic absorption and improving short-circuit current.

[0063] Therefore, in the process of preparing the back contact cell, the preparation method of the embodiment first deposits the first mask layer 101 on the substrate 1, so that it can cover the side of the N-type doped layer 3 away from the substrate 1 to provide protection, thereby reducing or avoiding damage to the N-type doped layer 3 in the subsequent patterning process; after the patterning process is completed, the residues generated in the patterning process (such as molten silicon generated by the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5) are removed by alkali etching, thereby avoiding the risk that the residues affect the subsequent ohmic contact and cause excessive contact resistance; after the alkali etching is completed, the first mask layer 101 previously covering the N-type doped layer 3 is removed by acid washing to restore the surface of the N-type doped layer 3 previously deposited, thereby expanding the effective contact area of the N-type doped layer 3 and creating conditions for subsequent good ohmic contact. And because of the protection of the first mask layer 101 to the N-type doped layer 3, the surface characteristics of the N-type doped layer 3 after acid washing are relatively small or even completely the same as the surface characteristics of the N-type doped layer 3 after deposition, which is conducive to reducing the series resistance and improving the fill factor, thereby enabling the finally formed back contact cell to have good photoelectric conversion efficiency.

[0064] In a possible implementation, in the process of alkali etching, a potassium hydroxide (KOH) solution with a concentration of 1% to 10% can be used in an environment with a temperature of 60°C to 80°C, so as to control the etching rate and achieve more accurate and gentle etching, and the product pass rate after alkali etching is high.

[0065] In a possible implementation, in the process of acid washing, a hydrofluoric acid (HF) solution with a concentration of 1% to 20% can be used in an environment with a temperature of 20°C to 25°C, so as to quickly oxidize the oxide layer and form a hydrophobic surface on the N-type doped layer 3, thereby improving the cleanliness of the surface of the N-type doped layer 3.

[0066] In a possible implementation, in the process of measuring the contact resistance of the N-type doped layer 3 after deposition / acid washing, the transmission line model (TLM) method can be used for testing, or a multimeter and four probes can be used for testing.

[0067] Optionally, in the process of preparing the back contact cell, the TLM and the multimeter or the TLM and the four probes can be combined for testing. The TLM can accurately calculate the contact resistivity, and the multimeter or the four probes can conveniently measure during preparation. Therefore, by combining the two, the measurement result of the multimeter or the four probes can be used as reference data for the calculation result of the TLM, which is conducive to improving the measurement accuracy and efficiency during preparation.

[0068] In a possible implementation, during the deposition of the N-type doped layer 3, a low pressure chemical vapor deposition (LPCVD) method can be used for deposition to improve the uniformity and continuity of the film layer, so as to form a high-quality N-type doped layer 3, which is conducive to further improving the passivation effect and electrical performance in the electron collection region 111. After the deposition by the LPCVD is completed, the N-type doped layer 3 can be re-doped with phosphorus atoms, so as to form an N-type doped layer 3 with a high concentration of phosphorus atoms (for example, the concentration of phosphorus atoms is greater than 10 19 atoms / cm 3 ) on the surface, to prepare for the subsequent formation of a good ohmic contact.

[0069] In a specific implementation, as shown in Figure 5 and Figure 6 , after the step of sequentially depositing the first mask layer 101, the intrinsic hydrogenated amorphous silicon layer 4, and the P-type hydrogenated amorphous silicon layer 5 on the first surface 11, the preparation method further includes: depositing a second mask layer 102 on the first surface 11.

[0070] In the embodiments of the present application, first, as shown in Figure 5 , after the first mask layer 101, the intrinsic hydrogenated amorphous silicon layer 4, and the P-type hydrogenated amorphous silicon layer 5 are sequentially deposited on the first surface 11, the projection of the first mask layer 101 along the first direction x covers only the electron collection region 111, and the projections of the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5 along the first direction x cover both the electron collection region 111 and the hole collection region 112.

[0071] Among the hole collection region 112, the intrinsic hydrogenated amorphous silicon layer 4 can saturate dangling bonds to form chemical passivation to reduce the recombination of electrons and holes, and the P-type hydrogenated amorphous silicon layer 5 can generate a built-in electric field to form field effect passivation to transport holes and block electrons, and through the synergistic effect of the two, a high-quality passivation effect can be formed, which is conducive to improving the open-circuit voltage and the fill factor of the back contact cell.

[0072] Second, as shown in Figure 6 , after the second mask layer 102 is deposited on the first surface 11, the second mask layer 102 is connected to the side of the P-type hydrogenated amorphous silicon layer 5 away from the substrate 1, at this time, the projection of the second mask layer 102 along the first direction x covers both the electron collection region 111 and the hole collection region 112.

[0073] In the subsequent process of patterning the electron collection region 111 by laser and etching the electron collection region 111 by alkaline solution at low temperature, the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5 of the hole collection region 112 are at risk of being scattered by laser and corroded by alkaline solution, which easily causes the passivation contact structure of the hole collection region 112 to be damaged, and further affects the electrical performance of the hole collection region 112 and the back contact cell. Therefore, the second mask layer 102 is deposited on the first surface 11 to protect the film layer of the hole collection region 112.

[0074] The second mask layer 102 can be an oxide layer, which is used to protect the P-type hydrogenated amorphous silicon layer 5 of the hole collection region 112, so as to reduce the influence of the P-type hydrogenated amorphous silicon layer 5 in the subsequent process of patterning, and improve the integrity of the P-type hydrogenated amorphous silicon layer 5, thereby ensuring the passivation quality of the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5 and the electrical performance of the hole collection region 112.

[0075] Therefore, in the process of preparing the back contact cell, the preparation method of the embodiment deposits the second mask layer 102 on the P-type hydrogenated amorphous silicon layer 5, so as to cover the side of the P-type hydrogenated amorphous silicon layer 5 away from the substrate 1 to provide a protection effect, thereby reducing or avoiding the damage of the P-type hydrogenated amorphous silicon layer 5 caused by the subsequent laser scattering and alkaline corrosion, and further maintaining the integrity of the passivation contact structure in the hole collection region 112, which is conducive to improving the production yield of the back contact cell.

[0076] In a possible implementation, since the projection of the second mask layer 102 along the first direction x covers at least the electron collection region 111, in the subsequent process of patterning the electron collection region 111 by laser, the P-type hydrogenated amorphous silicon layer 5 and the intrinsic hydrogenated amorphous silicon layer 4 can be removed synchronously, which provides working conditions for the subsequent reduction of the surface of the N-type doped layer 3 and the realization of ohmic contact. Further, the laser parameters can be adjusted so as to reduce the influence and effect on the mask layer 10 (i.e., the first mask layer 101 and the second mask layer 102) while removing the second mask layer 102, the P-type hydrogenated amorphous silicon layer 5 and the intrinsic hydrogenated amorphous silicon layer 4, thereby being conducive to ensuring the structural integrity and initial electrical performance of the N-type doped layer 3 and the P-type hydrogenated amorphous silicon layer 5.

[0077] In a specific implementation, as shown in Figure 6 the thickness of the first mask layer 101 along the first direction x is H1, the thickness of the second mask layer 102 along the first direction x is H2, and H1 and H2 satisfy H1≥H2, and H1 further satisfies 50nm≤H1≤200nm, and H2 further satisfies 30nm≤H2≤50nm.

[0078] In the embodiments of the present application, the first mask layer 101 located in the electron collection region 111 is mainly used to block the damage caused by direct laser, and the second mask layer 102 located in the hole collection region 112 is mainly used to block the damage caused by laser scattering. Therefore, compared with the second mask layer 102, the first mask layer 101 is not only more susceptible to laser damage, but also suffers greater damage effects.

[0079] To this end, the thickness of the first mask layer 101 can be greater than the thickness of the second mask layer 102, so as to improve the blocking ability of the first mask layer 101 to laser energy by thickening, thereby reducing the possibility of damage to the N-type doped layer 3 during the laser patterning process, and further achieving better protection effect on the N-type doped layer 3, which is conducive to further improving the possibility of the N-type doped layer 3 having a complete structure and initial electrical properties.

[0080] Meanwhile, when the thickness of the first mask layer 101 and the thickness of the second mask layer 102 satisfy H1≥H2, in the process of patterning the electron collection region 111 by laser, the second mask layer 102 located in the region can be removed to avoid the risk of damage to the N-type doped layer 3 caused by the subsequent burning through of the first mask layer 101 due to the increase of laser power. The thickness difference between the two can not only make each mask layer 10 effectively block the laser in each region, but also reduce the production cost of the mask layer 10 as a whole, which is more in line with the actual production needs.

[0081] In addition, when the thickness of the first mask layer 101 and the thickness of the second mask layer 102 are equal or have a small difference, the synchronous elimination between the two or the time difference between the elimination times of the two can be achieved in the subsequent pickling process, so as to avoid the risk of erosion of the N-type doped layer 3 and the P-type hydrogenated amorphous silicon layer 5 caused by the pickling time being too long, and further improve the control accuracy of the pickling process.

[0082] Optionally, the thickness of the first mask layer 101 can be 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, 150 nm, 155 nm, 160 nm, 165 nm, 170 nm, 175 nm, 180 nm, 185 nm, 190 nm, 195 nm, 200 nm, etc. When the thickness of the first mask layer 101 satisfies 50 nm≤H1≤200 nm, the first mask layer 101 can block higher laser energy and alkali etching, so as to effectively protect the N-type doped layer 3, so that the N-type doped layer 3 can pass through the patterning process and the alkali etching process without damage, thereby ensuring the structural integrity and initial electrical properties of the N-type doped layer 3, reducing the contact resistance of the electron collecting region 111, improving the fill factor, and further optimizing the electrical properties of the electron collecting region 111.

[0083] Optionally, the thickness of the second mask layer 102 can be 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, 41 nm, 42 nm, 43 nm, 44 nm, 45 nm, 46 nm, 47 nm, 48 nm, 49 nm, 50 nm, etc. When the thickness of the second mask layer 102 satisfies 30 nm≤H2≤50 nm, the second mask layer 102 can block part of the scattered laser energy and alkali etching, so as to effectively protect the P-type hydrogenated amorphous silicon layer 5, so that the P-type hydrogenated amorphous silicon layer 5 can pass through the patterning process and the alkali etching process without damage, thereby ensuring the structural integrity and initial electrical properties of the P-type hydrogenated amorphous silicon layer 5, reducing the contact resistance of the hole collecting region 112, improving the fill factor, and further optimizing the electrical properties of the hole collecting region 112. At the same time, the thickness of the second mask layer 102 can be appropriately thinned, so as to reduce the amount of mask layer 10 material while meeting the protection requirements, thereby reducing the overall production cost.

[0084] In a specific embodiment, the material of the first mask layer 101 and the second mask layer 102 is silicon oxide, silicon nitride, or silicon oxynitride.

[0085] In the embodiment of the present application, the mask layer 10 can be made of an oxide, i.e., silicon oxide, silicon nitride, or silicon oxynitride. The mask layer 10 can resist laser patterning and alkaline etching due to its good thermal stability and chemical stability. In addition, the mask layer 10 can be selectively etched by an acidic solution without damaging the N-type doped layer 3 and the P-type hydrogenated amorphous silicon layer 5. The mask layer 10 is beneficial to improve the reduction degree of the surface of the N-type doped layer 3 and the surface of the P-type hydrogenated amorphous silicon layer 5 after acid washing, and reduce the difference between the deposition and the acid washing of each film layer.

[0086] Therefore, the mask layer 10 can be used as a protective layer in the preparation process of the back contact cell to ensure that the difference between the deposition and the acid washing of the N-type doped layer 3 in the electron collection area 111 and the difference between the deposition and the acid washing of the P-type hydrogenated amorphous silicon layer 5 in the hole collection area 112 are small or even zero. This is beneficial to increase the effective contact area of the ohmic contact in each area, reduce the series resistance of the back contact cell, and improve the fill factor, thereby optimizing the photoelectric conversion efficiency of the back contact cell.

[0087] Optionally, the first mask layer 101 and the second mask layer 102 can be made of the same material, for example, silicon oxide or silicon nitride. This is beneficial to simplify the process steps, reduce the process difficulty, and improve the production efficiency.

[0088] Optionally, the first mask layer 101 and the second mask layer 102 can be made of different materials, for example, the first mask layer 101 is made of silicon nitride and the second mask layer 102 is made of silicon oxide. This is beneficial to protect each area specifically and improve the production yield and product quality of the back contact cell.

[0089] In a specific embodiment, as shown in Figure 6 , Figure 7 and Figure 8 , the step of sequentially performing patterning, alkaline etching, and acid washing on the electron collection area 111 to remove the first mask layer 101, the intrinsic hydrogenated amorphous silicon layer 4, the P-type hydrogenated amorphous silicon layer 5, and the second mask layer 102 on the N-type doped layer 3 specifically includes: The laser is used to perform patterning on the electron collection area 111 to remove the intrinsic hydrogenated amorphous silicon layer 4, the P-type hydrogenated amorphous silicon layer 5, and the second mask layer 102 on the first mask layer 101.

[0090] The alkaline solution is used to perform alkaline etching on the first surface 11 to clean the residues on the first mask layer 101 in the electron collection area 111.

[0091] The first surface 11 is subjected to pickling with an acidic solution to remove the first mask layer 101 in the electron collection region 111 on the N-type doped layer 3 and remove the second mask layer 102 in the hole collection region 112 on the P-type hydrogenated amorphous silicon layer 5.

[0092] In the embodiment, before the first surface 11 is subjected to pickling with an acidic solution, in the first direction x, the outermost film layer in the electron collection region 111 is the first mask layer 101, and the outermost film layer in the hole collection region 112 is the second mask layer 102. At this time, the first mask layer 101 and the second mask layer 102 can be removed synchronously by pickling, so as to shorten the time for removing the mask layer 10, simplify the work flow of the pickling process, improve the work efficiency of the pickling process, and be more in line with actual production needs.

[0093] By such a design manner, the time, concentration and temperature and other parameters of the pickling process can be uniformly controlled for precise regulation, which is conducive to improving the consistency of the surfaces of the N-type doped layer 3 and the P-type hydrogenated amorphous silicon layer 5, reducing the property difference between the electron collection region 111 and the hole collection region 112, and further improving the electrical performance of the back contact cell. Moreover, compared with the step-by-step removal of the first mask layer 101 and the second mask layer 102, the risk of pollution and secondary damage of the N-type doped layer 3 or the P-type hydrogenated amorphous silicon layer 5 can be reduced, so as to ensure the reduction degree of the N-type doped layer 3 or the P-type hydrogenated amorphous silicon layer 5 after pickling, so as to increase the effective contact area of the subsequent ohmic contact of each region, thereby reducing the series resistance of the back contact cell, improving the fill factor, and further optimizing the overall electrical performance of the back contact cell.

[0094] In a specific embodiment, as shown in Figure 2 , Figure 3 , Figure 4 and Figure 5 , the step of sequentially depositing the first mask layer 101, the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5 on the first surface 11 specifically includes: depositing the first mask layer 101 on the first surface 11.

[0095] The hole collection region 112 is subjected to patterning treatment by laser to remove the tunneling oxide layer 2, the N-type doped layer 3 and the first mask layer 101 in the hole collection region 112 on the substrate 1.

[0096] The hole collection region 112 is subjected to texturing to form a textured structure.

[0097] The hole collection region 112 is subjected to cleaning to remove the film layer in the hole collection region 112 on the substrate 1.

[0098] The intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5 are sequentially deposited on the first surface 11.

[0099] In the embodiment of the present application, first, as shown in Figure 2 After the first mask layer 101 is deposited on the first surface 11, the first mask layer 101 is connected to the side of the N-type doped layer 3 away from the substrate 1. At this time, the projection of the first mask layer 101 along the first direction x covers the electron collection region 111 and the hole collection region 112. This step is mainly used to deposit the first mask layer 101 to protect the N-type doped layer 3, so as to reduce the risk of damage to the N-type doped layer 3 in the subsequent process.

[0100] Second, as shown in Figure 3 The laser is used to perform patterning treatment on the hole collection region 112 to remove the tunneling oxide layer 2, the N-type doped layer 3 and the first mask layer 101 on the substrate 1 in the hole collection region 112. At this time, the electron collection region 111 is stacked with the tunneling oxide layer 2, the N-type doped layer 3 and the first mask layer 101, and the hole collection region 112 is exposed on the surface of the substrate 1. This step is mainly used to clearly divide the electron collection region 111 and the hole collection region 112, and to provide good working conditions for the subsequent texturing in the hole collection region 112.

[0101] After the laser is used to perform patterning treatment on the hole collection region 112, the hole collection region 112 is cleaned in time to remove the pollutants and damaged layers caused by the patterning treatment.

[0102] Then, as shown in Figure 4 The hole collection region 112 is textured to form a textured structure, which is beneficial to improve the reflectivity of the incident light and thus improve the short-circuit current of the back contact cell. After the hole collection region 112 is textured, the hole collection region 112 can be cleaned to remove chemical residues, metal contaminants or oxide film layers on the surface of the hole collection region 112 after the texturing, so as to improve the cleanliness of the surface of the textured structure and reduce the recombination of electrons and holes, thereby providing good working conditions for the subsequent deposition of the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5.

[0103] Then, as shown in Figure 5As shown in FIG. 1, the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5 are sequentially deposited on the first surface 11, and the projections of the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5 along the first direction x both cover the electron collection region 111 and the hole collection region 112. This step is mainly used to deposit the passivation contact structure of the hole collection region 112, so that the intrinsic hydrogenated amorphous silicon layer 4 can be saturated with dangling bonds to form chemical passivation, thereby reducing the recombination of electrons and holes, and the P-type hydrogenated amorphous silicon layer 5 can generate a built-in electric field to form field effect passivation, thereby transmitting holes and blocking electrons. Through the synergistic effect of the two, a high-quality passivation effect can be formed, which is conducive to improving the open-circuit voltage and fill factor of the back contact cell.

[0104] In one embodiment, the intrinsic hydrogenated amorphous silicon layer 4 has a thickness of 5 nm to 15 nm and is prepared at a temperature of 150°C to 250°C, and the P-type hydrogenated amorphous silicon layer 5 has a thickness of 15 nm to 35 nm and is prepared at a temperature of 150°C to 250°C.

[0105] Therefore, in the process of preparing the back contact cell, the embodiment is mainly used to form the electron collection region 111 and the hole collection region 112 with clear boundaries on the first surface 11 of the substrate 1, and to prepare the passivation contact structure in the hole collection region 112, so as to realize the selective transmission of carriers in the hole collection region 112 through the high-quality passivation effect, thereby being able to inhibit the recombination rate of electrons and holes, which is conducive to improving the open-circuit voltage and fill factor of the back contact cell, and further improving the photoelectric conversion efficiency of the back contact cell.

[0106] In one embodiment, as shown in FIG. 1, the passivation contact structure of the hole collection region 112 is prepared by sequentially depositing at least one passivation layer 7 and at least one anti-reflection layer 8 on the hole collection region 112. Figure 3 、 Figure 4 and Figure 5 As shown in FIG. 1, after the step of patterning the hole collection region 112 by using a laser to remove the tunneling oxide layer 2, the N-type doped layer 3 and the first mask layer 101 of the hole collection region 112 on the substrate 1, the preparation method further comprises: cleaning the second surface 12 to remove the phosphor-silicon glass and the N-type doped layer 3 on the substrate 1.

[0107] Meanwhile, the second surface 12 and the hole collection region 112 are textured to form a textured structure on the corresponding surface of the substrate 1.

[0108] In one embodiment, as shown in FIG. 1, the passivation contact structure of the hole collection region 112 is prepared by sequentially depositing at least one passivation layer 7 and at least one anti-reflection layer 8 on the hole collection region 112.

[0109] cleaning the hole collection region 112 to remove the passivation layer 7 and the anti-reflection layer 8 of the hole collection region 112 on the substrate 1.

[0110] In one embodiment, as shown in FIG. 1, the passivation contact structure of the hole collection region 112 is prepared by sequentially depositing at least one passivation layer 7 and at least one anti-reflection layer 8 on the hole collection region 112.

[0111] In the embodiment of the present application, first, as shown in Figure 3 The second surface 12 is cleaned to remove the phosphosilicate glass and the N-type doped layer 3 on the substrate 1. Since the LPCVD is used for deposition and phosphorus diffusion is performed on the N-type doped layer 3 in the process of depositing the N-type doped layer 3, the phosphosilicate glass and the N-type doped layer 3 are easily present on the second surface 12 of the substrate 1. Therefore, the cleaning can not only restore the second surface 12 of the substrate 1, but also clean the second surface 12 of the substrate 1 to reduce the possibility of contamination and residue attachment, thereby providing good preparation conditions for subsequent texturing and deposition.

[0112] The phosphosilicate glass and the N-type doped layer 3 on the second surface 12 can be removed by selective structure etching (SEE) to avoid affecting the first surface 11 of the substrate 1 while cleaning the second surface 12 of the substrate 1, thereby protecting the patterned structure and the N-type doped layer 3 on the first surface 11.

[0113] Second, as shown in Figure 4 The second surface 12 and the hole collection region 112 of the first surface 11 are simultaneously textured to form the textured structure on the corresponding positions of the substrate 1, thereby simplifying the texturing process and improving production efficiency while improving the reflectivity and short-circuit current.

[0114] After the textured structure is formed on the second surface 12, at least one passivation layer 7 and at least one anti-reflection layer 8 are sequentially deposited on the second surface 12. The passivation layer 7 saturates the dangling bonds of the second surface 12 to form chemical passivation, thereby reducing the recombination rate of electrons and holes at the second surface 12, which is beneficial to improve the open-circuit voltage and fill factor of the back contact cell. The anti-reflection layer 8 offsets the reflected light on the upper and lower surfaces to realize destructive interference, thereby reducing the reflectivity of the incident light on the front surface of the cell, which is beneficial to improve the short-circuit current of the back contact cell.

[0115] The passivation layer 7 with a thickness of 3 nm to 10 nm can be prepared at a temperature of 200℃ to 400℃, and the anti-reflection layer 8 with a thickness of 70 nm to 150 nm can be prepared at a temperature of 400℃ to 600℃.

[0116] After the passivation layer 7 and the antireflection layer 8 are deposited on the second surface 12, the hole collection area 112 can be cleaned to remove the passivation layer 7 and the antireflection layer 8 located on the substrate 1 in the hole collection area 112, and simultaneously remove chemical residues and metal contaminants on the surface of the hole collection area 112 after texturing, so as to improve the cleanliness of the textured surface, reduce the recombination of electrons and holes, and provide good working conditions for the subsequent deposition of the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5.

[0117] Among them, SSE and RCA cleaning methods can be used to clean the cavity collection area 112 to improve the cleanliness of the velvet surface in this area.

[0118] Then as Figure 5 As shown, an intrinsic hydrogenated amorphous silicon layer 4 and a P-type hydrogenated amorphous silicon layer 5 are sequentially deposited on the first surface 11 to form a passivated contact structure in the hole collection region 112, thereby reducing the recombination rate of electrons and holes in the hole collection region 112 and improving the open-circuit voltage and fill factor of the back contact battery.

[0119] Therefore, in the process of fabricating a back-contact battery, this embodiment is mainly used to simultaneously texturize the second surface 12 and the hole collection region 112, which helps to simplify the texturing process, improve production efficiency, and better meet actual production needs. Simultaneously, the passivation layer 7 and antireflection layer 8 deposited on the second surface 12 can reduce parasitic absorption and improve optical performance, thereby enhancing the photoelectric conversion efficiency of the back-contact battery.

[0120] In one specific implementation, such as Figure 9 and Figure 10 As shown, after sequentially patterning, etching, and acid washing the electron collection region 111 to remove the first mask layer 101, the intrinsic hydrogenated amorphous silicon layer 4, the P-type hydrogenated amorphous silicon layer 5, and the second mask layer 102 located on the N-type doped layer 3, the fabrication method further includes: A transparent conductive layer 6 is deposited on the first surface 11.

[0121] The transparent conductive layer 6 is patterned or etched to form an isolation region 113 between the electron collection region 111 and the hole collection region 112.

[0122] A first electrode 91 is printed in the electron collection region 111. The first electrode 91 is electrically connected to the N-type doped layer 3 through the transparent conductive layer 6.

[0123] A second electrode 92 is printed in the hole collection region 112. The second electrode 92 is electrically connected to the P-type hydrogenated amorphous silicon layer 5 through the transparent conductive layer 6.

[0124] In the embodiments of this application, firstly as follows: Figure 9As shown, the transparent conductive layer 6 is deposited on the first surface 11, at this time, the projection of the transparent conductive layer 6 along the first direction x covers the electron collection region 111 and the hole collection region 112.

[0125] In which, the transparent conductive layer 6 with a thickness of 50nm~200nm can be prepared in an environment with a temperature of 100℃~300℃. The transparent conductive layer 6 can form an ohmic contact between the N-type doped layer 3 in the electron collection region 111 and the P-type hydrogenated amorphous silicon layer 5 in the hole collection region 112, so that the electrons and holes can move from the electron collection region 111 and the hole collection region 112 to the transparent conductive layer 6 respectively, which is conducive to reducing the series resistance of the current transmission path in each region, thereby improving the current transmission efficiency of the back contact cell.

[0126] Secondly, as shown in Figure 10 After the transparent conductive layer 6 is deposited on the first surface 11, the transparent conductive layer 6 is subjected to a patterning process or an etching process to form an isolation region 113 between the electron collection region 111 and the hole collection region 112, at this time, the transparent conductive layer 6 can include first conductive segments (not marked in the figure) and second conductive segments (not marked in the figure) which are alternately arranged and spaced apart along the second direction y, the projection of the first conductive segments along the first direction x covers the electron collection region 111, and the projection of the second conductive segments along the first direction x covers the hole collection region 112.

[0127] In which, by removing the transparent conductive layer 6 located at the connection between the electron collection region 111 and the hole collection region 112, an isolation region 113 with insulation function can be formed therebetween, so that the electrical isolation between the electron collection region 111 and the hole collection region 112 can be achieved, thereby ensuring the independent flow of electrons and holes in the respective regions, so as to reduce the possibility of short circuit of the back contact cell, and the clear and clean isolation region 113 can reduce the leakage current path between the electron collection region 111 and the hole collection region 112, which is conducive to improving the stability and reliability of the back contact cell during operation.

[0128] After the formation of the isolation region 113, the electrode 9 can be prepared by screen printing, for example, a first electrode 91 is printed on the electron collection region 111, the first electrode 91 is electrically connected to the N-type doped layer 3 through the transparent conductive layer 6, and a second electrode 92 is printed on the hole collection region 112, the second electrode 92 is electrically connected to the P-type hydrogenated amorphous silicon layer 5 through the transparent conductive layer 6, at this time, the projection of the first electrode 91 along the first direction x is located within the projection range of the electron collection region 111, and the projection of the second electrode 92 along the first direction x is located within the projection range of the hole collection region 112.

[0129] Wherein, after the electron and the hole are moved from the base 1 to the transparent conductive layer 6, the lateral transmission can be carried out, so that the first electrode 91 and the second electrode 92 can be flowed to respectively, and the collected current can be transmitted to the corresponding gate line, which is beneficial to improve the current transmission efficiency of the back contact cell.

[0130] In summary, the preparation method provided in the application comprises: Figure 1 As shown in the figure, the base 1 subjected to polishing treatment is provided. As shown in the figure, Figure 2 As shown in the figure, the tunneling oxide layer 2, the N-type doped layer 3 and the first mask layer 101 are sequentially deposited on the first surface 11. As shown in the figure, Figure 3 As shown in the figure, the laser is used to carry out the patterning treatment on the hole collecting area 112, and then the hole collecting area 112 and the second surface 12 are sequentially cleaned. As shown in the figure, Figure 4 As shown in the figure, the second surface 12 and the hole collecting area 112 are simultaneously textured, and then the passivation layer 7 and the anti-reflection layer 8 are sequentially deposited on the second surface 12, and then the hole collecting area 112 is cleaned. As shown in the figure, Figure 5 As shown in the figure, the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5 are sequentially deposited on the first surface 11. As shown in the figure, Figure 6 As shown in the figure, the second mask layer 102 is deposited on the first surface 11. As shown in the figure, Figure 7 As shown in the figure, the laser is used to carry out the patterning treatment on the electron collecting area 111. As shown in the figure, Figure 8 As shown in the figure, the alkali etching is carried out on the first surface 11 by using the alkaline solution, and then the acid washing is carried out on the first surface 11 by using the acidic solution. As shown in the figure, Figure 9 As shown in the figure, the transparent conductive layer 6 is deposited on the first surface 11. As shown in the figure, Figure 10 As shown in the figure, the patterning treatment or the etching treatment is carried out on the transparent conductive layer 6, and then the first electrode 91 is printed on the electron collecting area 111, and the second electrode 92 is printed on the hole collecting area 112.

[0131] The embodiment of the application further provides a back contact cell made by using any one of the preparation methods. Figure 10 As shown in the figure, the back contact cell comprises the base 1, the tunneling oxide layer 2, the N-type doped layer 3, the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5, the first surface 11 of the base 1 comprises the electron collecting area 111 and the hole collecting area 112, the tunneling oxide layer 2 and the N-type doped layer 3 are sequentially and layerwisely arranged on the electron collecting area 111, and the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5 are sequentially and layerwisely arranged on the hole collecting area 112.

[0132] Wherein, the series resistance of the back contact cell is Rs, and Rs satisfies 0.0006Ω≤Rs≤0.0014Ω.

[0133] In the embodiment of the present application, the tunneling oxide layer 2 and the N-type doped layer 3 can form a passivation contact structure of the electron collection region 111 for collecting electrons, and the intrinsic hydrogenated amorphous silicon layer 4 and the P-type hydrogenated amorphous silicon layer 5 can form a passivation contact structure of the hole collection region 112 for collecting holes. Through such a design, not only can the shading area of the grid lines on the front surface of the cell be eliminated to maximize the absorption of incident light, but also the working performance of the whole back contact cell can be improved by combining the characteristics of the tunneling passivation contact cell and the heterojunction cell on the back surface of the cell.

[0134] In addition, the N-type doped layer 3 and the P-type hydrogenated amorphous silicon layer 5 are protected by the mask layer 10 during the preparation process, so that the surface characteristics of the N-type doped layer 3 after acid washing are similar to or even the same as the surface characteristics of the N-type doped layer 3 after deposition, and the surface characteristics of the P-type hydrogenated amorphous silicon layer 5 after acid washing are similar to or even the same as the surface characteristics of the P-type hydrogenated amorphous silicon layer 5 after deposition. Through such a design, the structural integrity of the N-type doped layer 3 and the P-type hydrogenated amorphous silicon layer 5 can be improved, so that both of them have initial electrical properties, which is beneficial to reduce the series resistance of the finally formed back contact cell, and thus the back contact cell can have good photoelectric conversion efficiency.

[0135] Alternatively, the series resistance of the finally formed back contact cell can be 0.0006Ω, 0.0007Ω, 0.0008Ω, 0.0009Ω, 0.001Ω, 0.0011Ω, 0.0012Ω, 0.0013Ω, 0.0014Ω, etc.

[0136] When the series resistance of the finally formed back contact cell satisfies 0.0006Ω≤Rs≤0.0014Ω, the lower series resistance can make the back contact cell have a higher fill factor, so that more current can be transmitted to the external circuit through the grid lines, which is beneficial to improve the photoelectric conversion efficiency of the back contact cell, and the back contact cell can also maintain stable output under high current load, which is beneficial to improve the stability and reliability of the back contact cell during operation. Therefore, the working performance of the back contact cell can be optimized by the above preparation method, so as to obtain a high-performance and high-quality back contact cell.

[0137] In a possible implementation, the contact resistivity of the back contact cell prepared by the above preparation method is ρc, and ρc satisfies 50mΩ·cm 2 ≤ρc≤150mΩ·cm 2 , specifically, 50mΩ·cm 2 , 55mΩ·cm 2 , 60mΩ·cm 2 , 65mΩ·cm 2 , 70mΩ·cm2 75 mΩ·cm 2 80 mΩ·cm 2 85 mΩ·cm 2 90 mΩ·cm 2 95 mΩ·cm 2 100 mΩ·cm 2 105 mΩ·cm 2 110 mΩ·cm 2 115 mΩ·cm 2 120 mΩ·cm 2 125 mΩ·cm 2 130 mΩ·cm 2 135 mΩ·cm 2 140 mΩ·cm 2 145 mΩ·cm 2 150 mΩ·cm 2 and when the contact resistivity of the back contact cell satisfies 50 mΩ·cm 2 ≤ ρc≤ 150 mΩ·cm 2 , the contact resistances between the transparent conductive layer 6 and the N-type doped layer 3 and the P-type hydrogenated amorphous silicon layer 5 are low, so that the current can be efficiently collected by the electrode 9 and then led out, which is beneficial to improve the current transmission efficiency of the back contact cell.

[0138] The embodiment of the present application also provides a back contact stacked cell, which comprises a back contact bottom cell and a perovskite top cell, the perovskite top cell is electrically connected with the front surface of the back contact bottom cell, and the back contact bottom cell is the back contact cell described in any one of the above.

[0139] In the embodiment of the present application, when the perovskite top cell and the back contact bottom cell are electrically connected to form a back contact stacked cell, the solar spectrum can be used in different wave bands to improve the overall photoelectric conversion efficiency, that is, the perovskite top cell can absorb high-energy short-wavelength photons with a wide band gap to reduce light loss and improve open-circuit voltage, and the back contact bottom cell can absorb low-energy long-wavelength photons with a narrow band gap to reduce light-heat loss and improve current density, and the back contact bottom cell has a low series resistance, so that the photoelectric conversion efficiency of the back contact stacked cell can be improved through the synergistic effect of the perovskite top cell and the back contact bottom cell, and the output effect of the back contact stacked cell under high current load is stable, which is beneficial to improve the stability and reliability of the back contact stacked cell during the working process. Meanwhile, the back contact stacked cell also comprises an interconnection layer, which is located between the perovskite top cell and the back contact bottom cell along the first direction x, so as to play a role in connecting and transmitting current, which is beneficial to realize the current matching between the two, and can reduce the series resistance and improve the fill factor to optimize the transmission efficiency of the charge.

[0140] Embodiments of the present application also provide a photovoltaic module, which comprises a cover plate, an encapsulation layer and at least one cell string, the cover plate is connected with the cell string through the encapsulation layer, and the cell string comprises a plurality of back contact cells or back contact laminated cells as described above.

[0141] In embodiments of the present application, the photovoltaic module can comprise a plurality of cell strings, the plurality of cell strings are electrically connected in series and / or in parallel, and the solar cell pieces of each cell string can be the back contact cells or the back contact laminated cells described above. Through such a design, the photovoltaic module using the back contact cells or the back contact laminated cells with extremely low series resistance can maximize the use of incident light to improve the photoelectric conversion efficiency, and can use a wider and thicker electrode 9 on the back of the cell piece layer, and further reduce the series resistance, improve the fill factor by optimizing the layout and interconnection of the electrode 9, thereby facilitating the improvement of the electrical performance of the photovoltaic module and the improvement of the safety and reliability of the photovoltaic module in the working process.

[0142] Optionally, the back contact cells can be electrically connected in the form of a whole piece or a plurality of split pieces to form a plurality of cell strings, and the plurality of cell strings are electrically connected in series and / or in parallel to form a cell piece layer. The back contact cells include but are not limited to IBC cells (Interdigitated Back Contact Battery), HBC cells (Heterojunction Back Contact Battery), TBC cells (TOPCon Back Contact Battery) or HPBC cells (Hybrid Passivated Back Contact Battery) and the like.

[0143] In a possible implementation, the cover plate can comprise a first cover plate and a second cover plate, the first cover plate can be located on the light-receiving surface of the cell string, and the second cover plate can be located on the back surface of the cell string. The encapsulation layer comprises a first encapsulation layer and a second encapsulation layer, the first encapsulation layer can be located between the first cover plate and the cell string, and the second encapsulation layer can be located between the second cover plate and the cell string, i.e. along the thickness direction of the photovoltaic module, the first cover plate, the first encapsulation layer, the cell string, the second encapsulation layer and the second cover plate are stacked and pressed against each other.

[0144] The surfaces of the first cover plate and the second cover plate on the side of the battery string can be concave-convex structures for increasing the utilization rate of incident light, and the materials of the first cover plate and the second cover plate can be glass or plastic; the first encapsulation layer and the second encapsulation layer can connect the first cover plate and the battery string and the second cover plate and the battery string together respectively, for playing an encapsulation protection role on the battery string, and the materials of the first encapsulation layer and the second encapsulation layer can be one or more of polyvinyl butyral adhesive film, ethylene-vinyl acetate copolymer adhesive film, polyethylene octene copolymer elastomer adhesive film and polyethylene terephthalate adhesive film.

[0145] The above detailed description of the embodiments shown in the drawings explains the structure, features and effects of the present application. The above description is only the preferred embodiments of the present application, but the present application is not limited by the drawings. Any changes or modifications made in accordance with the concept of the present application, or equivalent embodiments with equivalent changes, are still within the scope of the present application.

Claims

1. A method for preparing a back-contact battery, characterized in that, The preparation method includes: A substrate is provided, the substrate having a first surface and a second surface disposed opposite to each other along a first direction, the first surface including an electron collecting region and a hole collecting region; A tunneling oxide layer and an N-type doped layer are sequentially deposited on the first surface, and the contact resistance of the deposited N-type doped layer is Rc1; A first mask layer, an intrinsic hydrogenated amorphous silicon layer, and a P-type hydrogenated amorphous silicon layer are sequentially deposited on the first surface; The electron collection region is sequentially patterned, etched with alkali, and acid-washed to remove the first mask layer, the intrinsic hydrogenated amorphous silicon layer, and the P-type hydrogenated amorphous silicon layer located on the N-type doped layer. The contact resistance of the N-type doped layer after acid washing is Rc2. Among them, Rc1 and Rc2 satisfy 0Ω≤Rc2-Rc1≤30Ω.

2. The preparation method according to claim 1, characterized in that, After the steps of sequentially depositing the first mask layer, the intrinsic hydrogenated amorphous silicon layer, and the P-type hydrogenated amorphous silicon layer on the first surface, the fabrication method further includes: A second mask layer is deposited on the first surface.

3. The preparation method according to claim 2, characterized in that, Along the first direction, the thickness of the first mask layer is H1, the thickness of the second mask layer is H2, and H1 and H2 satisfy H1≥H2, H1 also satisfies 50nm≤H1≤200nm, and H2 also satisfies 30nm≤H2≤50nm.

4. The preparation method according to claim 2, characterized in that, The first mask layer and the second mask layer are made of silicon oxide, silicon nitride or silicon oxynitride.

5. The preparation method according to claim 2, characterized in that, The steps of sequentially patterning, etching, and acid washing the electron collection region to remove the first mask layer, the intrinsic hydrogenated amorphous silicon layer, and the P-type hydrogenated amorphous silicon layer located on the N-type doped layer include: The electron collection region is patterned using a laser to remove the intrinsic hydrogenated amorphous silicon layer, the P-type hydrogenated amorphous silicon layer, and the second mask layer located on the first mask layer; The first surface is etched with an alkaline solution to clean the residue located on the first mask layer in the electron collection area; The first surface is acid-washed with an acidic solution to remove the first mask layer located on the N-type doped layer in the electron collection region and the second mask layer located on the P-type hydrogenated amorphous silicon layer in the hole collection region.

6. The preparation method according to claim 1, characterized in that, The step of sequentially depositing the first mask layer, the intrinsic hydrogenated amorphous silicon layer, and the P-type hydrogenated amorphous silicon layer on the first surface includes: Deposit the first mask layer on the first surface; The hole collection region is patterned using a laser to remove the tunneling oxide layer, the N-type doped layer, and the first mask layer located on the substrate in the hole collection region. The cavity collection area is fuzzed to form a fuzzy structure; The hole collection area is cleaned to remove the membrane layer located on the substrate in the hole collection area; The intrinsic hydrogenated amorphous silicon layer and the P-type hydrogenated amorphous silicon layer are sequentially deposited on the first surface.

7. The preparation method according to claim 6, characterized in that, After the step of patterning the hole collection region using a laser to remove the tunneling oxide layer, the N-type doped layer, and the first mask layer located on the substrate in the hole collection region, the fabrication method further includes: The second surface is cleaned to remove the phosphosilicate glass and the N-type doped layer located on the substrate; Simultaneously, the second surface and the cavity collection area are texturing to form a texturing structure on the surface corresponding to the substrate; At least one passivation layer and at least one antireflection layer are sequentially deposited on the second surface; The hole collection area is cleaned to remove the passivation layer and the antireflection layer located on the substrate in the hole collection area; The intrinsic hydrogenated amorphous silicon layer and the P-type hydrogenated amorphous silicon layer are sequentially deposited on the first surface.

8. The preparation method according to any one of claims 1-7, characterized in that, After sequentially performing patterning, alkaline etching, and acid washing on the electron collection region to remove the first mask layer, the intrinsic hydrogenated amorphous silicon layer, and the p-type hydrogenated amorphous silicon layer located on the N-type doped layer, the fabrication method further includes: A transparent conductive layer is deposited on the first surface; The transparent conductive layer is patterned or etched to form an isolation region between the electron collection region and the hole collection region; A first electrode is printed in the electron collection region, and the first electrode is electrically connected to the N-type doped layer through the transparent conductive layer. A second electrode is printed in the hole collection region, and the second electrode is electrically connected to the P-type hydrogenated amorphous silicon layer through the transparent conductive layer.

9. A back-contact battery, manufactured using the preparation method according to any one of claims 1-8, characterized in that, The back contact battery includes a substrate, a tunneling oxide layer, an N-type doped layer, an intrinsic hydrogenated amorphous silicon layer, and a P-type hydrogenated amorphous silicon layer. The first surface of the substrate includes an electron collection region and a hole collection region. The tunneling oxide layer and the N-type doped layer are sequentially stacked in the electron collection region, and the intrinsic hydrogenated amorphous silicon layer and the P-type hydrogenated amorphous silicon layer are sequentially stacked in the hole collection region. The series resistance of the back contact battery is Rs, and Rs satisfies 0.0006Ω≤Rs≤0.0014Ω.

10. A back-contact stacked battery, characterized in that, The back-contact stacked battery includes a back-contact bottom battery and a perovskite top battery. The perovskite top battery is electrically connected to the front side of the back-contact bottom battery. The back-contact bottom battery is the back-contact battery as described in claim 9.

11. A photovoltaic module, characterized in that, The photovoltaic module includes a cover plate, an encapsulation layer, and at least one battery string. The cover plate is connected to the battery string through the encapsulation layer. The battery string includes a plurality of back-contact batteries as described in claim 9 or a plurality of back-contact stacked batteries as described in claim 10.

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