Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a display area and a peripheral area, and the part, located in the peripheral area, of the display panel comprises a first insulating layer, a plurality of metal pads arranged on the first insulating layer, an edge covering part arranged on the metal pads and the first insulating layer, and a second insulating layer arranged on the edge covering part and the first insulating layer. The part, located between two adjacent metal pads, of the edge covering part is provided with a first digging hole penetrating through the film layer where the edge covering part is located, and the first digging hole exposes the first insulating layer. A second digging hole penetrating through the second insulating layer is formed in the portion, located between every two adjacent metal pads, of the second insulating layer, and the second digging hole exposes the first insulating layer. The edge covering part covers the circumferential surface of the metal pad, so that metal wire-shaped residues can be prevented from being formed on the circumferential surface of the metal pad, electrical faults such as short circuit caused by the metal wire-shaped residues are avoided, and the reliability of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] In traditional organic light-emitting diode (OLED) display devices, the pins of the driver chip are electrically connected to the metal pads in the peripheral area of ​​the display panel to enable the driver chip to control the display panel. The peripheral area of ​​the display panel includes multiple layers, including interlayer insulating layers and touch insulating layers.

[0003] To achieve electrical connection between the driver chip and the metal pad, holes are typically punched in the touch insulating layer above the metal pad to expose it. However, the touch insulating layer may not form a uniform film at the edges of the metal pad, resulting in poor coverage of the circumferential surface of the metal pad. This leads to the presence of metal filaments on the circumferential surface of the metal pad, which can cause electrical faults such as short circuits, reducing the reliability of the display panel.

[0004] Furthermore, in traditional organic light-emitting diode (OLED) display devices, the circumferential surface of the metal pad is prone to over-etching during manufacturing, resulting in irregular contours and affecting the electrical connection quality between the driver chip and the metal pad. The top metal layer of the metal pad also carries the risk of warping during manufacturing, impacting the contact reliability between the driver chip and the metal pad.

[0005] In addition, in traditional organic light-emitting diode display devices, the bonding force between the interlayer insulating layer and the touch insulating layer of the display panel is weak between two adjacent metal pads. The touch insulating layer and the interlayer insulating layer are prone to peeling, which can cause display abnormalities in the display panel.

[0006] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0007] The purpose of this application is to provide a display panel and display device that aims to solve the technical problem of existing organic light-emitting diode display devices having metal filament residue on the circumferential surface of the metal pad.

[0008] This application provides a display panel, which includes a display area and a peripheral area. The portion of the display panel located in the peripheral area includes: a first insulating layer; a plurality of metal pads disposed on the first insulating layer; an edge portion disposed on the metal pads and the first insulating layer, wherein the portion of the edge portion located between two adjacent metal pads has a first hole penetrating the film layer in which the edge portion is located, and the first hole exposes the first insulating layer; and a second insulating layer disposed on the edge portion and the first insulating layer, wherein the portion of the second insulating layer located between two adjacent metal pads has a second hole penetrating the second insulating layer, and the second hole exposes the first insulating layer.

[0009] In the aforementioned display panel, the edging portion covers at least a portion of the surface of the metal pad away from the first insulating layer along the thickness direction of the display panel and the circumferential surface of the metal pad.

[0010] In the aforementioned display panel, the metal pad includes a first metal electrode disposed on the first insulating layer and a second metal electrode disposed on the first metal electrode, the second metal electrode covering the first metal electrode; the edging portion covers at least a portion of the surface of the second metal electrode away from the first insulating layer along the thickness direction of the display panel, the circumferential surface of the second metal electrode, and the circumferential surface of the first metal electrode.

[0011] In the aforementioned display panel, the metal pad includes a first metal electrode disposed on the first insulating layer and a second metal electrode disposed on the first metal electrode. The second metal electrode is disposed on the surface of the first metal electrode away from the first insulating layer along the thickness direction of the display panel and on the circumferential surface. The edging portion covers at least a portion of the surface of the second metal electrode away from the first insulating layer along the thickness direction of the display panel and the circumferential surface of the second metal electrode.

[0012] In the above-mentioned display panel, the portion of the display panel located in the display area includes a pixel defining layer, and the edge portion is located in the film layer where the pixel defining layer is located.

[0013] In the aforementioned display panel, from a top-down view of the display panel, the second cutout is located within the first cutout.

[0014] In the aforementioned display panel, the portion of the edging portion and the second insulating layer located on the surface of the metal pad away from the first insulating layer along the thickness direction of the display panel is provided with a third hole penetrating the edging portion and the second insulating layer, the third hole exposing the metal pad; the portion of the display panel located in the peripheral area further includes: an overlapping metal member disposed in the third hole and on the second insulating layer, the overlapping metal member being electrically connected to the metal pad.

[0015] In the aforementioned display panel, from a top-down view of the display panel, the distance between the edge of the portion of the edging portion located on the metal pad and the edge of the metal pad is greater than one-third of the radius of the smallest circumcircle of the third cutout.

[0016] In the aforementioned display panel, the portion of the display panel located in the peripheral area further includes: a gate insulating layer; and a metal trace disposed on the gate insulating layer; wherein, the first insulating layer is disposed on the metal trace and the gate insulating layer, and the metal pad is electrically connected to the metal trace through a through-hole penetrating the first insulating layer; from a top view of the display panel, the bezel portion at least partially overlaps with the metal trace.

[0017] This application also provides a display device, which includes a driver chip and the aforementioned display panel, wherein the pins of the driver chip are electrically connected to the metal pad.

[0018] The display panel provided in this application has an edge-covering portion on the metal pad and the first insulating layer, which covers the circumferential surface of the metal pad, thus protecting the circumferential surface of the metal pad. Covering the circumferential surface of the metal pad with the edge-covering portion prevents the formation of metal filament residue on the circumferential surface of the metal pad, avoiding electrical faults such as short circuits caused by metal filament residue, and improving the reliability of the display panel. Simultaneously, during the manufacturing process, the edge-covering portion prevents the circumferential surface of the metal pad from being over-etched, thereby maintaining the regular contour of the circumferential surface of the metal pad, avoiding the problem of irregular contours of the circumferential surface of the metal pad, and improving the electrical connection quality between the driver chip and the metal pad. Furthermore, the edge-covering portion covers at least a portion of the surface of the metal pad along the thickness direction of the display panel away from the first insulating layer, which can press the top metal layer of the metal pad, preventing the top metal layer of the metal pad from lifting during the manufacturing process, and improving the contact reliability between the driver chip and the metal pad.

[0019] The display panel provided in this application has a first perforation penetrating the film layer containing the edge portion located between two adjacent metal pads. This first perforation exposes the first insulating layer. Simultaneously, a second perforation penetrating the second insulating layer is provided between two adjacent metal pads, exposing the first insulating layer. This results in the removal of both the edge portion and the second insulating layer between the two adjacent metal pads, directly exposing the first insulating layer. Consequently, there is no interface between the edge portion and the first insulating layer, or between the second insulating layer and the first insulating layer, between the two adjacent metal pads. This avoids the problem of peeling due to weak adhesion between the edge portion and the first insulating layer, and between the second insulating layer and the first insulating layer, thus improving the reliability of the display panel and preventing display abnormalities. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0021] Figure 2 for Figure 1 The diagram shows a cross-sectional view of the display panel of the display device located in the display area.

[0022] Figure 3 for Figure 1 The diagram shows a cross-sectional view of the display panel of the display device located in the peripheral area. Detailed Implementation

[0023] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0024] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0025] The embodiments of this application can be combined with each other.

[0026] The embodiments of this application provide a display panel and a display device to solve the technical problems of existing organic light-emitting diode display devices having metal wire-like residues on the circumferential surface (side) of the metal pad and peeling between the first insulating layer (interlayer insulating layer) and the second insulating layer (touch insulating layer).

[0027] like Figure 1 As shown, the display device DA provided in the embodiments of this application includes a display panel DP and a driver chip DIC. The pins of the driver chip DIC are electrically connected to the metal pad BP of the peripheral area PA of the display panel DP, so as to realize the driving control of the display panel DP by the driver chip DIC.

[0028] The display panel DP provided in the embodiments of this application may be, for example, an OLED display panel, a Mini-LED display panel, or a Micro-LED display panel. The embodiments of this application will be described using an OLED display panel as an example.

[0029] like Figure 1 As shown, the display panel DP includes a display area AA and a peripheral area PA. The portion of the display panel DP located between the display area AA and the peripheral area PA includes a substrate PI. The substrate PI is made of polyimide material. The portion of the display panel DP located between the display area AA and the peripheral area PA also includes a buffer layer BUF disposed on the substrate PI and a gate insulating layer GI disposed on the buffer layer BUF. The buffer layer BUF is disposed on the substrate PI. The gate insulating layer GI is disposed on the buffer layer BUF.

[0030] like Figure 3 As shown, the portion of the display panel DP located in the peripheral area PA includes a metal trace ML disposed on the gate insulating layer GI, a first insulating layer (interlayer insulating layer) ILD disposed on the metal trace ML and the gate insulating layer GI, a plurality of metal pads BP disposed on the first insulating layer ILD, a bezel portion CP disposed on the metal pads BP and the first insulating layer ILD, a second insulating layer (touch insulating layer) TPIL disposed on the bezel portion CP and the first insulating layer ILD, and an overlapping metal piece CM disposed on the second insulating layer TPIL and the metal pads BP.

[0031] A metal trace ML is disposed on the gate insulating layer GI, and the metal trace ML is located on the first metal layer. A first insulating layer ILD is disposed on the metal trace ML and the gate insulating layer GI, and the first insulating layer ILD is made of silicon dioxide material.

[0032] A metal pad BP is disposed on a first insulating layer ILD. The metal pad BP includes a first metal electrode ME1 disposed on the first insulating layer ILD and a second metal electrode ME2 disposed on the first metal electrode ME1. The first metal electrode ME1 is located in a second metal layer, and the second metal electrode ME2 is located in a third metal layer. The second metal electrode ME2 is disposed on the surface (top surface) and circumferential surface (side surface) of the first metal electrode ME1 away from the first insulating layer ILD along the thickness direction of the display panel DP, and the second metal electrode ME2 covers the first metal electrode ME1. The first metal electrode ME1 is electrically connected to a metal trace ML through a through-hole penetrating the first insulating layer ILD. The material of the second metal electrode ME2 includes at least one of titanium, aluminum, and molybdenum. The material of the first metal electrode ME1 includes at least one of titanium, aluminum, and molybdenum. The top layer of the second metal electrode ME2 includes a titanium layer.

[0033] The edge-binding portion CP is disposed on the metal pad BP and the first insulating layer ILD. The edge-binding portion CP covers at least a portion of the surface (top surface) of the metal pad BP away from the first insulating layer ILD along the thickness direction of the display panel DP, and the circumferential surface (side surface) of the metal pad BP. The edge-binding portion CP covers at least a portion of the surface (top surface) of the second metal electrode ME2 away from the first insulating layer ILD along the thickness direction of the display panel DP, the circumferential surface (side surface) of the second metal electrode ME2, and the circumferential surface (side surface) of the first metal electrode ME1. The edge-binding portion CP is made of the material of the pixel defining layer PDL, and the material of the pixel defining layer PDL is an organic material. The portion of the edge-binding portion CP located between two adjacent metal pads BP is provided with a first perforation H1 penetrating the film layer on which the edge-binding portion CP is located, and the first perforation H1 exposes the first insulating layer ILD. The first perforation H1 separates the edge-binding portions CP located on two adjacent metal pads BP, so that the edge-binding portions CP located on two adjacent metal pads BP are disconnected and not connected to each other. From a top-view perspective of the display panel DP, the bezel portion CP and the metal trace ML at least partially overlap, and the overlapping portion of the bezel portion CP and the metal trace ML is OL. From a top-view perspective of the display panel DP, the width of the overlapping portion OL of the bezel portion CP and the metal trace ML is between 2 micrometers and 15 micrometers. For example, the width of this overlapping portion OL is any value among 3 micrometers, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, 9 micrometers, 10 micrometers, 11 micrometers, 12 micrometers, 13 micrometers, and 14 micrometers.

[0034] The second insulating layer TPIL is disposed on the edge portion CP and the first insulating layer ILD. The second insulating layer TPIL is the insulating layer between the fourth and fifth metal layers of the touch device TP. A second hole H2 is provided in the portion of the second insulating layer TPIL located between two adjacent metal pads BP, penetrating the second insulating layer TPIL and exposing the first insulating layer ILD. From a top-view perspective of the display panel DP, the second hole H2 is located within the first hole H1. The width (radius of the smallest circumscribed circle) of the second hole H2 is less than or equal to the width (radius of the smallest circumscribed circle) of the first hole H1. Specifically, from a top-view perspective of the display panel DP, the radius of the smallest circumscribed circle of the first hole H1 is greater than the radius of the smallest circumscribed circle of the second hole H2.

[0035] A third hole H3 is provided on the portion of the edging portion CP and the second insulating layer TPIL located on the surface of the metal pad BP along the thickness direction of the display panel DP, away from the first insulating layer ILD. The third hole H3 exposes the metal pad BP. The third hole H3 exposes at least a portion of the surface of the second metal electrode ME2 along the thickness direction of the display panel DP, away from the first insulating layer ILD. In a top view of the display panel DP, the distance D between the edge D of the portion of the edging portion CP located on the metal pad BP and the edge of the metal pad BP is greater than one-third of the radius R of the smallest circumscribed circle of the third hole H3.

[0036] The lap metal component CM is disposed within the third cutout H3 and on the second insulating layer TPIL. The lap metal component CM is disposed on the bottom surface and sidewall of the third cutout H3, and contacts the sidewall of the edge portion CP within the third cutout H3. The lap metal component CM is electrically connected to the metal pad BP. The lap metal component CM is electrically connected to the surface of the second metal electrode ME2 along the thickness direction of the display panel DP, away from the first insulating layer ILD. The lap metal component CM is located in the fifth metal layer.

[0037] By providing a bezel CP on the metal pad BP and the first insulating layer ILD, the bezel CP covers at least a portion of the surface of the second metal electrode ME2 away from the first insulating layer ILD along the thickness direction of the display panel DP, the circumferential surface of the second metal electrode ME2, and the circumferential surface of the first metal electrode ME1, thus protecting the circumferential surface of the metal pad BP. The bezel CP covers both the surface of the metal pad BP away from the first insulating layer ILD along the thickness direction of the display panel DP and the circumferential surface, preventing the formation of metal filament residue on the circumferential surface of the metal pad BP and avoiding electrical faults such as short circuits caused by such residue. The bezel CP also covers the circumferential surface of the metal pad BP, preventing excessive etching of the circumferential surface of the metal pad BP during manufacturing and maintaining the regular contour of the circumferential surface of the metal pad BP. The bezel CP covers at least a portion of the surface of the second metal electrode ME2 away from the first insulating layer ILD along the thickness direction of the display panel DP, pressing the second metal electrode ME2 and preventing the top titanium layer of the second metal electrode ME2 from lifting during manufacturing.

[0038] By creating a first perforation H1 in the portion of the edge banding CP located between two adjacent metal pads BP, and a second perforation H2 in the portion of the second insulating layer TPIL located between two adjacent metal pads BP, both the edge banding CP and the second insulating layer TPIL are removed between the two adjacent metal pads BP, directly exposing the first insulating layer ILD. Between the two adjacent metal pads BP, there is no interface between the edge banding CP and the first insulating layer ILD, nor between the second insulating layer TPIL and the first insulating layer ILD, thus avoiding the problem of peeling due to weak adhesion between the edge banding CP and the first insulating layer ILD, and between the second insulating layer TPIL and the first insulating layer ILD.

[0039] like Figure 2 As shown, the portion of the display panel DP located in the display area AA provided in the embodiments of this application includes a substrate PI, a buffer layer BUF disposed on the substrate PI, a semiconductor layer disposed on the buffer layer BUF, a gate insulating layer GI disposed on the semiconductor layer and the buffer layer BUF, a first metal layer disposed on the gate insulating layer GI, a first insulating layer ILD disposed on the first metal layer, a second metal layer and a third metal layer disposed on the first insulating layer ILD, a planarization layer PLN disposed on the third metal layer, an anode disposed on the planarization layer PLN, a pixel defining layer PDL disposed on the planarization layer PLN, an organic light emitting layer EL disposed within the pixel light emitting area defined by the pixel defining layer PDL, a cathode disposed on the organic light emitting layer EL, an encapsulation layer TFE disposed on the cathode, a touch device TP disposed on the encapsulation layer TFE, a light shielding layer BM disposed on the touch device TP, a color filter layer CF disposed on the touch device TP, an optical adhesive layer OCA disposed on the light shielding layer BM and the color filter layer CF, and a cover glass CG disposed on the optical adhesive layer OCA.

[0040] A semiconductor layer is disposed on the buffer layer BUF, and the material of the semiconductor layer is low-temperature polycrystalline silicon or oxide semiconductor. A gate insulating layer GI is disposed on the semiconductor layer and the buffer layer BUF, and the gate insulating layer GI is located between the semiconductor layer and the first metal layer. A first metal layer is disposed on the gate insulating layer GI, and the first metal layer forms the gate of the thin-film transistor (TFT). The first metal layer also includes a gate line and the aforementioned metal trace ML, and the first metal layer is made of molybdenum or aluminum. A first insulating layer ILD is disposed on the first metal layer, and the first insulating layer ILD is located between the first metal layer and the second metal layer. A second metal layer is disposed on the first insulating layer ILD, and the second metal layer forms the source, drain, and the aforementioned first metal electrode ME1 of the thin-film transistor (TFT). The second metal layer is made of molybdenum or aluminum. A third metal layer is disposed on the first insulating layer ILD, and the third metal layer forms the aforementioned second metal electrode ME2. The third metal layer is made of molybdenum or aluminum.

[0041] A planarization layer (PLN) is disposed on the third metal layer. The PLN is used to planarize the step height of the underlying layer and is made of organic material. An anode is disposed on the PLN. A pixel boundary layer (PDL) is disposed on the PLN, defining the pixel light-emitting region. An anode and an organic light-emitting layer (EL) are disposed within the pixel light-emitting region defined by the PDL. The EL includes a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The pixel light-emitting regions include red, green, and blue regions. The light-emitting layer corresponding to the red region emits red light, the light-emitting layer corresponding to the green region emits green light, and the light-emitting layer corresponding to the blue region emits blue light. A cathode is disposed on the EL.

[0042] The TFE encapsulation layer is disposed in the display area AA and the peripheral area PA. The TFE encapsulation layer is disposed on the cathode and includes alternating inorganic and organic encapsulation layers. The inorganic encapsulation layer is made of silicon nitride or silicon oxide, and the organic encapsulation layer is made of acrylic resin.

[0043] The touch device TP is disposed on the encapsulation layer TFE. The touch device TP includes a fourth metal layer and a fifth metal layer, and the second insulating layer TPIL is located between the fourth metal layer and the fifth metal layer. The lap metal component CM is located on the fifth metal layer and is electrically connected to the metal pad BP.

[0044] A light-shielding layer BM is disposed on the touch device TP. The light-transmitting area of ​​the light-shielding layer BM corresponds to the position of the organic light-emitting layer EL, and the light-shielding area of ​​the light-shielding layer BM corresponds to the position of the pixel delimiting layer PDL. The light-shielding layer BM is a black matrix layer. A color filter layer CF is disposed on the touch device TP. The color filter layer CF is located in the light-transmitting area of ​​the light-shielding layer BM. The color filter layer CF and the light-shielding layer BM together act as a polarizer. An optical adhesive layer OCA is disposed on the light-shielding layer BM and the color filter layer CF. The optical adhesive layer OCA is used to bond the color filter layer CF and the light-shielding layer BM to the cover glass CG. The cover glass CG is disposed on the optical adhesive layer OCA.

[0045] The portion of the display panel DP located in the display area AA includes the pixel delimiting layer (PDL), and the edge-capping portion (CP) is located on the same film layer as the pixel delimiting layer (PDL). The edge-capping portion (CP) and the pixel delimiting layer (PDL) are made of the same material and are formed in the same process step.

[0046] The display panel DP provided in the embodiments of this application can be, for example, a display panel without a polarizer. By setting a light-shielding layer BM and a color filter layer CF on the touch device TP, the light-shielding layer BM and the color filter layer CF together act as a polarizer, thus realizing a display panel without a polarizer.

[0047] The display device DA also includes a timing controller, and the display panel DP also includes a gate driving circuit, multiple scan lines, and multiple data lines. The timing controller is electrically connected to the gate driving circuit and the driver chip DIC; the scan lines are electrically connected to the gate driving circuit and the pixel units; and the data lines are electrically connected to the pixel units. The timing controller sends gate control signals to the gate driving circuit and data control signals to the driver chip DIC. The gate driving circuit outputs scan signals to the scan lines according to the gate control signals, and the driver chip DIC outputs data signals to the data lines according to the data control signals.

[0048] The display device DA provided in the embodiments of this application includes a driver chip DIC and the aforementioned display panel DP. The pins of the driver chip DIC are electrically connected to the metal pad BP. The driver chip DIC drives and controls the display panel DP by electrically connecting its pins to the metal pad BP. The method by which the driver chip DIC is electrically connected to the metal pad BP is a thin-film chip packaging method.

[0049] In the embodiments of this application, by providing a first hole H1 and a second hole H2 between two adjacent metal pads BP, the edge portion CP and the second insulating layer TPIL between the two adjacent metal pads BP are removed, allowing the first insulating layer ILD to be directly exposed, thus avoiding the problem of peeling between the first insulating layer ILD and the edge portion CP, and between the first insulating layer ILD and the second insulating layer TPIL. By providing the edge portion CP on the metal pad BP, the edge portion CP covers at least a portion of the surface of the metal pad BP away from the first insulating layer ILD along the thickness direction of the display panel DP and the circumferential surface of the metal pad BP, preventing the formation of metal wire residue on the circumferential surface of the metal pad BP, preventing the circumferential surface of the metal pad BP from being over-etched during the manufacturing process, and preventing the top titanium layer of the second metal electrode ME2 from lifting during the manufacturing process.

[0050] In one embodiment, the metal pad BP includes a first metal electrode ME1 disposed on a first insulating layer ILD and a second metal electrode ME2 disposed on the first metal electrode ME1, with the second metal electrode ME2 covering the first metal electrode ME1. A bezel CP covers at least a portion of the surface of the second metal electrode ME2 away from the first insulating layer ILD along the thickness direction of the display panel DP, the circumferential surface of the second metal electrode ME2, and the circumferential surface of the first metal electrode ME1. The second metal electrode ME2 completely covers the surface of the first metal electrode ME1 away from the first insulating layer ILD along the thickness direction of the display panel DP and the circumferential surface, forming a good electrical connection between the second metal electrode ME2 and the first metal electrode ME1. The bezel CP covers the circumferential surfaces of the second metal electrode ME2 and the first metal electrode ME1, providing comprehensive protection for the circumferential surface of the metal pad BP, preventing corrosion of the circumferential surface of the metal pad BP by etching solution during manufacturing, and preventing the formation of metal wire-like residues on the circumferential surface of the metal pad BP.

[0051] In one embodiment, the metal pad BP includes a first metal electrode ME1 disposed on a first insulating layer ILD and a second metal electrode ME2 disposed on the first metal electrode ME1. The second metal electrode ME2 is disposed on the surface of the first metal electrode ME1 away from the first insulating layer ILD along the thickness direction of the display panel DP and on the circumferential surface. A bezel CP covers at least a portion of the surface of the second metal electrode ME2 away from the first insulating layer ILD along the thickness direction of the display panel DP and the circumferential surface of the second metal electrode ME2. The second metal electrode ME2 is disposed on the surface of the first metal electrode ME1 away from the first insulating layer ILD along the thickness direction of the display panel DP and on the circumferential surface, and the second metal electrode ME2 covers the first metal electrode ME1, forming a good electrical connection between the second metal electrode ME2 and the first metal electrode ME1. The bezel CP covers the circumferential surface of the second metal electrode ME2, protecting the circumferential surface of the metal pad BP, preventing the circumferential surface of the second metal electrode ME2 from being corroded by etching solution during manufacturing, and preventing the formation of metal wire residue on the circumferential surface of the second metal electrode ME2.

[0052] In one embodiment, the area of ​​the edge portion CP covering the surface of the second metal electrode ME2 away from the first insulating layer ILD along the thickness direction of the display panel DP accounts for 10% to 50% of the total area of ​​the surface of the second metal electrode ME2 away from the first insulating layer ILD along the thickness direction of the display panel DP. For example, the area of ​​the edge portion CP covering the surface of the second metal electrode ME2 away from the first insulating layer ILD along the thickness direction of the display panel DP accounts for 20% to 40% of the total area of ​​the surface of the second metal electrode ME2 away from the first insulating layer ILD along the thickness direction of the display panel DP. Specifically, the area of ​​the edge portion CP covering the surface of the second metal electrode ME2 away from the first insulating layer ILD along the thickness direction of the display panel DP accounts for any value among 15%, 20%, 25%, 30%, 35%, 40%, and 45% of the total area of ​​the surface of the second metal electrode ME2 away from the first insulating layer ILD along the thickness direction of the display panel DP. Preferably, the area of ​​the edge portion CP covering the surface of the second metal electrode ME2 away from the first insulating layer ILD along the thickness direction of the display panel DP accounts for 30% of the total area of ​​the surface of the second metal electrode ME2 away from the first insulating layer ILD along the thickness direction of the display panel DP.

[0053] In one embodiment, the width of the first punch hole H1 is from 5 micrometers to 30 micrometers. The width of the second punch hole H2 is from 3 micrometers to 25 micrometers. For example, the width of the first punch hole H1 is any value among 6 micrometers, 8 micrometers, 10 micrometers, 12 micrometers, 15 micrometers, 18 micrometers, 20 micrometers, 22 micrometers, 25 micrometers, and 28 micrometers. The width of the second punch hole H2 is any value among 4 micrometers, 6 micrometers, 8 micrometers, 10 micrometers, 12 micrometers, 14 micrometers, 16 micrometers, 18 micrometers, 20 micrometers, and 22 micrometers.

[0054] In one embodiment, the thickness of the edging portion CP is from 0.5 micrometers to 3 micrometers. For example, the thickness of the edging portion CP is any value among 0.6 micrometers, 0.8 micrometers, 1 micrometer, 1.2 micrometers, 1.5 micrometers, 1.8 micrometers, 2 micrometers, 2.2 micrometers, 2.5 micrometers, and 2.8 micrometers.

[0055] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display panel, characterized by, The display panel includes a display panel including a display area and a peripheral area, a portion of the display panel located in the peripheral area includes: a first insulating layer; a plurality of metal pads disposed on the first insulating layer; a border portion disposed on the metal pads and the first insulating layer, a portion of the border portion located between two adjacent metal pads is provided with a first hole penetrating through a film layer where the border portion is located, and the first hole exposes the first insulating layer; and a second insulating layer disposed on the border portion and the first insulating layer, a portion of the second insulating layer located between two adjacent metal pads is provided with a second hole penetrating through the second insulating layer, and the second hole exposes the first insulating layer.

2. The display panel of claim 1, wherein, The border portion covers at least a portion of a surface of the metal pad away from a surface of the first insulating layer in a thickness direction of the display panel and a circumferential surface of the metal pad.

3. The display panel of claim 2, wherein, The metal pad includes a first metal electrode disposed on the first insulating layer and a second metal electrode disposed on the first metal electrode, and the second metal electrode covers the first metal electrode; The border portion covers at least a portion of a surface of the second metal electrode away from a surface of the first insulating layer in a thickness direction of the display panel, a circumferential surface of the second metal electrode, and a circumferential surface of the first metal electrode.

4. The display panel of claim 2, wherein, The metal pad includes a first metal electrode disposed on the first insulating layer and a second metal electrode disposed on the first metal electrode, and the second metal electrode is disposed on a surface of the first metal electrode away from a surface of the first insulating layer in a thickness direction of the display panel and a circumferential surface of the first metal electrode; The border portion covers at least a portion of a surface of the second metal electrode away from a surface of the first insulating layer in a thickness direction of the display panel and a circumferential surface of the second metal electrode.

5. The display panel of claim 1, wherein, A portion of the display panel located in the display area includes a pixel definition layer, and the border portion is located in a film layer where the pixel definition layer is located.

6. The display panel of claim 1, wherein, In a perspective view of the display panel, the second hole is located in the first hole.

7. The display panel of claim 1, wherein, The border portion and the second insulating layer are provided with a third hole penetrating through the border portion and the second insulating layer at a portion of the metal pad away from a surface of the first insulating layer in a thickness direction of the display panel, and the third hole exposes the metal pad; The portion of the display panel located in the peripheral area further includes: a lapping metal piece disposed in the third hole and on the second insulating layer, and the lapping metal piece is electrically connected with the metal pad.

8. The display panel of claim 7, wherein, In a perspective view of the display panel, a distance between an edge of a portion of the border portion located on the metal pad and an edge of the metal pad is greater than one third of a radius of a minimum circumscribed circle of the third hole.

9. The display panel of claim 1, wherein, The portion of the display panel located in the peripheral area further includes: a gate insulating layer; and a metal trace disposed on the gate insulating layer; The first insulating layer is disposed on the metal trace and the gate insulating layer, and the metal pad is electrically connected with the metal trace through a via hole penetrating through the first insulating layer; In a perspective view of the display panel, the edge covering portion at least partially overlaps the metal trace.

10. A display device, characterized by comprising: The display device comprises a driving chip and the display panel as claimed in any one of claims 1 to 9, and a pin of the driving chip is electrically connected with the metal pad.

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