Preparation method of semiconductor structure
By etching carbon-based semiconductor structures to form spacer grooves and control the source/drain and gate spacing, the problem of improving integration density is solved, achieving higher integration density and process reliability.
Patent Information
- Application Number
- CN202511595902.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-04
- Publication Date
- 2026-02-03
AI Technical Summary
Existing technologies struggle to achieve increased integration density when fabricating carbon-based semiconductor devices on a large scale, failing to meet the demands of 5nm and smaller node technologies.
By etching the functional structure layer to form a first and second groove spaced apart, and etching a third groove in between, the spacing between the source, drain and gate is controlled, the gate size is reduced and the integration density is increased.
This improved alignment accuracy, reduced the sidewall thickness between the gate and source/drain regions, enhanced the integration effect of the semiconductor structure, and improved the reliability and integration density of the process.
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Figure CN121463697A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a preparation method of semiconductor structure BACKGROUND
[0002] At present, the feature size of the key pattern of advanced silicon-based integrated circuit device has crossed the 10nm threshold, and when the transistor continues to develop to the 5nm or even smaller node technology, it is foreseeable that the silicon-based semiconductor technology is facing challenges from processing technology, device physical limit, performance, etc., and its further development must overcome the huge obstacles of power consumption, cost, etc., and the development space also has the trend of becoming smaller and smaller, so it is urgent to find new information devices to continue to promote the development of future semiconductor industry.
[0003] At present, carbon nanotubes have attracted a lot of attention and exploration from the academic and industrial circles due to their excellent carrier mobility, ultra-high carrier saturation speed and other electrical advantages, although the laboratory preparation of carbon-based devices has even exceeded the performance of the same node silicon-based semiconductor devices, but there are still many problems in large-scale preparation. For example, how to further improve the integration density in large-scale preparation. SUMMARY
[0004] In view of the deficiencies of the prior art, the present application provides a preparation method of semiconductor structure for improving the integration density during the preparation of carbon-based semiconductor.
[0005] The present application provides a preparation method of semiconductor structure, comprising: providing a substrate, sequentially forming a semiconductor layer, a work function layer and a functional structure layer on the substrate; etching the functional structure layer and the work function layer and stopping on the semiconductor layer to form a first groove and a second groove arranged at intervals, etching the functional structure layer between the first groove and the second groove and stopping on the work function layer to form a third groove; depositing a conductive material in the first groove and the second groove to form a source and a drain, respectively, and depositing a gate dielectric layer and a gate stack structure in the third groove to form a gate.
[0006] In one embodiment, the functional structure layer comprises a first sacrificial layer, a first mask layer, a second sacrificial layer and a second mask layer which are sequentially stacked.
[0007] In an embodiment, the etching the functional structure layer and the work function layer and stopping at the semiconductor layer to form the first recess and the second recess comprises: etching the second sacrificial layer through the second mask layer to form a plurality of transition recesses arranged in sequence at a preset distance apart in the second sacrificial layer; depositing an isolation layer with a preset thickness in the second sacrificial layer and the transition recesses; etching the isolation layer and the second sacrificial layer to form a plurality of isolation columns arranged in sequence at a preset distance apart on the first mask layer; etching the plurality of isolation columns and the first mask layer to form a plurality of mask columns arranged in sequence at a preset distance apart on the first sacrificial layer; etching the first sacrificial layer and the work function layer between two adjacent mask columns to form the first recess and the second recess arranged at a preset distance apart, and depositing a contact metal in the first recess and the second recess.
[0008] In an embodiment, the isolation layer comprises a first isolation part arranged in a horizontal direction on the second sacrificial layer and the bottom of the transition recess, and a second isolation part arranged in a vertical direction on the sidewall of the transition recess, and the etching the second sacrificial layer and the isolation layer to form a plurality of isolation columns arranged in sequence on the first mask layer comprises: removing the first isolation part and the second sacrificial layer to obtain the second isolation part arranged in a vertical direction, and the second isolation part is the isolation column.
[0009] In an embodiment, the mask column and the isolation column have the same vertical position, and the etching the plurality of isolation columns and the first mask layer to form a plurality of mask columns arranged in sequence on the first sacrificial layer comprises: removing the isolation column and part of the first mask layer to form the mask column with the same width as the isolation column at the position of the isolation column.
[0010] In an embodiment, the first recess and the second recess have a horizontal width less than or equal to the distance between two adjacent mask columns.
[0011] In an embodiment, the contact metal covers the first recess, the second recess, the first sacrificial layer, and the mask column, and abuts against the semiconductor layer at the bottom of the first recess and the bottom of the second recess.
[0012] In an embodiment, the semiconductor layer is one of a semiconductor type carbon nanotube film, a graphene nanoribbon, molybdenum disulfide, tungsten disulfide, black phosphorus, germanium, or a composite layer of any two of the above.
[0013] In an embodiment, the etching the functional structure layer between the first recess and the second recess and stopping at the work function layer to form a third recess comprises: filling a protection layer in the first recess and the second recess; etching to form the third recess between the first recess and the second recess; and removing the mask column and the protection layer.
[0014] In an embodiment, the first sacrificial layer further comprises a plurality of side walls, which are arranged between the third recess and the first recess, and between the third recess and the second recess.
[0015] In an embodiment, the plurality of mask columns comprises a first mask column, a second mask column and a third mask column, which are arranged in sequence along a horizontal direction. An exposure area is arranged on a side of the first mask column away from the second mask column, for etching the first sacrificial layer and the work function layer to form the first recess. An exposure area is arranged on a side of the second mask column away from the first mask column, for etching the first sacrificial layer and the work function layer to form the second recess. An exposure area is arranged between the first mask column and the second mask column, for etching the first sacrificial layer to form the third recess.
[0016] Compared with the prior art, the method for manufacturing a semiconductor structure provided by the embodiments of the present application can form a first recess and a second recess arranged at a preset distance by etching a functional structure layer, and form a third recess by etching the functional structure layer between the first recess and the second recess, thereby forming a semiconductor structure. By controlling the width between the first recess and the second recess, the width of the third recess formed subsequently can be effectively controlled. By controlling the interval between the source, the drain and the gate, the thickness of the side wall between the source, the drain and the gate can be reduced, thereby reducing the size of the gate and improving the integration effect of the semiconductor structure.
[0017] Figure 1 A flowchart of a method for manufacturing a semiconductor structure is provided in the embodiments of the present application.
[0018] Figure 2 A schematic diagram of a deposition structure before manufacturing a semiconductor structure is provided.
[0019] Figure 3 A flowchart of a method for etching a functional structure layer is provided.
[0020] Figure 4 A schematic diagram of a transition recess is provided.
[0021] Figure 5 A schematic diagram of an isolation layer is provided.
[0022] Figure 6 Structure diagram of the isolation column;
[0023] Figure 7 Structure diagram of the mask column;
[0024] Figure 8 Structure diagram of the first sacrificial layer and work function layer etching process;
[0025] Figure 9 Structure diagram of the contact metal deposition;
[0026] Figure 10 Structure diagram of the third groove manufacturing process;
[0027] Figure 11 Structure diagram of the third groove manufacturing process;
[0028] Figure 12 Structure diagram of the semiconductor device. DETAILED DESCRIPTION
[0029] In order to facilitate the understanding of the present application, the present application will be described in more detail below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0030] The following description of the embodiments is made with reference to the accompanying drawings, which illustrate specific embodiments in which the present application can be implemented. The serial numbers of the components in this paper, such as "first", "second", etc., are only used to distinguish the described objects, and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present application, unless otherwise specified, include direct and indirect connections (couplings). The direction terms mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side" and the like, are only with reference to the direction of the accompanying drawings, therefore, the direction terms used are for better, clearer description and understanding of the present application, and are not indicative or implied that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore, it cannot be understood as a limitation on the present application.
[0031] In the description of the present application, it is necessary to point out that, unless otherwise explicitly specified and limited, the terms "mount", "connect", "connection" should be understood in a broad sense, for example, can be fixedly connected, or can be detachably connected, or integrally connected, can be mechanically connected, can be directly connected, or indirectly connected through an intermediate medium, can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. It should be pointed out that the terms "first", "second" and the like in the specification and claims of the present application and the drawings are used to distinguish different objects, and are not used to describe a specific order.
[0032] In addition, the terms "include", "may include", "contain" or "may contain" used in the present application represent the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit other one or more functions, operations, elements, etc. In addition, the term "include" or "contain" means the existence of the corresponding features, numbers, steps, operations, elements, components or combinations thereof disclosed in the specification, and does not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components or combinations thereof, and is intended to cover non-exclusive inclusion. In addition, when describing the embodiments of the present application, "may" is used to represent "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.
[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments of the present application, and are not intended to limit the present application.
[0034] Please refer to Figure 1 , Figure 1 A flow chart of a method for manufacturing a semiconductor structure is provided for the embodiments of the present application.
[0035] As Figure 1 shown, the method for manufacturing a semiconductor structure 100 comprises:
[0036] Step S101, providing a substrate, and sequentially forming a semiconductor layer, a work function layer and a functional structure layer on the substrate.
[0037] As Figure 2 shown, Figure 2 is a schematic diagram of a deposition structure before manufacturing a semiconductor structure 100.
[0038] The substrate 101, the semiconductor layer 102 and the work function layer 103 are sequentially stacked, wherein the substrate 101 can be a semiconductor material, a hard insulating material or a high-temperature-resistant flexible insulating material, the semiconductor material is silicon, silicon-on-insulator (SOI), SiC, InAs, a III-V group material, a II-IV group material or other semiconductor materials, the insulating material is selected from silicon oxide, quartz, glass and aluminum oxide, and the high-temperature-resistant flexible insulating material is selected from polyethylene terephthalate (PET), polyethylene naphthalate (PEN) and polyimide. In this embodiment, the substrate 101 is a silicon substrate.
[0039] The band gap of the semiconductor layer 102 can be less than 1eV, and the semiconductor layer 102 can be one of a semiconductor carbon nanotube film, a graphene nanoribbon, molybdenum disulfide (MoS2), tungsten disulfide (WS2), black phosphorus (P), germanium (Ge) or a composite layer of any two of the above. In this embodiment, the semiconductor layer 102 is a carbon nanotube film.
[0040] In an embodiment, a dielectric layer (not shown) can be further provided between the support structure 101 and the semiconductor layer 102 for insulation between the semiconductor layers. The dielectric layer can be silicon oxide, silicon nitride, SiCN and other known or unknown dielectric insulating materials, which are not limited in this embodiment.
[0041] The work function layer 103 can be a P-type work function layer or an N-type work function layer, wherein the p-type work function material can be titanium nitride, the n-type work function material can be titanium aluminum carbide, and other materials can also be selected according to specific needs, which are not limited in this embodiment.
[0042] S102, etching the functional structure layer and stopping on the semiconductor layer to form a first groove and a second groove arranged at intervals, and etching the functional structure layer between the first groove and the second groove and stopping on the work function layer to form a third groove.
[0043] The functional structure layer 104 includes a first sacrificial layer 1041, a first mask layer 1042, a second sacrificial layer 1043 and a second mask layer 1044, wherein the functional structure layer is deposited on the work function layer 102, which includes sequentially depositing the first sacrificial layer 1041, the first mask layer 1042, the second sacrificial layer 1043 and the second mask layer 1044 on the work function layer 102.
[0044] In the embodiment, the first and second sacrificial layers 1041 and 1043, also referred to as mandrel layers, can be silicon nitride layers or polysilicon layers formed using chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD), and the first and second mask layers 1042 and 1044 can be hard masks formed of silicon oxide. The first mask layer 1042 can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition techniques.
[0045] In the exemplary embodiment, a photoresist layer (not shown) can be deposited over the second mask layer 1044 using spin coating, chemical vapor deposition, or other similar processes. The photoresist layer can include a bottom layer (not shown), a middle layer (not shown), and a top layer (not shown). The bottom and top layers can be formed of photosensitive materials, such as organic materials, and the middle layer can include inorganic materials, such as nitride, oxynitride, oxide, or the like. In some embodiments, the photoresist layer can also be a single layer or a bilayer structure.
[0046] Referring to Figure 3 , Figure 3 a flowchart of the etching method for the functional structure layer is shown.
[0047] As shown in Figure 3 , the functional structure layer 104 and the work function layer 103 are etched to form the first and second recesses G1 and G2 that stop at the semiconductor layer 102. The specific steps are as follows:
[0048] In step S1, the second sacrificial layer is etched through the second mask layer to form a plurality of transition recesses arranged at a predetermined distance from each other in the second sacrificial layer.
[0049] Specifically, as shown in Figure 4 , Figure 4 is a structural schematic diagram of the transition recesses. The second mask layer 1044 is etched through the patterned photoresist layer (not shown) to form a patterned second mask layer 1044, i.e., the pattern of the photoresist layer is transferred to the second mask layer 1044. The etching process can include dry etching processes (e.g., reactive ion etching), wet etching processes, other suitable etching processes, or combinations thereof. After the etching of the second mask layer 1044 is completed, the patterned photoresist layer can be removed by ashing or suitable methods.
[0050] After forming the patterned second mask layer 1044, the second sacrificial layer 1043 is etched to form a plurality of spaced transition grooves G on the second sacrificial layer 1043. Then, the second mask layer 1044 is removed by wet etching. The etching process for the second sacrificial layer 1043 can be a dry etching process (e.g., reactive ion etching (RIE)), a wet etching process, other suitable etching processes, or a combination thereof. After the second sacrificial layer 1043 is etched, the patterned second mask layer 1044 can be removed, leaving the second sacrificial layer 1043 including the plurality of transition grooves G.
[0051] Step S2: Deposit an isolation layer of a predetermined thickness in the second sacrificial layer and the transition groove.
[0052] like Figure 5 As shown, Figure 5 This is a schematic diagram of the isolation layer structure. Specifically, the isolation layer 105 covers the first mask layer 1042 and the second sacrificial layer 1043, that is, it covers the first mask layer 1042 and the transition groove G. The isolation layer 105 includes a first isolation portion 1051 disposed along a first direction F1 (horizontal direction) at the bottom of the second sacrificial layer 1043 and the transition groove G, and a second isolation portion 1052 disposed along a second direction F2 (vertical direction) on the inner wall of the transition groove G. Adjacent first isolation portions 1051 and second isolation portions 1052 abut against each other; that is, the isolation layer 105 is continuously disposed along the transition groove G formed by the second sacrificial layer 1043. In this embodiment, the isolation layer 105 can be fabricated using atomic layer deposition (ALD) technology.
[0053] Step S3: Etch the second sacrificial layer and the isolation layer to form a plurality of isolation pillars located on the first mask layer and spaced apart in sequence.
[0054] like Figure 6 As shown, Figure 6 This is a schematic diagram of the isolation pillar structure. Specifically, the isolation layer 105 and the second sacrificial layer 1043 are etched to form a plurality of isolation pillars 106 (second isolation parts 1052) arranged in sequence at intervals. That is, the first isolation part 1051 and the second sacrificial layer 1043 in the isolation layer 105 are removed by the etching process to obtain the second isolation part 1052 disposed on the side wall of the transition groove G. The plurality of isolation pillars 106 are arranged in sequence at a preset distance.
[0055] Step S4: Etch multiple isolation pillars and the first mask layer to form multiple mask pillars located on the first sacrificial layer and arranged at intervals in sequence.
[0056] like Figure 7 As shown, Figure 7This is a schematic diagram of the mask pillar structure. Specifically, multiple isolation pillars 106 and the first mask layer 1042 are etched using an etching process to remove the isolation pillars 106 and the area of the first mask layer 1042 outside the isolation pillars 106, so as to form multiple mask pillars 107 located in the first sacrificial layer 1041 at positions corresponding to the isolation pillars 106 in the vertical direction.
[0057] Step S5: Etch the first sacrificial layer and the work function layer at preset positions according to the mask pillar to form a first groove and a second groove spaced apart, and deposit contact metal in the first groove and the second groove.
[0058] like Figure 8 and Figure 9 As shown, Figure 8 This is a schematic diagram of the etching process for the first sacrificial layer and the work function layer. Figure 9 This is a schematic diagram of contact metal deposition. Positioning is achieved using mask pillar 107 to set exposure areas at preset locations for etching the first sacrificial layer 1041 and the work function layer 103, forming a first groove 108a and a second groove 108b. The first groove 108a and the second groove 108b are separated by a portion of the first sacrificial layer 1041. The first groove 108a and the second groove 108b are used to deposit source and drain materials, respectively.
[0059] For example, the plurality of mask pillars 107 include a first mask pillar 107a, a second mask pillar 107b, and a third mask pillar 107c. The first mask pillar 107a, the second mask pillar 107b, and the third mask pillar 107c are arranged sequentially in a horizontal direction. An exposure area is set on the side of the first mask pillar 107a away from the second mask pillar 107b for etching the first sacrificial layer 1041 to form a first groove 108a. An exposure area is set on the side of the third mask pillar 107c away from the second mask pillar 107b for etching the first sacrificial layer 1041 to form a second groove 108b.
[0060] After forming the first groove 108a and the second groove 108b, contact metal 109 is deposited in the first groove 108a, the second groove 108b, the first sacrificial layer 1041, and the mask pillar 107, such that the contact metal 109 completely covers the region of the semiconductor layer 102 away from the substrate 101. The contact metal 109 is deposited in the first groove 108a and the second groove 108b for electrical connection with the semiconductor layer 108.
[0061] In this embodiment of the application, by adjusting the width of the transition groove G in step S1, the distance between the isolation pillars 106 can be controlled. Since the mask pillars 107 and the isolation pillars 106 are in the same position in the vertical direction, it is also equivalent to controlling the distance between the mask pillars 107. By controlling the distance between the mask pillars 107, the spacing between the third groove 108c and the first groove 108a and the second groove 108b can be effectively controlled. Therefore, the overlap area between the gate and the source / drain regions can be precisely controlled, thereby achieving the effect of reducing the gate capacitance.
[0062] like Figure 10 and Figure 11 As shown, Figure 10 This is a schematic diagram illustrating the manufacturing process of the third groove. Figure 11 A schematic diagram of the completed third groove is shown. The functional structure layer 104 between the first groove G1 and the second groove G2 is etched and stops at the work function layer 102 to form the third groove G3. Specifically, this includes filling the first groove 108a and the second groove 108b with a protective layer 110, and etching the gap between the first mask pillar 107a and the second mask pillar 107b to form the third groove 108c. The first groove 108a and the third groove 108c, and the second groove 108b and the third groove 108c are separated by a first sacrificial layer 1041 acting as a sidewall w. Then, the mask pillar 107 and the protective layer 110 in the first groove 108a and the second groove 108b are removed to obtain the first groove 108a and the second groove 108b for depositing source and drain materials, and the third groove 108c for depositing gate materials.
[0063] S103, conductive materials are deposited in the first and second grooves to form the source and drain respectively, and a gate dielectric layer and a gate stack structure are deposited in the third groove to form the gate.
[0064] like Figure 12 As shown, Figure 12 The diagram shows the structure of a semiconductor device. Source and drain materials are deposited in the first groove 108a and the second groove 108b to form the source s and drain d, respectively. A gate dielectric layer and gate material are deposited in the third groove 108c to form the gate, thereby constituting a semiconductor device T, or a transistor.
[0065] It can be understood that, for the convenience of description, the embodiment is described by a manufacturing method of a semiconductor device, and a plurality of semiconductor devices arranged adjacent to each other can be manufactured by the method of the embodiment on the same substrate 101 in a normal process production. In the embodiment, the source-drain region and the side wall of the gate (i.e., the first sacrificial layer 1041 between the first recess 108a, the second recess 108b, and the third recess 108c) are simultaneously formed by double exposure to form the source-drain and the gate. Due to the formation of the isolation column and the mask column, the alignment accuracy of the gate and the source-drain region is effectively improved, so that the spacing distance between the gate and the source-drain region can be more accurately controlled, thereby effectively reducing the gate capacitance, increasing the reliability of the process, and adjusting the size of the gate as needed by the method provided in the embodiment, thereby improving the integration density of the semiconductor device.
[0066] It should be understood that the application is not limited to the above examples, and those of ordinary skill in the art can make improvements or changes according to the above description, and all these improvements and changes shall belong to the protection scope of the appended claims of the application.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided on which a semiconductor layer, a work function layer and a functional structure layer are sequentially formed. The functional structure layer and the work function layer are etched and the etching stops at the semiconductor layer to form a first groove and a second groove spaced apart. The functional structure layer between the first groove and the second groove is etched and the etching stops at the work function layer to form a third groove. Conductive materials are deposited in the first and second grooves to form the source and drain, respectively, and a gate dielectric layer and gate material are deposited in the third groove to form the gate.
2. The method for preparing the semiconductor structure according to claim 1, characterized in that, The functional structure layer includes a first sacrificial layer, a first mask layer, a second sacrificial layer, and a second mask layer stacked sequentially.
3. The method for preparing the semiconductor structure as described in claim 2, characterized in that, The step of "etching the functional structure layer and the work function layer and stopping at the semiconductor layer to form a first groove and a second groove" includes: The second sacrificial layer is etched using the pattern of the second mask layer to form a plurality of transition grooves arranged sequentially at predetermined intervals in the second sacrificial layer; An isolation layer of predetermined thickness is deposited within the second sacrificial layer and the transition groove; The isolation layer and the second sacrificial layer are etched to form a plurality of isolation pillars located on the first mask layer and arranged at intervals in sequence; The plurality of isolation pillars and the first mask layer are etched to form a plurality of mask pillars located on the first sacrificial layer and arranged at intervals in sequence; The first sacrificial layer and the work function layer at a preset position are etched according to the mask pillar to form the first groove and the second groove that are spaced apart, and contact metal is deposited in the first groove and the second groove.
4. The method for preparing a semiconductor structure as described in claim 3, characterized in that, The isolation layer includes a first isolation portion stacked horizontally on the second sacrificial layer and the bottom of the transition groove, and a second isolation portion disposed vertically parallel to the sidewall of the transition groove. The phrase "etching the second sacrificial layer and the isolation layer to form a plurality of isolation pillars located on the first mask layer and spaced apart in sequence" includes: removing the first isolation portion and the second sacrificial layer to obtain a second isolation portion arranged in a vertical direction, wherein the second isolation portion is the isolation pillar.
5. The method for preparing a semiconductor structure as described in claim 4, characterized in that, The mask pillars and the isolation pillars are arranged correspondingly in the vertical direction. The step of "etching the plurality of isolation pillars and the first mask layer to form a plurality of mask pillars located on the first sacrificial layer and arranged sequentially at intervals" includes: removing the isolation pillars and part of the first mask layer to form a plurality of mask pillars at positions corresponding to the isolation pillars in the vertical direction.
6. The method for preparing a semiconductor structure as described in claim 5, characterized in that, The contact metal covers the first groove, the second groove, the first sacrificial layer, and the mask pillar, and abuts against the semiconductor layer at the bottom of the first groove and the bottom of the second groove.
7. The method for preparing a semiconductor structure as described in claim 6, characterized in that, The semiconductor layer is a composite layer consisting of one or a combination of semiconductor-type carbon nanotube thin films, graphene nanoribbons, molybdenum disulfide, tungsten disulfide, black phosphorus, and germanium.
8. The method for preparing a semiconductor structure according to any one of claims 3-7, characterized in that, The phrase "etching the functional structure layer between the first groove and the second groove and stopping at the work function layer to form the third groove" includes: A protective layer is filled into the first and second grooves; The third groove is formed by etching the first sacrificial layer between the first groove and the second groove; Remove the mask pillars and the protective layer.
9. The method for preparing a semiconductor structure as described in claim 8, characterized in that, The first sacrificial layer also includes a plurality of sidewalls, which are disposed between the third groove and the first groove, and between the third groove and the second groove.
10. The method for preparing the semiconductor structure according to claim 9, characterized in that, The plurality of mask pillars includes a first mask pillar, a second mask pillar, and a third mask pillar, which are arranged sequentially in a horizontal direction. An exposure area is provided on the side of the first mask pillar away from the second mask pillar for etching the first sacrificial layer and the work function layer to form the first groove. An exposure area is provided on the side of the second mask pillar away from the first mask pillar for etching the first sacrificial layer and the work function layer to form the second groove. An exposure area is provided between the first mask pillar and the second mask pillar for etching the first sacrificial layer to form the third groove.