Chitosan-based memristor, preparation method thereof and logic operation device

Abstract

The application relates to the technical field of memristor, and provides a chitosan-based memristor, which comprises, from bottom to top, a substrate, a buffer layer, a composite dielectric layer and a top electrode; the buffer layer is formed by heat treatment after PEDOT:PSS aqueous solution is spin-coated on the substrate; and the composite dielectric layer is formed by heat treatment after an ultrasonic composite solution formed by graphene oxide aqueous dispersion and chitosan acetic acid solution is spin-coated on the buffer layer. Through the synergistic architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT:PSS buffer layer, the prepared bio-based memristor has the effects of high switching, low operating voltage and good performance stability. Meanwhile, based on the stable high and low resistance states of the device, all seven basic logic operations including the non-gate, the and gate, the or gate, the not-and gate, the not-or gate, the exclusive or gate and the same or gate are completely realized on a single bio-based platform, the function correctness rate can reach 100%, and unexpected effects are achieved.

Description

Technical Field

[0001] This invention relates to the field of memristor technology, and in particular to a chitosan-based memristor, its preparation method, and a logic operation device. Background Technology

[0002] With the rapid development of artificial intelligence and big data technologies, the demands on computing systems for performance and energy efficiency are increasing daily. However, the traditional von Neumann computing architecture, due to the physical separation of storage and processing units, suffers from the memory wall problem, where frequent data transfer between the two leads to high energy consumption and low efficiency. Moreover, at the hardware level, traditional CMOS processes face physical limits such as increased quantum effects, soaring manufacturing complexity, and difficulty in controlling leakage power as device sizes continue to shrink.

[0003] Memristors, as a novel non-volatile device combining information storage and logic processing functions, have attracted widespread attention. Memristors can store information through non-volatile changes in their resistance state and directly execute logic operations using their resistance-state switching characteristics, potentially enabling the construction of a novel in-memory computing architecture and realizing low-power, highly integrated intelligent computing systems. In recent years, memristors based on natural biomaterials have become a research hotspot due to their unique advantages. These devices typically use natural polysaccharides, proteins, and DNA as functional media, offering advantages such as being environmentally friendly, biocompatible, having abundant raw material sources, and being low-cost. They also align with the concept of sustainable development, showing broad application prospects in fields such as biodegradable electronics and biomedical interfaces. For example, patent [CN202111485633.2] discloses a biodegradable memristor based on silk fibroin, verifying the feasibility of biomaterials in the field of information storage. Chitosan, a natural polysaccharide rich in amino and hydroxyl groups, is widely used in bio-memristor research due to its excellent charge trapping and ion migration capabilities. Patent [CN202110605703.7] proposes a memristor with a chitosan derivative as the dielectric layer, demonstrating its potential in simulating synaptic plasticity.

[0004] However, most reported bio-memristors generally suffer from problems such as low switching ratio, high operating voltage, insufficient resistive state retention characteristics, and poor inter-device consistency. These defects severely restrict their practical application in high-reliability logic circuits and large-scale integrated systems. Secondly, traditional top electrode fabrication methods (such as magnetron sputtering and thermal evaporation) usually involve high-energy particles or high-temperature processes, which can easily cause thermal damage or structural destruction to the heat-sensitive bio-medium layer, affecting device performance and yield. At the same time, existing research on bio-memristors is mostly focused on basic resistive switching characteristics or single synaptic simulation. There is still a lack of systematic technical solutions on how to use them to build complete digital logic circuit systems and further explore their potential in advanced functions such as multi-value storage and hierarchical control. For example, although flexible memristors (such as those described in patent [CN202011576186.7]) have been explored in the field of wearable devices, their focus is on mechanical adaptability, while they are insufficient in terms of environmental protection and logic function integration. As mentioned earlier, the unstable performance and high operating voltage of single chitosan-based memristors also limit their expansion into high-performance computing applications.

[0005] Therefore, it is of great significance to develop a memristor that not only possesses the advantages of green and environmentally friendly biomaterials, but also significantly improves electrical performance (such as high switching ratio, low operating voltage, and high stability) and can effectively realize various logic operations and even multi-level storage functions. Summary of the Invention

[0006] The purpose of this invention is to overcome the problems of low switching ratio, high operating voltage, and poor stability in existing bio-based memristors, and to provide a chitosan-based memristor, its preparation method, and a logic operation device. This memristor, through the synergistic architecture of a chitosan-graphene oxide composite dielectric layer and a PEDOT:PSS buffer layer, exhibits high switching ratio, low operating voltage, and good performance stability.

[0007] A first aspect of the present invention provides a chitosan-based memristor, comprising a substrate, a buffer layer, a composite dielectric layer and a top electrode stacked sequentially from bottom to top; The buffer layer is formed by spin-coating a PEDOT:PSS aqueous solution onto the substrate and then heat-treating it. The composite medium layer is formed by spin-coating an ultrasonic composite solution of graphene oxide aqueous dispersion and chitosan acetic acid solution onto the buffer layer and then heat-treating it.

[0008] This invention provides a chitosan-based memristor, comprising a substrate, a buffer layer, a composite dielectric layer, and a top electrode stacked sequentially from bottom to top. The buffer layer is formed by spin-coating a PEDOT:PSS aqueous solution onto the substrate followed by heat treatment. The composite dielectric layer is formed by spin-coating an ultrasonic composite solution of graphene oxide aqueous dispersion and chitosan acetic acid solution onto the buffer layer followed by heat treatment. By employing a synergistic architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT:PSS buffer layer, the prepared bio-based memristor exhibits high on / off ratio, low operating voltage, and good performance stability. Furthermore, the prepared memristor demonstrates excellent bipolar resistive switching characteristics, with an on / off ratio as high as 10. 3 Up to 10 4 The magnitudes are all below 2.0V, with the absolute values ​​of both Set / Reset voltages below 2.0V, and exhibiting over 10 at a read voltage of 0.1V. 4 The device maintains a persistent resistive state for seconds. Furthermore, based on the stable high and low resistance states of this device, all seven basic logic operations, including NOT, AND, OR, NAND, NOR, XOR, and XNOR gates, have been fully implemented on a single bio-based platform with a 100% accuracy rate, achieving unexpected results.

[0009] Furthermore, PEDOT:PSS is a composite material system consisting of two components: PEDOT: The full name is poly(3,4-ethylenedioxythiophene).

[0010] PSS stands for poly(styrene sulfonate).

[0011] Furthermore, the substrate is ITO glass, and the top electrode is a W probe.

[0012] Furthermore, the mass concentration of the PEDOT:PSS aqueous solution is 1.0% to 1.5%.

[0013] Furthermore, the mass concentration of the graphene oxide aqueous dispersion is 0.1% to 0.3%; and the mass concentration of the chitosan acetic acid solution is 1% to 2%.

[0014] Furthermore, in the ultrasonic composite solution, the volume ratio of the graphene oxide aqueous dispersion to the chitosan acetic acid solution is 0.5–2:1. Preferably, in the ultrasonic composite solution, the volume ratio of the graphene oxide aqueous dispersion to the chitosan acetic acid solution is 0.5–1:1.

[0015] A second aspect of the present invention provides a method for preparing the above-described chitosan-based memristor, comprising the following steps: PEDOT:PSS aqueous solution was spin-coated onto the substrate and heat-treated to form a buffer layer. An ultrasonic composite solution formed by an aqueous dispersion of graphene oxide and a chitosan acetic acid solution was spin-coated onto the buffer layer, and then heat-treated to form a composite medium layer. The top electrode is made into point contact with the surface of the composite dielectric layer.

[0016] Further details regarding the specific operation of the buffer layer: Spin-coat the PEDOT:PSS aqueous solution onto the substrate, first at a speed of 800-1000 rpm for 5-10 seconds, then at a speed of 3000-5000 rpm for 40-60 seconds; then heat at 80-100℃ for 5-10 minutes.

[0017] Furthermore, the specific operational process of the composite dielectric layer: The ultrasonic composite solution formed by the graphene oxide aqueous dispersion and the chitosan acetic acid solution was spin-coated onto the buffer layer. The solution was first rotated at a speed of 500-1000 rpm for 5-20 seconds, and then rotated at a speed of 2000-3000 rpm for 30-40 seconds. Subsequently, it was heated at 60-90 ℃ for 5-15 minutes.

[0018] A third aspect of the present invention provides a logic operation device comprising at least two chitosan-based memristors as described above or prepared by the above-described preparation method, wherein the at least two chitosan-based memristors are connected in a circuit to realize a logic gate function.

[0019] Based on the stable high and low impedance states of the device, all seven basic logic operations, including NOT, AND, OR, NAND, NOR, XOR, and XNOR, were fully implemented on a single bio-based platform with a 100% accuracy rate, achieving unexpected results.

[0020] Furthermore, the logic gate functions include at least one of NOT gate, AND gate, OR gate, NAND gate, and NOR gate; and / or, also include XOR gate and / or XNOR gate.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention provides a chitosan-based memristor, comprising a substrate, a buffer layer, a composite dielectric layer, and a top electrode stacked sequentially from bottom to top. The buffer layer is formed by spin-coating a PEDOT:PSS aqueous solution onto the substrate followed by heat treatment. The composite dielectric layer is formed by spin-coating an ultrasonic composite solution of graphene oxide aqueous dispersion and chitosan acetic acid solution onto the buffer layer followed by heat treatment. By employing a synergistic architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT:PSS buffer layer, the prepared bio-based memristor exhibits high on / off ratio, low operating voltage, and good performance stability.

[0022] Meanwhile, the fabricated memristor exhibits excellent bipolar resistive switching characteristics, with an on / off ratio as high as 10. 3 Up to 10 4 Quantity, V SET / V RESET The absolute values ​​are all below 2.0V, and exhibit more than 10 at a read voltage of 0.1V. 4 The device maintains a persistent resistive state for seconds. Furthermore, based on the stable high and low resistance states of this device, all seven basic logic operations, including NOT, AND, OR, NAND, NOR, XOR, and XNOR gates, have been fully implemented on a single bio-based platform with a 100% accuracy rate, achieving unexpected results. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the configuration of the memristor of the present invention.

[0024] Figure 2 The graph shows the IV characteristic test results of the memristors prepared for comparative examples 1-3.

[0025] Figure 3 The graph shows the IV characteristic test results of the memristors prepared in Examples 1-3.

[0026] Figure 4 The diagram shows the retention capability of the high and low resistance states of the memristor prepared in Example 1.

[0027] Figure 5 The graph shows the IV characteristics of the memristor prepared in Example 1 under four different Icc conditions.

[0028] Figure 6 This is a diagram showing the changing characteristics of a memristor circuit and the schematic of a NOT gate circuit.

[0029] Figure 7 This is a schematic diagram of an AND gate and a NAND gate circuit.

[0030] Figure 8 This is a schematic diagram of an OR gate and a NOR gate circuit.

[0031] Figure 9 This is a test diagram of an XOR gate and its resistance value.

[0032] Figure 10 Resistance diagram for NOR gates and their resistance values. Detailed Implementation

[0033] The present invention will now be described in further detail with reference to specific embodiments. However, this should not be construed as limiting the scope of the present invention to the following embodiments; all technologies implemented based on the content of the present invention fall within the scope of the present invention.

[0034] Unless otherwise specified, the use of terms such as "upper," "lower," "left," "right," "center," "inner," and "outer" to indicate orientation or positional relationships in the description of specific embodiments of the present invention is based on the orientation or positional relationships shown in the accompanying drawings, or the orientation or positional relationship in which the product / equipment / device is typically placed during use. These terms are merely for the purpose of facilitating the description of the present invention or simplifying the description in specific embodiments, enabling those skilled in the art to quickly understand the solution, and do not indicate or imply that a particular device / component / element must have a specific orientation, or be constructed and operated in a specific positional relationship. Therefore, they should not be construed as limitations on the present invention.

[0035] Furthermore, the use of terms such as "horizontal," "vertical," "suspended," and "parallel" does not imply that the corresponding device / component / element must be absolutely horizontal, vertical, suspended, or parallel, but rather that it can be slightly tilted or have a deviation. For example, "horizontal" merely means that its direction is more horizontal relative to "vertical," not that the structure must be completely horizontal, but that it can be slightly tilted. Alternatively, it can be simplified to mean that the corresponding device / component / element, when set in a "horizontal," "vertical," "suspended," or "parallel" direction, can have an error / deviation of ±10% relative to the corresponding direction, more preferably within ±8%, more preferably within ±6%, more preferably within ±5%, and more preferably within ±4%. As long as the corresponding device / component / element is within the error / deviation range, it can still achieve its function in the present invention.

[0036] Furthermore, the use of terms such as "first," "second," and "third" in terminology is merely for distinguishing descriptions of identical or similar components and should not be interpreted as emphasizing or implying the relative importance of a particular component.

[0037] Furthermore, in the description of the embodiments of the present invention, "several", "more than", and "a number of" represent at least two. The number can be any number, such as 2, 3, 4, 5, 6, 7, 8, or 9, and can even exceed nine.

[0038] Furthermore, in the description of the technical solution of this invention, unless otherwise explicitly specified / limited / restricted, the terms "set up," "install," "connect," "link," "provided with," "laid out," and "arranged" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to common connection methods in the art, such as welding, riveting, bolting, and threaded connections. Such connections can be mechanical, electrical, or communication connections; they can be direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components.

[0039] Memristors, as a new generation of non-volatile storage and computing units, have significant application potential in fields such as in-memory computing, neuromorphic computing, and brain-like intelligence. However, existing technical solutions still have some insurmountable shortcomings.

[0040] On the one hand, organic flexible memristors excel in mechanical flexibility and deformation adaptability, making them suitable for applications such as wearable electronics and flexible sensors. For example, existing patents have proposed achieving flexible resistive switching characteristics through liquid electrolytes and flexible packaging structures. However, the research focus of these devices is mainly on mechanical adaptability, with insufficient optimization of electrical performance. This results in low on / off ratios, high operating voltages, limited resistance retention capabilities, and a lack of application expansion at the logic circuit level, making it difficult to balance flexibility with high-performance computing requirements.

[0041] On the other hand, bio-based memristors have gradually gained attention due to their advantages of readily available, renewable, biodegradable, and environmentally friendly raw materials. Related research and patents have reported memristor devices based on natural polymers such as silk fibroin and chitosan, validating their potential in green electronics and information storage. However, existing bio-based memristors still suffer from problems such as insufficient resistance switching stability, poor inter-device consistency, relatively high operating voltage, and limited logic functionality, making it difficult to meet the practical needs of high-performance neuromorphic computing and low-power logic circuits.

[0042] In summary, existing technologies have made some progress in both the direction of flexibility and bio-based technologies, but they still cannot simultaneously meet the needs of green environmental protection, excellent resistive switching performance and the expansion of logic circuit functions.

[0043] Therefore, the purpose of this invention is to provide a memristor based on CS-GO composite material and its logic circuit application method. By introducing GO into CS, its two-dimensional layered structure and oxygen-containing functional groups significantly enhance the formation and controllability of conductive channels. Simultaneously, the introduction of a PEDOT:PSS buffer layer between ITO and the dielectric layer effectively reduces interface resistance and improves electric field uniformity, thereby achieving a higher on / off ratio, lower operating voltage, and superior holding performance. This invention not only inherits the environmentally friendly and biodegradable advantages of biomaterials but also achieves a comprehensive improvement in electrical performance.

[0044] like Figure 1 As shown, this embodiment provides a first aspect of a chitosan-based memristor, comprising a substrate, a buffer layer, a composite dielectric layer, and a top electrode stacked sequentially from bottom to top; The buffer layer is formed by spin-coating a PEDOT:PSS aqueous solution onto the substrate and then heat-treating it. The composite medium layer is formed by spin-coating an ultrasonic composite solution of graphene oxide aqueous dispersion and chitosan acetic acid solution onto the buffer layer and then heat-treating it.

[0045] By employing a synergistic architecture of a chitosan-graphene oxide composite dielectric layer and a PEDOT:PSS buffer layer, a bio-based memristor was fabricated, exhibiting high on / off ratio, low operating voltage, and good performance stability. Furthermore, the fabricated memristor demonstrated excellent bipolar resistive switching characteristics, with an on / off ratio as high as 10. 3 Up to 10 4 Quantity, V SET / V RESET The absolute values ​​are all below 2.0V, and exhibit more than 10 at a read voltage of 0.1V. 4 The device maintains a persistent resistive state for seconds. Furthermore, based on the stable high and low resistance states of this device, all seven basic logic operations, including NOT, AND, OR, NAND, NOR, XOR, and XNOR gates, have been fully implemented on a single bio-based platform with a 100% accuracy rate, achieving unexpected results.

[0046] In some embodiments, PEDOT:PSS is a composite material system consisting of two components: PEDOT: The full name is poly(3,4-ethylenedioxythiophene).

[0047] PSS stands for poly(styrene sulfonate).

[0048] In some embodiments, the substrate is ITO glass and the top electrode is a W probe.

[0049] In some embodiments, the mass concentration of the PEDOT:PSS aqueous solution is 1.0% to 1.5%.

[0050] In some embodiments, the mass concentration of the graphene oxide aqueous dispersion is 0.1% to 0.3%; and the mass concentration of the chitosan acetic acid solution is 1% to 2%.

[0051] Studies have found that the mass concentrations of PEDOT:PSS aqueous solution, graphene oxide aqueous dispersion, and chitosan acetic acid solution are key factors affecting memristor performance. If the same preparation method and process are used, changing only the mass concentrations of PEDOT:PSS aqueous solution and / or graphene oxide aqueous dispersion and / or chitosan acetic acid solution, and adjusting the mass concentrations too low or too high, will lead to a significant reduction in the overall performance of the memristor.

[0052] In some embodiments, the volume ratio of the graphene oxide aqueous dispersion to the chitosan acetic acid solution in the ultrasonic composite solution is 0.5–2:1. Studies have found that the volume ratio of the graphene oxide aqueous dispersion to the chitosan acetic acid solution is also a key factor affecting memristor performance. Research has shown that if the same preparation method and process are used, changing only the volume ratio of the graphene oxide aqueous dispersion to the chitosan acetic acid solution—whether too low or too high—will lead to a significant decrease in the overall performance of the memristor. Preferably, the volume ratio of the graphene oxide aqueous dispersion to the chitosan acetic acid solution in the ultrasonic composite solution is 0.5–1:1.

[0053] The second aspect of this embodiment provides the above-mentioned method for preparing a chitosan-based memristor, comprising the following steps: PEDOT:PSS aqueous solution was spin-coated onto the substrate and heat-treated to form a buffer layer. An ultrasonic composite solution formed by an aqueous dispersion of graphene oxide and a chitosan acetic acid solution was spin-coated onto the buffer layer, and then heat-treated to form a composite medium layer. The top electrode is made into point contact with the surface of the composite dielectric layer.

[0054] In some embodiments, the specific operation process of the buffer layer is as follows: A PEDOT:PSS aqueous solution is spin-coated onto the substrate, first at 800-1000 rpm for 5-10 seconds, then at 3000-5000 rpm for 40-60 seconds; followed by heating at 80-100℃ for 5-10 minutes. Adjusting the appropriate spin-coating process parameters for aqueous solutions of specific concentrations can better ensure the spin-coating effect and contribute to improving the overall performance of the memristor.

[0055] In some embodiments, the specific operation process of the composite dielectric layer is as follows: An ultrasonic composite solution formed by an aqueous dispersion of graphene oxide and a chitosan-acetic acid solution is spin-coated onto the buffer layer. The spin-coating process involves rotating at 500-1000 rpm for 5-20 seconds, followed by rotation at 2000-3000 rpm for 30-40 seconds. This is then followed by heating at 60-90 °C for 5-15 minutes. Adjusting the spin-coating process parameters to suit specific concentrations of the graphene oxide aqueous dispersion and chitosan-acetic acid solution can better ensure the spin-coating effect and contribute to improving the overall performance of the memristor.

[0056] A third aspect of this embodiment provides a logic operation device comprising at least two chitosan-based memristors prepared by the above-described method, wherein the at least two chitosan-based memristors are connected in a circuit to realize a logic gate function.

[0057] Based on the stable high and low impedance states of the device, all seven basic logic operations, including NOT, AND, OR, NAND, NOR, XOR, and XNOR, were fully implemented on a single bio-based platform with a 100% accuracy rate, achieving unexpected results.

[0058] In some embodiments, the logic gate functions include at least one of NOT gate, AND gate, OR gate, NAND gate, and NOR gate; and / or, further include XOR gate and / or XNOR gate.

[0059] The study found that, using the same preparation method, if only graphene oxide is replaced with carbon nanotubes, the prepared memristor has a low switching efficiency, poor retention characteristics, and cannot achieve effective and stable turn-off.

[0060] To better understand the technical solutions of the above embodiments, the following more detailed embodiments are provided for further explanation: Sources of raw materials and instruments in the following examples and comparative examples Chitosan: Brand Aladdin, Product No. C105799; Graphene oxide: Manufacturer: Shenzhen Suiheng Technology Co., Ltd., Item No.: SH-GO-1266; PEDOT:PSS: Brand: Heraeus, Germany; Model: OPV-PEDOT:PSS1000; Concentration: 1.0%–1.3% aqueous solution. ITO conductive glass: Manufacturer Opivet, 10*10*1.1mm, 14~17Ω sheet resistance; Acetic acid: Brand: Maclean, Product No.: A801299; Magnetic stirrer (SUNNE, Shanghai Shangpu Instrument Equipment Co., Ltd.); Cascade EPS150 probe station; Keithley 2450 semiconductor tester. Example 1

[0061] Preparation of the medium layer mixed solution: Weigh 10 mg of GO powder and add it to 10 ml of deionized water. Disperse the mixture by sonication for 30 min to obtain a uniform GO dispersion. Take 1 ml of the above GO dispersion and mix it with 1 ml of 1 wt% CS solution (prepared by the same process as Comparative Example 1; Examples 2-3 and Comparative Examples 2-3 below all use the same chitosan solution prepared by the same method as Comparative Example 1). Continue to sonicate for 30 min to ensure that GO is fully and uniformly dispersed in the CS matrix, and obtain a CS–GO composite solution with a CS:GO volume ratio of 2:1.

[0062] Substrate cleaning and pretreatment: ITO glass with dimensions of 1cm × 1cm was selected as the substrate. The substrate was sequentially immersed in acetone, anhydrous ethanol, and deionized water, and ultrasonically cleaned for 10 minutes each step to remove residual organic matter and particulate impurities from the surface. After cleaning, the substrate was dried with nitrogen gas and stored in a clean environment for later use.

[0063] Introducing the PEDOT:PSS buffer layer: The PEDOT:PSS solution (model OPV-PEDOT:PSS 1000, approximately 1.0-1.3 wt% aqueous solution) was brought to room temperature and thoroughly shaken or gently sonicated to avoid phase separation caused by prolonged standing. The solution was filtered through a 0.45 μm PTFE membrane to remove agglomerated particles and ensure film uniformity. Using a spin-coating process, the filtered PEDOT:PSS solution was dropped onto the cleaned ITO substrate surface. The substrate was first rotated at 500 rpm for 10 s to spread the solution evenly, then rotated at 5000 rpm for 60 s to form a uniform thin film. Subsequently, it was heated at 120 °C for 10 min to remove residual solvent and enhance film density and adhesion to ITO. After cooling to room temperature, a uniform PEDOT:PSS buffer layer was obtained for subsequent deposition of CS or CS-GO films. This buffer layer can reduce the series resistance of the device, improve the electric field distribution, and enhance the uniformity of subsequent dielectric layer deposition.

[0064] Dielectric layer formation: An appropriate amount of CS-GO mixed solution was drop-coated onto the cleaned ITO substrate surface. A spin-coating process was used, first rotating at 500 rpm for 10 s to evenly spread the solution, then rotating at 3000 rpm for 60 s to obtain a uniform composite film. The sample was then placed on a 90 ℃ heating stage for 10 min to accelerate solvent evaporation and improve film density and interfacial adhesion. After treatment, the film was allowed to cool naturally at room temperature for 30 min to obtain the CS-GO composite film.

[0065] Top electrode selection: A W probe is used as the top electrode. The probe position is precisely adjusted using a probe stage to establish a stable electrical contact between the probe tip and the surface of the composite film. The contact pressure is controlled within a range that ensures stable conduction without damaging the dielectric layer, thereby ensuring the accuracy of the test and the integrity of the device surface.

[0066] Device performance testing: The fabricated device was fixed on the probe stage, and IV characteristics were tested using a Keithley 2450 source meter, such as... Figure 3As shown in (3) in the figure. Compared to the device without the PEDOT:PSS buffer layer, this device exhibits clear bipolar switching, and cyclic scanning under Icc constraints shows stable switching behavior and an adjustable window. Example 2

[0067] Preparation of the medium layer mixed solution: Weigh 10 mg of GO powder, add it to 10 ml of deionized water, and sonicate for 30 min to obtain a uniform GO dispersion. Take 1 ml of the above GO dispersion and mix it with 1 ml of 1 wt% CS solution. Continue to sonicate for 30 min to ensure that GO is fully and uniformly dispersed in the CS matrix, and obtain a CS–GO composite solution with a CS:GO volume ratio of 1:1.

[0068] Substrate cleaning and pretreatment: ITO glass with dimensions of 1cm × 1cm was selected as the substrate. The substrate was sequentially immersed in acetone, anhydrous ethanol, and deionized water, and ultrasonically cleaned for 10 minutes each step to remove residual organic matter and particulate impurities from the surface. After cleaning, the substrate was dried with nitrogen gas and stored in a clean environment for later use.

[0069] Introducing the PEDOT:PSS buffer layer: The PEDOT:PSS solution (model OPV-PEDOT:PSS 1000, approximately 1.0-1.3 wt% aqueous solution) was brought to room temperature and thoroughly shaken or gently sonicated to avoid phase separation caused by prolonged standing. The solution was filtered through a 0.45 μm PTFE membrane to remove agglomerated particles and ensure film uniformity. Using a spin-coating process, the filtered PEDOT:PSS solution was dropped onto the cleaned ITO substrate surface. The substrate was first rotated at 500 rpm for 10 s to spread the solution evenly, then rotated at 5000 rpm for 60 s to form a uniform thin film. Subsequently, it was heated at 120 °C for 10 min to remove residual solvent and enhance film density and adhesion to ITO. After cooling to room temperature, a uniform PEDOT:PSS buffer layer was obtained for subsequent deposition of CS or CS-GO films. This buffer layer can reduce the series resistance of the device, improve the electric field distribution, and enhance the uniformity of subsequent dielectric layer deposition.

[0070] Dielectric layer formation: An appropriate amount of CS-GO mixed solution was drop-coated onto the cleaned ITO substrate surface. A spin-coating process was used, first rotating at 500 rpm for 10 s to evenly spread the solution, then rotating at 3000 rpm for 60 s to obtain a uniform composite film. The sample was then placed on a 90 ℃ heating stage for 10 min to accelerate solvent evaporation and improve film density and interfacial adhesion. After treatment, the film was allowed to cool naturally at room temperature for 30 min to obtain the CS-GO composite film.

[0071] Top electrode selection: A W probe is used as the top electrode. The probe position is precisely adjusted using a probe stage to establish a stable electrical contact between the probe tip and the surface of the composite film. The contact pressure is controlled within a range that ensures stable conduction without damaging the dielectric layer, thereby ensuring the accuracy of the test and the integrity of the device surface.

[0072] Device performance testing: The fabricated device was fixed on the probe stage, and I-V characteristics were tested using a Keithley 2450 source meter, such as... Figure 3 (2) Compared to the curve of PEDOT:PSS without the buffer layer, there is obvious fluctuation / bidding, and the response is unstable, showing random opening and closing of local channels. The hysteresis characteristics of this curve tend to be regular and the bifurcation phenomenon is reduced; however, compared to 2:1, the switching ratio is smaller. Example 3

[0073] Preparation of the dielectric layer mixed solution: Weigh 10 mg of graphene oxide (GO) powder, dissolve it in 10 ml of deionized water, and ultrasonically disperse for 30 min to obtain a uniform and stable GO dispersion. Take 2 ml of the above GO dispersion and mix it with 1 ml of chitosan (CS) solution with a concentration of 1 wt%, and continue to ultrasonically treat for 30 min to make GO uniformly dispersed in the CS matrix, thereby obtaining a CS–GO mixed solution with a doping ratio of 1:2.

[0074] Substrate cleaning and pretreatment: ITO glass with dimensions of 1cm × 1cm was selected as the substrate. The substrate was sequentially immersed in acetone, anhydrous ethanol, and deionized water, and ultrasonically cleaned for 10 minutes each step to remove residual organic matter and particulate impurities from the surface. After cleaning, the substrate was dried with nitrogen gas and stored in a clean environment for later use.

[0075] Introducing the PEDOT:PSS buffer layer: The PEDOT:PSS solution (model OPV-PEDOT:PSS 1000, approximately 1.0-1.3 wt% aqueous solution) was brought to room temperature and thoroughly shaken or gently sonicated to avoid phase separation caused by prolonged standing. The solution was filtered through a 0.45 μm PTFE membrane to remove agglomerated particles and ensure film uniformity. Using a spin-coating process, the filtered PEDOT:PSS solution was dropped onto the cleaned ITO substrate surface. The substrate was first rotated at 500 rpm for 10 s to spread the solution evenly, then rotated at 5000 rpm for 60 s to form a uniform thin film. Subsequently, it was heated at 120 °C for 10 min to remove residual solvent and enhance film density and adhesion to ITO. After cooling to room temperature, a uniform PEDOT:PSS buffer layer was obtained for subsequent deposition of CS or CS-GO films. This buffer layer can reduce the series resistance of the device, improve the electric field distribution, and enhance the uniformity of subsequent dielectric layer deposition.

[0076] Dielectric layer formation: The prepared CS–GO mixed solution was drop-coated onto the surface of an ITO substrate modified with PEDOT:PSS. A spin-coating process was used, first rotating at 500 rpm for 10 s to ensure uniform spreading of the solution, then rotating at 3000 rpm for 60 s to obtain a uniform composite film. The sample was then heated on a 90 ℃ heating stage for 10 min to accelerate solvent evaporation and improve film density and interfacial adhesion. After treatment, the film was allowed to cool naturally at room temperature for 30 min to obtain the CS–GO composite film.

[0077] Top electrode selection: A tungsten (W) probe is used as the top electrode. The probe position is precisely adjusted using a probe stage to establish a stable electrical contact between the probe tip and the surface of the composite film. The contact pressure is controlled within a range that ensures stable conduction without damaging the dielectric layer, thereby ensuring the accuracy of the test and the integrity of the device surface.

[0078] Device performance testing: The fabricated device was fixed on the probe stage, and I-V characteristics were tested using a Keithley 2450 source meter, such as... Figure 3 (1) It can be observed that parasitic capacitance is further suppressed, I–V is more symmetrical and repeatability is better, but it is still mainly linearly conductive and is not suitable as the main storage window. This shows that PEDOT:PSS improves stability and conductivity, but the trap / channel density is still low at this ratio, making it difficult to form robust reversible filaments. Comparative Example 1

[0079] Preparation of the medium layer solution: Weigh 100 mg of CS powder and dissolve it in 10 ml of 1% acetic acid solution. Stir magnetically at 1000 rpm for 480 min at 40 ℃ until a homogeneous and transparent solution is formed. The mass fraction of the resulting solution is approximately 1 wt%. After stirring, cool the solution to room temperature and filter it using a 0.22 μm PTFE membrane to remove undissolved particles and impurities. Store the filtered solution in a sealed container, protected from light, and refrigerated for later use.

[0080] Substrate cleaning and pretreatment: ITO glass with dimensions of 1cm × 1cm was selected as the substrate. The ITO substrate was sequentially immersed in acetone, anhydrous ethanol, and deionized water, and ultrasonically cleaned for 10 minutes at each step to remove residual organic contaminants and particulate impurities from the surface. After cleaning, the substrate was dried with nitrogen gas and then placed in a clean bench for later use.

[0081] Dielectric layer formation: A suitable amount of 1wt% CS solution was drop-coated onto the cleaned ITO substrate surface. Using a spin-coating process, the solution was rotated sequentially at 500 rpm for 10 s and then at 3000 rpm for 60 s to ensure uniform spread and thin film formation on the substrate surface. After spin-coating, the sample was heated on a 90 ℃ heating stage for 10 min to promote solvent evaporation and improve film density. It was then allowed to cool naturally at room temperature for 30 min to obtain a uniform and dense CS film.

[0082] Top electrode selection: A W probe is selected as the top electrode. The probe position is precisely adjusted using a probe stage to ensure stable contact between the probe tip and the dielectric layer surface. The contact pressure is preferably controlled within a range that ensures stable electrical conduction without damaging the dielectric layer surface, thereby achieving accurate device performance testing while avoiding film damage.

[0083] Device performance testing: The prepared device sample was fixed on the probe stage, and the I-V characteristics of the device were tested using a Keithley 2450 source meter, such as... Figure 2 (1) The I–V curves exhibit obvious symmetry and a wide hysteresis loop, showing a significant capacitance effect. This indicates that charge accumulates and releases strongly at the interface or in the bulk phase, but lacks a stable conductive channel, and therefore does not exhibit obvious resistive switching behavior. Comparative Example 2

[0084] Preparation of the dielectric layer mixed solution: Weigh 10 mg of GO powder, dissolve it in 10 ml of deionized water, and sonicate for 30 min to obtain a uniform and stable GO dispersion. Take 2 ml of the above GO dispersion and mix it with 1 ml of 1 wt% CS solution. Continue sonication for 30 min to ensure that GO is uniformly dispersed in the CS matrix, thereby obtaining a CS-GO mixed solution with a doping ratio of 1:2.

[0085] Substrate cleaning and pretreatment: ITO glass with dimensions of 1cm × 1cm was selected as the substrate. The substrate was sequentially immersed in acetone, anhydrous ethanol, and deionized water, and ultrasonically cleaned for 10 minutes each step to remove residual organic matter and particulate impurities from the surface. After cleaning, the substrate was dried with nitrogen gas and stored in a clean environment for later use.

[0086] Dielectric layer formation: An appropriate amount of CS-GO mixed solution was drop-coated onto the cleaned ITO substrate surface. A spin-coating process was used, first rotating at 500 rpm for 10 s to evenly spread the solution, then rotating at 3000 rpm for 60 s to obtain a uniform composite film. The sample was then placed on a 90 ℃ heating stage for 10 min to accelerate solvent evaporation and improve film density and interfacial adhesion. After treatment, the film was allowed to cool naturally at room temperature for 30 min to obtain the CS-GO composite film.

[0087] Top electrode selection: A W probe is used as the top electrode. The probe position is precisely adjusted using a probe stage to establish a stable electrical contact between the probe tip and the surface of the composite film. The contact pressure is controlled within a range that ensures stable conduction without damaging the dielectric layer, thereby ensuring the accuracy of the test and the integrity of the device surface.

[0088] Device performance testing: The fabricated device was fixed on the probe stage, and I-V characteristics were tested using a Keithley 2450 source meter, such as... Figure 2 (2) Compared to memristors with pure CS dielectric, with the introduction of GO, the hysteresis loop of the device shrinks significantly, the capacitance effect is suppressed, and the IV response gradually transforms into memristor characteristics. This indicates that GO plays a role in improving charge transport and regulating the distribution of trapped states, thus stabilizing the electrical behavior of the device. Comparative Example 3

[0089] Preparation of the medium layer mixed solution: Weigh 10 mg of GO powder, add it to 10 ml of deionized water, and sonicate for 30 min to obtain a uniform GO dispersion. Take 1 ml of the above GO dispersion and mix it with 1 ml of 1 wt% CS solution. Continue to sonicate for 30 min to ensure that GO is fully and uniformly dispersed in the CS matrix, and obtain a CS–GO composite solution with a CS:GO volume ratio of 1:1.

[0090] Substrate cleaning and pretreatment: ITO glass with dimensions of 1cm × 1cm was selected as the substrate. The substrate was sequentially immersed in acetone, anhydrous ethanol, and deionized water, and ultrasonically cleaned for 10 minutes each step to remove residual organic matter and particulate impurities from the surface. After cleaning, the substrate was dried with nitrogen gas and stored in a clean environment for later use.

[0091] Dielectric layer formation: An appropriate amount of CS-GO mixed solution was drop-coated onto the cleaned ITO substrate surface. A spin-coating process was used, first rotating at 500 rpm for 10 s to evenly spread the solution, then rotating at 3000 rpm for 60 s to obtain a uniform composite film. The sample was then placed on a 90 ℃ heating stage for 10 min to accelerate solvent evaporation and improve film density and interfacial adhesion. After treatment, the film was allowed to cool naturally at room temperature for 30 min to obtain the CS-GO composite film.

[0092] Top electrode selection: A W probe is used as the top electrode. The probe position is precisely adjusted using a probe stage to establish a stable electrical contact between the probe tip and the surface of the composite film. The contact pressure is controlled within a range that ensures stable conduction without damaging the dielectric layer, thereby ensuring the accuracy of the test and the integrity of the device surface.

[0093] Device performance testing: The fabricated device was fixed on the probe stage, and I-V characteristics were tested using a Keithley 2450 source meter, such as... Figure 2 (3) When the doping ratio is 1:1, the I-V curve of the device shows obvious fluctuations and irregularities, which is manifested as unstable current response. This indicates that the matching degree between GO and CS is poor at this ratio, which easily leads to uneven formation and breakage of local conductive channels, thereby weakening the consistency and controllability of device performance. Comparative Example 4

[0094] Preparation of the medium layer mixed solution: Weigh 10 mg of GO powder, add it to 10 ml of deionized water, and sonicate for 30 min to obtain a uniform GO dispersion. Take 1 ml of the above GO dispersion and mix it with 1 ml of 1 wt% CS solution. Continue to sonicate for 30 min to ensure that GO is fully and uniformly dispersed in the CS matrix, and obtain a CS–GO composite solution with a CS:GO volume ratio of 2:1.

[0095] Substrate cleaning and pretreatment: ITO glass with dimensions of 1cm × 1cm was selected as the substrate. The substrate was sequentially immersed in acetone, anhydrous ethanol, and deionized water, and ultrasonically cleaned for 10 minutes each step to remove residual organic matter and particulate impurities from the surface. After cleaning, the substrate was dried with nitrogen gas and stored in a clean environment for later use.

[0096] Dielectric layer formation: An appropriate amount of CS-GO mixed solution was drop-coated onto the cleaned ITO substrate surface. A spin-coating process was used, first rotating at 500 rpm for 10 s to evenly spread the solution, then rotating at 3000 rpm for 60 s to obtain a uniform composite film. The sample was then placed on a 90 ℃ heating stage for 10 min to accelerate solvent evaporation and improve film density and interfacial adhesion. After treatment, the film was allowed to cool naturally at room temperature for 30 min to obtain the CS-GO composite film.

[0097] Top electrode selection: A W probe is used as the top electrode. The probe position is precisely adjusted using a probe stage to establish a stable electrical contact between the probe tip and the surface of the composite film. The contact pressure is controlled within a range that ensures stable conduction without damaging the dielectric layer, thereby ensuring the accuracy of the test and the integrity of the device surface.

[0098] Device performance testing: The fabricated device was fixed on the probe stage, and IV characteristics were tested using a Keithley 2450 source meter, such as... Figure 2 As shown in (4) in the figure. When the volume ratio of CS solution to GO aqueous dispersion is 2:1, the current response of the device tends to be stable, the capacitance effect is almost negligible, and the overall performance is closer to the typical memristor behavior. However, it can be observed that the overall current magnitude of the device is relatively small, indicating that although doping with GO is beneficial to suppressing the capacitance effect, it will weaken the ability to form continuous conductive channels, thereby reducing conductivity and switching current amplitude.

[0099] from Figure 2 and Figure 3 As shown, the study found that the overall performance of the device was significantly improved after introducing the PEDOT:PSS buffer layer. Firstly, in terms of conductivity, the device current increased to 10...-1 The current is on the order of A, while the overall current is lower without the buffer layer. Secondly, regarding resistive switching characteristics, especially at a CS–GO ratio of 2:1, the device exhibits stable bipolar resistive switching, whereas without the buffer layer, the same ratio only shows a weakened capacitive effect and lacks clear switching behavior. Simultaneously, the introduction of PEDOT:PSS improves the energy level matching and carrier injection uniformity of the electrodes / interface, resulting in V… SET / V RESET Slightly reduced and with better repeatability (approximately +1.8 V / -1.5 V), and achieved resistive hold of over 10,000 s at a small bias (0.1 V), with both HRS and LRS remaining stable, and an on / off ratio of up to 10. 3 -10 4 Furthermore, by adjusting the current limit Icc, the I–V window of the device expands and different current plateaus appear, demonstrating the programmable characteristics of multi-level resistance states. The mechanism lies in the fact that PEDOT:PSS, as a high work function, p-type conductive polymer layer, can effectively reduce the surface roughness and series resistance of ITO, improve energy level docking and hole injection, and passivate interface traps, thereby weakening parasitic capacitance effects and improving the controllability and consistency of the formation and reset of conductive channels (such as conductive filaments or defect pathways).

[0100] The devices prepared in Examples 1-3 and Comparative Examples 1-4 were fixed on a probe stage, and IV characteristics were tested using a Keithley 2450 source meter. By comparing the electrical performance of pure CS dielectric devices, CS-GO composite devices with different doping ratios, and devices with a PEDOT:PSS buffer layer, the comprehensive impact of PEDOT:PSS and GO doping on key parameters such as device on / off ratio, operating voltage, and cycle durability can be evaluated. The test results are as follows: Figures 2-5 As shown.

[0101] like Figure 2 As shown in (1), the memristor composed of pure CS dielectric exhibits obvious capacitive characteristics, and its I-V curve shows a large hysteresis loop, indicating that the device has a strong capacitive effect during charge storage. With the gradual introduction of GO ( Figure 2 In (2)–(4) of the figure, the capacitance effect is significantly reduced. When the doping ratio is 1:2 and 1:1, the hysteresis loop gradually shrinks, indicating that the introduction of GO effectively suppresses the accumulation and release of charge, and the device tends to exhibit a conductivity response closer to that of memristors. It is worth noting that when the ratio of GO to CS reaches 2:1 ( Figure 2In (4) of the above, the capacitance effect is almost negligible, but the device does not exhibit obvious reversible switching behavior, and the overall current level is low. This indicates that while appropriately adjusting the doping ratio of GO can weaken the capacitance effect, it can also reduce the ability to form conductive channels, thereby limiting the switching behavior of the memristor device. In order to reduce the surface roughness and series resistance of the ITO electrode and thus improve the overall conductivity of the device, a PEDOT:PSS layer was introduced between the ITO and the dielectric layer as a buffer layer, and the device was subjected to electrical tests. Figure 3 As shown, the device's current can reach 10. -1 The performance is on the order of A, significantly better than the case without a buffer layer. Especially... Figure 3 In (3), when the dielectric layer has a CS-GO mass ratio of 2:1, the device exhibits obvious bipolar resistive switching characteristics. Under Icc = 100 mA conditions, voltage scans were performed sequentially from 0→3 V, 3 V→0 V, 0 V→-3 V, and -3 V→0 V. The process of the device switching from HRS to LRS and back from LRS can be clearly observed. Specifically, when the voltage rises to approximately +1.8 V, the device switches from HRS to LRS; while when the voltage reverses to approximately -1.5 V, the device recovers from LRS to HRS, exhibiting stable non-volatile storage characteristics. Figure 4 As shown, the device prepared in Example 1 underwent a stability test for 10,000 s at a small bias voltage of 0.1 V. The results showed that the resistance of the HRS remained at approximately 10. 6 -10 7 The Ω level is used, while the LRS level is stable at 10. 2 -10 3 Within the Ω range, the resistance does not change significantly with time, indicating that the device has good electrical stability. Therefore, the on / off ratio of the device is approximately 10. 3 -10 4 This meets the basic requirements of non-volatile storage. Furthermore, such as... Figure 5 As shown, by changing the current limit value Icc, the device prepared in Example 1 was subjected to cyclic scanning. The results show that as Icc increases, the I–V window of the device gradually expands, exhibiting different current response plateaus. This indicates that the device has the ability to control the resistance state at multiple levels, demonstrating potential for multi-level memory applications.

[0102] The memristor logic gates of this invention are constructed using MAGIC logic, treating HRS as logic "0" and LRS as logic "1". The resistance variation characteristics of the memristor are as follows: Figure 6 As shown in (1), the polarity of the memristor is indicated in black. This terminal is defined as the input terminal. When current flows from the input terminal to the output terminal, the voltage exceeds the threshold voltage V.SET When the device switches from HRS to LRS, that is, from logic "0" to logic "1", the voltage exceeds the threshold voltage V when current flows from the output to the input. RESET When the device switches from LRS to HRS, that is, from logic "1" to logic "0". ② Specific Implementation: The memristors used in the logic gate operations of this invention are all memristors prepared in Example 1, which can be defined as input memristors (A / B), output memristors (Y), and temporary result memristors (Y1 / Y2 / Y3). The memristors are connected in appropriate ways according to different logic operations, and appropriate input conditions are adjusted. Input memristors A or B are adjusted to appropriate resistance states, and the resistance value of output memristor Y is tested to determine whether the logic operation can be completed correctly. This invention implements a total of 7 logic operations, such as... Figure 6 As shown in (2), an NOT gate is implemented by connecting two memristors in series with opposite polarities. If A is "0", then it is HRS, and Y cannot reach a suitable V. RESET The output is "1" if Y is true and "0" otherwise. This conforms to the logic of a NOT gate. Figure 7 As shown in (1) and (2), by introducing another input memristor B and connecting it in series appropriately, an AND gate and a NAND gate can be constructed. In the AND gate, if A=1 and B=1, Y reaches a suitable V. SET Y=1; if A or B are both 0, or either of them is 0, Y cannot reach a suitable V. SET At this point, Y=0. This conforms to the logic of an AND gate. Similarly, in a NAND gate, when A=B=1, Y reaches V. RESET When A=B=0, the output is 0; when A=B=0, Y cannot reach V. SET Output 1; when A=1 and B=0, Y cannot reach V. SET Output 1; when A=0 and B=1, Y cannot reach V. SET The output is 1. This conforms to the logical operation of a NAND gate. Figure 8 As shown, parallel connections can form OR gates and NOR gates. In an OR gate, if A=0 and B=0, then Y cannot reach V. SET Therefore, Y=0; when either memristor A or B has a logic value of 1, Y can reach V. SET At this point, Y=1. Specifically, this invention implements XNOR and XOR gates based on the preceding logic gates. In particular, based on AND, OR, and NOT gates, the memristor can be processed using the XOR logic expression as follows: Figure 9(1) The connection shown uses temporary memristors Y1 / Y2 / Y3 to implement the XOR logic operation. In the XOR gate, firstly, S1 and S2 are closed, and S3 and S4 are open, forming two NOT gates, temporarily storing the opposite results of A and B in Y1 and Y2; then S1 and S2 are opened, and S3 and S4 are closed, using Y1 and Y2 as the inputs of the XOR gate. If A=1, B=1, Y1=0, Y2=0, Y=0; if A=0, B=0, Y1=1, Y2=1, Y=0; if A=1, B=0, Y1=1, Y2=0, Y=1; if A=0, B=1, Y1=0, Y2=1, Y=1. Figure 9 As shown in (2), the resistance measurement results of the memristor prepared in Example 1 are consistent with the truth table of the XOR gate. Similarly, as Figure 10 As shown in (1), by introducing a temporary memristor Y3 on the basis of the XOR gate, a NAND gate can be constructed. Figure 10 (2) As shown, the resistance measurement results of the memristor prepared in Example 1 are consistent with the truth table of the XOR gate.

[0103] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A chitosan-based memristor, characterized in that, It includes a substrate, a buffer layer, a composite dielectric layer, and a top electrode, which are stacked sequentially from bottom to top; The buffer layer is formed by spin-coating a PEDOT:PSS aqueous solution onto the substrate and then heat-treating it. The composite dielectric layer is formed by spin-coating an ultrasonic composite solution of graphene oxide aqueous dispersion and chitosan acetic acid solution onto the buffer layer and then heat-treating it; the top electrode is a W probe that forms point contact with the surface of the composite dielectric layer.

2. The chitosan-based memristor according to claim 1, characterized in that, The mass concentration of PEDOT:PSS aqueous solution is 1.0% to 1.5%.

3. The chitosan-based memristor according to any one of claims 1-2, characterized in that, The mass concentration of the graphene oxide aqueous dispersion is 0.1% to 0.3%; the mass concentration of the chitosan acetic acid solution is 1% to 2%.

4. The chitosan-based memristor according to claim 3, characterized in that, In the ultrasonic composite solution, the volume ratio of graphene oxide aqueous dispersion to chitosan acetic acid solution is 0.5 to 2:

1.

5. The chitosan-based memristor according to claim 4, characterized in that, In the ultrasonic composite solution, the volume ratio of the graphene oxide aqueous dispersion to the chitosan acetic acid solution is 0.5 to 1:

1.

6. The method for preparing a chitosan-based memristor according to any one of claims 1-5, characterized in that, Includes the following steps: PEDOT:PSS aqueous solution was spin-coated onto the substrate and heat-treated to form a buffer layer. An ultrasonic composite solution formed by an aqueous dispersion of graphene oxide and a chitosan acetic acid solution was spin-coated onto the buffer layer, and then heat-treated to form a composite medium layer. The top electrode is made into point contact with the surface of the composite dielectric layer.

7. The preparation method according to claim 6, characterized in that, The specific operation process of the buffer layer is as follows: spin-coat the PEDOT:PSS aqueous solution onto the substrate, first at a speed of 800-1000 rpm for 5-10 seconds, then at a speed of 3000-5000 rpm for 40-60 seconds; heat at 80-100℃ for 5-10 minutes.

8. The preparation method according to claim 7, characterized in that, The specific operation process of the composite medium layer is as follows: the ultrasonic composite solution formed by the graphene oxide aqueous dispersion and the chitosan acetic acid solution is spin-coated onto the buffer layer, first at a speed of 500-1000 rpm for 5-20 seconds, then at a speed of 2000-3000 rpm for 30-40 seconds; then heated at 60-90℃ for 5-15 minutes.

9. A logic operation device, characterized in that, The device comprises at least two chitosan-based memristors as described in any one of claims 1-5 or prepared by any one of claims 6-8, and implements logic gate functions by connecting the at least two chitosan-based memristors in a circuit.

10. The logic operation device according to claim 9, characterized in that, The logic gate functions include at least one of NOT gate, AND gate, OR gate, NAND gate, and NOR gate; and / or, also include XOR gate and / or XNOR gate.

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