ESD (Electro-Static Discharge) rapid detection circuit with reset fuse trimming function
Patent Information
- Application Number
- CN202511560215.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-29
- Publication Date
- 2026-02-06
AI Technical Summary
Traditional ESD protection modules are prone to accidental triggering and lack a fast reset mechanism, leading to abnormal chip function. Furthermore, fuse adjustment operations are unsafe, affecting chip mass production yield and reliability.
An ESD fast detection circuit with reset fuse adjustment function was designed, including an ESD fast detection module, a reset module and a fuse adjustment function module. By accurately detecting ESD events and safely resetting the logic control module at the initial power-on stage, the safety and reliability of fuse adjustment operation are ensured.
It effectively suppresses ESD false triggering, enables rapid recovery, improves chip mass production yield and long-term reliability, and solves the system-level failure and performance discrepancy problems caused by ESD false triggering.
Smart Images
Figure CN121477752A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electrostatic discharge (ESD) protection technology for integrated circuits, and in particular to an ESD fast detection circuit with reset fuse adjustment function. Background Technology
[0002] With the continuous advancement of semiconductor process technology, chip size is increasing and integration is significantly improving. Modern system-on-a-chip (SoC) often contains dozens or even hundreds of functional modules and independent power domains. This high level of complexity and integration poses unprecedented challenges to the electrostatic discharge (ESD) protection design of chips.
[0003] In such complex systems, traditional local ESD protection modules have significant limitations. First, power disturbances caused by noise, surges, or switching of individual modules in the power network can easily lead to false triggering of the ESD detection circuit. Once falsely triggered, the power switch or logic unit it controls will experience abnormal reset or latch-up, interrupting the normal operation of that local functional module. More seriously, traditional ESD circuits lack an effective fast reset mechanism after a false trigger. The system can only passively wait for its internal RC timing circuit to finish its natural delay. During this abnormal period, the unstable current generated by the falsely opened discharge path will continuously disrupt the voltage stability of that local power domain. This disturbance not only affects the local module but may also couple and propagate through the shared power network to other normally operating modules, causing difficult-to-diagnose cascading faults and even leading to system-wide malfunction.
[0004] Secondly, after chip manufacturing, due to the discreteness of process corners, key parameters such as trigger thresholds and response times of various ESD protection modules will deviate. To calibrate these performance parameters post-production, fuse trimming technology is widely used. However, in traditional designs, the enable signal for fuse programming is often directly generated by the logic control module, lacking effective safety authentication. During power-on or operation, any brief power supply noise or logic error can lead to the false activation of the trimming enable signal, resulting in the false programming of the fuse. This misoperation is irreversible, directly causing chip malfunction or performance degradation, severely restricting the chip's mass production yield and long-term field reliability.
[0005] Therefore, there is an urgent need in this field for an ESD protection solution that can effectively suppress false triggering, recover quickly after false triggering, and ensure safe and reliable fuse adjustment operations. Summary of the Invention
[0006] To solve the above technical problems, the present invention provides an ESD fast detection circuit with reset fuse adjustment function, comprising: an ESD fast detection module, a reset module, a fuse adjustment function module and a logic control module;
[0007] The ESD fast detection module is used to detect transient voltage changes on the power supply and distinguish between electrostatic discharge events and normal power-on. Its output terminal generates a trigger signal (V1).
[0008] The reset module has its input terminal coupled to the trigger signal (V1) and the output signal of the logic control module. It is used to reset the output of the logic control module to an invalid level in response to the trigger signal (V1) at the beginning of each power-on, so as to prevent malfunction.
[0009] The fuse trimming function module, coupled to the reset module and the logic control module, includes a fuse resistor (R3) and a trimming bit generation circuit based on current comparison; the trimming bit generation circuit outputs a first trimming level when the fuse resistor (R3) is not blown, and outputs a second trimming level when the fuse resistor (R3) is blown.
[0010] The output signal of the logic control module controls the fuse resistor (R3) to blow in the non-reset state, and the trigger signal (V1) serves as a gating signal to ensure that the fuse blowing operation is only performed in the safe state of non-power-on transient.
[0011] In one embodiment of the present invention, the ESD fast detection module includes:
[0012] An RC delay network, formed by the first resistor (R0) and the first capacitor (C1) connected in series, is connected between the power supply (BIAS) and ground (GND).
[0013] The second capacitor (C2) has its upper end connected to the power supply (BIAS) and its lower end outputting the trigger signal (V1);
[0014] An inverter composed of a first PMOS transistor (PM1) and a first NMOS transistor (NM1) has its input terminal coupled to the output terminal of a second resistor (R1), and its output terminal controls the gate of a second NMOS transistor (NM2); and the common node of the first resistor (R0) and the first capacitor (C1) is coupled to the input terminal of the second resistor (R1).
[0015] The drain of the second NMOS transistor (NM2) is connected to the power supply (BIAS), and the source is grounded (GND) to provide a discharge path in the event of an ESD incident.
[0016] In one embodiment of the present invention, the second NMOS transistor (NM2) is a large-size NMOS transistor used to form a low-impedance discharge path between the power supply (BIAS) and ground (GND) in an ESD event.
[0017] In one embodiment of the present invention, the reset module includes a third NMOS transistor (NM3) and a fourth NMOS transistor (NM4);
[0018] The gate of the third NMOS transistor (NM3) receives the trigger signal (V1), and its drain is coupled to the output node of the logic control module.
[0019] The gate of the fourth NMOS transistor (NM4) is coupled to the drain of the third NMOS transistor (NM3), and its drain is coupled to the lower end of the fuse resistor (R3).
[0020] During the power-on process, the pulse of the trigger signal (V1) turns on the third NMOS transistor (NM3) and pulls the gate potential of the fourth NMOS transistor (NM4) down to a low level, ensuring that it is in the off state.
[0021] In one embodiment of the present invention, the reset module is further provided with redundant resistors or capacitors for adjusting the pulse width of the trigger signal (V1), and / or with redundant NMOS devices for enhancing the pull-down capability of the third NMOS transistor (NM3).
[0022] In one embodiment of the present invention, the adjustment position generation circuit includes:
[0023] First current mirror and second current mirror;
[0024] The bias current of the first current mirror is greater than the bias current of the second current mirror;
[0025] The gates of the second PMOS transistor (PM2) and the third PMOS transistor (PM3) are controlled by the first current mirror, and the gates of the fifth NMOS transistor (NM5) and the sixth NMOS transistor (NM6) are controlled by the second current mirror.
[0026] When the fuse resistor (R3) is not blown, the first current mirror operates, pulling the adjustment position up to the first adjustment level through PM2 and PM3;
[0027] When the fuse resistor (R3) blows, the first current mirror is turned off, and the second current mirror pulls the adjustment position down to the second adjustment level through NM5 and NM6.
[0028] In one embodiment of the invention, the trim bit output is used to fine-tune the address matching threshold of the internal circuitry of the chip or to enable / disable specific trimming functions.
[0029] In one embodiment of the present invention, a test port (TEST) is further included, connected to the fuse trimming function module, for forcibly setting the state of the trimming bit in test mode, without performing actual fuse programming.
[0030] In one embodiment of the present invention, the logic control module outputs multiple sets of control signals to control multiple identical reset modules and fuse adjustment function modules in a distributed structure, thereby realizing independent adjustment and protection of multiple power domains or function modules in the chip.
[0031] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The ESD fast detection circuit of the present invention deeply integrates ESD detection, safety reset and fuse tuning logic to construct a "multi-factor authentication" tuning enable mechanism. This design greatly improves the fuse writing yield and long-term reliability of the chip in mass production testing, and effectively solves the system-level failure and performance discretization problem caused by ESD false triggering in multiple power domains of complex chips. Attached Figure Description
[0032] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.
[0033] Figure 1 This is a schematic diagram of the application topology of the ESD fast detection circuit with reset fuse adjustment function proposed in this invention;
[0034] Figure 2 This is a schematic diagram illustrating the design principle of the ESD fast detection circuit described in this invention;
[0035] Figure 3 This is a schematic diagram illustrating the design principle of the reset module and fuse adjustment function module described in this invention. Detailed Implementation
[0036] The present invention proposes an ESD fast detection circuit design and application with reset fuse adjustment function, the system-level topology of which is as follows: Figure 1As shown, the main components include: a logic control module, an ESD fast detection module, a reset module, and a fuse tuning module. In a preferred embodiment, the logic control module outputs 20 sets of control signals, distributedly connected to each input terminal of the 20 reset modules, and simultaneously distributedly connected to each input terminal of the 20 fuse tuning modules; the ESD fast detection module generates a set of global trigger signals (V1) distributedly connected to each input terminal of all 20 reset modules. This distributed architecture makes the present invention particularly suitable for complex system-on-chips (SoCs) with multiple power domains or a large number of functional modules requiring independent tuning.
[0037] like Figure 2 The ESD fast detection circuit design shown is described. The ESD fast detection module is the sensing core of the system. Its core design goal is to accurately distinguish between dangerous ESD fast pulses and normal slow power-on.
[0038] The module comprises: a first resistor R0, a second resistor R1, a first capacitor C1, a second capacitor C2, a first PMOS transistor PM1, a first NMOS transistor NM1, and a second NMOS transistor NM2. Its connection is characterized as follows: the upper end of the first resistor R0 is connected to the power supply BIAS, and its lower end is connected to the upper end of the first capacitor C1; the lower end of the first capacitor C1 is connected to GND. The upper end of the second resistor R1 is connected to the common node (denoted as node A) of the first resistor R0 and the first capacitor C1, and its lower end is connected to the gate of the first PMOS transistor PM1. The source of the first PMOS transistor PM1 is connected to BIAS, and its drain is connected to the drain of the first NMOS transistor NM1. The gate of the first NMOS transistor NM1 is connected to the gate of PM1, and its source is connected to GND. The upper end of the second capacitor C2 is connected to BIAS, and its lower end is connected to the gate of the second NMOS transistor NM2 (i.e., output port V1). The drain of the second NMOS transistor NM2 is connected to BIAS, and its source is connected to GND.
[0039] Specifically, R0 and C1 form an RC delay network, which acts as the "clock" for the detection circuit. During normal slow power-up, BIAS slowly charges C1 through R0, causing the voltage at node A to rise gradually. R1 limits the coupling current to prevent overshoot. When an ESD event occurs, the BIAS voltage spikes dramatically. Due to the extremely low impedance of C2, the spike in BIAS is directly and strongly coupled to node V1, causing its voltage to rapidly exceed the toggling threshold of the inverter composed of PM1 and NM1. This inverter, as the core logic decision unit, converts the analog voltage transient into a digital trigger signal: its output (i.e., the drain of NM1) toggles from high to low. This low-level signal directly turns off the second NMOS transistor NM2, thus forming a low-impedance path between BIAS and GND, safely discharging the large current generated by the ESD to ground.
[0040] like Figure 3 As shown, the reset module and the fuse trimming function module are closely coupled to form a safe fuse trimming logic controller.
[0041] The reset module is characterized by including a third NMOS transistor NM3 and a fourth NMOS transistor NM4. The gate of the third NMOS transistor NM3 is connected to the trigger signal V1 output by the ESD fast detection module, its drain is coupled to the output node (i.e., signal Ctrl) of the logic control module, and its source is connected to GND. The gate of the fourth NMOS transistor NM4 is connected to the drain of NM3, its drain is connected to the lower end of the third fuse resistor R3, and its source is connected to GND.
[0042] Specifically, the reset mechanism works as follows: Upon power-up, the V1 signal generated by the ESD fast detection module produces a brief high-level pulse. This pulse momentarily turns on the NM3 transistor, forcibly pulling down the output signal Ctrl of the logic control module (if it is currently in an uncertain state or high) to a low level (i.e., resetting it to an invalid level). This effectively releases the gate charge of the fourth NMOS transistor NM4, ensuring that the fuse resistor R3 will never blow accidentally during power-up instability. The reset effect can be ensured by precisely designing the width of the V1 pulse (e.g., by adjusting the values of R0, C1, or C2) and the width-to-length ratio (W / L) of the NM3 transistor. Simulations show that, under worst-case process corner conditions, a reset pulse of only about 1µs is needed to improve yield from 70% to 100%. To further improve design margin, redundant devices can be reserved for R0, R1, C1, and the NM3 transistor in the layout design to adjust the time constant or pull-down capability via metal options.
[0043] The fuse adjustment function module is characterized by including a third fuse resistor R3, a second PMOS transistor PM2, a third PMOS transistor PM3, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a first current mirror, a second current mirror, and a first adjustment position module.
[0044] The specific connection relationships are as follows: the upper end of the third fuse resistor R3 is connected to BIAS, and the lower end is connected to the drain of the fourth NMOS transistor NM4. The gates of the second PMOS transistor PM2 and the third PMOS transistor PM3 are connected to the output of the first current mirror, forming a PMOS stack structure with a current mirror load. The source of PM2 is connected to the lower end of the fuse resistor R3, and the test port TEST is also brought out. The gates of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are connected to the output of the second current mirror, forming an NMOS stack structure with a current mirror load. The drain of PM3 is connected to the drain of NM5, and they are both connected to the input terminal of the first adjustment module.
[0045] Adjustment position generation mechanism: Set the bias current of the first current mirror to be greater than the bias current of the second current mirror.
[0046] When the fuse resistor R3 is not blown: the BIAS voltage can allow the first current mirror to operate normally through R3. Since the driving capability of the first current mirror is stronger than that of the second current mirror, the adjustment node is pulled up to a high level (first adjustment level) by PM2 and PM3.
[0047] When fuse resistor R3 blows: the first current mirror shuts down due to loss of power. At this time, the second current mirror pulls the trimming node down to a low level (second trimming level) through NM5 and NM6.
[0048] The static configuration signal output by the trimming module can be used to fine-tune the threshold for matching memory addresses within the chip, or to enable / disable specific functional circuits.
[0049] Testing Function: Through the TEST test port, a known voltage can be forcibly applied using an external probe in chip test mode to simulate the state before and after the fuse blows, thereby verifying the functional correctness of the entire tuning logic module without performing real, irreversible fuse burning, which greatly improves testing efficiency and safety.
[0050] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.
Claims
1. An ESD fast detection circuit with reset fuse adjustment function, characterized in that, It includes an ESD fast detection module, a reset module, a fuse adjustment function module, and a logic control module; The ESD fast detection module is used to detect transient voltage changes on the power supply and distinguish between electrostatic discharge events and normal power-on. Its output terminal generates a trigger signal. The reset module has its input terminal coupled to the trigger signal and the output signal of the logic control module, and is used to reset the output of the logic control module to an invalid level in response to the trigger signal at the beginning of each power-on. The fuse trimming function module is coupled to the reset module and the logic control module, and includes a fuse resistor and a trimming position generation circuit based on current comparison; the trimming position generation circuit outputs a first trimming level when the fuse resistor is not blown, and outputs a second trimming level when the fuse resistor is blown. The output signal of the logic control module controls the fuse resistor's melting operation in the non-reset state, and the trigger signal serves as a gating signal.
2. The ESD fast detection circuit according to claim 1, characterized in that, The ESD fast detection module includes: An RC delay network, formed by the first resistor and the first capacitor connected in series, is connected between the power supply and ground. The second capacitor has its upper end connected to the power supply and its lower end outputting the trigger signal. An inverter composed of a first PMOS transistor and a first NMOS transistor has its input terminal coupled to the output terminal of a second resistor, and the common node of the first resistor and the first capacitor is coupled to the input terminal of the second resistor. The output terminal of the inverter controls the gate of the second NMOS transistor. The drain of the second NMOS transistor is connected to the power supply, and the source is grounded.
3. The ESD fast detection circuit according to claim 2, characterized in that, The second NMOS transistor is a large-size NMOS transistor, used to form a low-impedance discharge path between power supply and ground in the event of an ESD.
4. The ESD fast detection circuit according to claim 1, characterized in that, The reset module includes a third NMOS transistor and a fourth NMOS transistor; The gate of the third NMOS transistor receives the trigger signal, and its drain is coupled to the output node of the logic control module. The gate of the fourth NMOS transistor is coupled to the drain of the third NMOS transistor, and its drain is coupled to the lower end of the fuse resistor. During the power-on process, the pulse of the trigger signal turns on the third NMOS transistor, pulling the gate potential of the fourth NMOS transistor down to a low level.
5. The ESD fast detection circuit according to claim 4, characterized in that, The reset module also includes redundant resistors or capacitors for adjusting the pulse width of the trigger signal, and redundant NMOS devices for enhancing the pull-down capability of the third NMOS transistor.
6. The ESD fast detection circuit according to claim 1, characterized in that, The adjustment and position generation circuit includes: First current mirror and second current mirror; The bias current of the first current mirror is greater than the bias current of the second current mirror; The gates of the second PMOS transistor and the third PMOS transistor are controlled by the first current mirror, and the gates of the fifth NMOS transistor and the sixth NMOS transistor are controlled by the second current mirror. When the fuse resistor is not blown, the first current mirror works, pulling the adjustment level up to the first adjustment level through the second PMOS transistor and the third PMOS transistor. When the fuse resistor blows, the first current mirror is turned off, and the second current mirror pulls the adjustment bit down to the second adjustment level through the fifth NMOS transistor and the sixth NMOS transistor.
7. The ESD fast detection circuit according to claim 6, characterized in that: The trim bit output is used to fine-tune the address matching threshold of the chip's internal circuitry or to enable / disable specific trimming functions.
8. The ESD fast detection circuit according to claim 1, characterized in that, It also includes a test port connected to the fuse trimming function module, used to forcibly set the state of the trimming bit in test mode without performing actual fuse programming.
9. The ESD fast detection circuit according to claim 1, characterized in that, The logic control module outputs multiple sets of control signals to control multiple identical reset modules and fuse adjustment function modules in a distributed structure.