Industrial internet server power supply automatic detection method and system

Abstract

The invention relates to the technical field of computers, discloses an industrial internet server power supply automatic detection method and system, and aims to solve the problems of missing detection and false alarm of microsecond-level instantaneous power supply fluctuation events in the prior art. According to the method, a hardware-level state machine is deployed through an FPGA, and the voltage change rate is monitored in real time; low-speed sampling is carried out in a normal state, once the change rate exceeds a threshold value, high-speed and high-precision sampling is immediately switched, waveform data and hardware timestamps before and after triggering are locked, and a complete event packet is packaged and reported. The system comprises an analog signal conditioning and pre-differential module, a double-path analog-to-digital conversion module, an FPGA dynamic control module and a high-speed interface module. According to the invention, nanosecond response and capture delay within five microseconds are realized, the omission ratio and false alarm rate are obviously reduced, and the real-time performance and reliability of power supply monitoring are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of computers, and particularly relates to an industrial internet server power automatic detection method and system. BACKGROUND

[0002] With the deep penetration of the industrial internet in the fields of intelligent manufacturing, energy management and critical infrastructure, the reliability of the server power system has become a core element to ensure the continuity of production. The instantaneous voltage fluctuation (such as microsecond-level sudden drop caused by lightning or surge caused by power grid switching) commonly existing in industrial scenarios is extremely easy to trigger unplanned downtime of key devices such as programmable logic controllers (PLC), edge computing nodes, etc. The duration of such events is usually less than 10 microseconds, but it is difficult to be effectively captured due to the inherent defects of the existing detection system, which seriously threatens the stability and security of the industrial control system.

[0003] Among them, the power automatic detection technology focuses on real-time perception and response to voltage transient changes. Its basic goal is to complete signal acquisition, feature identification and alarm output at the first time of fluctuation, so as to provide decision basis for subsequent protection mechanisms (such as redundancy switching or load unloading). However, the current mainstream scheme generally adopts a vertical architecture of "sensor collection-network transmission-center server analysis", which places signal processing at a high level of software stack far away from the physical layer, resulting in that the entire detection link cannot meet the real-time requirements of industry.

[0004] The existing technology exposes multiple structural defects when dealing with high dynamic power events. First, the sampling delay is too high. Due to the dependence on operating system kernel scheduling and network protocol stack transmission, the end-to-end response time is generally more than 100 milliseconds, which is much higher than the duration window of microsecond-level fluctuation, resulting in a large number of missed detections. Secondly, the coordination fault between hardware and software makes it necessary to configure the sampling mode switching of the high-speed ADC chip through the MCU software, which introduces a switching delay of more than 10 microseconds, causing the high-precision detection window to miss the event itself. The above problems together constitute the industry dilemma of "seeing the fluctuation but not catching the event", and there is an urgent need for a new detection architecture that can realize sub-microsecond dynamic perception and closed-loop response at the front end of hardware. SUMMARY

[0005] The technical problem to be solved by the present application is to provide an industrial internet server power automatic detection method and system to overcome the missed detection and false alarm problems of microsecond-level transient power fluctuation events caused by high sampling delay, lack of dynamic response mechanism and coordination fault between hardware and software in the prior art.

[0006] In order to solve the above technical problems, the application provides an industrial internet server power supply automatic detection method, which realizes nanosecond-level real-time monitoring and determination of the power supply voltage signal change rate by deploying a field programmable gate array-based hardware-level state machine in a data acquisition front end. The method maintains low-speed monitoring sampling in a normal state. Once the voltage change rate exceeds the preset hardware threshold, the state transition is triggered within a single clock cycle, seamlessly switching to a high-speed high-precision sampling mode, and synchronously locking the monitoring data of a specific time window before triggering and the high-precision event data after triggering, finally encapsulating and reporting the complete waveform data packet containing the event lead-in, event process and hardware timestamp, thereby realizing deterministic capture of the voltage transient event with a duration of less than ten microseconds.

[0007] According to one aspect of the application, an industrial internet server power supply automatic detection method is provided, which comprises the following steps: The power bus voltage of the industrial internet server is collected in real time through an analog signal conditioning and pre-differentiation module, and an analog differential signal proportional to the time change rate of the power bus voltage is generated; The power bus voltage and the analog differential signal are processed by a dual-channel analog-to-digital conversion module, wherein the dual-channel analog-to-digital conversion module comprises: a monitoring analog-to-digital converter that works continuously at a first preset sampling frequency, used to convert the power bus voltage into a monitoring voltage data sequence; and a capture analog-to-digital converter that works at a second preset sampling frequency, which is higher than the first preset sampling frequency; The following sub-steps are performed by a dynamic state control and data processing module based on a field programmable gate array: The digital results of the analog differential signal are compared with a preset hardware change rate threshold by using a built-in hardware differential comparator unit on a clock-by-clock basis; When the digital results do not exceed the hardware change rate threshold, the monitoring state is maintained, wherein the monitoring analog-to-digital converter continuously works, and the generated monitoring voltage data sequence is written into a pre-configured hardware pre-trigger cycle buffer unit in real time; When the digital results exceed the hardware change rate threshold, the event capture state is triggered, and the dynamic state control and data processing module performs the following parallel operations: The capture analog-to-digital converter is activated instantaneously to sample the power bus voltage at the second preset sampling frequency to generate an event voltage data sequence, which is stored in a hardware event capture buffer unit; The hardware pre-trigger cycle buffer unit is locked, and the monitoring voltage data sequence of a preset time length before the triggering time is extracted as a lead-in waveform data from the hardware pre-trigger cycle buffer unit; A high-precision hardware timestamp is generated to record the absolute time of event triggering; The event capture unit combines and encapsulates the preamble waveform data, the event voltage data sequence, and the high-precision hardware timestamp to form a structured event data packet. The structured event data packet is sent to an upper monitoring server through a high-speed data interface module.

[0008] As an embodiment of the present application, the analog signal conditioning and pre-differentiation module specifically comprises: a high-input-impedance differential amplification circuit for obtaining a voltage signal from the power supply bus without disturbance; a fourth-order Butterworth active band-pass filter with a passband frequency range set to 1 kHz to 1 MHz for filtering out power frequency harmonics and high-frequency radio frequency interference; an active analog differentiation circuit based on an operational amplifier for calculating the time derivative of the filtered voltage signal in real time to generate the analog differentiated signal.

[0009] As an embodiment of the present application, the first preset sampling frequency is set to 100,000 samples per second, and the monitoring analog-to-digital converter adopts a successive approximation type register structure with a resolution of 16 bits; the second preset sampling frequency is set to 5,000,000 samples per second, and the capture analog-to-digital converter adopts a pipeline type structure with a resolution of 18 bits, and the conversion time from the standby state to the active state is less than 50 ns.

[0010] As an embodiment of the present application, the hardware differential comparator unit in the dynamic state control and data processing module based on the field programmable gate array is synthesized into a pure combinational logic circuit through a hardware description language, the hardware change rate threshold is stored in a 32-bit register that can be dynamically configured through the high-speed data interface module, and the logic delay of the comparison operation is limited within two main clock periods of the field programmable gate array.

[0011] Further, the adaptive sampling clock generation unit in the dynamic state control and data processing module generates the monitoring clock corresponding to the first preset sampling frequency and the capture clock corresponding to the second preset sampling frequency from a single stable crystal oscillator source by using a mixed-mode clock manager primitive inside the field programmable gate array; the output signal of the hardware differential comparator unit directly controls a two-way data selector for selecting a clock signal output to the dual-path analog-to-digital conversion module, and the clock switching process is realized through dedicated clock gating logic to achieve non-glitch switching.

[0012] Further, the hardware pre-trigger cycle buffer unit is implemented by a block random access memory inside the field programmable gate array, with a depth of 1024 words and a width of 16 bits, for storing the monitoring voltage data in the first 10 milliseconds before the trigger; the hardware event capture buffer unit is also implemented by a block random access memory, with a depth of 4096 words and a width of 18 bits, for storing the high-precision event voltage data in the next 800 microseconds after the trigger.

[0013] Further, the event-driven data capture and packaging unit is implemented as a four-state hardware finite state machine, with the state transition logic completely implemented by hardware circuits, and the specific states including: a monitoring state, in which the monitoring analog-to-digital converter works, and data is continuously written into the hardware pre-trigger cycle buffer unit; a trigger state, in which the state machine jumps from the monitoring state as soon as the hardware differential comparator unit outputs a valid signal; a capture state, in which the operations of activating the capture analog-to-digital converter, locking and extracting the leading waveform data, and writing the high-precision event data into the hardware event capture buffer unit are performed in parallel; a packaging and transmission state, in which the state machine jumps from the capture state after the completion of the capture operation, performs the structured packaging of the data packet, and hands over the data packet to the high-speed data interface module, and then returns to the monitoring state automatically.

[0014] According to another aspect of the present application, an industrial internet server power automatic detection system is provided, which includes: an analog signal conditioning and pre-differentiation module, configured to collect the power bus voltage of the industrial internet server in real time, and generate an analog differential signal proportional to the time rate of change of the power bus voltage; a dual-channel analog-to-digital conversion module, coupled to the analog signal conditioning and pre-differentiation module, configured to perform parallel digital processing on the power bus voltage and the analog differential signal, including a monitoring analog-to-digital converter working at a first preset sampling frequency, and a capture analog-to-digital converter working at a second preset sampling frequency, which is higher than the first preset sampling frequency; a field programmable gate array-based dynamic state control and data processing module, coupled to the dual-channel analog-to-digital conversion module, configured to perform hardware-level seamless switching between the monitoring state and the event capture state according to the comparison result of the digital result of the analog differential signal and a preset hardware rate threshold, and in the event capture state, to capture the event waveform, lock the leading waveform, and generate a timestamp in parallel, and finally to package the data into a structured event data packet; A high-speed data interface module is coupled to the dynamic state control and data processing module, and is configured to send the structured event data packet to an upper monitoring server.

[0015] As an embodiment of the present application, the analog signal conditioning and pre-differentiation module comprises a high input impedance differential amplification circuit, a fourth-order Butterworth active band-pass filter, and an active analog differentiation circuit based on an operational amplifier.

[0016] As an embodiment of the present application, the dynamic state control and data processing module specifically comprises: A hardware differentiation comparator unit is configured to perform hardware logic comparison between the digitized result of the analog differentiated signal and the hardware change rate threshold value; An adaptive sampling clock generation unit is configured to switch between a monitoring clock corresponding to the first preset sampling frequency and a capture clock corresponding to the second preset sampling frequency according to the comparison result of the hardware differentiation comparator unit; A hardware pre-trigger loop buffer unit is configured to cyclically store a monitoring voltage data sequence generated by the monitoring analog-to-digital converter in a monitoring state; A hardware event capture buffer unit is configured to store an event voltage data sequence generated by the capture analog-to-digital converter in an event capture state; An event-driven data capture and packaging unit is configured to control the entire event capture process, and perform leading data extraction, timestamp generation, and data packet packaging operations.

[0017] In summary, the present application has at least one of the following beneficial technical effects: (1) The present application completely eliminates the millisecond-level delay caused by network transmission, operating system scheduling, and software application layer processing in the traditional architecture by completely hardwareizing the detection logic and deploying it in a field programmable gate array at the front end of data acquisition. Based on the hardware comparison trigger mechanism of the analog differentiated signal, the present application realizes nanosecond-level abnormal change rate response, compresses the overall delay from power fluctuation to starting high-precision data capture to within five microseconds, and ensures the deterministic capture of microsecond-level transient events required by industrial standards.

[0018] (2) The adaptive sampling method proposed in the present application performs instantaneous seamless switching between the low-speed monitoring mode and the high-speed capture mode through a hardware state machine, which not only ensures the complete high-fidelity recording of high-speed transient event waveforms, but also avoids the massive invalid data and power consumption caused by continuous high-frequency sampling during the stable period. This sampling rate dynamic adjustment mechanism driven by the signal itself fundamentally solves the missed detection problem of the fixed sampling rate scheme when facing high change rate events, and reduces the missed detection rate to less than 0.005%.

[0019] (3): This invention uses a hardware threshold based on the voltage time change rate as the trigger condition. Compared with the traditional voltage amplitude threshold method, it can more effectively distinguish between steep-edge transient faults caused by lightning strikes, load changes, etc., and periodic, slowly changing interferences such as inverter harmonics. This mechanism significantly improves the accuracy of fault identification, reducing the false alarm rate caused by environmental noise from more than 30% to less than 1 / 1000, and greatly reducing unnecessary downtime for maintenance.

[0020] (4): This invention integrates signal conditioning, analog-to-digital conversion, event judgment, data caching and encapsulation into the front-end detection module through integrated hardware design, constructing an ultra-low latency critical path without software intervention. The host computer is only responsible for post-event analysis and storage, rather than real-time decision-making, which completely solves the problem of hardware and software collaboration gap in the prior art, and provides industrial Internet servers with unprecedented real-time performance and reliability of power quality monitoring. Attached Figure Description

[0021] Fig. 1 This is a schematic diagram of the overall technical solution architecture proposed in this invention; Fig. 2 This is a schematic diagram of the dynamic state control and data processing module based on field-programmable gate array in this invention; Detailed Implementation

[0022] This invention provides an automatic power supply detection method and system for industrial internet servers, aiming to solve the problems of missed detection and false alarms of microsecond-level instantaneous power fluctuation events caused by excessively high sampling delays, lack of dynamic response mechanisms, and hardware-software coordination gaps in existing technologies. This method deploys a hardware-level state machine based on a field-programmable gate array (FPGA) at the data acquisition front end to achieve nanosecond-level real-time monitoring and judgment of the power supply voltage signal change rate. Upon detecting an anomaly, it seamlessly switches to a high-speed, high-precision sampling mode, thereby ensuring deterministic capture of voltage transient events lasting less than ten microseconds.

[0023] Reference Figs. 1-2 The automatic power supply detection method for industrial internet servers includes the following steps, which are numbered for ease of understanding, as follows: S1 acquires the power bus voltage of the industrial internet server in real time through the analog signal conditioning and pre-differentiation module, and generates an analog differential signal that is proportional to the time change rate of the power bus voltage.

[0024] S2, the power bus voltage and analog differential signal are processed in parallel by a dual-channel analog-to-digital converter module. The dual-channel analog-to-digital converter module includes a monitoring analog-to-digital converter that operates continuously at a first preset sampling frequency to convert the power bus voltage into a monitoring voltage data sequence; and a capture analog-to-digital converter that operates at a second preset sampling frequency, which is higher than the first preset sampling frequency.

[0025] S3 executes the following sub-steps through the dynamic state control and data processing module based on field-programmable gate array.

[0026] S31 uses a built-in hardware differential comparator unit to compare the digitized result of the analog differential signal with a preset hardware rate of change threshold clock cycle.

[0027] S32 maintains a monitoring state as long as the digitization result does not exceed the hardware rate of change threshold, wherein the monitoring analog-to-digital converter continues to work and writes the generated monitoring voltage data sequence into a pre-configured hardware pre-trigger cyclic buffer unit in real time.

[0028] S33, when the digitization result exceeds the hardware change rate threshold, the event capture state is immediately triggered, and the dynamic state control and data processing module performs the following parallel operations.

[0029] S331 instantaneously activates the capture analog-to-digital converter to perform high-precision sampling of the power bus voltage at a second preset sampling frequency, generate an event voltage data sequence, and store it in a hardware event capture buffer unit.

[0030] S332 locks the hardware pre-trigger loop buffer unit and extracts the monitoring voltage data sequence of a preset time length before the trigger moment as the preamble waveform data.

[0031] S333 generates a high-precision hardware timestamp to record the absolute moment the event was triggered.

[0032] S34, in the event-driven data capture and encapsulation unit, combines and encapsulates the preamble waveform data, event voltage data sequence, and high-precision hardware timestamp to form a structured event data packet.

[0033] S4 sends structured event data packets to the upper-level monitoring server through the high-speed data interface module.

[0034] In step S1, the analog signal conditioning and pre-differentiation module specifically includes a high input impedance differential amplifier circuit, a fourth-order Butterworth active bandpass filter, and an operational amplifier-based active analog differentiator circuit. The high input impedance differential amplifier circuit obtains the voltage signal from the power bus of the industrial internet server without disturbance. Its input impedance is not less than 100 megohms, and its common-mode rejection ratio is not less than 120 decibels, to ensure accurate extraction of the power bus voltage without introducing load effects.

[0035] The passband frequency range of the fourth-order Butterworth active bandpass filter is set to 1 kHz to 1 MHz. It is used to filter out the 50 Hz power frequency and its harmonic components, while suppressing high-frequency noise from radio frequency interference sources. Its passband ripple is less than 0.5 dB and its stopband attenuation is greater than 60 dB.

[0036] The active analog differentiating circuit receives the filtered voltage signal, calculates the time derivative of the signal in real time, and outputs an analog differential signal that is proportional to the rate of voltage change. Its differential time constant is set to 200 nanoseconds to match the typical rising edge characteristics of transient events in industrial power supplies.

[0037] In step S2, the dual-channel analog-to-digital converter (ADC) performs parallel digital processing on the power bus voltage and the analog differential signal. The ADC is monitored to operate continuously at a first preset sampling frequency of 100,000 samples per second, employing a 16-bit successive approximation register structure. Its integral nonlinearity error does not exceed ±1 Least Significant Bit, its differential nonlinearity error does not exceed ±0.5 Least Significant Bit, and its signal-to-noise ratio is not less than 92 dB.

[0038] The capture analog-to-digital converter operates at a second preset sampling frequency of five million samples per second, employing an 18-bit pipelined architecture. Its conversion time from standby to fully active state is less than fifty nanoseconds, the integral nonlinearity error does not exceed ±2 least significant bits, and the signal-to-noise ratio is not less than 96 dB. Both analog-to-digital converters share the same reference voltage source, provided by a low-temperature drift reference chip, with a temperature coefficient not exceeding five ppm per degree Celsius, ensuring strict consistency of the two data streams in terms of amplitude scale.

[0039] In step S3, the dynamic state control and data processing module based on a field-programmable gate array (FPGA) is the core execution unit of the entire method. This module integrates a hardware differential comparator unit, an adaptive sampling clock generation unit, a hardware pre-triggered circular buffer unit, a hardware event capture buffer unit, and an event-driven data capture and encapsulation unit.

[0040] In sub-step S31, the hardware differential comparator unit receives the digitization result of the analog differential signal from the output of the monitoring analog-to-digital converter and compares it with the hardware rate of change threshold stored in the 32-bit register clock cycle by clock cycle.

[0041] This comparator is synthesized into a pure combinational logic circuit using a hardware description language, containing no sequential components. Its logic delay is strictly limited to within two cycles of the field-programmable gate array's master clock. The master clock frequency is set to 250 MHz, corresponding to a clock cycle of four nanoseconds; therefore, the completion time of the comparison operation does not exceed eight nanoseconds. The hardware rate of change threshold can be dynamically configured by the host monitoring server via a high-speed data interface module. Its default value is set to the digital equivalent of a voltage change rate of five volts per microsecond, calculated based on the reference voltage of the analog-to-digital converter and the time constant of the differentiating circuit.

[0042] In sub-step S32, when the output of the hardware differential comparator unit indicates that the rate of change of voltage does not exceed the threshold, the system remains in monitoring state. In this state, the monitoring analog-to-digital converter continues to operate at a frequency of 100,000 samples per second, and its output sixteen-bit monitoring voltage data sequence is written to the hardware pre-trigger circular buffer unit in real time.

[0043] This buffer unit is implemented using the block random access memory within a field-programmable gate array (FPGA), with a depth of 1024 words and a width of 16 bits, corresponding to a storage time of 10 milliseconds. The write address is generated by an 11-bit cyclic counter, which automatically resets to zero whenever it overflows, achieving cyclic overwriting of data. This buffer unit always maintains the latest 10-millisecond voltage waveform data, providing complete preamble information for subsequent possible events.

[0044] In sub-step S33, once the hardware differential comparator unit detects that the voltage change rate exceeds the threshold, the system immediately enters the event capture state. This state transition is completed by the hardware state machine within one clock cycle, without any software intervention or interrupt delay.

[0045] In sub-step S331, the capture analog-to-digital converter (ADC) is instantaneously activated. The activation signal is directly driven by the output of the hardware differential comparator unit and transmitted to the control pin of the capture ADC via a dedicated enable path. Since this path is a purely hardware connection, the propagation delay is less than two nanoseconds. Combined with the capture ADC's own activation delay of fifty nanoseconds, the entire startup process is completed within fifty-two nanoseconds.

[0046] Upon activation, the capture analog-to-digital converter samples the power bus voltage with high precision at a frequency of five million samples per second, generating an 18-bit event voltage data sequence, which is then sequentially written into the hardware event capture buffer unit. This buffer unit is also implemented using block random access memory, with a depth of 4,096 words and a width of 18 bits, capable of storing 800 microseconds of high-precision event data.

[0047] In sub-step S332, the hardware pre-triggered circular buffer unit is immediately locked. The locking operation is achieved by disabling its write enable signal, ensuring that the buffer contents are not overwritten by new data during event capture. Subsequently, the event-driven data capture and encapsulation unit reads the current value of the circular counter, which indicates the write position in the buffer at the trigger moment. Based on this position, the system backtracks one thousand sampling points (corresponding to ten milliseconds) to extract the complete preamble waveform data. The data extraction process is completed by a dedicated read address generator, which sequentially outputs the contents of all memory cells from the start address to the trigger address.

[0048] In sub-step S333, a high-precision hardware timestamp is generated. This timestamp is provided by a 64-bit free-running counter, whose clock source is a 100 MHz temperature-compensated crystal oscillator, corresponding to a time resolution of 10 nanoseconds. The counter value is latched at the trigger moment and encapsulated together with the preamble waveform data and the event voltage data sequence.

[0049] In sub-step S34, the event-driven data capture and encapsulation unit combines the preamble waveform data, event voltage data sequence, and high-precision hardware timestamp into a structured event data packet. This data packet uses a fixed format, including a header, timestamp field, preamble data field, event data field, and checksum. The header identifies the data packet type and version information; the timestamp field occupies eight bytes; the preamble data field contains 1024 sixteen-bit integers; the event data field contains 4096 eighteen-bit integers, padded with zeros to 32-bit alignment; the checksum is generated using a 32-bit cyclic redundancy check algorithm. The entire encapsulation process is controlled by a hardware state machine and is executed automatically after capture.

[0050] In step S4, the structured event data packets are sent to the upper-level monitoring server through a high-speed data interface module. This interface module uses a gigabit Ethernet physical layer and supports the IEEE 1588 precision time protocol, ensuring low latency and high reliability of data transmission. The data packets are transmitted through a direct memory access channel, bypassing the operating system kernel, with an end-to-end transmission latency of less than one hundred microseconds.

[0051] The adaptive sampling clock generation unit within the dynamic state control and data processing module of the field-programmable gate array (FPGA) utilizes the mixed-mode clock manager primitive within the FPGA to generate a monitor clock and a capture clock from a single stable crystal oscillator source. The crystal oscillator frequency is 100 MHz, and the mixed-mode clock manager generates a 10 kHz monitor clock and a 5 MHz capture clock via a phase-locked loop (PLL) and a digital clock manager, respectively. The output signal of the hardware differential comparator unit directly controls a 2-to-1 data selector to select the clock signal output to the dual-channel analog-to-digital converter (ADC). The clock switching process is implemented using dedicated clock gating logic to ensure no glitches occur during switching, preventing sampling errors in the ADC due to clock jitter.

[0052] The event-driven data capture and encapsulation unit is implemented as a four-state hardware finite state machine, with its state transition logic entirely implemented by hardware circuitry. The states include: monitoring state, trigger state, capture state, and encapsulation and transmission state. In the monitoring state, the system continuously acquires low-speed data. When the comparator output is valid, the state machine transitions to the trigger state within one clock cycle. The trigger state lasts only one clock cycle before entering the capture state. In the capture state, the system performs high-precision sampling, preamble data locking, and timestamp generation in parallel. When the capture buffer is full or the preset sampling duration is reached, the state machine transitions to the encapsulation and transmission state. In this state, data packet encapsulation is completed and the data is transferred to the high-speed data interface module. After completion, it automatically returns to the monitoring state. The entire state transition process is performed without software intervention, and the delay is deterministic and controllable.

[0053] Additionally, the industrial internet server power automatic detection system includes an analog signal conditioning and pre-differentiation module, a dual-channel analog-to-digital converter module, a dynamic state control and data processing module based on a field-programmable gate array (FPGA), and a high-speed data interface module. The analog signal conditioning and pre-differentiation module is deployed in the analog front-end area of ​​the printed circuit board, employing a four-layer board design, one layer of which is a complete ground plane to minimize electromagnetic interference. The dual-channel FPGA module is located adjacent to the analog signal conditioning module, and its analog input traces use a 50-ohm controlled impedance design with full grounding. The FPGA uses Xilinx Artix-7 series devices, whose internal resources are sufficient to implement all hardware functional modules, including at least twenty blocks of random access memory, four mixed-mode clock managers, and ample lookup tables and flip-flops. The high-speed data interface module is integrated within the FPGA, achieving gigabit Ethernet connectivity via a gigabit transceiver.

[0054] The system is powered by the auxiliary power rail of the industrial internet server, and converted to the required voltage for each module via a local low-dropout regulator. The analog section's power supply is processed by a π-type filter network, while the digital section's power supply uses a multi-stage decoupling capacitor network to ensure power integrity. The entire system is encapsulated in a metal shielded enclosure, with the enclosure connected to the system ground at a single point to prevent external electromagnetic fields from interfering with the internal sensitive analog circuitry.

[0055] Through the above method and system, this invention achieves deterministic capture of microsecond-level transient events of power bus voltage in industrial internet servers. The overall delay from the occurrence of voltage fluctuations to the initiation of high-precision sampling is compressed to less than five microseconds, with a false negative rate of less than 0.5% and a false positive rate of less than 0.1%, completely solving the detection failure problem caused by architectural defects and algorithm delays in existing technologies.

[0056] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects.

[0057] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An automatic power supply detection method for industrial internet servers, characterized in that, include: The power bus voltage of the industrial internet server is acquired in real time through an analog signal conditioning and pre-differentiation module, and an analog differential signal proportional to the time change rate of the power bus voltage is generated. The power bus voltage and the analog differential signal are processed in parallel by a dual-channel analog-to-digital converter module. The dual-channel analog-to-digital converter module includes a monitoring analog-to-digital converter that operates continuously at a first preset sampling frequency to convert the power bus voltage into a monitoring voltage data sequence, and a capture analog-to-digital converter that operates at a second preset sampling frequency, which is higher than the first preset sampling frequency. Through the dynamic state control and data processing module based on field-programmable gate array, the event is captured based on voltage change rate comparison, and high-speed sampling and encapsulation are used to form a structured event data packet; The structured event data packets are sent to the upper-level monitoring server via a high-speed data interface module.

2. The automatic power supply detection method for industrial internet servers according to claim 1, characterized in that, Event data packets are acquired through the dynamic state control and data processing module, including the following operations: using the built-in hardware differential comparator unit, the digitization result of the analog differential signal is compared with a preset hardware rate of change threshold clock cycle. When the digitization result does not exceed the hardware rate of change threshold, the monitoring state is maintained, in which the monitoring analog-to-digital converter continues to work and writes the generated monitoring voltage data sequence into a pre-configured hardware pre-trigger loop buffer unit in real time. When the digitization result exceeds the hardware change rate threshold, the event capture state is immediately triggered. The dynamic state control and data processing module instantly activates the capture analog-to-digital converter to perform high-precision sampling of the power bus voltage at the second preset sampling frequency, generate an event voltage data sequence and store it in a hardware event capture buffer unit. At the same time, the hardware pre-trigger loop buffer unit is locked and the monitoring voltage data sequence of a preset time length before the trigger time is extracted from it as the preamble waveform data, and a high-precision hardware timestamp is generated to record the absolute moment of the event trigger. The event-driven data capture and encapsulation unit combines and encapsulates the preamble waveform data, event voltage data sequence, and high-precision hardware timestamp to form a structured event data packet.

3. The automatic power supply detection method for industrial internet servers according to claim 1, characterized in that, The analog signal conditioning and predifferentiation module includes: A high input impedance differential amplifier circuit for obtaining voltage signals from the power bus without disturbance; A fourth-order Butterworth active bandpass filter with a passband frequency range of 1 kilohertz to 1 megahertz is used to filter out power frequency harmonics and high-frequency radio frequency interference. An active analog differentiator circuit based on an operational amplifier is used to calculate the time derivative of the filtered voltage signal in real time and generate an analog differential signal.

4. The automatic power supply detection method for industrial internet servers according to claim 1, characterized in that, The hardware differential comparator unit is synthesized into a pure combinational logic circuit using a hardware description language. The hardware rate of change threshold is stored in a 32-bit register that can be dynamically configured via a high-speed data interface module. The logic delay of the comparison operation is limited to two master clock cycles of the field-programmable gate array.

5. The automatic power supply detection method for industrial internet servers according to claim 2, characterized in that, The adaptive sampling clock generation unit in the dynamic state control and data processing module uses the mixed-mode clock manager primitive inside the field-programmable gate array to generate a monitoring clock corresponding to the first preset sampling frequency and a capture clock corresponding to the second preset sampling frequency from a single stable crystal oscillator source. The output signal of the hardware differential comparator unit directly controls a 2-to-1 data selector to select the clock signal output to the dual-channel analog-to-digital converter module. The clock switching process is achieved through dedicated clock gating logic to achieve glitch-free switching.

6. The automatic power supply detection method for industrial internet servers according to claim 2, characterized in that, The event-driven data capture and encapsulation unit is implemented as a four-state hardware finite state machine, with its state transition logic entirely implemented by hardware circuitry. The specific states include: In monitoring mode, the analog-to-digital converter is monitored, and the circular buffer unit is triggered before data is continuously written to the hardware. Trigger state: When the output of the hardware differential comparator unit is valid, the state machine immediately jumps from the monitoring state to this state; Capture state: In this state, the operations of activating the capture analog-to-digital converter, locking and extracting the preamble waveform data, and writing high-precision event data into the hardware event capture buffer unit are performed in parallel. Encapsulation and Transmission State: After the capture operation is completed, the state machine jumps to this state, performs structured encapsulation of the data packet, and hands the data packet over to the high-speed data interface module. After completion, it automatically returns to the monitoring state.

7. The automatic power supply detection method for industrial internet servers according to claim 2, characterized in that, Structured event data packets use a fixed format, including a header, timestamp field, preamble field, event data field, and checksum; The timestamp field occupies 8 bytes; the preamble data field contains 1024 sixteen-bit integers; the event data field contains 4096 eighteen-bit integers, with high-order bits padded with zeros to 32-bit alignment; the checksum is generated using a 32-bit cyclic redundancy check algorithm.

8. An automatic power supply detection system for industrial internet servers, characterized in that, include: The analog signal conditioning and pre-differentiation module is used to acquire the power bus voltage of the industrial internet server in real time and generate an analog differential signal that is proportional to the time change rate of the power bus voltage. A dual-channel analog-to-digital converter module, coupled to an analog signal conditioning and pre-differentiation module, is used to perform parallel digital processing of power bus voltage and analog differential signal. It includes a monitoring analog-to-digital converter that operates continuously at a first preset sampling frequency, and a capture analog-to-digital converter that operates at a second preset sampling frequency, the second preset sampling frequency being higher than the first preset sampling frequency. The dynamic state control and data processing module based on the field-programmable gate array is coupled to the dual-channel analog-to-digital converter module. It is used to seamlessly switch between the monitoring state and the event capture state at the hardware level based on the comparison result of the digitization result of the analog differential signal and a preset hardware rate of change threshold. In the event capture state, it captures the event waveform in parallel, locks the preamble waveform and generates a timestamp, and finally encapsulates the data into a structured event data packet. The high-speed data interface module, coupled to the dynamic status control and data processing module, is used to send structured event data packets to the upper-level monitoring server.

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