Hardware acceleration operator library design method for PDLP linear programming algorithm

Abstract

The invention belongs to the technical field of linear programming algorithm hardware acceleration, and discloses a PDLP linear programming algorithm hardware acceleration operator library design method, which comprises three core steps of operator static storage planning, operator scheduling template design and operator online scheduling optimization. The life cycle of variables in the graph is calculated through an analysis operator, storage sharing distribution is carried out, and storage requirements are reduced; hardware resource constraints are adapted through a circular dicing and Ping-Pong execution mode; and scheduling parameters are optimized on line according to sparse matrix characteristics. And finally generating a high-performance operator library code which can be matched with the PDLP algorithm hardware acceleration device. According to the method, the page view of an off-chip memory is effectively reduced, the hardware resource utilization rate and the algorithm execution efficiency are improved, linear programming problems of different scales can be solved, and the problem that an existing PDLP hardware acceleration scheme lacks fine-grained hardware resource optimization is solved.

Description

Technical Field

[0001] This invention belongs to the field of hardware acceleration technology for linear programming algorithms, and particularly relates to a design method for a hardware acceleration operator library for the PDLP linear programming algorithm. Background Technology

[0002] Linear programming (LP) is a mathematical theory and method for studying the extremum problems of a linear objective function under linear constraints. It is an important branch of operations research and is widely used in fields requiring optimal resource allocation, such as transportation and logistics, economic analysis, military operations, and engineering. The standard form of a maximizing linear programming problem can be expressed as: Given n real numbers c1, c2, ..., c... n m real numbers b1, b2, ..., b m ; and mn real numbers a ij Let i = 1, 2, ..., m, and j = 1, 2, ..., n. The goal is to find n real numbers x1, x2, ..., xn. n ,

[0003] maximize

[0004] Satisfy constraints

[0005]

[0006] x j ≥0, j=1,2,…,n (3)

[0007] (1) is the objective function, and (2) and (3) are the constraints. Each constraint corresponds to a half-space in n-dimensional space, and the feasible region formed by the intersection of these half-spaces is called the simplex.

[0008] Classical methods for solving linear programming problems primarily employ the Simplex Method and the Interior Point Method (IPM). The Simplex Method leverages the convexity of the simplex and the linearity of the objective function, moving along the outer edge of the feasible region and maintaining a feasible solution corresponding to a simplex vertex in each iteration until a locally optimal (actually globally optimal) vertex is found. While the Simplex Method is typically quite fast in practice, its time complexity can be exponential in the worst case. The Interior Point Method moves within the feasible region and iterates along a central path, eventually approximating the optimal vertex. The Interior Point Method offers better numerical stability and its time complexity is polynomial. However, both the Simplex Method and the Interior Point Method are difficult to extend to large-scale linear programming problems because they rely on LU decomposition (simplex method) or Cholesky decomposition (interior point method). Although LU decomposition or Cholesky decomposition is computationally expensive, it involves fine-grained, long-sequence dependencies, making it difficult to utilize the advantages of modern computing architectures such as GPUs and distributed computing. Therefore, the Simplex Method and the Interior Point Method primarily operate on a single CPU.

[0009] First-order methods are a new class of linear programming algorithms that use gradient descent to find the optimal solution. Their core computation is SpMV, which exhibits excellent parallelism and is naturally adapted to modern computing architectures such as distributed computing and GPUs, showing great potential for solving large-scale linear programming problems. However, traditional first-order methods generally suffer from a tailing effect: the algorithm can quickly obtain a relatively accurate approximate solution, but the speed of approaching the exact solution gradually slows down. To address this issue, the PDLP algorithm significantly improves its convergence by introducing enhancement techniques.

[0010] Currently, there are few hardware acceleration solutions for the PDLP algorithm, mainly including GPU-based cuPDLP and general-purpose SpMV-based PDLP hardware accelerator solutions. The former uses GPUs to accelerate SpMV operations and various types of vector operations in the PDLP algorithm, accelerating it to a level comparable to mainstream commercial solvers, and even outperforming it in large-scale linear programming solutions. SpMV is implemented using the high-performance cuSparse library, element-wise vector operations are implemented using a custom CUDA core, and Reduce vector operations are implemented in two steps: element-wise and Reduce operations. The latter proposes a PDLP algorithm hardware accelerator device that simultaneously supports general-purpose SpMV operations and vector operations. It unifies the data transmission of SpMV and vector operations through an on-chip network, enabling the fusion of CSR SpMV operations and vector operations. Reduce-type vector operations are implemented in one step, but the specific optimization and implementation scheme of its operators are not disclosed.

[0011] The hardware acceleration device and two-operator fusion scheme for the PDLP algorithm applicable to this invention are as follows: Figure 1 As shown, its characteristic is that the PDLP algorithm hardware acceleration device is responsible for the core calculation of adaptive step-size iteration, and the two-operator fusion scheme only includes the basic solution update operator. Figure 1 (①) and dual solution update operator ( Figure 1 (②) In this scheme, the dual solution update operator integrates the CSR SpMV and CSC SpMV operations. Compared with existing hardware acceleration schemes for PDLP algorithms, this fusion scheme significantly reduces the amount of off-chip memory access, which is beneficial for improving the processing performance of storage-constrained PDLP algorithms.

[0012] While operator fusion schemes can significantly optimize off-chip memory access between operators, off-chip memory access is still required during operator computation. Furthermore, limited local storage capacity necessitates cyclical chunking of operator operations to support linear programming problems of varying scales. Therefore, the operator fusion scheme is a relatively macroscopic description, failing to consider the hardware resource constraints of PDLP algorithm hardware acceleration devices and thus preventing direct computation on PDLP algorithm hardware acceleration devices. Publicly available and effective methods and technologies for converting the PDLP algorithm's operator fusion scheme into a corresponding high-performance operator library are still lacking. Summary of the Invention

[0013] This invention addresses the problem that existing hardware acceleration schemes for the PDLP algorithm are limited to relatively macroscopic operator fusion schemes and lack consideration for the microscopic hardware resource constraints of the hardware acceleration device. It proposes a hardware acceleration operator library design method for the PDLP linear programming algorithm. Through steps such as operator static storage planning, operator scheduling templates, and operator online scheduling optimization, the operator fusion scheme of the PDLP algorithm can be converted and optimized into a corresponding high-performance operator library. This further reduces off-chip memory access from the operator operation and optimizes the processing performance of the PDLP algorithm.

[0014] To address the aforementioned technical problems, the specific technical solution of the hardware acceleration operator library design method for the PDLP linear programming algorithm of the present invention is as follows:

[0015] A hardware-accelerated operator library design method for the PDLP linear programming algorithm, wherein the method takes as input an operator fusion scheme for the PDLP algorithm and outputs as the code implementation of the fusion operator, and includes the following steps:

[0016] Step 1: Static storage planning for operators. By analyzing the lifetime of each variable in the operator computation graph, variables with non-overlapping lifetimes are allocated to the same storage space, generating a serialized operator operation order and variable storage allocation scheme.

[0017] Step 2: Operator scheduling template design. Hardware constraints are introduced into the operator operation process through cyclic block cutting to form a multi-layer data structure. A scheduling template including local loop order, block size and Ping-Pong execution mode is designed.

[0018] Step 3: Online operator scheduling optimization. For operators containing SpMV operations, a performance analysis model is constructed, and the optimal scheduling parameters are selected online.

[0019] Step 4: Operator library code generation. Based on the scheduling template and optimal parameters, the configuration and instruction flow of the hardware acceleration device are generated to form a callable operator library.

[0020] Furthermore, the operator static storage planning in step 1 includes the following steps:

[0021] Step 1.1: Analyze and calculate the lifetime of each variable in the graph, and construct a register interferogram (RIG) based on the lifetime;

[0022] Step 1.2: Transform the variable storage allocation problem into a minimum coloring problem using RIG, that is, use the fewest colors to color nodes connected by edges, so that nodes with the same color can share the same storage space. The minimum number of colors corresponds to the minimum number of storage spaces.

[0023] Furthermore, in step 2:

[0024] The multi-layered data structure includes complete vectors / matrices, block vectors / matrices, and basic vectors / matrices; the size of the basic vectors / matrices is determined by the parallelism of the hardware data path.

[0025] The size of the block vector / matrix is ​​limited by the hardware storage capacity and supports Ping-Pong execution. Furthermore, in step 3: the performance analysis model takes as input a sparse matrix of a linear programming problem, an operator scheduling template, and dedicated hardware storage constraints, and outputs optimal scheduling parameters.

[0026] Furthermore, in step 4, the CPU is responsible for converting the optimal operator scheduling into the configuration and instruction stream of the PDLP algorithm hardware acceleration device, and in conjunction with the corresponding driver function, forming an operator call to the PDLP algorithm hardware acceleration device.

[0027] Furthermore, the task division between the main processor (CPU) and the PDLP hardware acceleration device during PDLP algorithm execution is as follows: First, the main processor (CPU) reads and preprocesses the linear programming problem to obtain the corresponding vectors, sparse matrix K, and initial parameters. Second, the PDLP hardware acceleration device performs core calculations for adaptive step-size iteration based on the preprocessed data, including updating the basic solution x, the dual solution y, and the step size η. Finally, the main processor (CPU) determines whether the step size η meets the performance requirements. If not, it continues the current iteration to update the basic solution x, the dual solution y, and the step size η. If it does, it determines whether the convergence condition is met. If not, it starts the next iteration. If it does, it outputs the final result including the basic solution x and the dual solution y. The PDLP hardware acceleration device adopts a two-operator fusion scheme, including a basic solution update operator and a dual solution update operator.

[0028] Furthermore, the storage allocation for the basic solution update operator and the dual solution update operator is included: the basic solution update operator consists of a vector operation sequence of Axpy→Axpy→Cmp→Cmp→Axpy→Nrm, where each operation depends on the input of the previous operation, and the order of operations is fixed. The lifetime of each variable can be determined based on the data dependency graph of the basic solution update operator, and the RIG of the basic solution update operator is generated. Based on the RIG coloring, the allocation of basic solution update variables and the order of operations are determined. The RIG of the dual solution update operator is generated based on the data dependency graph, and the backtracking method is used for coloring.

[0029] Furthermore, the data partitioning and scheduling templates for the basic solution update operator and the dual solution update operator are as follows: The basic solution update operator consists entirely of vector operations. The basic unit of vector partitioning is a basic vector composed of P elements, where P is the parallelism of the data path of the hardware acceleration device. A vector with M elements will be partitioned into M2 block vectors, and each block vector contains M1 basic vectors. The scheduling template of the basic solution update operator is controlled by a single for loop to schedule the block vectors. In the for loop, the block vectors required for each vector operation are read sequentially from off-chip memory. The vector operation is performed, and the final result block vector is written back to off-chip storage. In the dual solution update operator, the basic unit of matrix segmentation is a basic matrix composed of PxP elements, where P is the parallelism of the data path of the hardware acceleration device. An N-row M-column matrix will be segmented into N2×M2 block matrices, each block matrix containing N1×M1 basic matrices. The hardware acceleration device is configured to store sparse matrix blocks of M2×N1×M1 basic matrices. That is, in the first for loop, the data block reading, calculation and writing back of the SpMV and vector operation are triggered.

[0030] Furthermore, for the basic solution update operator, the calculation of its block size includes: assuming that the local storage capacity of the hardware acceleration device is HW_MEM, directly calculating the capacity size of the block vector according to the formula 2×(M1×3)<HW_MEM to obtain the value of M1; for the dual solution update operator, the calculation of its block size: directly calculating the value of N1 according to 2×(M2×N1×M1+3×N1)<HW_MEM, and setting the result block vector of CSC SpMV to be preferably the same size as the result block vector of CSR SpMV, that is, M1 = N1. For the sparse matrix K, M2×M1 represents the number of non-zero values in a row. Calculate the number of non-zero values in N1 rows of the matrix online. After obtaining these scheduling parameters, the CPU generates the configuration and instruction stream required by the hardware acceleration device online.

[0031] The design method of the hardware acceleration operator library for a PDLP linear programming algorithm of the present invention has the following advantages:

[0032] 1. Significantly reduce off-chip memory access volume

[0033] Through operator static storage planning, variables with non-overlapping life cycles are allocated to the same storage space, maximizing the utilization of limited on-chip storage resources, reducing frequent access to off-chip memory, and thus reducing memory access latency and energy consumption.

[0034] 2. Improve the utilization rate of hardware resources

[0035] Through operator scheduling template design, large-scale vectors / matrices are sliced into basic blocks suitable for hardware parallel processing, and combined with the Ping-Pong execution mode to achieve data reuse and pipeline execution, significantly improving the utilization rate of data paths and storage resources.

[0036] 3. Support flexible adaptation to problems of different scales

[0037] Through loop slicing and parameterized scheduling templates, the same set of hardware acceleration architectures can efficiently process linear programming problems of different scales, with good scalability and generality.

[0038] 4. Optimize the performance of sparse matrix operations

[0039] For the SpMV operation in the dual solution update operator, an online scheduling optimization mechanism is proposed, dynamically selecting the optimal scheduling parameters according to the actual structure of the sparse matrix, avoiding performance degradation caused by uneven sparsity, and improving the overall calculation efficiency.

[0040] 5. Achieve seamless conversion from algorithm to hardware

[0041] Provide a complete operator library code generation process, automatically convert high-level algorithm descriptions into low-level hardware instruction streams, reduce development complexity, shorten the development cycle, and improve system integration efficiency.

[0042] 6. Improve the overall system energy efficiency ratio

[0043] By reducing off-chip memory access, optimizing data locality, and increasing parallelism, the processing throughput and energy efficiency of the PDLP algorithm are significantly improved while ensuring computational accuracy. It is especially suitable for resource-constrained scenarios such as edge computing and embedded systems.

[0044] 7. Filling existing technological gaps

[0045] Existing PDLP acceleration solutions mostly focus on macroscopic operator fusion, lacking fine-grained optimization for hardware resource constraints. This invention, for the first time, systematically proposes a complete design method from storage planning to scheduling optimization to code generation, filling a technological gap in this field.

[0046] In summary, this invention achieves efficient mapping and execution of the PDLP algorithm on hardware accelerators through a multi-level and systematic design method. It has the advantages of high performance, high energy efficiency, and high flexibility, and is suitable for real-time solving of large-scale linear programming problems. It has important industrial application value and academic research significance. Attached Figure Description

[0047] Figure 1 A schematic diagram of the hardware acceleration device for the PDLP algorithm to which this invention is applicable and its two-operator fusion scheme;

[0048] Figure 2 A schematic diagram of the hardware acceleration operator library design scheme based on storage planning and scheduling optimization of this invention;

[0049] Figure 3 A schematic diagram illustrating the storage allocation example for the basic and dual solution update operators;

[0050] Figure 4 A schematic diagram illustrating the data segmentation and scheduling template of the basic and dual solution update operators. Detailed Implementation

[0051] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides a hardware acceleration operator library design method for the PDLP linear programming algorithm.

[0052] This invention provides a hardware-accelerated operator library design method for the PDLP linear programming algorithm. Its input is an operator fusion scheme for the PDLP algorithm, and its output is the code implementation of the fusion operator, such as... Figure 2 As shown, the specific design method is as follows:

[0053] Step 1: Static Storage Planning for Operators: By analyzing the lifetimes of variables in the operator computation graph, variables with non-overlapping lifetimes are allocated to the same storage space, thereby reducing the size of the storage space, increasing the block size, and reducing loop overhead. Its input is the operator computation graph, and the output is the serialized operator operation order and variable storage allocation. The basic principle of static storage planning for operators is similar to register allocation in traditional compilers, as follows:

[0054] Step 1.1: Analyze the lifetime of each variable in the computation graph and construct a Register Inference Graph (RIG) based on the lifetime. In the RIG, a node represents a variable, and the edges between nodes indicate that the lifetimes of two variables overlap, making it impossible to allocate the same storage space to them.

[0055] Step 1.2: The storage allocation problem of variables is transformed into a minimum coloring problem of RIG using RIG. That is, using the fewest possible colors to color nodes connected by edges, nodes with the same color can share the same storage space. The minimum number of colors corresponds to the minimum number of storage spaces. Although the minimum coloring problem is NP-hard, the PDLP algorithm has a fixed computation graph and a relatively small scale, so the minimum coloring problem can be solved by backtracking.

[0056] Step 2: Operator Scheduling Template Design: Hardware constraints are added to the operator operation process by using loop-based block segmentation, transforming the input from a single complete vector / matrix into a three-layer structure: complete vector / matrix -> block vector / matrix -> basic vector / matrix. The basic vector / matrix reflects the parallel processing capability of the hardware data path, while the block vector / matrix reflects hardware storage capacity constraints. Here, a Ping-Pong execution block approach is considered, where the variable storage requirement for the corresponding block must be less than the hardware storage capacity limit to support solving linear programming problems of different scales. Local storage data reuse can be further optimized by adjusting the loops within the same layer. The main parameters of the operator scheduling template include local loop order, block size, and Ping-Pong execution.

[0057] Step 3: Online Operator Scheduling Optimization: This step primarily targets dual solution update operators involving SpMV operations. Basic solution update operators involving pure vector operations have relatively simple scheduling and do not require online optimization. Considering the non-fixed and potentially changing sparse matrix of linear programming problems, a performance analysis model is constructed using an operator scheduling template. This model calculates the prediction performance online under various scheduling parameter configurations and selects the scheduling parameters with the optimal prediction performance. The inputs are the sparse matrix of the linear programming problem, the operator scheduling template, and dedicated hardware storage constraints; the output is the optimal scheduling parameters.

[0058] Step 4: Operator library code generation: Based on the operator scheduling template and optimal scheduling parameters, and in conjunction with the runtime of the PDLP algorithm hardware acceleration device, the CPU is responsible for converting the optimal operator scheduling into the configuration and instruction stream of the PDLP algorithm hardware acceleration device, and in conjunction with the corresponding driver functions, forming operator calls to the PDLP algorithm hardware acceleration device.

[0059] Reference Figure 1 This diagram illustrates the task division between the main processor (CPU) and the PDLP hardware acceleration device when executing the PDLP algorithm. First, the CPU reads and preprocesses the linear programming problem, obtaining the corresponding vectors, sparse matrix K, and initial parameters such as ω and η. Second, the PDLP hardware acceleration device performs core calculations based on the preprocessed data, including updating the basic solution x, the dual solution y, and the step size η. Finally, the CPU determines whether the step size η meets the performance requirements. If not, it continues the current iteration, updating the basic solution x, the dual solution y, and the step size η. If they meet the requirements, it checks if the convergence condition is satisfied. If not, it starts the next iteration. If they do meet the requirements, it outputs the final result, including the basic solution x and the dual solution y. The PDLP hardware acceleration device employs a two-operator fusion scheme, including a basic solution update operator (① in the diagram) and a dual solution update operator (② in the diagram).

[0060] Reference Figure 3 This shows the storage allocation for the basic and dual update operators. The basic update operator consists of a sequence of vector operations: Axpy→Axpy→Cmp→Cmp→Axpy→Nrm. Each operation depends on the input of the previous operation, and the order of operations is fixed. Their data dependencies are as follows: Figure 3 As shown in a), blue nodes represent data obtained through computation, while yellow nodes represent data obtained by accessing off-chip storage. Based on the data dependency graph of the basic solution update operator, the lifetime of each variable can be determined, and the RIG of the basic solution update operator can be generated, as shown below. Figure 3 As shown in b), three different colors can be observed, therefore the on-chip storage needs to be divided into three minimum regions. Based on the RIG coloring, the allocation of base solution update variables and the order of operations can be determined, as shown in 3c). Figure 3 In section d), a data dependency graph of the dual solution update operator is shown. Blue nodes represent computed data, and yellow nodes represent data read from off-chip memory. It can be observed that multiple operations depend on the same operation; for example, res0 and res1 depend on the computation of Δy, and tmp0 and ΔKx depend on Kx. t+1 The calculation of K T y t+1 Δy depends on y t+1The computation of this process leads to multiple possible computation orders for the dual solution update operator, thus affecting the lifetime of input and output variables. A RIG of the dual solution update operator is generated based on the data dependency graph and colored using a backtracking method, as shown in the following example. Figure 3 As shown in e), the variables K and ΔKx have many connections with other nodes, which conforms to... Figure 3 The long lifespan characteristic embodied in d) is shown in the coloring results. The coloring results indicate that the dual solution update operator's RIG requires at least four colors, meaning that the dual solution update operator needs at least four storage spaces to store the variables. The storage allocation results are as follows: Figure 3 As shown in f).

[0061] Reference Figure 4 This shows the data partitioning and scheduling templates for the basic and dual solution update operators. The basic solution update operator consists entirely of vector operations, and its data partitioning and scheduling template are relatively simple. Vector partitioning is as follows: Figure 4 As shown in a), the basic unit of vector partitioning is a basic vector consisting of P elements, where P is the parallelism of the data path in the hardware acceleration device. A vector with M elements will be partitioned into M2 block vectors, each block vector containing M1 basic vectors. The scheduling template for the basic solution update operator is as follows: Figure 4 As shown in b), the scheduling of block vectors is controlled by a single for loop. Within the for loop, the block vectors required for each vector operation are sequentially read from off-chip memory, the vector operations are performed, and the final result block vector is written back to off-chip memory. The dual solution update operator, due to the inclusion of SpMV operations, requires matrix partitioning, as shown in [the diagram]. Figure 4 As shown in c) of the diagram. The basic unit of matrix partitioning is a basic matrix consisting of P x P elements, where P is the parallelism of the data path in the hardware acceleration device. An N x M matrix will be partitioned into N² × M² block matrices, each block matrix containing N¹ × M¹ basic matrices. The scheduling template for the dual solution update operator is as follows: Figure 4 As shown in d), the CSR and CSC SpMV operations consist of four nested for loops. Since the vector operations after CSR SpMV depend on the calculation result of CSR SpMV, the i2 loop is outside the j2 loop, and the vector operations can begin after the j2 loop completes. The order of the i1 and j1 loops is uncertain. To achieve the reuse of matrix K for CSR SpMV and CSR SpMV operations, the hardware acceleration device needs to be able to store sparse matrix blocks of M2×N1×M1 basic matrices. That is, within the first for loop, the data block that triggers SpMV and vector operations is read, calculated, and written back.

[0062] For the basic solution update operator, the calculation of its block size is relatively simple, from Figure 3c) It can be obtained that considering the Ping-Pong operation form, six storage spaces are required to store the block vectors. Assuming the local storage capacity of the hardware acceleration device is HW_MEM, according to the formula 2×(M1×3) < HW_MEM, the capacity size of the block vector can be directly calculated to obtain the value of M1. For the dual solution update operator, the calculation of its chunk size is relatively complex. From Figure 3 f) It can be obtained that considering the Ping-Pong operation form, 2×(M2×N1×M1 + 3×N1) < HW_MEM, and the value of N1 can be directly calculated. To make full use of the local storage, the result block vector of CSC SpMV is preferably the same size as the result block vector of CSR SpMV, that is, M1 = N1. For the sparse matrix K, M2×M1 represents the number of non-zero values in a row. Due to the difference in sparse distribution, the number of non-zero values in each row is not exactly the same. Therefore, it is necessary to calculate the number of non-zero values in N1 rows of the matrix online. After obtaining these scheduling parameters, the CPU can generate the configuration and instruction stream required by the hardware acceleration device online.

[0063] It can be understood that the present invention is described through some embodiments. As is known to those skilled in the art, without departing from the spirit and scope of the present invention, various changes or equivalent replacements can be made to these features and embodiments. In addition, under the teaching of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the scope protected by the present invention.

Claims

1. A method for designing a hardware-accelerated operator library for the PDLP linear programming algorithm, characterized in that, The method takes the operator fusion scheme of the PDLP algorithm as input and outputs the code implementation of the fusion operator, including the following steps: Step 1: Static storage planning for operators. By analyzing the lifetime of each variable in the operator computation graph, variables with non-overlapping lifetimes are allocated to the same storage space, generating a serialized operator operation order and variable storage allocation scheme. Step 2: Operator scheduling template design. Hardware constraints are introduced into the operator operation process through cyclic block cutting to form a multi-layer data structure. A scheduling template including local loop order, block size and Ping-Pong execution mode is designed. Step 3: Online operator scheduling optimization. For operators containing SpMV operations, a performance analysis model is constructed, and the optimal scheduling parameters are selected online. Step 4: Operator library code generation. Based on the scheduling template and optimal parameters, the configuration and instruction flow of the hardware acceleration device are generated to form a callable operator library.

2. The hardware acceleration operator library design method for the PDLP linear programming algorithm according to claim 1, characterized in that, The static storage planning of the operator in step 1 includes the following steps: Step 1.1: Analyze and calculate the lifetime of each variable in the graph, and construct a register interferogram (RIG) based on the lifetime; Step 1.2: Transform the variable storage allocation problem into a minimum coloring problem using RIG, that is, use the fewest colors to color nodes connected by edges, so that nodes with the same color can share the same storage space. The minimum number of colors corresponds to the minimum number of storage spaces.

3. The hardware acceleration operator library design method for the PDLP linear programming algorithm according to claim 1, characterized in that, In step 2: The multi-layered data structure includes complete vectors / matrices, block vectors / matrices, and basic vectors / matrices; The size of the basic vector / matrix is ​​determined by the parallelism of the hardware data path; The size of the block vector / matrix is ​​limited by the hardware storage capacity and supports Ping-Pong execution mode.

4. The hardware acceleration operator library design method for the PDLP linear programming algorithm according to claim 1, characterized in that, In step 3: the performance analysis model takes as input a sparse matrix of a linear programming problem, an operator scheduling template, and dedicated hardware storage constraints, and outputs the optimal scheduling parameters.

5. The hardware acceleration operator library design method for the PDLP linear programming algorithm according to claim 1, characterized in that, In step 4, the CPU is responsible for converting the optimal operator scheduling into the configuration and instruction stream of the PDLP algorithm hardware acceleration device, and in conjunction with the corresponding driver function, forming an operator call to the PDLP algorithm hardware acceleration device.

6. The hardware acceleration operator library design method for the PDLP linear programming algorithm according to claim 1, characterized in that, The task division between the main processor (CPU) and the PDLP hardware acceleration device when executing the PDLP algorithm is as follows: First, the main processor (CPU) reads and preprocesses the linear programming problem to obtain the corresponding vectors, sparse matrix K, and initial parameters. Second, the PDLP hardware acceleration device performs core calculations for adaptive step-size iteration based on the preprocessed data, including updating the basic solution x, the dual solution y, and the step size η. Finally, the main processor (CPU) determines whether the step size η meets the performance requirements. If not, it continues the current iteration to update the basic solution x, the dual solution y, and the step size η. If the requirements are met, it checks whether the convergence condition is satisfied. If not, it starts the next iteration. If the conditions are met, it outputs the final result including the basic solution x and the dual solution y. The PDLP hardware acceleration device adopts a two-operator fusion scheme, including a basic solution update operator and a dual solution update operator.

7. The hardware acceleration operator library design method for the PDLP linear programming algorithm according to claim 1, characterized in that, Storage allocation for the basic solution update operator and the dual solution update operator: The basic solution update operator consists of a sequence of vector operations Axpy→Axpy→Cmp→Cmp→Axpy→Nrm. Each operation depends on the input of the previous operation, and the order of operations is fixed. Based on the data dependence graph of the basic solution update operator, the lifetime of each variable can be determined, and the RIG of the basic solution update operator can be generated. According to the coloring situation of the RIG, the allocation and operation order of the basic solution update variables can be determined. The RIG of the dual solution update operator is generated based on the data dependence graph, and backtracking is used for coloring.

8. The hardware acceleration operator library design method for the PDLP linear programming algorithm according to claim 1, characterized in that, Data chunking and scheduling templates for the basic solution update operator and the dual solution update operator: The basic solution update operator consists entirely of vector operations. The basic unit of vector chunking is a basic vector composed of P elements, where P is the parallelism of the data path of the hardware acceleration device. A vector with M elements will be sliced into M2 block vectors, and each block vector contains M1 basic vectors. The scheduling template of the basic solution update operator is controlled by a single for loop to schedule the block vectors. In the for loop, the block vectors required for each vector operation are sequentially read from off-chip storage, the vector operations are calculated, and the final result block vectors are written back to off-chip storage. In the dual solution update operator, the basic unit of matrix chunking is a basic matrix composed of PxP elements, where P is the parallelism of the data path of the hardware acceleration device. An N-row M-column matrix will be sliced into N2×M2 block matrices, and each block matrix contains N1×M1 basic matrices. It is set that the hardware acceleration device can store M2×N1×M1 basic matrix blocks of the sparse matrix. That is, within the first for loop, the data block reading, calculation, and writing back of SpMV and vector operations are triggered.

9. The hardware acceleration operator library design method for the PDLP linear programming algorithm according to claim 8, characterized in that, For the basic solution update operator, the calculation of its chunk size includes: assuming that the local storage capacity of the hardware acceleration device is HW_MEM, according to the formula 2×(M1×3)<HW_MEM, the capacity size of the block vector is directly calculated to obtain the value of M1. For the dual solution update operator, the calculation of its chunk size: according to 2×(M2×N1×M1+3×N1)<HW_MEM, the value of N1 is directly calculated. It is set that the result block vector of CSC SpMV is preferably the same size as the result block vector of CSR SpMV, that is, M1 = N1. For the sparse matrix K, M2×M1 represents the number of non-zero values in a row. The number of non-zero values in N1 rows of the matrix is calculated online. After obtaining these scheduling parameters, the CPU generates the configuration and instruction stream required by the hardware acceleration device online.

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