Memory allocation method and device, electronic equipment, storage medium and chip

Abstract

This application provides a memory allocation method, apparatus, electronic device, storage medium, and chip. The method includes: extracting tensor data for each tensor in a kernel program; constructing a control flow graph based on the kernel program; allocating first address information in static random access memory (SRAM) for each tensor data; determining the active path for each tensor based on the control flow graph, wherein the active path includes a first node involving the tensor; constructing an interference graph for the tensors based on the active paths, wherein each second node in the interference graph represents a different tensor, and the edges between the second nodes represent interference relationships between the tensors; adjusting the first address information of each tensor data based on the interference graph to obtain second address information for each tensor data, wherein, in different steps of the kernel program, if there is no interference relationship between two tensors, the storage areas of the two tensor data are reused. This application can improve memory reuse efficiency.

Description

Technical Field

[0001] This application relates to computer technology, and more particularly to a memory allocation method, apparatus, electronic device, storage medium, and chip. Background Technology

[0002] Artificial intelligence (AI) chips, also known as AI accelerators or computing cards, are modules specifically designed to handle the large amounts of computational tasks in AI applications (other non-computational tasks are still handled by the central processing unit (CPU)). They are hardware devices that emerged during the rapid development of AI applications to process computational tasks, and any chip designed for AI applications is called an AI chip. In related technologies, AI chips, in their hardware design, only support kernel operations that do not contain control flow in their computational logic. Kernel operations refer to computational operations that need to be accelerated and are sent to the hardware accelerator, such as matrix multiplication and function activation. This often results in the static random access memory (SRAM) resources within the kernel being difficult to reuse effectively, leading to a waste of SRAM storage space. Summary of the Invention

[0003] This application provides a memory allocation method, apparatus, electronic device, computer-readable storage medium, and chip that can improve memory reuse rate.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] This application provides a memory allocation method, the method comprising:

[0006] Extract tensor data for each tensor in the kernel program, wherein the kernel program is stored in static random access memory;

[0007] A control flow graph is constructed based on the kernel program, wherein any first node in the control flow graph represents a step in the kernel program, and a path formed by multiple first nodes represents the execution order of the steps;

[0008] Assign a first address in the static random access memory to each of the tensor data;

[0009] An active path for each tensor is determined based on the control flow graph, wherein the active path includes a first node involving the tensor;

[0010] An interferometric graph of the tensor is constructed based on the active path, wherein each second node in the interferometric graph represents a different tensor, and the edges between the second nodes represent the interference relationship between the tensors;

[0011] The first address information of each tensor data is adjusted according to the interferogram to obtain the second address information of each tensor data. In different steps of the kernel program, if there is no interference relationship between two tensors, the second address information of the two tensor data is reused.

[0012] This application provides a memory allocation device, including:

[0013] A data extraction module is used to extract tensor data for each tensor in the kernel program, wherein the kernel program is stored in static random access memory;

[0014] The graph construction module is used to construct a control flow graph based on the kernel program, wherein any first node in the control flow graph represents a step in the kernel program, and a path formed by multiple first nodes represents the execution order of the steps;

[0015] The memory allocation module is used to allocate first address information in the static random access memory to each of the tensor data.

[0016] The graph construction module is further configured to determine an active path for each tensor based on the control flow graph, wherein the active path includes a first node involving the tensor;

[0017] The graph construction module is further configured to construct an interference graph of the tensor based on the active path, wherein each second node in the interference graph represents a different tensor, and the edges between the second nodes represent the interference relationship between the tensors;

[0018] The memory allocation module is further configured to adjust the first address information of each tensor data according to the interference diagram to obtain the second address information of each tensor data, wherein, in different steps of the kernel program, if there is no interference relationship between two tensors, the second address information of the two tensor data is reused.

[0019] This application provides an electronic device, the electronic device comprising:

[0020] Memory is used to store executable instructions or computer programs.

[0021] The processor, when executing computer-executable instructions or computer programs stored in the memory, implements the memory allocation method provided in the embodiments of this application.

[0022] This application provides a computer-readable storage medium storing computer-executable instructions or computer programs, which, when executed by a processor, implement the memory allocation method provided in this application.

[0023] This application provides a computer program product, including a computer program or computer executable instructions, which, when executed by a processor, implements the memory allocation method provided in this application.

[0024] This application provides a chip for implementing the memory allocation method provided in this application.

[0025] The embodiments of this application have the following beneficial effects:

[0026] A control flow graph is constructed based on the kernel program, and the active paths of tensor data for each tensor in the kernel program are determined based on the control flow graph. An interference graph of tensor data is constructed based on the overlap relationship between active paths. The interference relationship between tensors is determined by the edges between nodes in the interference graph, and the first address information of each tensor data is adjusted according to the interference relationship to obtain the second address information of each tensor data. In different steps of the kernel program, if there is no interference relationship between two tensors, the storage areas of the two tensor data are reused. Adjusting the first address information of each tensor data according to the interference relationship avoids address conflicts of tensor data in the same step and reuses storage areas in different steps of the kernel program, thereby improving memory reuse rate. Attached Figure Description

[0027] Figure 1 This is a schematic diagram illustrating the application mode of the memory allocation method provided in the embodiments of this application;

[0028] Figure 2 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application;

[0029] Figure 3 This is a first flowchart illustrating the memory allocation method provided in this application embodiment;

[0030] Figure 4 This is a second flowchart illustrating the memory allocation method provided in the embodiments of this application;

[0031] Figure 5 This is a third flowchart illustrating the memory allocation method provided in the embodiments of this application;

[0032] Figure 6 This is a control flow graph of the memory allocation method provided in the embodiments of this application;

[0033] Figure 7 This is an interference diagram of the memory allocation method provided in the embodiments of this application.

[0034] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0037] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0038] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0040] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0041] 1) Triton: An open-source programming language and compiler designed to simplify the writing of high-performance graphics processing unit (GPU) cores. Triton provides Python-like syntax and reduces the complexity of GPU programming through high-level abstractions while maintaining high performance.

[0042] 2) Kernel: A Graphics Processing Unit (GPU) kernel refers to a function that runs on the GPU hardware accelerator and is executed in parallel by a large number of threads, used for high-throughput computation on large-scale data. This embodiment uses the XPU Kernel, a custom computing kernel typically used to accelerate high-performance computing tasks such as deep learning. The XPU Kernel is a function that executes on the accelerated hardware and is run by a large number of parallel threads (threads / warps / threadblocks). This function is scheduled by the Central Processing Unit (CPU) Host, and the XPU (Device) runs in parallel under an independent execution model.

[0043] 3) Static Random-Access Memory (SRAM): This is a type of random access memory. The term "static" means that the data stored in this type of memory is permanently retained as long as power is supplied. In contrast, the data stored in Dynamic Random-Access Memory (DRAM) needs to be updated periodically. However, when the power supply is interrupted, the data stored in SRAM is lost (this is called volatile memory), unlike Read-Only Memory (ROM) or flash memory, which retain data even after power is lost.

[0044] 4) Control Flow: Control flow refers to the execution order of instructions during program execution. It dynamically changes the code's execution path through structures such as conditional statements and loops. Control flow specifies the normal execution order of statements in a program, from the main function forwards or backwards, or from top to bottom, to perform a certain function.

[0045] 5) Register coloring: This is a method of register allocation that uses the coloring of an interferogram to allocate physical registers. Register coloring is used to map virtual registers (variables) in a program to a limited number of physical registers, resolving variable conflicts. Different colors represent different physical registers, and adjacent nodes have different colors.

[0046] Artificial intelligence (AI) chips, also known as AI accelerators or computing cards, are modules specifically designed to handle the large amounts of computational tasks in AI applications (other non-computational tasks are still handled by the central processing unit (CPU)). They are hardware devices born from the era of rapid development in AI applications, and any chip designed for AI applications is called an AI chip. In related technologies, AI chips, in their hardware design, only support kernel operations that do not contain control flow in their computational logic. Kernel operations refer to the computational operations that need to be accelerated and are sent to the hardware accelerator, such as matrix multiplication and function activation. Within the kernel, static random access memory (SRAM) resources are often difficult to reuse effectively, leading to wasted SRAM storage space.

[0047] This application provides a memory allocation method, a memory allocation device, an electronic device, a computer-readable storage medium, and a computer program product, which can improve memory reuse rate.

[0048] The following describes exemplary applications of the electronic devices provided in the embodiments of this application. These electronic devices can be implemented as terminal devices, such as laptops, tablets, desktop computers, set-top boxes, smart TVs, in-vehicle terminals, virtual reality (VR) devices, augmented reality (AR) devices, and other various types of terminals. They can also be implemented as servers. The following will describe exemplary applications when the electronic device is implemented as a terminal device or a server.

[0049] refer to Figure 1 , Figure 1 This is a schematic diagram illustrating the application mode of the memory allocation method provided in the embodiments of this application; for example, Figure 1 The system involves server 200, network 300, and terminal device 400. Terminal device 400 is connected to server 200 through network 300, which can be a wide area network (WAN), a local area network (LAN), or a combination of both.

[0050] For example, terminal device 400 has an application installed, and server 200 can be a server for the platform corresponding to the application. The application could be, for example, an AI-based question-and-answer application. Server 200 could be a server for an AI platform.

[0051] In some embodiments, an AI-based question-and-answer application runs on the terminal device 400. The user enters a question (text or image) in the application. The terminal device 400 sends a request carrying the device identifier and the question to the server 200 via the network 300. The server 200 calls the AI ​​application to obtain the answer according to the request and sends the answer to the terminal device 400. During the running of the application, the terminal device 400 calls the memory allocation method provided in the embodiments of this application to adjust the memory address of the tensors used by the application and improve memory reuse rate.

[0052] In some embodiments, the memory allocation method of this application can also be applied in the following application scenarios: taking the source code (or structured representation) of the kernel program written by Triton as input, adjusting the storage location of tensors in the kernel program based on the memory allocation method provided in this application, and reading the corresponding tensor from memory according to the adjusted storage location of the tensor during the operation of the kernel program, thereby improving the memory reuse rate.

[0053] See Figure 2 , Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may be... Figure 1 400 terminal devices Figure 2 The terminal device 400 shown includes at least one processor 410, a memory 450, at least one network interface 420, and a user interface 430. The various components in the terminal device 400 are coupled together via a bus system 440. It is understood that the bus system 440 is used to implement communication between these components. In addition to a data bus, the bus system 440 also includes a power bus, a control bus, and a status signal bus. However, for clarity, ... Figure 2 The general labeled all buses as Bus System 440.

[0054] Processor 410 can be an integrated circuit chip with signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., where the general-purpose processor can be a microprocessor or any conventional processor, etc.

[0055] User interface 430 includes one or more output devices 431 that enable the presentation of media content, including one or more speakers and / or one or more visual displays. User interface 430 also includes one or more input devices 432, including user interface components that facilitate user input, such as a keyboard, mouse, microphone, touch screen display, camera, other input buttons and controls.

[0056] The memory 450 may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state storage, hard disk drives, optical disk drives, etc. The memory 450 may optionally include one or more storage devices physically located away from the processor 410.

[0057] The memory 450 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), and the volatile memory may be random access memory (RAM). The memory 450 described in this application embodiment is intended to include any suitable type of memory.

[0058] In some embodiments, memory 450 is capable of storing data to support various operations, examples of which include programs, modules, and data structures or subsets or supersets thereof, as illustrated below.

[0059] Operating system 451 includes system programs for handling various basic system services and performing hardware-related tasks, such as the framework layer, core library layer, driver layer, etc., for implementing various basic business functions and handling hardware-based tasks;

[0060] The network communication module 452 is used to reach other electronic devices via one or more (wired or wireless) network interfaces 420, exemplary network interfaces 420 including: Bluetooth, WiFi, and Universal Serial Bus (USB), etc.

[0061] Presentation module 453 is configured to enable the presentation of information (e.g., a user interface for operating peripheral devices and displaying content and information) via one or more output devices 431 (e.g., a display screen, a speaker, etc.) associated with user interface 430.

[0062] The input processing module 454 is used to detect and translate one or more user inputs or interactions from one or more input devices 432.

[0063] In some embodiments, the memory allocation device provided in this application can be implemented in software. Figure 2 A memory allocation device 455 stored in memory 450 is shown. This device can be software in the form of programs and plug-ins, including the following software modules: a data extraction module 4551, a graph construction module 4552, and a memory allocation module 4553. These modules are logically linked and can therefore be arbitrarily combined or further split according to their implemented functions. Figure 2 For ease of explanation, all the above modules are shown at once, and the functions of each module will be explained below.

[0064] In other embodiments, the memory allocation device provided in this application can be implemented in hardware. As an example, the memory allocation device provided in this application can be a processor in the form of a hardware decoding processor, which is programmed to execute the memory allocation method provided in this application. For example, the processor in the form of a hardware decoding processor can be one or more application-specific integrated circuits (ASICs), digital signal processing devices (DSPs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), or other electronic components.

[0065] The memory allocation method provided in this application will be described in conjunction with exemplary applications and implementations of the terminal devices provided in the embodiments of this application.

[0066] The memory allocation method provided in the embodiments of this application will be described below. As mentioned above, the electronic device implementing the memory allocation method of the embodiments of this application can be a terminal device or a server, or a combination of both. Therefore, the executing entity of each step will not be described again below.

[0067] It should be noted that the storage processing examples below are illustrated using the source code of an application. Those skilled in the art can apply the memory allocation method provided in the embodiments of this application to the processing of other types of code data based on their understanding of the following text.

[0068] See Figure 3 , Figure 3 This is a flowchart illustrating the memory allocation method provided in the embodiments of this application, which will be combined with... Figure 3 The steps shown are explained. Figure 3 The entity responsible for executing the steps is Figure 1 400 terminal devices.

[0069] In step 301, tensor data for each tensor in the kernel program is extracted.

[0070] Here, the kernel program is stored in static random access memory.

[0071] For example, this embodiment uses a kernel program written in Triton as an example. The XPU Kernel refers to a function executed on accelerated hardware and run by a large number of parallel threads (threads / warps / threadblocks). Tensors are the core data structure in PyTorch used for storing and manipulating multidimensional data. Tensors are a generalized form of multidimensional arrays and can represent scalar (0-dimensional), vector (1-dimensional), matrix (2-dimensional), or higher-dimensional data. Tensor data includes the tensor's declaration, definition, and usage position. The declaration determines the tensor's name and basic attributes (type, dimensions, etc.). The definition (or initialization) is the statement position used to allocate memory space and assign initial values ​​to the declared tensor, giving it actual storage space and initial data. The usage position refers to the statement position where the tensor is read (as input for computation) or written (updated). Static random access memory (SRAM) is a type of random access memory. When the power supply stops, the data stored in SRAM will be lost.

[0072] For example, prior to step 301, a memory allocation instruction (alloc) determines a specified size of storage space for the kernel program in memory (static random access memory) and returns the address of that space for subsequent access to the kernel program.

[0073] In step 302, a control flow graph is constructed based on the kernel program.

[0074] Here, any first node in the control flow graph represents a step in the kernel program, and a path composed of multiple first nodes represents the execution order of the steps.

[0075] For example, a control flow graph is a structured representation of a computational task (such as a neural network model or a complex algorithm). A control flow graph contains nodes (representing operations, such as convolution or matrix multiplication) and edges (representing data dependencies, such as the input-output relationship of a tensor). It may also contain control flow logic such as branches and loops (e.g., conditional statements or dynamic loops in the model). For instance, if steps 1 to 3 are executed sequentially according to their step numbers, then the nodes of steps 1 to 3 are connected in series to form a path.

[0076] In some embodiments, step 302 can be implemented by: determining each step of the kernel program and constructing a first node for each step; determining the execution order between each first node according to the dominance relationship between each step; and concatenating the first nodes according to the execution order to obtain a control flow graph.

[0077] For example, each step of a kernel program performs a specific function. The source code can be broken down according to the functional semantics in the kernel program's source code to obtain each step. The boundaries between each step are clear, and the start and end of each step are clearly marked (such as function calls, code block boundaries, and keyword separations), with no ambiguous overlap. The input (dependent data) and output (results) of each step can be clearly defined, facilitating subsequent analysis (such as address conflicts and scheduling optimizations).

[0078] For example, domination in a directed graph means that if all paths from the entry node to the target node pass through node A, then node A is said to dominate the target node. Domination relationships can be used to identify paths that must be executed in a program. An active path of a tensor refers to the path formed by the nodes (steps) in the control flow graph that apply to that tensor. (See reference) Figure 6 , Figure 6 This is the control flow graph of the memory allocation method provided in the embodiments of this application; it is assumed that there are six steps in the control flow, each node in the control flow graph represents a step, and the direction of the edge between each node represents the dominance relationship between the steps. Figure 6 In the first part, node 1 points to nodes 6 and 2, which represent different branch steps indicated by the if-else clause. Node 2 points to node 3, node 3 points to node 4, and node 4 points to node 5. Node 6 also points to node 5.

[0079] In step 303, a first address information in static random access memory is assigned to each tensor data.

[0080] For example, the first address information is the initial address of the tensor data, which includes the starting address and the address offset. The starting address is the starting location of the tensor's occupied memory. The address offset (SRAM offset) is the offset of the data storage location relative to a certain base address. The first address information can be determined by using a greedy algorithm to allocate the address offset of the initial static random access memory for all tensors that need to be allocated.

[0081] In step 304, the active path for each tensor is determined based on the control flow graph.

[0082] Here, the active path includes the first node involving the tensor.

[0083] For example, "active" refers to a tensor's participation in computation within the corresponding step of the control flow, such as tensor involvement in operations, data transfer, or merging. An active path represents the buffer live range of a tensor within a step; an active path including the first node involving the tensor means that the active path consists of the first node of the step involving tensor involvement in operations, data transfer, or merging.

[0084] In some embodiments, step 304 can be implemented by performing the following processing for each tensor: determining the target steps involved in the tensor data of the tensor; and taking the path formed by the first node group of each target step as the active path of the tensor.

[0085] For example, assuming there exists a tensor A, continue based on Figure 6 Let's take a control flow graph as an example. Tensor A is applied in the following steps: Step 1 → Step 2 → Step 3 → Step 5; then the active path of tensor A is composed of the first nodes corresponding to steps 1, 2, 3, and 5 respectively. By combining the first nodes corresponding to steps 1, 2, 3, and 5 into a sequence according to the order of the steps, we can obtain the active path of tensor A.

[0086] In step 305, an interferogram of tensors is constructed based on the active paths.

[0087] Here, each second node in the interferogram represents a different tensor, and the edges between the second nodes represent the interference relationship between the tensors.

[0088] For example, an interference graph is an undirected graph where an edge represents an overlap in the active range of two nodes (tensor data) (i.e., an interference relationship). Conversely, if there is no edge between two nodes, then there is no relationship between the tensors corresponding to the two nodes.

[0089] In some embodiments, reference Figure 4 , Figure 4 This is a schematic diagram of the second process of the memory allocation method provided in the embodiments of this application. Step 305 can be achieved through... Figure 4 Steps 3051 to 3054 are implemented, and the details are explained below.

[0090] In step 3051, the second node corresponding to each tensor is constructed.

[0091] For example, each tensor is treated as a node. To illustrate this, the following example demonstrates the concept. Assume there are tensors A to D, and continue based on... Figure 6 Let's take a control flow graph as an example. Tensor A is applied in the following steps: Step 1 → Step 2 → Step 3 → Step 5; Tensor B is applied in the following steps: Step 1 → Step 2 → Step 4 → Step 5; Tensor C is applied in the following steps: Step 1 → Step 6; Tensor D is applied in the following steps: Step 1 → Step 2 → Step 5, and Step 1 → Step 6 → Step 5. Construct a node for each of tensors A through D.

[0092] In step 3052, each second node is traversed, and the following processing is performed on the traversed second node: the active path of the traversed second node is compared with the active paths of other second nodes to obtain the comparison result.

[0093] For example, if two tensors interfere with each other's states in the same step (such as computation, data transfer, or merging), then an interference edge exists. If both tensors are output in a certain step without interference, then no interference edge exists between the two tensors.

[0094] In step 3053, when the comparison result indicates that the two active paths at least partially overlap, the two second nodes are connected.

[0095] For example, continuing with the example above, suppose that tensor A (output of step 3) and tensor B (output of step 4) are merged in step 5, creating a dependency, and there is an edge between tensor A and tensor B.

[0096] Tensor A and tensor D share computational resources in step 5, thus creating a dependency. There is an edge between tensor A and tensor D.

[0097] Tensor D (applied in step 5) and tensor B (applied in step 4) are combined in step 5, creating a dependency. There is an edge between tensor D and tensor B.

[0098] Tensor D (applied in step 6) and Tensor C (applied in step 6) share storage resources in step 6, thus creating a dependency.

[0099] Tensor B and tensor C belong to different branches, have no common steps, and have no dependencies. Tensor A and tensor C belong to different branches, have no common steps, and have no dependencies.

[0100] refer to Figure 7 , Figure 7 This is an interference graph of the memory allocation method provided in this application embodiment. Each node in the interference graph represents a tensor, for example: tensor A to tensor D. There is an interference relationship between node A and nodes B and D, and there is an interference relationship between node D and nodes B and C. There is no interference relationship between node B and node C, and there is no interference relationship between node A and node C.

[0101] In step 3054, in response to the completion of comparisons between all second nodes, an interferogram is obtained.

[0102] For example, after all comparisons between second nodes are completed, a comparison is performed between any two second nodes. That is, when traversing to node A, the active paths of node A and node B are compared once, so when traversing to node B, there is no need to compare node A and node B again.

[0103] In this embodiment, an interference graph of tensors is constructed by the overlapping relationship between active paths of tensors. The edges in the interference graph can intuitively represent the interference relationship of tensors, which can improve the efficiency of constructing the interference graph of tensors. Then, the storage area of ​​tensor data is adjusted based on the interference relationship of tensors to avoid storage area conflicts of tensors and improve memory reuse rate.

[0104] Continue to refer to Figure 3 In step 306, the first address information of each tensor data is adjusted according to the interferogram to obtain the second address information of each tensor data.

[0105] Here, in different steps of the kernel program, if there is no interference between two tensors, the storage areas of the two tensor data are reused.

[0106] For example, the second address information is the modified first address information. The second address information includes an address offset and a starting address. The address offset in the second address information is the same as the address offset in the first address information.

[0107] In some embodiments, step 306 can be implemented by traversing each second node in the interferogram and performing the following processing on the traversed second nodes:

[0108] Based on the interferogram, a first target tensor data that has an interference relationship with the tensor data of the second node and a second target tensor data that does not have an interference relationship with the tensor data of the second node are identified. When the first address information of the tensor data of the second node overlaps at least partially with the address information of the first target tensor, the first address information is adjusted according to the address information of the second target tensor to obtain the second address information.

[0109] In some embodiments, the first address information includes a first starting address and a first address offset; the second address information includes a second starting address and a second address offset; the second address information is obtained by adjusting the first address information according to the address information of the second target tensor, which can be achieved by: using the storage area indicated by the third starting address and the second address offset of the second target tensor as the first free storage area; using the storage area that does not store any tensor data as the second free storage area. The second starting address in the second address information is determined based on the address ranges corresponding to the first and second free storage areas.

[0110] In some embodiments, when the first address offset is less than or equal to the second address offset, a first difference between the second address offset and the first address offset is determined, and the first starting address is modified to the second starting address. The second starting address is located in the address range between the third starting address and the target address, and the target address is the sum of the third starting address and the first difference.

[0111] In some embodiments, when the first address offset is greater than the second address offset and the first free storage area and the second free storage area are not contiguous, the first starting address is modified to the second starting address, wherein the second starting address is located in the second free storage area.

[0112] In some embodiments, when the first address offset is greater than the second address offset and the first free storage area is contiguous with the second free storage area, the first starting address is modified to the second starting address, wherein the second starting address is located in the first free storage area.

[0113] In this embodiment, a control flow graph is constructed based on the kernel program, and the active paths of tensor data for each tensor in the kernel program are determined based on the control flow graph. An interference graph of tensor data is constructed based on the overlap relationship between active paths. The interference relationship between tensors is determined by the edges between nodes in the interference graph, and the first address information of each tensor data is adjusted according to the interference relationship to obtain the second address information of each tensor data. In different steps of the kernel program, if there is no interference relationship between two tensors, the storage areas of the two tensor data are reused. Adjusting the first address information of each tensor data according to the interference relationship avoids address conflicts of tensor data in the same step and reuses storage areas in different steps of the kernel program, thereby improving memory reuse rate.

[0114] The following will describe an exemplary application of the memory allocation method of this application in a real-world application scenario.

[0115] In related technologies, most AI chips only support kernel operations that do not contain control flow in their computational logic. Kernel operations refer to the management, configuration, compilation, and optimization of the operating system kernel, and the computational operations (such as matrix multiplication and function activation) that need acceleration, which are then distributed to hardware accelerators. This results in the difficulty of effectively reusing static random access memory resources in kernels with complex control flow (such as conditional if-else statements and loop control). Related technologies use graph compilers to segment the original computation graph (e.g., tensor graph forward analysis) to convert complex control flow into multiple simple, control-flow-free subgraphs, which are then distributed separately. For kernels with simple control flow, a point-to-point (ad-hoc) approach is used for case-by-case optimal allocation, but a unified system solution is lacking. For very complex content, such as kernels with multi-level nested loops, reuse is generally not considered. However, control flow splitting increases scheduling and data movement overhead, affecting overall performance. The lifecycle of data is the entire time period from when data is allocated and used during the computation process to when it is finally released. Static random access memory allocation strategies do not fully explore the reuse potential between data with non-overlapping lifecycles, resulting in waste of static random access memory.

[0116] This application aims to address the problem of difficulty in reusing static random access memory (SRAM) in complex control flow kernels in related technologies. It proposes a memory allocation method capable of handling multiplexing allocation of SRAM with control flow, thereby maximizing the utilization of SRAM space. The memory allocation method provided in this application will be explained below with reference to the accompanying drawings. Figure 5 , Figure 5 This is a schematic diagram of the third process of the memory allocation method provided in the embodiments of this application. (The diagram will be combined with...) Figure 5 The steps shown are explained. Figure 5 This is a schematic diagram of the third process of the memory allocation method provided in the embodiments of this application. Figure 5 The entity responsible for executing the steps is Figure 1 400 terminal devices.

[0117] In step 501, the alias cache indicated by the memory allocation instruction is analyzed.

[0118] For example, the memory allocation instruction (alloc) is used to request a block of memory of a specified size for data (such as variables, objects, arrays, etc.) and returns the address of that space (for subsequent access). An alias buffer is used to represent memory mapping relationships, referring to the phenomenon where multiple different buffers are mapped to the same underlying memory region. Analyzing the alias buffer indicated by the memory allocation instruction is equivalent to analyzing the situation where multiple different identifiers (such as variable names, pointers, view objects, etc.) point to the same underlying buffer memory space.

[0119] In this embodiment, the source code (or structured representation) of the kernel program written in Triton is used as input to extract the declaration, definition, and usage positions of intermediate tensors. Tensors are a core data structure in PyTorch used for storing and manipulating multidimensional data. Tensors are a generalized form of multidimensional arrays and can represent scalar (0-dimensional), vector (1-dimensional), matrix (2-dimensional), or higher-dimensional data. Declaration is used to determine the name and basic attributes (type, dimension, etc.) of the tensor. Definition / Initialization is the statement position used to allocate memory space and assign initial values ​​to the declared tensor, giving it actual storage space and initial data. Usage position refers to the statement position where the tensor is read (as input for computation) or written (updated).

[0120] In step 502, the active range of each tensor with respect to the buffer is calculated.

[0121] For example, the buffer live range represents the steps a tensor is active in the control flow. "Active" means that the tensor participates in computation in the corresponding step of the control flow, such as participating in operations, data transfer, or merging. The live range of a tensor relative to the buffer can be determined by constructing a control flow graph, and each tensor's live range can be represented as an active path in the control flow graph. Multiple tensor live paths are combined into a set of active paths.

[0122] For example, a computation graph (the control flow graph mentioned above) is a structured representation of a computational task (such as a neural network model or a complex algorithm). A computation graph contains nodes (representing operations, such as convolution or matrix multiplication) and edges (representing data dependencies, such as the input-output relationship of tensors), and may also contain control flow logic such as branches and loops (such as conditional statements or dynamic loops in a model). Subgraphs without control flow do not contain control flow logic such as branches (if-else) or loops (for / while), and consist only of computation nodes with pure data dependencies. Computation graphs with control flow, however, have complex control processes. A control flow graph is constructed from the kernel program's source code, and the set of active paths for all tensors is derived based on dominance analysis. Steps in the control flow graph are represented as nodes, and the connections between nodes represent the dominance relationships between steps. Dominance analysis is a core concept in compiler optimization, used to determine the dominance relationships between nodes in a program (control flow graph), thereby guiding code optimization. Dominance in a directed graph means that if all paths from the entry node to the target node must pass through node A, then node A is said to dominate the target node. Domination relationships can be used to identify the paths that must be executed in a program. The active path of a tensor refers to the path formed by the nodes (steps) that apply to the tensor in the control flow graph.

[0123] For ease of explanation, the following examples are provided for reference. Figure 6 , Figure 6 This is the control flow graph of the memory allocation method provided in the embodiments of this application; it is assumed that there are six steps in the control flow, each node in the control flow graph represents a step, and the direction of the edge between each node represents the dominance relationship between the steps. Figure 6 In the first part, node 1 points to nodes 6 and 2, which represent different branch steps indicated by the if-else clause. Node 2 points to node 3, node 3 points to node 4, and node 4 points to node 5. Node 6 also points to node 5.

[0124] In step 503, the initial address offset of the static random access memory is allocated using a greedy algorithm.

[0125] For example, the SRAM offset is the offset of the data storage location relative to a base address. A greedy algorithm is used to allocate the initial SRAM offset for all tensors that need allocation. For all tensors, a greedy initial allocation is performed, based on a heuristic strategy to maximize SRAM reuse. After allocation, each tensor will have a corresponding starting address (the starting position of the tensor's memory usage) and memory usage (calculated based on the tensor's dimensions and data type, in bytes). Greedy algorithms include Greedy Coloring and Heuristic Priority Coloring. Greedy algorithms are used to allocate initial storage addresses for tensors. Initial storage addresses may overlap, which will be adjusted in subsequent steps to ensure that tensors' storage addresses do not overlap within the same time period, while reusing the same storage address to store different tensors at different times, thus saving storage space.

[0126] In step 504, an interference map is constructed and the buffer area is colored.

[0127] For example, an interference graph is an undirected graph where nodes represent tensor data that needs to be buffered, and edges represent overlapping active regions (i.e., interference) between two nodes (data points). Buffer coloring is used to map virtual registers (variables) in a program to a limited number of physical registers, resolving variable conflicts. Different colors represent different physical registers, and adjacent nodes have different colors.

[0128] For example, an interferometric graph is constructed for all tensors. An edge represents an overlap in the active range of two nodes (tensor data) (i.e., an interference relationship). If the active paths of two tensors intersect, a conflict is considered to exist. If there is an edge between the corresponding nodes of two tensors in the interferometric graph, it indicates that the active ranges of the paths of the two tensors in the control flow graph overlap. Assuming there is a path from tensor A to tensor D, continue based on... Figure 6 Let's take a control flow graph as an example. Tensor A is applied in the following steps: Step 1 → Step 2 → Step 3 → Step 5; Tensor B is applied in the following steps: Step 1 → Step 2 → Step 4 → Step 5; Tensor C is applied in the following steps: Step 1 → Step 6; Tensor D is applied in the following steps: Step 1 → Step 2 → Step 5, and Step 1 → Step 6 → Step 5. If two tensors interfere with each other's states in the same step (such as computation, data transfer, or merging), then an interference edge exists. If both tensors output in a certain step without interference, then there is no interference edge between the two tensors.

[0129] Suppose that tensor A (output of step 3) and tensor B (output of step 4) are merged in step 5, creating a dependency, and there is an edge between tensor A and tensor B.

[0130] Tensor A and tensor D share computational resources in step 5, thus creating a dependency. There is an edge between tensor A and tensor D.

[0131] Tensor D (applied in step 5) and tensor B (applied in step 4) are combined in step 5, creating a dependency. There is an edge between tensor D and tensor B.

[0132] Tensor D (applied in step 6) and Tensor C (applied in step 6) share storage resources in step 6, thus creating a dependency.

[0133] Tensor B and tensor C belong to different branches, have no common steps, and have no dependencies. Tensor A and tensor C belong to different branches, have no common steps, and have no dependencies.

[0134] For ease of explanation, the following examples are provided for reference. Figure 7 , Figure 7 This is an interference graph of the memory allocation method provided in this application embodiment. Each node in the interference graph represents a tensor, for example: tensor A to tensor D. There is an interference relationship between node A and nodes B and D, and there is an interference relationship between node D and nodes B and C. There is no interference relationship between node B and node C, and there is no interference relationship between node A and node C.

[0135] For example, if the lifetimes of tensors do not overlap, several tensors can be allocated to the same static random access memory (SRAM) block. If the lifetimes of two data segments do not overlap (i.e., one data segment is no longer used before the other begins to be allocated and used), they can logically share the same storage space because they will not be used simultaneously, and there is no need to reserve separate storage space for them. Greedy coloring and heuristic priority coloring are used to color nodes in the graph with the fewest colors possible, and adjacent nodes have different colors. Each color corresponds to a SRAM interval (different SRAM intervals have different colors), and tensors with conflicting storage locations are resolved using unallocated SRAM. The SRAM layout can be defined as a linear address model, and offset calculations ensure that different colored blocks do not overlap in the address space. For cases with variable sizes or dynamic path control at runtime, conservative analysis or a dynamic adjustment-supporting SRAM scheduling model is introduced to fine-tune the SRAM layout at runtime.

[0136] If there is a conflict in the storage address of a tensor, step 505 is executed to allocate new space for the conflicting tensor data. After step 505, step 504 is executed until there is no conflict between the storage addresses of the tensors, and the memory allocation ends after step 504.

[0137] For example, conflicts between storage addresses are also known as conflicts between living ranges or address offsets. After step 504, existing storage addresses are reallocated by coloring. If overlapping storage addresses still exist in the result of the reallocation, step 504 is executed again until there are no conflicts between the storage addresses of tensors in the same time period, at which point the memory allocation ends.

[0138] For example, for the final storage address of the adjusted tensor, the starting address and size of its static random access memory (SRAM) are recorded for each tensor, and read / write scheduling instructions are inserted into the intermediate representation (IR). The intermediate representation is a structured representation generated by the compiler during source code processing, situated between the source code and the target machine code. It is independent of both the specific source code syntax (e.g., Python, C++) and the target hardware architecture (e.g., graphics processing unit, central processing unit), serving as an intermediate language for the compiler's analysis, optimization, and code generation. In tensor computation (e.g., the Triton kernel, deep learning frameworks), the intermediate representation typically exists in the form of instruction sequences, data flow graphs, or structured syntax trees, used to describe the logic of tensor operations, memory access, and control flow. For example, the intermediate representation of the Triton compiler contains instructions for loading data, storing data, matrix multiplication (dot), and metadata such as the tensor's memory address and size. After compilation, target code with precise SRAM allocation information is generated. During execution, the target code reads the corresponding tensor from memory based on the allocation information it carries.

[0139] The memory allocation method provided in this application is applicable to static random access memory (SRAM) graph allocation methods with complex control flows and does not rely on subgraph partitioning. It can effectively improve SRAM reuse rate, enhance performance, and reduce access to slower off-chip memory, such as Double Data Rate (DDR) SDRAM. It offers high compile-time SRAM allocation efficiency and good scalability and versatility. Heuristic algorithms are used to improve SRAM utilization for specific hardware.

[0140] The following description continues to illustrate the exemplary structure of the memory allocation device 455 provided in the embodiments of this application as a software module. In some embodiments, such as... Figure 2 As shown, the software modules stored in the memory allocation device 455 of the memory 450 may include:

[0141] The data extraction module 4551 is used to extract tensor data for each tensor in the kernel program, wherein the kernel program is stored in static random access memory; the graph construction module 4552 is used to construct a control flow graph based on the kernel program, wherein any first node in the control flow graph represents a step in the kernel program, and a path formed by multiple first nodes represents the execution order of the steps; the memory allocation module 4553 is used to allocate first address information in the static random access memory to each tensor data; the graph construction module 4552 is also used to determine the liveness of each tensor based on the control flow graph. The active path includes a first node involving the tensor; the graph construction module 4552 is further configured to construct an interference graph of the tensor based on the active path, wherein each second node in the interference graph represents a different tensor, and the edges between the second nodes represent interference relationships between the tensors; the memory allocation module 4553 is further configured to adjust the first address information of each tensor data according to the interference graph to obtain the second address information of each tensor data, wherein, in different steps of the kernel program, if there is no interference relationship between two tensors, the second address information of the two tensor data is reused.

[0142] In some embodiments, the graph construction module 4552 is configured to determine each step of the kernel program and construct a first node for each step; determine the execution order between each first node according to the dominance relationship between each step; and concatenate the first nodes according to the execution order to obtain the control flow graph.

[0143] In some embodiments, the graph construction module 4552 is configured to perform the following processing for each tensor: determine the target steps involved in the tensor data of the tensor; and take the path formed by the first node group of each target step as the active path of the tensor.

[0144] In some embodiments, the graph construction module 4552 is configured to construct a second node corresponding to each tensor; traverse each second node and perform the following processing on the traversed second node: compare the active path of the traversed second node with the active path of other second nodes to obtain a comparison result; when the comparison result indicates that the two active paths at least partially overlap, connect the two second nodes; and obtain the interference graph in response to the completion of the comparison between all second nodes.

[0145] In some embodiments, the memory allocation module 4553 is configured to traverse each of the second nodes in the interference graph and perform the following processing on the traversed second nodes: based on the interference graph, determine a first target tensor data that has an interference relationship with the tensor data of the second node, and a second target tensor data that does not have an interference relationship with the tensor data of the second node; when the first address information of the tensor data of the second node overlaps at least partially with the address information of the first target tensor, adjust the first address information based on the address information of the second target tensor to obtain the second address information.

[0146] In some embodiments, the first address information includes: a first starting address and a first address offset; the second address information includes: a second starting address and a second address offset; the memory allocation module 4553 is used to take the storage area indicated by the third starting address and the second address offset of the second target tensor as a first free storage area; and to take the storage area that does not store any tensor data as a second free storage area; when the first address offset is less than or equal to the second address offset, a first difference between the second address offset and the first address offset is determined, and the first starting address is modified to the second starting address, wherein the second starting address is located in the address interval between the third starting address and the target address, and the target address is the sum of the third starting address and the first difference; when the first address offset is greater than the second address offset, and the first free storage area and the second free storage area are not continuous, the first starting address is modified to the second starting address, wherein the second starting address is located in the second free storage area; when the first address offset is greater than the second address offset, and the first free storage area and the second free storage area are continuous, the first starting address is modified to the second starting address, wherein the second starting address is located in the first free storage area.

[0147] This application provides a computer program product, which includes a computer program or computer executable instructions. A processor executes the computer program or computer executable instructions to implement the memory allocation method described in this application.

[0148] This application provides a computer-readable storage medium storing computer-executable instructions or a computer program. When the computer-executable instructions or the computer program are executed by a processor, the processor will execute the memory allocation method provided in this application, for example... Figure 3 The memory allocation method is shown.

[0149] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0150] In some embodiments, computer-executable instructions may take the form of programs, software, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.

[0151] As an example, computer-executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple co-located files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0152] As an example, computer-executable instructions can be deployed to execute on a single electronic device, or on multiple electronic devices located in one location, or on multiple electronic devices distributed across multiple locations and interconnected via a communication network.

[0153] In summary, this application's embodiments construct a control flow graph based on the kernel program, determine the active paths of tensor data for each tensor in the kernel program based on the control flow graph, construct an interference graph of tensor data based on the overlap relationships between active paths, determine the interference relationships between tensors through the edges between nodes in the interference graph, and adjust the first address information of each tensor data according to the interference relationships to obtain the second address information of each tensor data. In different steps of the kernel program, if there is no interference relationship between two tensors, the storage areas of the two tensor data are reused. Adjusting the first address information of each tensor data according to the interference relationships avoids address conflicts of tensor data in the same step and reuses storage areas in different steps of the kernel program, thereby improving memory reuse rate.

[0154] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A memory allocation method characterized by comprising: The method includes: Extract tensor data for each tensor in the kernel program, wherein the kernel program is stored in static random access memory; A control flow graph is constructed based on the kernel program, wherein any first node in the control flow graph represents a step in the kernel program, and a path formed by multiple first nodes represents the execution order of the steps; Assign a first address in the static random access memory to each of the tensor data; An active path for each tensor is determined based on the control flow graph, wherein the active path includes a first node involving the tensor; An interference graph of the tensor is constructed based on the active paths, wherein the interference graph is a node graph constructed based on the interference relationship between the active paths of the tensor, the interference relationship indicating that at least part of the active paths of the tensor overlaps, each second node in the interference graph represents a different tensor, and the edges between the second nodes represent the interference relationship between the tensors; The first address information of each tensor data is adjusted according to the interferogram to obtain the second address information of each tensor data. In different steps of the kernel program, if there is no interference relationship between two tensors, the storage areas of the two tensor data are reused. The first address information includes: a first starting address and a first address offset; the second address information includes: a second starting address and a second address offset. The step of adjusting the first address information of each tensor data according to the interferogram to obtain the second address information of each tensor data includes: When the first address offset is less than or equal to the second address offset, a first difference between the second address offset and the first address offset is determined, and the first starting address is modified to the second starting address. The second starting address is located in the address range between the third starting address and the target address. The third starting address is the starting address of the second target tensor that has no interference relationship with the tensor of the second node. The target address is the sum of the third starting address and the first difference. When the first address offset is greater than the second address offset, and the first free storage area and the second free storage area are not contiguous, the first starting address is modified to the second starting address, wherein the second starting address is located in the second free storage area, the second free storage area is a storage area that does not store any tensor data, and the first free storage area is the storage area indicated by the third starting address and the second address offset of the second target tensor. When the first address offset is greater than the second address offset, and the first free storage area is contiguous with the second free storage area, the first starting address is modified to the second starting address, wherein the second starting address is located in the first free storage area.

2. The method of claim 1, wherein, The step of constructing the control flow graph based on the kernel program includes: Determine each step of the kernel program and construct the first node for each step; The execution order between each of the first nodes is determined based on the dominance relationship between each of the steps; The control flow graph is obtained by concatenating the first nodes according to the execution order.

3. The method of claim 1, wherein, Determining the active path of each tensor based on the control flow graph includes: Perform the following processing for each of the tensors: The target steps involved in determining the tensor data of the tensor; The path formed by the first node group of each target step is taken as the active path of the tensor.

4. The method according to claim 1, characterized in that, The step of constructing the tensor interferogram based on the active path includes: Construct a second node corresponding to each of the tensors; Iterate through each of the second nodes and perform the following processing on each of the traversed second nodes: The active paths of the traversed second node are compared with the active paths of other second nodes to obtain the comparison results; When the comparison result indicates that the two active paths at least partially overlap, connect the two second nodes; The interferogram is obtained after the comparison is completed among all the second nodes.

5. The method according to any one of claims 1 to 4, characterized in that, The step of adjusting the first address information of each tensor data according to the interferogram to obtain the second address information of each tensor data includes: Traverse each of the second nodes in the interferogram and perform the following processing on the traversed second nodes: Based on the interferogram, a first target tensor data that has an interfering relationship with the tensor data of the second node and a second target tensor data that does not have an interfering relationship with the tensor data of the second node are determined. When the first address information of the tensor data of the second node overlaps at least partially with the address information of the first target tensor data, the process proceeds to adjusting the first address information of each tensor data according to the interferogram to obtain the second address information of each tensor data.

6. A memory allocation device, characterized in that, The device includes: A data extraction module is used to extract tensor data for each tensor in the kernel program, wherein the kernel program is stored in static random access memory; The graph construction module is used to construct a control flow graph based on the kernel program, wherein any first node in the control flow graph represents a step in the kernel program, and a path formed by multiple first nodes represents the execution order of the steps; The memory allocation module is used to allocate first address information in the static random access memory to each of the tensor data. The graph construction module is further configured to determine an active path for each tensor based on the control flow graph, wherein the active path includes a first node involving the tensor; The graph construction module is further configured to construct an interference graph of the tensor based on the active paths, wherein the interference graph is a node graph constructed based on the interference relationship between the active paths of the tensor, the interference relationship indicating that at least part of the active paths of the tensor overlaps, each second node in the interference graph represents a different tensor, and the edges between the second nodes represent the interference relationship between the tensors; The memory allocation module is further configured to adjust the first address information of each tensor data according to the interference map to obtain the second address information of each tensor data. In different steps of the kernel program, if there is no interference relationship between two tensors, the second address information of the two tensor data is reused. The first address information includes: a first starting address and a first address offset; the second address information includes: a second starting address and a second address offset. The step of adjusting the first address information of each tensor data according to the interferogram to obtain the second address information of each tensor data includes: When the first address offset is less than or equal to the second address offset, a first difference between the second address offset and the first address offset is determined, and the first starting address is modified to the second starting address. The second starting address is located in the address range between the third starting address and the target address. The third starting address is the starting address of the second target tensor that has no interference relationship with the tensor of the second node. The target address is the sum of the third starting address and the first difference. When the first address offset is greater than the second address offset, and the first free storage area and the second free storage area are not contiguous, the first starting address is modified to the second starting address, wherein the second starting address is located in the second free storage area, the second free storage area is a storage area that does not store any tensor data, and the first free storage area is the storage area indicated by the third starting address and the second address offset of the second target tensor. When the first address offset is greater than the second address offset, and the first free storage area is contiguous with the second free storage area, the first starting address is modified to the second starting address, wherein the second starting address is located in the first free storage area.

7. An electronic device, characterized in that, The electronic device includes: Memory is used to store executable instructions or computer programs. A processor, when executing computer-executable instructions or computer programs stored in the memory, implements the memory allocation method according to any one of claims 1 to 5.

8. A computer-readable storage medium storing computer-executable instructions or a computer program, characterized in that, When the computer-executable instructions or computer program are executed by a processor, they implement the memory allocation method according to any one of claims 1 to 5.

9. A chip, characterized in that, The chip is used to implement the memory allocation method according to any one of claims 1 to 5.

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