A method of managing an i2c channel

Abstract

The embodiment of the present application provides a kind of management I2C channel method, including obtaining the I2C bus number involved in communication with the equipment to be communicated, setting communication lock to the I2C bus corresponding number;Obtain the address array of hardware involved in communication path with the equipment to be communicated, the channel number array of hardware involved in communication path with the equipment to be communicated, according to hardware address array and channel number array, layer by layer control with the channel of the equipment to be communicated communication path, open necessary communication channel;Establish communication between the equipment to be communicated;If judging communication is completed, remove communication lock.

Description

Technical Field

[0001] This invention belongs to the field of computer technology, and specifically relates to a method for managing I2C channels. Background Technology

[0002] To expand the connectivity of the motherboard's I2C bus and add I2C channels to connect more external devices, an I2C expansion chip is typically used. One end of the I2C expansion chip connects to the motherboard, and the other end connects to either the motherboard or an external device.

[0003] By using I2C expansion chip adapters, the baseboard management controller can manage more external devices, improving system scalability.

[0004] However, by using I2C expansion chips for connection, a large I2C topology network can be built in a multi-level cascade (series) or parallel manner.

[0005] In a network topology, existing I2C drivers can only open all I2C channels of an I2C extension chip simultaneously. This can lead to access conflicts and resource contention, resulting in data conflicts, data corruption, and ultimately, communication errors.

[0006] Therefore, there is an urgent need for a solution that can effectively manage complex I2C topology networks and ensure the exclusivity and accuracy of I2C channel access at the software level, especially at the application layer. Summary of the Invention

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0008] A method for managing I2C channels includes: acquiring the I2C bus number involved in communication with a device to be communicated; setting a communication lock on the I2C bus with the corresponding number; acquiring the address array of the hardware involved in the communication path with the device to be communicated and the channel number array of the hardware involved in the communication path with the device to be communicated; controlling the channels involved in the communication path with the device to be communicated layer by layer according to the hardware address array and the channel number array, and opening necessary communication channels; establishing communication with the device to be communicated; and releasing the communication lock if it is determined that communication is complete.

[0009] Furthermore, a method for managing I2C channels includes: presetting an I2C topology network data structure; the I2C topology network data structure includes at least an I2C bus number, an I2C address of the device to be communicated, a hardware address array, a channel number array, and a data read / write length; and obtaining the first I2C topology network data structure of the device to be communicated.

[0010] Furthermore, a method for managing I2C channels includes a preset association relationship between the array indices of the hardware address array and the array indices of the channel number array; if the value of the i-th number in the hardware address array is valid, then the value of the i-th number in the hardware address array represents the address of the i-th hardware; if the value of the i-th number in the channel number array is valid, then the value of the i-th number in the channel number array represents the i-th channel of the i-th hardware.

[0011] Furthermore, a method for managing I2C channels includes: S41 initializing the value of array index i; S42 reading the value of the i-th number in the hardware address array and judging the value; if the value of the i-th number in the hardware address array is valid, proceed to step S43; S43 reading the value of the i-th number in the channel number array and judging the value; if the value of the i-th number in the channel number array is valid, determine the hardware address based on the value of the i-th number in the hardware address array, open the channel corresponding to the i-th number of the hardware based on the value of the i-th number in the channel number array, close the other channels of the hardware, and proceed to step S44; if the value of the i-th number in the channel number array is invalid, close all channels of the i-th hardware, and proceed to step S44; S44 obtaining the value of the data read / write length n, incrementing the value of i by 1, and judging whether the value of i is greater than the value of the data read / write length n; if i ≤ n, proceed to step S42; if i > n, proceed to step S50.

[0012] Furthermore, a method for managing an I2C channel, S42 includes proceeding to step S50 if the value of the i-th number in the hardware address array is invalid.

[0013] Furthermore, a method for managing an I2C channel includes establishing communication with the device to be communicated and performing communication verification; if the communication verification is successful, communication is initiated.

[0014] Furthermore, a method for managing I2C channels is provided, which determines whether communication is successful. If communication fails, the number of communication failures is counted, and the success of communication is determined again after a preset time. If the number of communication failures reaches the preset number, the process proceeds to step S40.

[0015] Compared with the prior art, the present invention has the following significant advantages:

[0016] Precise channel control: Through a dedicated data structure, it accurately describes arbitrarily complex multi-level I2C topologies, enabling the opening of a unique access path on demand and the explicit closure of irrelevant paths, fundamentally preventing device conflicts and misoperations caused by accidental channel opening.

[0017] Effective conflict avoidance: By introducing a locking mechanism into the application layer interface, exclusive access to I2C bus resources is guaranteed throughout the critical phase of configuring the channel link, resolving resource contention issues in a multi-process environment and ensuring the atomicity and consistency of data transmission.

[0018] High flexibility and compatibility: This solution does not rely on specific kernel driver modifications, is implemented at the application layer, and is easy to port and adapt. Its data structure design can well describe multi-level I2C expansion chip networks with serial, parallel, or mixed connections, and has good hardware compatibility.

[0019] Enhanced system stability: Sequential channel opening and closing control and error retry mechanism reduce communication failures caused by transient interference or race conditions, improving the overall reliability and system stability of BMC-managed I2C devices. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of an I2C topology network according to an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of a method for managing I2C channels according to an embodiment of the present invention. Detailed Implementation

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a” and “the” as used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0025] The terms "first" and "second" are used for descriptive purposes only, to distinguish objects, such as substances, from one another, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. For example, without departing from the scope of the embodiments of this application, "first" may also be referred to as "second," and similarly, "second" may also be referred to as "first." Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0026] Servers and embedded systems include a motherboard and a Baseboard Management Controller (BMC). The motherboard is connected to the BMC. The motherboard has an I2C bus (inter-integrated circuit, low-speed serial bus). The BMC connects to and manages other hardware through the I2C bus.

[0027] The baseboard management controller communicates with several external devices via the I2C bus, including sensors, solid-state drives, communication modules, etc.

[0028] To expand the connectivity of the motherboard's I2C bus and add I2C channels to connect more external devices, an I2C expansion chip is typically used. One end of the I2C expansion chip connects to the motherboard, and the other end connects to either the motherboard or an external device.

[0029] By using I2C expansion chip adapters, the baseboard management controller can manage more external devices, improving system scalability.

[0030] However, by using I2C expansion chips for connection, a large I2C topology network can be built in a multi-level cascade (series) or parallel manner.

[0031] like Figure 1 As shown, the motherboard is connected to the Baseboard Management Controller (BMC) and two I2C expansion chips (such as the PCA9548 chip). The Baseboard Management Controller is connected to the PCA9548 chip through the I2C bus on the motherboard.

[0032] The baseboard management controller is connected to a first PCA9548 chip with address 0x70 via I2C bus number 2 (I2C2); and to a second PCA9548 chip with address 0x71 via I2C bus number 8 (I2C8).

[0033] The PCA9548 chip has 8 I2C channels, and the second I2C channel of the first PCA9548 chip is connected to the backplane.

[0034] The backplane is connected to three I2C expansion chips (e.g., PCA9546 chips). The first PCA9546 chip has an address of 0x72, the second PCA9546 chip has an address of 0x73, and the third PCA9546 chip has an address of 0x74.

[0035] The PCA9546 chip has four I2C channels. The fourth I2C channel is connected to a solid-state drive (such as an NVMe drive). The slave address of the NVMe drive is 0x56.

[0036] In such Figure 1 In the I2C topology network shown, or a more complex I2C topology network, existing I2C drivers can only open all I2C channels of the I2C expansion chip at the same time when processing the I2C expansion chip. Therefore, problems such as access conflicts and resource contention can occur. For example, when the board management controller manages several external devices, in a context of multi-process concurrent access, data from multiple external devices will travel along multiple I2C channels, eventually converging at the motherboard I2C bus channel, competing for the right to use the motherboard I2C bus channel, resulting in data conflicts, confusion, and ultimately communication errors.

[0037] Therefore, there is an urgent need for a solution that can effectively manage complex I2C topology networks and ensure the exclusivity and accuracy of I2C channel access at the software level, especially at the application layer.

[0038] To address the aforementioned issues, a method for managing I2C channels is provided to precisely manage I2C channels in an I2C topology network.

[0039] A server system for applying an I2C channel management method, the server system comprising:

[0040] The server system includes a motherboard, a baseboard management controller, and several external hardware components. The motherboard is connected to the baseboard management controller, and the several external hardware components are connected to the motherboard. The baseboard management controller is connected to the several external hardware components through the motherboard's I2C bus.

[0041] Several external hardware components are connected in series or in parallel to form an I2C topology network.

[0042] like Figure 2 As shown, a method for managing an I2C channel includes...

[0043] S10 defaults to I2C topology network data structure;

[0044] The I2C topology network data structure includes at least the I2C bus number, the I2C address of the device to be communicated with, a hardware address array, a channel number array, and a data read / write length; the array indices of the hardware address array and the array indices of the channel number array have a pre-defined association relationship.

[0045] S20 acquires the first I2C topology network data structure of the device to be communicated with;

[0046] S30 sets a communication lock on the I2C bus with the corresponding number according to the I2C bus number in the first I2C topology network data structure.

[0047] S40 controls the channels involved in the communication path with the device to be communicated layer by layer according to the hardware address array and channel number array in the first I2C topology network data structure, and opens the necessary communication channels.

[0048] S50 establishes communication with the device to be communicated and performs communication verification.

[0049] S60 is used for communication;

[0050] S70 determines whether communication is complete. If communication is complete, it releases the file lock.

[0051] Specifically,

[0052] S10 defaults to I2C topology network data structure.

[0053] The I2C topology network data structure includes at least the I2C bus number, the I2C address of the device to be communicated with, the address array of the hardware involved in the communication path with the device to be communicated with (hereinafter referred to as the hardware address array), the channel number array of the channel involved in the communication path with the device to be communicated with (hereinafter referred to as the channel number array), and the data read / write length.

[0054] The addresses of the hardware involved in the communication path with the device to be communicated include the addresses of intermediate hardware involved in the communication path (hereinafter referred to as intermediate hardware) and the addresses of hardware connected in parallel with the intermediate hardware involved in the communication path (hereinafter referred to as parallel hardware). The intermediate hardware involved in the communication path includes, but is not limited to, I2C expansion chips. It can be understood that if there are several intermediate hardware and several parallel hardware, the addresses of the hardware involved in the communication path with the device to be communicated are an address array.

[0055] The channel number involved in the communication path with the device to be communicated is the channel number of the intermediate hardware and the parallel hardware. It can be understood that if there are several intermediate hardware and parallel hardware, the channel number involved in the communication path with the device to be communicated is an array of channel numbers.

[0056] There is a pre-defined association between the array indices of the hardware address array and the array indices of the channel number array.

[0057] Furthermore, the array indices of the hardware address array and the channel number array are the same and correspond one-to-one. That is, if the array index of the hardware address array is A and the array index of the channel number array is B, then A equals B. In other words, there is a pre-defined association between the i-th number in the hardware address array and the i-th number in the channel number array.

[0058] If the value of the i-th number in the hardware address array is valid, then the value of the i-th number in the hardware address array represents the address of the i-th hardware; if the value of the i-th number in the hardware address array is invalid, it means that the i-th number in the hardware address array corresponds to no hardware. In this embodiment, 0 is an invalid value and serves as an end marker. Non-zero values ​​are valid values.

[0059] If the value of the i-th number in the channel number array is valid, then the value of the i-th number in the channel number array represents the i-th channel of the i-th hardware. If the value of the i-th number in the channel number array is invalid, then it represents all channels of the i-th hardware. In this embodiment, 0 is an invalid value, which means that all channels of the corresponding hardware are turned off. Non-zero values ​​are valid values.

[0060] The number of elements in the hardware address array and channel number array shall not exceed the data read / write length.

[0061] Specifically, the code for the preset data structure is as follows:

[0062] typedef struct {

[0063] INT8U I2CBus; / / I2C bus number used

[0064] INT8U SlaveAddress; / / I2C address of the device to be communicated with; 0 indicates no device

[0065] INT8U SwitchAddress[MAX_SWITCH_LEVEL]; / / Hardware address array; 0 is close all channels, channels from 1-n

[0066] INT8U ChannelNumber[MAX_SWITCH_LEVEL]; / / Channel number array, INT8U *writeBuffer; / / Pointer to the write buffer.

[0067] INT8U *readBuffer; / / Pointer to the read data buffer

[0068] int writeLen; / / Length of data to be written

[0069] int readLen; / / Expected length of data to be read

[0070] } PACKED OEM_I2C_MULTI_SWITCH_INFO;

[0071] The SwitchAddress and ChannelNumber arrays correspond one-to-one with the same index, jointly defining the access path.

[0072] by Figure 1 For example, the default data structure for accessing an NVMe hard drive is:

[0073] The I2C bus used is numbered I2CBus = 2.

[0074] The final target device's I2C address is SlaveAddress = 0x56.

[0075] The hardware address array SwitchAddress = {0x70, 0x72, 0x73, 0x74, 0}

[0076] Channel number array: ChannelNumber = {2, 4, 0, 0, 0}.

[0077] S20 acquires the first I2C topology network data structure of the device to be communicated with;

[0078] S30 sets a communication lock on the I2C bus with the corresponding number according to the I2C bus number in the first I2C topology network data structure.

[0079] Specifically, the communication lock is used at the operating system level to prevent other processes from using the I2C bus with the corresponding number, and at the software level to lock the first I2C bus. For a process that has set the communication lock, it can ensure that the process has exclusive access to the first I2C bus channel; for other processes that have not set the communication lock and want to use the I2C bus, they need to wait for the communication lock to be unlocked before they can use the I2C bus.

[0080] S40 controls the channels involved in the communication path with the device to be communicated layer by layer according to the hardware address array and channel number array in the first I2C topology network data structure, and opens the necessary communication channels.

[0081] Specifically, controlling the communication path between the layer-by-layer control and the communication device includes opening necessary channels at the hardware level, physically disconnecting the connection, and closing unnecessary channels;

[0082] S40 includes

[0083] S41 initializes the value of array index i.

[0084] S42 reads the value of the i-th number SwitchAddress[i] in the hardware address array and makes a judgment on that value;

[0085] If the value of the i-th number in the hardware address array is invalid, proceed to step S50.

[0086] If the value of the i-th number in the hardware address array is valid, proceed to step S43.

[0087] S43 reads the value of the i-th number ChannelNumber[i] in the channel number array and makes a judgment on that value;

[0088] If the value of the i-th number in the channel number array is valid, then the hardware address is determined based on the value of the i-th number in the hardware address array. Based on the value of the i-th number in the channel number array, the channel corresponding to the i-th number of the hardware is opened, and the other channels of the hardware are closed. Proceed to step S44. For example, if the value of the first number in the hardware address array is 0x70 and the value of the first number in the channel number array is 2, then the second channel of the hardware with address 0x70 is opened, and the other channels of the hardware are closed.

[0089] If the value of the i-th number in the channel number array is invalid, shut down all channels of the i-th hardware and proceed to step S44.

[0090] S44 increments the value of i by 1 and determines whether the value of i is greater than the data read / write length n in the first I2C topology network data structure.

[0091] If i≤n, then proceed to step S42;

[0092] For example: after reading and judging the value of the first number in the hardware address array and the value of the first number in the channel number array, the corresponding channel is closed or opened; if 2 is less than the data read / write length, then the value of the second number in the hardware address array and the value of the second number in the channel number array are read and judged.

[0093] If i > n, then proceed to step S50.

[0094] Steps S41-S44 configure each level of switch in sequence to build a precise access channel and close unnecessary channels on the path.

[0095] S50 establishes communication with the device to be communicated and performs communication verification.

[0096] S50 includes

[0097] S51 determines whether communication is successful.

[0098] If communication verification fails, proceed to S52;

[0099] S52 counts the number of communication verification failures and checks whether the communication is successful again after a preset time.

[0100] If the number of communication verification failures reaches the preset number, proceed to step S40;

[0101] If the communication verification is successful, proceed to S60;

[0102] S60 is used for communication;

[0103] S70 determines whether communication is complete. If communication is complete, it releases the file lock.

[0104] Using the above method, even if multiple application processes simultaneously request access to devices on different branches of the same I2C bus, the application-level locking mechanism serializes these accesses. Each process, after acquiring the lock, can exclusively control the bus. Through preset data structures and their parsing and execution, I2C channels can be configured sequentially and precisely according to the preset data structures, ensuring necessary channels are open and unnecessary channels are closed. The lock is released immediately upon completion, thus efficiently and conflict-free sharing of complex I2C topology resources.

[0105] By pre-setting a data structure and parsing and executing the pre-set data structure, this lock can be precisely controlled to ensure that other processes cannot operate on the same I2C bus when the current process is performing subsequent critical operations.

[0106] Compared with the prior art, the present invention has the following significant advantages:

[0107] Precise channel control: Through a dedicated data structure, it accurately describes arbitrarily complex multi-level I2C topologies, enabling the opening of a unique access path on demand and the explicit closure of irrelevant paths, fundamentally preventing device conflicts and misoperations caused by accidental channel opening.

[0108] Effective conflict avoidance: By introducing a locking mechanism into the application layer interface, exclusive access to I2C bus resources is guaranteed throughout the critical phase of configuring the channel link, resolving resource contention issues in a multi-process environment and ensuring the atomicity and consistency of data transmission.

[0109] High flexibility and compatibility: This solution does not rely on specific kernel driver modifications, is implemented at the application layer, and is easy to port and adapt. Its data structure design can well describe multi-level I2C expansion chip networks with serial, parallel, or mixed connections, and has good hardware compatibility.

[0110] Enhanced system stability: Sequential channel opening and closing control and error retry mechanism reduce communication failures caused by transient interference or race conditions, improving the overall reliability and system stability of BMC-managed I2C devices.

[0111] The method described in this invention can be integrated into the firmware or operating system of the BMC as a software module. The system module division corresponds to the aforementioned method steps, and each module works collaboratively to complete the I2C communication task with conflict avoidance.

[0112] A computer device includes a memory, a processor, and a computer program stored in the memory, characterized in that the processor executes the computer program to implement a method for managing an I2C channel in any of the above method embodiments.

[0113] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, implements a method for managing an I2C channel in any of the above method embodiments.

[0114] This invention also provides a computer program or a computer program product including a computer program, which, when executed on a computer, will enable the computer to implement an I2C channel management method in any of the above method embodiments.

[0115] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for managing an I2C channel, characterized in that, include S10: Preset I2C topology network data structure. The I2C topology network data structure includes I2C bus number, hardware address array, and channel number array. There is a preset association relationship between the array index of the hardware address array and the array index of the channel number array. S30: Obtain the I2C bus number involved in communicating with the device to be communicated, set a communication lock for the corresponding I2C bus, the communication lock is used to prevent other processes from using the corresponding I2C bus at the operating system level, and to lock the I2C bus at the software level. For a process that has set a communication lock, it can ensure that the process has exclusive access to the channel of the I2C bus. S40: Obtain the address array of the hardware involved in the communication path with the device to be communicated and the channel number array of the hardware involved in the communication path with the device to be communicated. Traverse the hardware address array and channel number array layer by layer, control the channels involved in the communication path with the device to be communicated layer by layer according to the index order, open the necessary communication channels and close the unnecessary channels. The address of the hardware involved in the communication path with the device to be communicated includes the address of the intermediate hardware involved in the communication path and the address of the hardware connected in parallel with the intermediate hardware involved in the communication path. S50: Establish communication with the device to be communicated; S70: If communication is determined to be complete, release the communication lock. Also includes: S41: Initialize the value of array index i; S42: Read the value of the i-th number in the hardware address array and judge that value; If the value of the i-th number in the hardware address array is valid, proceed to step S43; S43: Read the value of the i-th number in the channel number array and judge that value; If the value of the i-th number in the channel number array is valid, then the hardware address is determined according to the value of the i-th number in the hardware address array. According to the value of the i-th number in the channel number array, the channel of the hardware with the value of the i-th number is opened, and the other channels of the hardware are closed. Proceed to step S44. If the value of the i-th number in the channel number array is invalid, shut down all channels of the i-th hardware and proceed to step S44; S44: Get the value of data read / write length n, increment the value of i by 1, and determine whether the value of i is greater than the value of data read / write length n; If i≤n, then proceed to step S42.

2. The method for managing an I2C channel as described in claim 1, characterized in that, The I2C topology network data structure also includes the I2C address of the device to be communicated with and the data read / write length. The method also includes... S20: Obtain the first I2C topology network data structure of the device to be communicated with.

3. The method for managing an I2C channel as described in claim 2, characterized in that, include If the value of the i-th number in the hardware address array is valid, then the value of the i-th number in the hardware address array represents the address of the i-th hardware. If the value of the i-th number in the channel number array is valid, then the value of the i-th number in the channel number array represents the i-th channel of the i-th hardware.

4. The method for managing an I2C channel as described in claim 3, characterized in that, include If i > n, then proceed to step S50.

5. The method for managing an I2C channel as described in claim 4, characterized in that, S42 includes If the value of the i-th number in the hardware address array is invalid, proceed to step S50.

6. A method for managing an I2C channel as described in any one of claims 1-5, characterized in that, include S50: Establish communication with the device to be communicated and perform communication verification; S60: If the communication verification is successful, proceed with the communication.

7. A method for managing an I2C channel as described in claim 6, characterized in that, S50 includes S51: Determine if communication was successful; If communication fails, proceed to S52; S52: Count the number of communication failures and check whether the communication is successful again after a preset time; If the number of communication failures reaches the preset number, proceed to step S40.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1-7.

9. A computer-readable storage medium having instructions stored thereon, characterized in that, When executed by the processor, this instruction implements the steps of the method according to any one of claims 1-7.

10. A computer program product, comprising instructions, characterized in that, When executed by the processor, this instruction implements the steps of the method according to any one of claims 1-7.

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