Verification method and device of passive algorithm module and computer device

Abstract

The application relates to a passive algorithm module verification method and device and a computer device. The method comprises the following steps: obtaining a virtual sequence; the virtual sequence comprises a configuration sequence, an excitation sequence and a data collection sequence in sequence; based on the configuration sequence, configuration information of the passive algorithm module is configured, and based on the configuration information, a reference output result is generated through a reference model; based on the excitation sequence, excitation data of the passive algorithm module is generated, the excitation data is input into the passive algorithm module, an algorithm processing result of the passive algorithm module and an interrupt signal corresponding to the processing result are generated; based on the interrupt signal, a current trigger event is identified through the data collection sequence, and based on the current trigger event, the algorithm processing result and the reference output result are compared and verified to obtain a verification result of the passive algorithm module. The method can improve the verification accuracy of the passive algorithm module to be verified.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital IC verification, in particular to a passive algorithm module verification method and device and computer equipment. BACKGROUND

[0002] In the field of IC (Integrated Circuit) verification, the first choice for module verification is white box verification, and a reference model is needed as an output comparison. Among them, the passive algorithm module to be verified is downstream of the AD (Analog-to-Digital Converter) in the SOC (System on a Chip) chip. The upstream AD receives the radar signal after analog-to-digital conversion and outputs the processing result to the passive algorithm module to be verified. The passive algorithm module inside performs a series of channelization processing such as serial-parallel conversion, parallel-serial conversion, multiple filtering, FFT (Fast Fourier Transform), CORDIC (Coordinate Rotation Digital Computer), serial-parallel conversion and amplitude autocorrelation, etc. to detect the pulse width, frequency, amplitude, phase, etc. of the output signal of the AD, and output the detection result. Therefore, how to improve the verification accuracy of the passive algorithm module to be verified is the current research focus.

[0003] The traditional verification method of the passive algorithm module to be verified is to use systemverilog or systemc to write a reference model for verification. However, this method has limitations for modules with extremely complex algorithm functions. It is very difficult to implement many algorithm functions, and the correctness cannot be guaranteed, resulting in low verification accuracy of the passive algorithm module to be verified. SUMMARY

[0004] Therefore, it is necessary to provide a passive algorithm module verification method, device and computer equipment to solve the above technical problems.

[0005] In a first aspect, the present application provides a passive algorithm module verification method, comprising:

[0006] obtaining a virtual sequence; the virtual sequence includes a configuration sequence, a stimulus sequence and a data collection sequence in sequence;

[0007] based on the configuration sequence, configuring the configuration information of the passive algorithm module, and based on the configuration information, generating a reference output result through a reference model;

[0008] generating excitation data of the passive algorithm module based on the excitation sequence, and inputting the excitation data into the passive algorithm module to generate an algorithm processing result of the passive algorithm module and an interrupt signal corresponding to the processing result;

[0009] based on the interrupt signal, identifying a current trigger event through the data collection sequence, and performing comparison and verification processing on the algorithm processing result and the reference output result based on the current trigger event to obtain a verification result of the passive algorithm module.

[0010] Optionally, the generating of the reference output result based on the configuration information through the reference model comprises:

[0011] sending the configuration information to the reference model through a first analysis port;

[0012] generating the reference output result corresponding to the configuration information through an external mathematical tool function based on the reference model and the configuration information.

[0013] Optionally, the generating of the excitation data of the passive algorithm module based on the excitation sequence comprises:

[0014] generating an excitation transaction conforming to a preset constraint based on the excitation sequence, and identifying parameters of the excitation transaction;

[0015] generating excitation data through an external data tool function based on the parameters of the excitation transaction.

[0016] Optionally, the inputting of the excitation data into the passive algorithm module to generate the algorithm processing result of the passive algorithm module and the interrupt signal corresponding to the processing result comprises:

[0017] inputting the excitation data into the passive algorithm module according to a preset timing through an excitation driver;

[0018] performing signal detection processing on the excitation data through the passive algorithm module to generate the algorithm processing result of the passive algorithm module, storing the algorithm processing result in an internal memory, and generating an interrupt signal storing the algorithm processing result.

[0019] Optionally, the identifying of the current trigger event based on the interrupt signal through the data collection sequence comprises:

[0020] identifying a target sub-channel corresponding to the interrupt signal through a data collection agent in the data collection sequence for listening to each sub-channel; the internal memory comprises a plurality of sub-channels, and the algorithm processing result is stored in a target sub-channel among the sub-channels.

[0021] The channel address of the target sub-channel is taken as a current trigger event.

[0022] Optionally, the comparison and verification processing of the algorithm processing result and the reference output result based on the current trigger event obtains a verification result of the passive algorithm module, and the comparison and verification processing includes:

[0023] The algorithm processing result in the target sub-channel is sent to a score board based on the current trigger event, and the reference output result is sent to the score board;

[0024] The algorithm processing result and the reference output result are compared by the score board to obtain a comparison result, and the verification result of the passive algorithm module is generated based on the comparison result.

[0025] In a second aspect, the present application further provides a verification device of a passive algorithm module, including:

[0026] An acquisition module is configured to acquire a virtual sequence; the virtual sequence includes a configuration sequence, an excitation sequence and a data collection sequence in sequence;

[0027] A configuration module is configured to configure configuration information of the passive algorithm module based on the configuration sequence, and generate a reference output result by a reference model based on the configuration information;

[0028] A generation module is configured to generate excitation data of the passive algorithm module based on the excitation sequence, and input the excitation data into the passive algorithm module to generate an algorithm processing result of the passive algorithm module and an interrupt signal corresponding to the processing result;

[0029] A verification module is configured to identify a current trigger event by the data collection sequence based on the interrupt signal, and perform comparison and verification processing of the algorithm processing result and the reference output result based on the current trigger event to obtain a verification result of the passive algorithm module.

[0030] Optionally, the configuration module is specifically configured to:

[0031] The configuration information is sent to the reference model through a first analysis port;

[0032] The reference output result corresponding to the configuration information is generated by an external mathematical tool function based on the reference model and the configuration information.

[0033] Optionally, the generation module is specifically configured to:

[0034] generate an incentive transaction conforming to preset constraints based on the incentive sequence, and identify parameters of the incentive transaction;

[0035] generate incentive data through an external data tool function based on the parameters of the incentive transaction.

[0036] Optionally, the generating module is specifically configured to:

[0037] input the incentive data into the passive algorithm module according to a preset timing sequence through an incentive driver;

[0038] perform signal detection processing on the incentive data through the passive algorithm module, generate an algorithm processing result of the passive algorithm module, store the algorithm processing result in an internal memory, and generate an interrupt signal storing the algorithm processing result.

[0039] Optionally, the verifying module is specifically configured to:

[0040] identify a target sub-channel corresponding to the interrupt signal based on the interrupt signal through a data collection agent listening to each sub-channel in the data collection sequence; the internal memory includes a plurality of sub-channels, and the algorithm processing result is stored in a target sub-channel among the sub-channels;

[0041] take a channel address of the target sub-channel as a current trigger event.

[0042] Optionally, the verifying module is specifically configured to:

[0043] send the algorithm processing result in the target sub-channel to a score board and send the reference output result to the score board based on the current trigger event;

[0044] compare the algorithm processing result with the reference output result through the score board to obtain a comparison result, and generate a verification result of the passive algorithm module based on the comparison result.

[0045] In a third aspect, a computer device is provided. The computer device includes a memory and a processor. The memory stores a computer program. When the processor executes the computer program, steps of the method in any one of the first aspect are implemented.

[0046] In a fourth aspect, a computer readable storage medium is provided. The computer readable storage medium stores a computer program. When the computer program is executed by a processor, steps of the method in any one of the first aspect are implemented.

[0047] In a fifth aspect, the present application provides a computer program product. The computer program product comprises a computer program which, when executed by a processor, implements the steps of the method of any one of the first aspect.

[0048] The verification method and device of the passive algorithm module and the computer device, by obtaining a virtual sequence; the virtual sequence contains a configuration sequence, an excitation sequence and a data collection sequence in sequence; based on the configuration sequence, the configuration information of the passive algorithm module is configured, and based on the configuration information, a reference output result is generated by referring to a reference model; based on the excitation sequence, the excitation data of the passive algorithm module is generated, and the excitation data is input into the passive algorithm module to generate the algorithm processing result of the passive algorithm module and the interrupt signal corresponding to the processing result; based on the interrupt signal, the current trigger event is identified through the data collection sequence, and based on the current trigger event, the algorithm processing result and the reference output result are compared and verified to obtain the verification result of the passive algorithm module. In this scheme, MATLAB is used to generate excitation and reference results, ensuring the mathematical correctness of the excitation signal and the algorithm accuracy of the reference model, keeping consistent with the passive algorithm module design source (MATLAB prototype) and avoiding errors that may be introduced by manual translation model. Secondly, the complex mathematical calculation and model simulation are unloaded to MATLAB, and the simulation platform focuses on verification process control, excitation driving, response collection and result comparison, with clear division of labor, improving the execution efficiency and development efficiency of the simulation platform. Thirdly, through uvm_event (a core communication mechanism for component "synchronization and event triggering" in UVM general verification methodology) and the waiting mechanism in the reference model, the synchronization problem between the zero-delay of the software model and the time-delay of the hardware timing is ingeniously solved, ensuring the correct timing of the result comparison, making the verification process complete and reliable. Finally, the whole process of this scheme, from parameter configuration, excitation generation, passive algorithm module simulation, data collection to result comparison, is all automatically completed. The platform components are constructed based on the general verification method technology, with good reusability and scalability, which can be easily adapted to different test scenarios and passive algorithm module configurations. The verification accuracy of the passive algorithm module to be verified is effectively improved. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the description of the embodiments of the present application or the related art will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0050] Figure 1A flowchart of a verification method of a passive algorithm module in an embodiment;

[0051] Figure 2 A flowchart of a verification example of a passive algorithm module in an embodiment;

[0052] Figure 3 A block diagram of a verification device of a passive algorithm module in an embodiment;

[0053] Figure 4 An internal structure diagram of a computer device in an embodiment. DETAILED DESCRIPTION

[0054] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0055] It should be noted that the terms "first", "second" and the like used in the present application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "include" and "have" and any variations thereof used in the present application are intended to cover non-exclusive inclusion. The term "multiple" used in the present application refers to two and more than two. The term "and / or" used in the present application refers to one of the options or any combination of multiple options.

[0056] The passive algorithm module verification method provided by the embodiments of the present application can be applied to a system for verifying a passive algorithm module. The system can be applied to a terminal, which can be, but is not limited to, various personal computers, notebook computers, medium-sized computers and the like. The terminal first generates an excitation and a reference result by using MATLAB, ensures the mathematical correctness of the excitation signal and the algorithm accuracy of the reference model, is consistent with the passive algorithm module design source (MATLAB prototype), and avoids errors that can be introduced by manually translating the model. Secondly, the complex mathematical calculation and model simulation are unloaded to MATLAB, the simulation platform focuses on the verification process control, excitation driving, response collection and result comparison, the division of labor is clear, and the execution efficiency and development efficiency of the simulation platform are improved. Thirdly, by using the uvm_event and the waiting mechanism in the reference model, the synchronization problem between the zero delay of the software model and the time delay of the hardware timing is ingeniously solved, the correct timing of the result comparison is ensured, the verification process is complete and reliable. Finally, the entire process of the present scheme, from parameter configuration, excitation generation, passive algorithm module simulation, data acquisition to result comparison, is automatically completed. The platform components are constructed based on the general verification method technology, have good reusability and scalability, and can be conveniently adapted to different test scenarios and passive algorithm module configurations. The verification accuracy of the passive algorithm module to be verified is effectively improved.

[0057] In one exemplary embodiment, as shown in Figure 1 A passive algorithm module verification method is provided, and the method is described by taking a terminal as an example, and includes the following steps S101 to S104, wherein:

[0058] In step S101, a virtual sequence is acquired.

[0059] The virtual sequence includes a configuration sequence, an excitation sequence and a data collection sequence in sequence.

[0060] In the embodiment, when the terminal performs passive algorithm module verification, the simulation task of the passive algorithm module is started in the verification environment of the passive algorithm module constructed by the UVM. Then the virtual sequence is obtained through the MATLAB program. The virtual sequence is an execution sequence corresponding to the mathematical calculation and model simulation process of parameter configuration, excitation generation and data acquisition of the passive algorithm based on MATLAB execution. The virtual sequence includes a configuration sequence, an excitation sequence and a data collection sequence. The virtual sequence (virtual sequence) is a controller of the test process, and starts apb_seq (apb sub-sequence), adc_seq (adc sub-sequence), axi0_seq (axi0 sub-sequence) and axil_seq (axil sub-sequence) in sequence. The configuration sequence includes a plurality of configuration agents arranged according to the execution sequence. The configuration agent (apb_master_agt) completes the configuration of the passive algorithm module and broadcasts the configuration parameters through the analysis port. The excitation sequence includes a plurality of excitation agents arranged according to the execution sequence. The excitation agent (adc_master_agt) integrates the MATLAB calling function in the driver, and can dynamically generate excitation data according to the constraint parameters generated by the sequence. The data collection sequence includes a plurality of data collection agents for monitoring different sub-channels in the internal memory of the passive algorithm module. The data collection agent (axi_master_agt) includes monitoring logic for detecting interrupt signals and triggering uvm_event, and responding to events to execute bus read operations. In the embodiment of the present scheme, the sampling detection of 6 signal types with a frequency range of 1200MHz (1.2GHz-2.4GHz) is supported. In the embodiment, the 1.8GHz point frequency signal is exemplarily described.

[0061] In step S102, the configuration information of the passive algorithm module is configured based on the configuration sequence, and the reference output result is generated through the reference model based on the configuration information.

[0062] In this embodiment, the terminal configures the configuration information of the passive algorithm module based on the configuration sequence through the MATLAB script, and generates the reference output result based on the configuration information through the reference model. The configuration sequence is used to configure the configuration information of the passive algorithm module generator working mode, each sub-channel center frequency, various threshold values, and pulse width offset values. The generation process of the reference model will be described in detail later. The passive algorithm module is in the SOC chip, and the upstream is AD, and the downstream is connected to the srio module through the axi bus. The overall data flow is that AD receives radar signals, and the results are output to the passive algorithm module through analog-to-digital conversion. The internal memory of the passive algorithm module includes 16 sub-channels. Through channelization processing, the instantaneous measurement result and the amplitude and phase result of the corresponding sub-channel are generated according to the signal frequency, and the downstream srio module is notified through the interrupt signal of the corresponding sub-channel. The reference model is a software model used to simulate the channel detection process of the passive algorithm module, thereby generating the simulation instantaneous measurement result and the simulation amplitude and phase result. The model is represented as a software detection program.

[0063] In step S103, the excitation data of the passive algorithm module is generated based on the excitation sequence, and the excitation data is input into the passive algorithm module to generate the algorithm processing result of the passive algorithm module and the interrupt signal corresponding to the algorithm processing result.

[0064] In this embodiment, the terminal generates the excitation data of the passive algorithm module based on the excitation sequence through the MATLAB script, and inputs the excitation data into the passive algorithm module to generate the algorithm processing result of the passive algorithm module and the interrupt signal corresponding to the algorithm processing result through the MATLAB script. The interrupt signal is the interrupt signal corresponding to the sub-channel where the algorithm processing result is stored in the internal storage. The interrupt signal is used to represent that the sub-channel stores the algorithm processing result. The specific generation process will be described in detail later.

[0065] In step S104, the current trigger event is identified based on the interrupt signal through the data collection sequence, and the algorithm processing result and the reference output result are compared and verified based on the current trigger event to obtain the verification result of the passive algorithm module.

[0066] In this embodiment, the terminal identifies the current trigger event based on the interrupt signal through the data collection sequence, and compares and verifies the algorithm processing result and the reference output result based on the current trigger event to obtain the verification result of the passive algorithm module. The current trigger event is an event based on the data processing result stored in the target sub-channel where the algorithm processing result is stored in each sub-channel. The specific comparison and verification process will be described in detail later.

[0067] Based on the above scheme, first, the excitation and reference results are generated by MATLAB to ensure the mathematical correctness of the excitation signal and the algorithm accuracy of the reference model, which is consistent with the source (MATLAB prototype) of the passive algorithm module design, and avoids errors that may be introduced by manual translation of the model. Secondly, the complex mathematical calculations and model simulations are offloaded to MATLAB, and the simulation platform focuses on verifying the process control, excitation driving, response collection and result comparison, with clear division of labor, improving the execution efficiency and development efficiency of the simulation platform. Thirdly, through the uvm_event and the waiting mechanism in the reference model, the synchronization problem between the zero delay of the software model and the time delay of the hardware timing is cleverly solved, ensuring the correct timing of the result comparison, making the verification process complete and reliable. Finally, the entire process of the scheme, from parameter configuration, excitation generation, passive algorithm module simulation, data acquisition to result comparison, is automatically completed. The platform components are constructed based on the general verification method technology, have good reusability and scalability, and can be easily adapted to different test scenarios and passive algorithm module configurations. The verification accuracy of the passive algorithm module to be verified is effectively improved.

[0068] Optionally, based on the configuration information, a reference output result is generated through the reference model, including: sending the configuration information to the reference model through the first analysis port; based on the reference model and the configuration information, generating the reference output result corresponding to the configuration information through an external mathematical tool function.

[0069] In this embodiment, the terminal sends the configuration information to the reference model through the first analysis port; based on the reference model and the configuration information, the reference output result corresponding to the configuration information is generated through an external mathematical tool function. The first analysis port is a uvm_analysis_port of UVM. The external mathematical tool function is a MATLAB function, which is called through a system task $system. Specifically, the terminal controls the reference model to generate the output result simulated and output by the passive algorithm module based on the configuration information through the external mathematical tool function, to obtain the reference output result.

[0070] Based on the above scheme, the simulation output operation of the reference model is executed through the MATLAB function, the complex mathematical calculations and model simulations are offloaded to MATLAB, and the UVM platform focuses on verifying the process control, excitation driving, response collection and result comparison, with clear division of labor, improving the execution efficiency and development efficiency of the simulation platform.

[0071] Optionally, based on the excitation sequence, the excitation data of the passive algorithm module is generated, including: based on the excitation sequence, generating an excitation transaction conforming to a preset constraint, and identifying parameters of the excitation transaction; based on the parameters of the excitation transaction, generating the excitation data through an external data tool function.

[0072] In this embodiment, the terminal generates an incentive transaction conforming to preset constraints based on the incentive sequence, and identifies parameters of the incentive transaction. The incentive transaction conforming to the preset constraints is a format of incentive data preset in the terminal corresponding to different signal types. For example, in a 1.8 GHz point frequency signal type, the terminal, based on the incentive data, constrains the signal type of the incentive data to a point frequency, constrains the frequency parameter to 1.8 GHz, constrains the energy parameter to a reasonable range, constrains the pulse width parameter to a reasonable range, and constrains the noise parameter to a reasonable range. The above reasonable range is the preset constraint preset in the terminal. The incentive parameters of the incentive transaction are the above frequency parameter, energy parameter, pulse width parameter, and noise parameter. Specifically, finally, the terminal generates incentive data based on the parameters of the incentive transaction through an external data tool function. The external data tool function is a MATLAB function, which is called through a system task $system. The incentive data is digital incentive data waveform.

[0073] Based on the above scheme, the process of generating the incentive data is transferred to the MATLAB function, so that the UVM (universal verification methodology) platform focuses on verification process control, incentive driving, response collection, and result comparison, the division of labor is clear, and the execution efficiency and development efficiency of the simulation platform are improved.

[0074] Optionally, the incentive data is input into the passive algorithm module to generate an algorithm processing result of the passive algorithm module and an interrupt signal corresponding to the algorithm processing result, including: inputting the incentive data into the passive algorithm module according to a preset timing through an incentive driver; performing signal detection processing on the incentive data through the passive algorithm module to generate the algorithm processing result of the passive algorithm module, storing the algorithm processing result in an internal memory, and generating an interrupt signal storing the algorithm processing result.

[0075] In this embodiment, the terminal inputs the incentive data into the passive algorithm module according to a preset timing through an incentive driver. Then, the terminal performs signal detection processing on the incentive data through the passive algorithm module to generate an algorithm processing result of the passive algorithm module, stores the algorithm processing result in an internal memory, and generates an interrupt signal storing the algorithm processing result. The incentive driver is an adc_sequencer (a main agent generating an ADC output signal). The preset timing is an interface timing of the passive algorithm module. In one embodiment, after receiving a 1.8 GHz point frequency signal, the passive algorithm module performs channelization detection on the input signal according to a configuration value of an apb_master_agt (a main agent of an APB bus) and outputs, temporarily stores the detection result in a ram corresponding to a subchannel, and pulls up an interrupt of the corresponding subchannel to obtain an interrupt signal, so as to notify a downstream which subchannel needs to move data.

[0076] Based on the above scheme, through the excitation data input by the preset timing, it is ensured that the passive algorithm module can normally detect the output algorithm processing result, and through the interruption of the pull-up subchannel, the obtained interruption signal provides path guidance for subsequent retrieval of the algorithm processing result, and improves the retrieval accuracy.

[0077] Optionally, based on the interruption signal, the current trigger event is identified through the data collection sequence, including: based on the interruption signal, identifying the target subchannel corresponding to the interruption signal through the data collection agent in the data collection sequence for listening to each subchannel; the internal memory includes a plurality of subchannels, and the algorithm processing result is stored in the target subchannel in each subchannel; the channel address of the target subchannel is taken as the current trigger event.

[0078] In this embodiment, the terminal identifies the target subchannel corresponding to the interruption signal through the data collection agent in the MATLAB data collection sequence for listening to each subchannel based on the interruption signal; the internal memory includes a plurality of subchannels, and the algorithm processing result is stored in the target subchannel in each subchannel; the channel address of the target subchannel is taken as the current trigger event. Among them, each data collection agent in the data collection sequence is Axi0_master_agt (AXI0 bus interface master agent) and axi1_master_agt (AXI1 bus interface master agent). Among them, Axi0_master_agt is responsible for detecting the trigger of uvm_event of 0-7 subchannels, and axi1_master_agt is responsible for detecting the trigger of uvm_event of 8-15 subchannels. The data collection agent identifies the triggered subchannel based on the interruption signal, reads the channel address of the subchannel, and obtains the current trigger event. For example, the point frequency of 1.8GHz corresponds to subchannel 7, after axi0_master_agt detects the trigger of uvm_event of subchannel 7, reads the ram address corresponding to subchannel 7, and sends the read data to scoreboard (scoreboard) through uvm_analysis_port (UVM platform built simulation environment). Get the current trigger event.

[0079] Based on the above scheme, through the MATLAB data collection sequence, the current trigger event is listened to and triggered in real time, which improves the trigger accuracy of the current trigger event and reduces the data processing amount of the UVM platform.

[0080] Optionally, based on the current trigger event, the algorithm processing result and the reference output result are compared and verified to obtain the verification result of the passive algorithm module, including: based on the current trigger event, the algorithm processing result in the target sub-channel is sent to the scoreboard, and the reference output result is sent to the scoreboard; the algorithm processing result and the reference output result are compared and processed by the scoreboard to obtain a comparison result, and the verification result of the passive algorithm module is generated based on the comparison result.

[0081] In this embodiment, the terminal sends the algorithm processing result in the target sub-channel to the scoreboard based on the current trigger event, and sends the reference output result to the scoreboard. Since the Matlab function generates results without consuming simulation time, and the passive algorithm module generates results through timing logic, when the scoreboard receives the reference output result, it interrupts to determine whether the passive algorithm module has generated a result. If the passive algorithm module has generated a result, the verification environment constructed based on the UVM platform will send the result to the scoreboard. If the passive algorithm module has not generated a result, the verification environment constructed based on the UVM platform will output a log file to ensure the integrity of the overall verification process.

[0082] Finally, the terminal compares and processes the algorithm processing result and the reference output result through the scoreboard to obtain a comparison result, and generates the verification result of the passive algorithm module based on the comparison result. The comparison process is that the terminal compares the instantaneous result and the amplitude and phase result in the algorithm processing result and the reference output result at the bit level (bit level, i.e., a single binary bit), and if the comparison is consistent, the verification passes and outputs test_pass (test pass), otherwise the functional verification fails and outputs test_fail (test success). The verification result corresponding to test_pass is verification pass, and the verification result corresponding to test_fail is verification failure. In the example, the write function of the scoreboard receives data from the passive algorithm module and the reference model respectively. It has two queues (queue) inside to buffer the two-way data. When the data from the same transaction (for example, the same test, the same sub-channel) arrives, the scoreboard calls the comparison function for bit-by-bit comparison. If they are completely consistent, the uvm_info (information printing macro) prints success information; if there is any inconsistency, the uvm_error (error log macro) prints error information.

[0083] Based on the above scheme, the entire process from parameter configuration, stimulus generation, passive algorithm module simulation, data acquisition to result comparison is automatically completed. The platform components are constructed based on UVM, have good reusability and scalability, and can be easily adapted to different test scenarios and passive algorithm module configurations.

[0084] The application also provides a verification example of a passive algorithm module, as shown in Figure 2 The specific processing process includes the following steps:

[0085] Step S201, obtaining a virtual sequence.

[0086] Step S202, configuring configuration information of the passive algorithm module based on the configuration sequence.

[0087] Step S203, sending the configuration information to the reference model through the first analysis port.

[0088] Step S204, generating a reference output result corresponding to the configuration information through an external mathematical tool function based on the reference model and the configuration information.

[0089] Step S205, generating an excitation transaction meeting a preset constraint based on the excitation sequence, and identifying parameters of the excitation transaction.

[0090] Step S206, generating excitation data through an external data tool function based on the parameters of the excitation transaction.

[0091] Step S207, inputting the excitation data into the passive algorithm module according to a preset timing through an excitation driver.

[0092] Step S208, performing signal detection processing on the excitation data through the passive algorithm module, generating an algorithm processing result of the passive algorithm module, storing the algorithm processing result in an internal memory, and generating an interrupt signal of the stored algorithm processing result.

[0093] Step S209, identifying a target sub-channel corresponding to the interrupt signal through a data collection agent listening to each sub-channel in the data collection sequence based on the interrupt signal.

[0094] Step S210, taking a channel address of the target sub-channel as a current trigger event.

[0095] Step S211, sending the algorithm processing result in the target sub-channel to a score board and sending the reference output result to the score board based on the current trigger event.

[0096] Step S212, comparing the algorithm processing result and the reference output result through the score board to obtain a comparison result, and generating a verification result of the passive algorithm module based on the comparison result.

[0097] It should be understood that although the steps in the flowcharts involved in the embodiments described above are shown in sequence according to the arrows, the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the embodiments described above can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of the steps or stages is not necessarily sequential, but can be alternately or alternately executed with at least part of other steps or steps or stages in other steps. It can be understood that the steps in different embodiments can be freely combined as needed, and various non-contradictory schemes formed by the combination are within the scope of protection of the present application.

[0098] Based on the same inventive concept, the embodiments of the present application also provide a passive algorithm module verification device for implementing the passive algorithm module verification method described above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more passive algorithm module verification device embodiments provided below can refer to the limitations of the passive algorithm module verification method described above, which will not be repeated here.

[0099] In one exemplary embodiment, as shown in Figure 3 A passive algorithm module verification device is provided, comprising: an acquisition module 310, a configuration module 320, a generation module 330 and a verification module 340, wherein:

[0100] The acquisition module 310 is configured to acquire a virtual sequence; the virtual sequence sequentially includes a configuration sequence, an excitation sequence and a data collection sequence;

[0101] The configuration module 320 is configured to configure configuration information of the passive algorithm module based on the configuration sequence, and generate a reference output result through a reference model based on the configuration information;

[0102] The generation module 330 is configured to generate excitation data of the passive algorithm module based on the excitation sequence, and input the excitation data into the passive algorithm module to generate an algorithm processing result of the passive algorithm module and an interrupt signal corresponding to the processing result;

[0103] The verification module 340 is configured to identify a current trigger event through the data collection sequence based on the interrupt signal, and perform comparison and verification processing on the algorithm processing result and the reference output result based on the current trigger event to obtain a verification result of the passive algorithm module.

[0104] Optionally, the configuration module 320 is specifically used for:

[0105] sending the configuration information to a reference model through a first analysis port;

[0106] generating a reference output result corresponding to the configuration information through an external mathematical tool function based on the reference model and the configuration information.

[0107] Optionally, the generation module 330 is specifically used for:

[0108] generating an incentive transaction conforming to a preset constraint based on the incentive sequence and identifying parameters of the incentive transaction;

[0109] generating incentive data through an external data tool function based on the parameters of the incentive transaction.

[0110] Optionally, the generation module 330 is specifically used for:

[0111] inputting the incentive data into the passive algorithm module according to a preset timing through an incentive driver;

[0112] performing signal detection processing on the incentive data through the passive algorithm module, generating an algorithm processing result of the passive algorithm module, storing the algorithm processing result in an internal memory, and generating an interrupt signal storing the algorithm processing result.

[0113] Optionally, the verification module 340 is specifically used for:

[0114] identifying a target subchannel corresponding to the interrupt signal through a data collection agent listening to each subchannel in the data collection sequence based on the interrupt signal; the internal memory includes a plurality of subchannels, and the algorithm processing result is stored in a target subchannel among the subchannels;

[0115] taking a channel address of the target subchannel as a current trigger event.

[0116] Optionally, the verification module 340 is specifically used for:

[0117] sending the algorithm processing result in the target subchannel to a score board and sending the reference output result to the score board based on the current trigger event;

[0118] comparing the algorithm processing result and the reference output result through the score board to obtain a comparison result, and generating a verification result of the passive algorithm module based on the comparison result.

[0119] Each module in the verification device of the passive algorithm module can be implemented by software, hardware and a combination thereof in whole or in part. The modules can be embedded in or independent of a processor in a computer device in hardware form, or stored in a memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to the modules.

[0120] In an exemplary embodiment, a computer device, which can be a terminal, is provided, and an internal structure diagram of the computer device can be as shown in Figure 4 The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to perform wired or wireless communication with external terminals. The wireless communication can be achieved through WIFI, mobile cellular network, near field communication (NFC) or other technologies. The computer program is executed by the processor to implement a passive algorithm module verification method. The display unit of the computer device is configured to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0121] Those skilled in the art can understand that Figure 4 The structure shown in the above description is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0122] In an exemplary embodiment, a computer device is provided, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the beer warehouse inventory optimization method.

[0123] In one embodiment, a computer readable storage medium is provided, having stored thereon a computer program which, when executed by a processor, implements the steps of the inventory optimization method for a beer brewery.

[0124] In one embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the steps of the inventory optimization method for a beer brewery.

[0125] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant regulations.

[0126] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0127] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0128] The above-described embodiments are merely illustrative of several embodiments of the present application, and the description is relatively specific and detailed, but should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A method of verifying a passive algorithm module, characterized by, The method comprises: acquiring a virtual sequence; the virtual sequence comprises a configuration sequence, an excitation sequence and a data collection sequence in sequence; based on the configuration sequence, configuring configuration information of the passive algorithm module, and based on the configuration information, generating a reference output result through a reference model; based on the excitation sequence, generating excitation data of the passive algorithm module, and inputting the excitation data into the passive algorithm module to generate an algorithm processing result of the passive algorithm module and an interrupt signal corresponding to the processing result; based on the interrupt signal, identifying a current trigger event through the data collection sequence, and based on the current trigger event, performing comparison and verification processing on the algorithm processing result and the reference output result to obtain a verification result of the passive algorithm module.

2. The method of claim 1, wherein, The method comprises: sending the configuration information to the reference model through a first analysis port; based on the reference model and the configuration information, generating a reference output result corresponding to the configuration information through an external mathematical tool function.

3. The method of claim 1, wherein, The method comprises: based on the excitation sequence, generating an excitation transaction conforming to a preset constraint, and identifying parameters of the excitation transaction; based on the parameters of the excitation transaction, generating excitation data through an external data tool function.

4. The method of claim 1, wherein, The method comprises: inputting the excitation data into the passive algorithm module through an excitation driver according to a preset timing; performing signal detection processing on the excitation data through the passive algorithm module to generate an algorithm processing result of the passive algorithm module, storing the algorithm processing result in an internal memory, and generating an interrupt signal storing the algorithm processing result.

5. The method of claim 4, wherein, The method comprises: based on the interrupt signal, identifying a target subchannel corresponding to the interrupt signal through a data collection agent in the data collection sequence listening to each subchannel; the internal memory comprises a plurality of subchannels, and the algorithm processing result is stored in a target subchannel in each subchannel; taking a channel address of the target subchannel as a current trigger event.

6. The method of claim 5, wherein, The method comprises: based on the current trigger event, sending the algorithm processing result in the target subchannel to a score board and sending the reference output result to the score board; through the score board, performing comparison processing on the algorithm processing result and the reference output result to obtain a comparison result, and based on the comparison result, generating a verification result of the passive algorithm module.

7. A verification apparatus of a passive algorithm module, characterized by, The device comprises: An acquisition module is configured to acquire a virtual sequence; the virtual sequence comprises a configuration sequence, an excitation sequence and a data collection sequence in sequence; A configuration module is configured to configure configuration information of the passive algorithm module based on the configuration sequence, and generate a reference output result through a reference model based on the configuration information; A generation module is configured to generate excitation data of the passive algorithm module based on the excitation sequence, input the excitation data into the passive algorithm module, generate an algorithm processing result of the passive algorithm module and an interrupt signal corresponding to the processing result; A verification module is configured to identify a current trigger event through the data collection sequence based on the interrupt signal, and perform comparison and verification processing on the algorithm processing result and the reference output result based on the current trigger event, to obtain a verification result of the passive algorithm module.

8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that, The processor executes the computer program to implement the steps of the method in any one of claims 1 to 6.

9. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 6.

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