Chip instruction verification method and device, and storage medium

Abstract

The invention discloses an instruction verification method and device of a chip and a storage medium, and belongs to the technical field of chip testing. The method is applied to a to-be-tested chip, the to-be-tested chip comprises a plurality of chip partitions, each chip partition comprises a plurality of storage partitions, and the method comprises the following steps: obtaining a plurality of test instructions; a control model is adopted to perform time delay control on the plurality of test instructions to form a test instruction sequence, and the test instruction sequence comprises a plurality of test instructions whose time sequences conform to a preset time sequence; and outputting the test instruction sequence to the chip to be tested. Based on the technical scheme, the time delay can be automatically added between the two test instructions through the control model to form the test instruction sequence, and the test instructions can be automatically issued, so that the chip test efficiency is improved; the time delay is not missed even under the condition that the types of the test instructions are various, and the accurate control of the test instructions is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, in particular to a chip instruction verification method and device and a storage medium. BACKGROUND

[0002] The phase change memory is also called PCM (phase change memory) or PCRAM (phase change random access memory). The phase change memory includes a plurality of array-arranged storage units, and its working principle is to realize the resistance state switching of a single storage unit by using the reversible phase change phenomenon of chalcogenide compounds, and to represent 0 and 1 by using different resistance states, that is, to realize non-volatility. For example, a high resistance state can be used to represent 1, and a low resistance state can be used to represent 0.

[0003] The PCM has rich and customized command (CMD for short) types to meet more user requirements. The PCM has numerous complex scenarios, and the random control requirement of the time delay between the commands is high. When the commands continue to increase, it is particularly important to accurately control the time delay between the commands, and the time delay problem of the commands will directly affect the basic functions of the phase change memory chip to be tested and the reliability and completeness of the verification work.

[0004] In the related art, a manual time delay adding manner is used to add a time delay between two adjacent commands. This manner relies on manual work and is inefficient and cannot automatically issue commands. SUMMARY

[0005] The present application provides a chip instruction verification method, device and storage medium, and aims to solve the problem of low efficiency in adding a time delay between two adjacent commands.

[0006] In a first aspect, a chip instruction verification method is provided. The method is applied to a chip to be tested, and the chip to be tested includes a plurality of chip partitions. Each chip partition includes a plurality of storage partitions. The method includes the following steps: Obtaining a plurality of test commands; Controlling the time delay of the plurality of test commands by using a control model to form a test command sequence. The test command sequence includes a plurality of test commands with a time sequence meeting a preset. Outputting the test command sequence to the chip to be tested.

[0007] In some embodiments, the time delay of the plurality of test commands is controlled by using a control model, including the following steps: Selecting a current command from the plurality of test commands; Performing storage partition time conflict verification on the current command; performing the chip partition time conflict verification on the current instruction; performing the bus position conflict verification on the current instruction.

[0008] In some embodiments, each memory partition comprises a plurality of sub-partitions. performing the memory partition time conflict verification on a current instruction in a plurality of test instructions, comprising: obtaining a first execution object of the current instruction, a second execution object of the current instruction, and an instruction sequence list; the instruction sequence list comprises a plurality of first instructions, a first execution object of each of the first instructions, and a second execution object of each of the first instructions; the first instructions comprise instructions being executed and instructions having been executed; the first execution object is a sub-partition for executing the instruction; and the second execution object is a memory partition for executing the instruction; detecting, based on the instruction sequence list, whether there is a time conflict between the current instruction and the first instructions within the memory partition.

[0009] In some embodiments, the instruction sequence list further comprises a remaining operation duration of each of the first instructions. detecting, based on the instruction sequence list, whether there is a time conflict between the current instruction and the first instructions within the memory partition, comprising: selecting, from the first instructions of the instruction sequence list, second instructions; the first execution object of the second instructions and the first execution object of the current instruction are at least partially the same, and / or the second execution object of the second instructions and the second execution object of the current instruction are the same; detecting whether the remaining operation duration of the second instructions is equal to 0; if the remaining operation duration of all the second instructions is equal to 0, determining that there is no time conflict between the current instruction and the first instructions within the memory partition.

[0010] In some embodiments, after detecting whether the remaining operation duration of the second instructions is equal to 0, the method further comprises: if the remaining operation duration of at least some of the second instructions is not equal to 0, waiting for a preset time interval, and then updating the remaining operation duration of the first instructions; detecting again whether the remaining operation duration of the second instructions is equal to 0; if the remaining operation duration of all the second instructions is equal to 0, determining that there is no time conflict between the current instruction and the first instructions within the memory partition.

[0011] In some embodiments, performing the chip partition time conflict verification on the current instruction, comprising: obtaining a second execution object of the current instruction, a third execution object of the current instruction, and an instruction sequence list; the instruction sequence list comprises a plurality of first instructions, a second execution object of each of the first instructions, and a third execution object of each of the first instructions; the first instructions comprise instructions being executed and instructions having been executed; the second execution object is a storage partition for executing the instruction; and the third execution object is a chip partition for executing the instruction; detecting, based on the instruction sequence list, whether there is a time conflict between the current instruction and the first instruction within the chip partition; detecting, based on the instruction sequence list, whether there is a time conflict between the current instruction and the first instruction between the chip partitions.

[0012] In some embodiments, the instruction sequence list further comprises: a remaining operation duration of each of the first instructions. detecting, based on the instruction sequence list, whether there is a time conflict between the current instruction and the first instruction within the chip partition, comprises: selecting, from the first instructions of the instruction sequence list, third instructions; the second execution object of the third instruction and the second execution object of the current instruction are at least partially the same, and / or the third execution object of the third instruction and the third execution object of the current instruction are the same; detecting whether a remaining operation duration of the third instruction is equal to 0; if the remaining operation durations of all the third instructions are equal to 0, determining that there is no time conflict between the current instruction and the first instruction within the chip partition.

[0013] In some embodiments, after detecting whether the remaining operation duration of the third instruction is equal to 0, the method further comprises: if the remaining operation duration of at least part of the third instructions is not equal to 0, waiting for a preset time interval, and then updating the remaining operation duration of the first instruction; detecting again whether the remaining operation duration of the third instruction is equal to 0; if the remaining operation durations of all the third instructions are equal to 0, determining that there is no time conflict between the current instruction and the first instruction within the chip partition.

[0014] In some embodiments, the instruction sequence list further comprises: a remaining operation duration of each of the first instructions. detecting, based on the instruction sequence list, whether there is a time conflict between the current instruction and the first instruction between the chip partitions, comprises: filtering a fourth instruction from the first instruction in the instruction timing list; the third execution object of the fourth instruction and the third execution object of the current instruction are at least partially same; detecting whether the remaining operation duration of the fourth instruction is equal to 0; if the remaining operation duration of all the fourth instructions is equal to 0, determining that there is no time conflict between the current instruction and the first instruction among the chip partitions.

[0015] In some embodiments, after detecting whether the remaining operation duration of the fourth instruction is equal to 0, the method further comprises: if the remaining operation duration of at least part of the fourth instructions is not equal to 0, waiting for a preset time interval, and then updating the remaining operation duration of the first instruction; detecting again whether the remaining operation duration of the fourth instruction is equal to 0; if the remaining operation duration of all the fourth instructions is equal to 0, determining that there is no time conflict between the current instruction and the first instruction among the chip partitions.

[0016] In some embodiments, the chip to be tested further comprises a bus and a controller, the bus being coupled between the plurality of chip partitions and between the chip partitions and the controller; performing bus location conflict verification on the current instruction, comprising: obtaining preset location information of the current instruction and a location information list; the location information list comprises a plurality of first instructions and first location information of each first instruction; the first instructions comprise instructions being executed and instructions having been executed; the first location information comprises location information of test data generated by the first instruction on the bus; the preset location information comprises location information of test data generated by the current instruction on the bus; based on the location information list, detecting whether the preset location information of the current instruction and the first location information of the first instruction have location conflict.

[0017] In some embodiments, based on the location information list, detecting whether the preset location information of the current instruction and the first location information of the first instruction have location conflict, comprises: obtaining a first execution object of the current instruction, a second execution object of the current instruction, a third execution object of the current instruction, and an instruction timing list; the instruction timing list comprises a plurality of first instructions, a first execution object of each of the first instructions, a second execution object of each of the first instructions, and a third execution object of each of the first instructions; the first execution object is a sub-partition for executing the instruction; the second execution object is a storage partition for executing the instruction; and the third execution object is a chip partition for executing the instruction; screening a second instruction from the first instruction of the position information list; the first execution object of the second instruction is at least partially the same as the first execution object of the current instruction, and / or the second execution object of the second instruction is the same as the second execution object of the current instruction; screening a third instruction from the first instruction of the position information list; the second execution object of the third instruction is at least partially the same as the second execution object of the current instruction, and / or the third execution object of the third instruction is the same as the third execution object of the current instruction; screening a fourth instruction from the first instruction of the position information list; the third execution object of the fourth instruction is at least partially the same as the third execution object of the current instruction; detecting whether the preset position information of the current instruction and the first position information of the second instruction or the third instruction or the fourth instruction have the same region; if not, determining that the preset position information of the current instruction and the first position information of the first instruction do not have a position conflict.

[0018] In some embodiments, after detecting whether the preset position information of the current instruction and the first position information of the second instruction or the third instruction or the fourth instruction have the same region, the method further comprises: if so, waiting for a preset time interval, updating the preset position information of the current instruction, and updating the first position information of the first instruction; detecting again whether the preset position information of the current instruction and the first position information of the second instruction or the third instruction or the fourth instruction have the same region; if not, determining that the preset position information of the current instruction and the first position information of the first instruction do not have a position conflict.

[0019] The second aspect also provides an instruction verification device of a chip, the device being in communication connection with a to-be-tested chip, the to-be-tested chip comprising a plurality of chip partitions, each of the chip partitions comprising a plurality of storage partitions, and the device being configured to perform the steps of the method according to any one of the above embodiments.

[0020] The third aspect also provides a readable storage medium, which stores computer instructions, and the instructions are executed by a processor to implement the steps of the method according to any one of the above embodiments.

[0021] The technical solution of the present application can achieve the following technical effects: based on a chip instruction verification method, a control model can be used to automatically add a time delay between two test instructions to form a test instruction sequence, and the automatic distribution of test instructions is realized, which improves the chip test efficiency; even in the case of a large number of test instructions, the time delay will not be missed, and the precise control of test instructions is realized; it is not necessary to consider the test instruction timing problem in different scenarios, and the tedious delay processing of directional use cases is eliminated, the test instructions are randomly arranged but a time delay is automatically added between adjacent two test instructions, which better plays the role of random use cases and guarantees the test effect.

[0022] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0024] Figure 1 is a schematic diagram of a chip test flow of a chip to be tested; Figure 2 is a flowchart of a chip instruction verification method provided by some embodiments of the present application; Figure 3 is a flowchart of a chip instruction verification method provided by some embodiments of the present application; Figure 4 is a schematic diagram of a chip test flow of a chip to be tested. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0026] In the description of the application, it should be understood that the terms "first", "second" are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0027] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0028] The use of "adapted to" or "configured to" in this application means open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps. In addition, the use of "based on" means open and inclusive because a process, step, calculation or other action that "based on" one or more stated conditions or values can be based on additional conditions or values beyond those stated.

[0029] In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any embodiment described as "exemplary" in this application is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, for the purpose of explanation, details are set forth. It should be appreciated that one of ordinary skill in the art can realize and implement other embodiments without using these specific details. In other instances, well-known structures and processes are not elaborated in order not to obscure the description of the application with unnecessary details. Therefore, the application is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0030] In the related art, Figure 1The chip testing process for the chip under test (DUT) is demonstrated. The DUT includes a phase-change memory chip. TB_TOP provides a verification environment (Env). A large number of test instructions are generated in the instruction generation module, including CMD(1), CMD(2), and CMD(3). The verification environment (Env) is used to complete the test process. In related technologies, a manual delay method is used. A delay Delay1 is added between CMD(1) and CMD(2), and a delay Delay2 is added between CMD(2) and CMD(3). Then, CMD(1) is sent to the interface driver module (Drv). After Delay1, CMD(2) is sent to the interface driver module. After Delay2, CMD(3) is sent to the interface driver module. The interface driver module receives CMD(1) and sends CMD(1) to the DUT. The DUT executes CMD(1) and obtains the actual output result 1. The reference result 1 is obtained through the reference model (Ref). The reference result output by the reference model represents the expected output when the DUT has no defects. The scoring board (Scb) is used to compare the actual output result 1 with the reference result 1 to obtain the test result 1 of the chip under test. The interface driver module receives CMD (2) and sends CMD (2) to the chip under test. The chip under test executes CMD (2) to obtain the actual output result 2, and obtains the reference result 2 through the reference model. The scoring board is used to compare the actual output result 2 with the reference result 2 to obtain the test result 2 of the chip under test. Based on the same principle, the test result 3 can be obtained. Test result 1, test result 2, and test result 3 can reflect the accuracy and stability of the chip under test.

[0031] In the chip testing process described above, a delay is manually added between two adjacent instructions. This method relies on manual operation, is inefficient, and cannot automate instruction issuance.

[0032] To address the inefficiency of manually adding latency, this application proposes a chip instruction verification method, apparatus, and storage medium to overcome the aforementioned problem.

[0033] This application provides an instruction verification method for a chip, the method being applied to a chip under test, the chip under test including a phase-change memory chip. The chip under test includes multiple chip dies, and each chip die includes multiple memory banks, such as... Figure 2 As shown, the chip instruction verification method includes the following steps: S101: Obtain several test commands.

[0034] S102: A control model is used to control the delay of several test instructions to form a test instruction sequence, which includes multiple test instructions whose timing conforms to a preset sequence.

[0035] S103: output the test instruction sequence to the chip to be tested.

[0036] In some embodiments, the control model (also referred to as a command to command controlled model, C2C Model) is based on a UVM (universal verification methodology) platform, and implements automatic issuance and automatic addition of delay of test instructions through transaction level modeling.

[0037] In some embodiments, a delay is automatically added between two adjacent test instructions in the test instruction sequence. The test instructions in the test instruction sequence can be automatically controlled to be issued (output) to the chip to be tested according to the delay.

[0038] Based on the above manner, the control model can automatically add a delay between two test instructions to form a test instruction sequence, and automatically issue the test instructions, thereby improving the chip testing efficiency. Even in the case of a large number of test instruction types, the delay will not be missed, and the test instructions can be accurately controlled. The test instruction timing problem in different scenarios does not have to be considered, and the tedious delay processing of directional use cases is avoided. The test instructions are randomly arranged, but a delay is automatically added between two adjacent test instructions, which better plays the role of random use cases and successfully completes the random verification task.

[0039] In some embodiments, the control model is used to control the delay of a plurality of test instructions, including: S1: selecting a current instruction from a plurality of test instructions; S2: performing storage partition time conflict verification on the current instruction; S3: performing chip partition time conflict verification on the current instruction; S4: performing bus position conflict verification on the current instruction.

[0040] In some embodiments, a test instruction is randomly selected from a plurality of test instructions as a current instruction. Then, storage partition time conflict verification is performed on the current instruction. If the verification is passed, chip partition time conflict verification is performed on the current instruction. If the verification is passed, bus position conflict verification is performed on the current instruction. If the verification is passed, the current instruction is issued to the chip to be tested. The time required for the above three verifications constitutes the delay of the current instruction. Then, another test instruction is randomly selected from the plurality of test instructions as a current instruction, and the above steps are repeated until all test instructions are issued to the chip to be tested. The test instructions issued in sequence form a "test instruction sequence".

[0041] It should be noted that the application does not limit the verification sequence of the "storage partition time conflict verification", the "chip partition time conflict verification", and the "bus position conflict verification". In some embodiments, the storage partition time conflict verification can be performed on the current instruction first. If the verification is passed, the bus position conflict verification is performed on the current instruction. If the verification is passed, the chip partition time conflict verification is performed on the current instruction. If the verification is passed, the current instruction is issued to the chip under test.

[0042] The specific steps of the "storage partition time conflict verification" are described below. The "storage partition time conflict verification" is to verify that there is no time conflict between the current instruction and other instructions within the same storage partition.

[0043] In some embodiments, each storage partition (bank) includes a plurality of sub-partitions (half bank); and each sub-partition includes a plurality of array-arranged storage units.

[0044] The storage partition time conflict verification is performed on the current instruction in the test instructions, and specifically includes: S1: obtaining a first execution object of the current instruction, a second execution object of the current instruction, and an instruction timing list; the instruction timing list includes a plurality of first instructions, a first execution object of each first instruction, and a second execution object of each first instruction; the first instruction includes an executing instruction and an executed instruction; the first execution object is a sub-partition for executing the instruction; and the second execution object is a storage partition for executing the instruction. S2: detecting, based on the instruction timing list, whether there is a time conflict between the current instruction and the first instruction within the storage partition.

[0045] In some embodiments, the execution of each first instruction is recorded in the instruction timing list.

[0046] In some embodiments, the instruction timing list further includes a remaining operation duration of each first instruction. If the remaining operation duration corresponding to the first instruction is not equal to 0, the first instruction is being executed and will be executed in the remaining operation duration. If the remaining operation duration corresponding to the first instruction is equal to 0, the first instruction has been executed.

[0047] For example, if the remaining operation duration corresponding to the first instruction M01 is equal to 5 microseconds, it indicates that the first instruction M01 is being executed and will be executed after 5 microseconds. If the remaining operation duration corresponding to the first instruction M02 is equal to 0, it indicates that the first instruction M02 has been executed.

[0048] In some embodiments, based on the instruction timing list, whether there is a time conflict between the current instruction and the first instruction within the storage partition is detected, and specifically includes: S1: screening the second instruction from the first instruction of the instruction timing list; the first execution object of the second instruction and the first execution object of the current instruction are at least partially the same, and / or the second execution object of the second instruction and the second execution object of the current instruction are the same; S2: detecting whether the remaining operation duration of the second instruction is equal to 0; S3: if the remaining operation duration of all the second instructions is equal to 0, determining that there is no time conflict between the current instruction and the first instruction within the storage partition.

[0049] For example, the first execution object of the second instruction includes half bank01 and half bank02, and the first execution object of the current instruction includes half bank01, half bank02 and half bank03 (half bank01, half bank02 and half bank03 belong to the same storage partition), and it is considered that the first execution object of the second instruction and the first execution object of the current instruction are at least partially the same.

[0050] For example, the first execution object of the second instruction includes half bank01, half bank02 and half bank03, and the first execution object of the current instruction includes half bank01 and half bank02, and it is considered that the first execution object of the second instruction and the first execution object of the current instruction are at least partially the same.

[0051] For example, the second execution object of the second instruction includes bank01, and the second execution object of the current instruction includes bank01, and it is considered that the second execution object of the second instruction and the second execution object of the current instruction are the same.

[0052] If the remaining operation duration of all the second instructions is equal to 0, it indicates that the second instructions belonging to the same storage partition (bank) of the current instruction are all executed, and there is no time conflict between the current instruction and other instructions (the first instruction) within the same storage partition, and the verification is passed.

[0053] In some embodiments, after detecting whether the remaining operation duration of the second instruction is equal to 0, the method further comprises: S1: if the remaining operation duration of at least part of the second instructions is not equal to 0, waiting for a preset time interval, and updating the remaining operation duration of the first instruction; S2: detecting again whether the remaining operation duration of the second instruction is equal to 0; S3: if the remaining operation duration of all the second instructions is equal to 0, determining that there is no time conflict between the current instruction and the first instruction within the storage partition.

[0054] If the remaining operation time length of at least part of the second instructions is not equal to 0, it indicates that the second instructions belonging to the same storage bank as the current instruction are not all executed, and there is a time conflict between the second instructions and the current instruction in the same storage bank. At this time, after waiting for a preset time interval (tCK), the remaining operation time length of the first instruction is updated, and the updated remaining operation time length of the first instruction is reduced by a preset time interval (tCK) compared with the remaining operation time length before the update. The preset time interval (tCK) is a clock cycle.

[0055] The remaining operation time length of the updated second instruction is detected again. If the remaining operation time length of all the second instructions is equal to 0, it is determined that there is no time conflict between the current instruction and the first instruction in the storage bank. If the remaining operation time length of at least part of the second instructions is not equal to 0, after waiting for a preset time interval again, the remaining operation time length of the first instruction is updated until the remaining operation time length of all the second instructions is equal to 0.

[0056] In some embodiments, a state machine is configured for each first instruction, the state machine representing the occupation state (i.e. the remaining operation time length) of the instruction. The state machine runs when the remaining operation time length is not equal to 0, and the state machine stops running when the remaining operation time length is equal to 0. The remaining operation time length can be determined by the design document of the chip under test.

[0057] The specific steps of the "chip bank time conflict verification" are described below. The "chip bank time conflict verification" is to verify that there is no time conflict between the current instruction and other instructions in the same chip bank and between multiple chip banks.

[0058] In some embodiments, the chip bank time conflict verification of the current instruction includes: S1: obtaining a second execution object of the current instruction, a third execution object of the current instruction, and an instruction timing list; the instruction timing list includes a plurality of first instructions, a second execution object of each first instruction, and a third execution object of each first instruction; the first instruction includes an instruction being executed and an instruction executed; the second execution object is a storage bank for executing the instruction; and the third execution object is a chip bank for executing the instruction; S2: detecting whether there is a time conflict between the current instruction and the first instruction in the chip bank based on the instruction timing list; S3: detecting whether there is a time conflict between the current instruction and the first instruction between the chip banks based on the instruction timing list.

[0059] The step S2 is to verify that there is no time conflict between the current instruction and other instructions within the same chip partition. The step S3 is to verify that there is no time conflict between the current instruction and other instructions between different chip partitions.

[0060] In some embodiments, based on the instruction timing list, detecting whether there is a time conflict between the current instruction and the first instruction within the chip partition specifically comprises: S1: filtering third instructions from the first instruction of the instruction timing list; the second execution object of the third instruction and the second execution object of the current instruction are at least partially the same, and / or the third execution object of the third instruction and the third execution object of the current instruction are the same; S2: detecting whether the remaining operation duration of the third instruction is equal to 0; S3: if the remaining operation duration of all the third instructions is equal to 0, determining that there is no time conflict between the current instruction and the first instruction within the chip partition.

[0061] For example, the second execution object of the third instruction includes bank01 and bank02, and the second execution object of the current instruction includes bank01, bank02, and bank03 (bank01, bank02, and bank03 belong to the same chip partition), and it is considered that the second execution object of the third instruction and the second execution object of the current instruction are at least partially the same.

[0062] For example, the second execution object of the third instruction includes bank01, bank02, and bank03, and the second execution object of the current instruction includes bank01 and bank02, and it is considered that the second execution object of the third instruction and the second execution object of the current instruction are at least partially the same.

[0063] For example, the third execution object of the third instruction includes die01, and the third execution object of the current instruction includes die01, and it is considered that the third execution object of the third instruction and the third execution object of the current instruction are the same.

[0064] If the remaining operation duration of all the third instructions is equal to 0, it means that the third instructions belonging to the same chip partition (die) of the current instruction are all executed, and there is no time conflict between the current instruction and other instructions within the same chip partition.

[0065] In some embodiments, after detecting whether the remaining operation duration of the third instruction is equal to 0, the method further comprises: S1: if the remaining operation duration of at least part of the third instructions is not equal to 0, waiting for a preset time interval, and updating the remaining operation duration of the first instruction; S2: detecting whether the remaining operation time length of the third instruction is equal to 0 again; S3: if the remaining operation time length of all the third instructions is equal to 0, determining that there is no time conflict between the current instruction and the first instruction within the chip partition.

[0066] If the remaining operation time length of at least part of the third instructions is not equal to 0, it indicates that the third instructions belonging to the same chip partition (die) as the current instruction are not all executed, and there is a time conflict between the third instructions and the current instruction within the same chip partition. At this time, after waiting for a preset time interval (tCK), the remaining operation time length of the first instruction is updated. The remaining operation time length of the third instruction after the update is detected again. If the remaining operation time length of all the third instructions is equal to 0, it is determined that there is no time conflict between the current instruction and the third instruction within the chip partition. If the remaining operation time length of at least part of the third instructions is not equal to 0, the remaining operation time length of the first instruction is updated again after waiting for a preset time interval until the remaining operation time length of all the third instructions is equal to 0.

[0067] In some embodiments, based on the instruction timing list, whether there is a time conflict between the current instruction and the first instruction between the chip partitions is detected, specifically including: S1: filtering out a fourth instruction from the first instruction of the instruction timing list; the third execution object of the fourth instruction and the third execution object of the current instruction are at least partially the same; S2: detecting whether the remaining operation time length of the fourth instruction is equal to 0; S3: if the remaining operation time length of all the fourth instructions is equal to 0, determining that there is no time conflict between the current instruction and the first instruction between the chip partitions.

[0068] For example, the third execution object of the fourth instruction includes die01 and die02, and the third execution object of the current instruction includes die01, die02 and die03. It is considered that the third execution object of the fourth instruction and the third execution object of the current instruction are at least partially the same.

[0069] For example, the third execution object of the fourth instruction includes die01, die02 and die03, and the third execution object of the current instruction includes die01 and die02. It is considered that the third execution object of the fourth instruction and the third execution object of the current instruction are at least partially the same.

[0070] For example, the third execution object of the fourth instruction includes die01 and die02, and the third execution object of the current instruction includes die01 and die02. It is considered that the third execution object of the fourth instruction and the third execution object of the current instruction are at least partially the same.

[0071] If the remaining operation time length of all fourth instructions equals to 0, it indicates that the fourth instructions having the common chip partition with the current instruction are all executed, and there is no time conflict between the current instruction and other instructions in different chip partitions.

[0072] In some embodiments, after detecting whether the remaining operation time length of the fourth instruction equals to 0, the method further comprises: S1: If the remaining operation time length of at least part of the fourth instruction does not equal to 0, waiting for a preset time interval, updating the remaining operation time length of the first instruction; S2: Detecting again whether the remaining operation time length of the fourth instruction equals to 0; S3: If the remaining operation time length of all fourth instructions equals to 0, determining that there is no time conflict between the current instruction and the first instruction in different chip partitions.

[0073] If the remaining operation time length of at least part of the fourth instruction does not equal to 0, it indicates that the fourth instructions having the common chip partition with the current instruction are not all executed, and there is a time conflict between the fourth instruction and the current instruction in different chip partitions, at this time, waiting for a preset time interval (tCK), updating the remaining operation time length of the first instruction. Detecting again whether the remaining operation time length of the fourth instruction after updating equals to 0; if the remaining operation time length of all fourth instructions equals to 0, determining that there is no time conflict between the current instruction and the fourth instruction in different chip partitions. If the remaining operation time length of at least part of the fourth instruction does not equal to 0, waiting for a preset time interval again, updating the remaining operation time length of the first instruction, until the remaining operation time length of all fourth instructions equals to 0.

[0074] In the case that there is no time conflict between the current instruction and the first instruction in the chip partition, and there is no time conflict between the current instruction and the first instruction in different chip partitions, the detection passes.

[0075] The specific steps of the "bus position conflict verification" are described below. The "bus position conflict verification" is to verify whether the test data generated by the current instruction and the test data generated by other instructions exist position conflict on the bus in different levels (inside the same memory partition, inside the same chip partition, between different chip partitions).

[0076] In some embodiments, the chip to be tested further comprises a bus and a controller, the bus is coupled between the plurality of chip partitions, and is further coupled between the chip partition and the controller; the bus comprises an IO (Input / Output) bus, i.e., an input / output bus.

[0077] When the first instruction is executed, test data of the first instruction is generated. The test data of the first instruction needs a certain time to be transmitted on the bus. The execution of the first instruction is not equal to the transmission of the test data. Therefore, it is necessary to detect whether the test data generated by the current instruction and the test data generated by other instructions have a location conflict on the bus.

[0078] In some embodiments, the bus location conflict verification is performed on the current instruction, and specifically includes: S1: obtaining preset location information of the current instruction and a location information list; the location information list includes a plurality of first instructions, and first location information of each first instruction; the first instruction includes an executing instruction and an executed instruction; the first location information includes location information of test data generated by the first instruction on the bus; the preset location information includes location information of test data generated by the current instruction on the bus; S2: based on the location information list, detecting whether the preset location information of the current instruction and the first location information of the first instruction have a location conflict.

[0079] In some embodiments, based on the location information list, detecting whether the preset location information of the current instruction and the first location information of the first instruction have a location conflict, specifically includes: S1: obtaining a first execution object of the current instruction, a second execution object of the current instruction, a third execution object of the current instruction, and an instruction timing list; the instruction timing list includes a plurality of first instructions, a first execution object of each first instruction, a second execution object of each first instruction, and a third execution object of each first instruction; the first execution object is a sub-partition for executing the instruction; the second execution object is a storage partition for executing the instruction; and the third execution object is a chip partition for executing the instruction; S2: filtering out a second instruction from the first instructions in the location information list; the first execution object of the second instruction and the first execution object of the current instruction are at least partially the same, and / or the second execution object of the second instruction and the second execution object of the current instruction are the same; S3: filtering out a third instruction from the first instructions in the location information list; the second execution object of the third instruction and the second execution object of the current instruction are at least partially the same, and / or the third execution object of the third instruction and the third execution object of the current instruction are the same; S4: filtering out a fourth instruction from the first instructions in the location information list; the third execution object of the fourth instruction and the third execution object of the current instruction are at least partially the same; S5: detecting whether the preset location information of the current instruction and the first location information of the second instruction or the third instruction or the fourth instruction have the same region; S6: If not, it is determined that the preset position information of the current instruction and the first position information of the first instruction do not have position conflict.

[0080] Specifically, the second instruction, the third instruction and the fourth instruction at the same level as the current instruction are screened out, and it is detected whether the preset position information of the current instruction and the first position information of the second instruction or the third instruction or the fourth instruction have the same region. If the preset position information of the current instruction and the first position information of any one of the second instruction, the third instruction and the fourth instruction have position overlap, that is, have the same region on the bus, it is determined that the preset position information of the current instruction and the first position information of the first instruction have position conflict, and the detection is failed. If the preset position information of the current instruction and the first position information of any one of the second instruction, the third instruction and the fourth instruction do not have position overlap, that is, do not have the same region on the bus, it is determined that the preset position information of the current instruction and the first position information of the first instruction do not have position conflict, and the detection is passed.

[0081] In some embodiments, after detecting whether the preset position information of the current instruction and the first position information of the second instruction or the third instruction or the fourth instruction have the same region, the method further comprises: S1: If yes, after waiting for a preset time interval, the preset position information of the current instruction is updated, and the first position information of the first instruction is updated; S2: The preset position information of the current instruction and the first position information of the second instruction or the third instruction or the fourth instruction are detected again whether they have the same region; S3: If not, it is determined that the preset position information of the current instruction and the first position information of the first instruction do not have position conflict.

[0082] If the preset position information of the current instruction and the first position information of any one of the second instruction, the third instruction and the fourth instruction have position overlap, that is, have the same region on the bus, after waiting for a preset time interval (tCK), the preset position information of the current instruction is updated, and the first position information of the first instruction is updated; the preset position information of the current instruction and the first position information of the second instruction or the third instruction or the fourth instruction are detected again whether they have the same region until they do not have the same region.

[0083] In the case that the above three detections are all passed, all the preset time intervals (tCK) passed are accumulated and summed up, and the result of the accumulation and summation is the delay (delay) of the current instruction.

[0084] In the case that the above three detections are all passed, the current instruction is sent to the chip to be tested.

[0085] Based on the above embodiments, whether there is a conflict is detected within the storage partition, within the chip partition, between the chip partitions, and on the bus, improving the comprehensiveness of the detection and the accuracy of the calculation delay.

[0086] In some embodiments, referring to Figure 3 As shown in the figure, after obtaining the current instruction, the storage partition time conflict verification is performed on the current instruction to detect whether there is a time conflict within the same storage partition. If yes, the instruction timing list is updated after waiting for a preset time interval, and the detection is performed again. If no, the chip partition time conflict verification is performed on the current instruction to detect whether there is a time conflict within the same chip partition. If yes, the instruction timing list is updated after waiting for a preset time interval, and the detection is performed again. If no, whether there is a time conflict between different chip partitions is detected. If yes, the instruction timing list is updated after waiting for a preset time interval, and the detection is performed again. If no, the bus position conflict verification is performed on the current instruction to detect whether the preset position information of the current instruction and the first position information of the first instruction have a position conflict. If yes, the position information list is updated after waiting for a preset time interval, and the detection is performed again. If no, the current instruction is sent to the chip under test. The preset time intervals are summed to obtain the delay of the current instruction.

[0087] In some embodiments, referring to Figure 4As shown, a large number of test instructions are generated in the instruction generation module, including CMD(1), CMD(2), CMD(3), …, CMD(n), CMD(n+1), and these test instructions are randomized (Random). The verification environment (Env) is used to complete the test process. The instruction generation module takes CMD(1) as the current instruction, and sends CMD(1) to the interface driver module (Drv). The control model (C2C Model) is arranged in the interface driver module. The control model is used to perform the following steps: storage partition time conflict verification on the current instruction; chip partition time conflict verification on the current instruction; bus position conflict verification on the current instruction; if all verifications pass, the delay delay1 corresponding to CMD(1) is obtained, and CMD(1) is sent to the chip under test. And the time elapsed from receiving CMD(1) from the control model to sending CMD(1) is equal to delay1. Similarly, take CMD(2) as the current instruction, and send CMD(2) to the interface driver module (Drv). The control model performs three verifications, and if all verifications pass, the delay delay2 corresponding to CMD(2) is obtained, and CMD(2) is sent to the chip under test. The chip under test executes CMD(1) to obtain the actual output result 1, and the reference result 1 is obtained through the reference model (Ref). The reference result output by the reference model represents the expected output in the case that the chip under test has no defects. The score board (Scb) is used to compare the actual output result 1 and the reference result 1 to obtain the test result 1 of the chip under test. The chip under test executes CMD(2) to obtain the actual output result 2, and the reference result 2 is obtained through the reference model. The score board is used to compare the actual output result 2 and the reference result 2 to obtain the test result 2 of the chip under test. The test result 1 and the test result 2 can reflect the accuracy and stability of the chip under test.

[0088] Through the above embodiment, the blocking port (uvm_blocking_put_port) is instantiated in the interface driver module to realize blocking communication, and the control model is derived from the UVM component. During the blocking of the control model (at least once the verification fails), the interface driver module will not send the test instruction to the chip under test until the control model completes the blocking (all three verifications pass). For the chip under test, the test instruction it receives meets all the timing conditions.

[0089] Among them, the three verifications refer to: storage partition time conflict verification, chip partition time conflict verification, bus position conflict verification; the chip partition time conflict verification includes: whether there is a time conflict between the current instruction and the first instruction within the chip partition, whether there is a time conflict between the current instruction and the first instruction between the chip partitions.

[0090] Based on the above embodiments, the interface driving module can maximize the full-bandwidth instruction sending, guarantee the completeness of verification and testing and meet the automation requirements, reduce the development difficulty and improve the work efficiency; and the control model reusability is improved, the redundant code is reduced, the portability is strong and the later maintenance is facilitated.

[0091] In some embodiments, based on the chip instruction verification method provided in the present application, a large number of test instructions can be issued in a short time, and the sending success rate reaches 100%, guaranteeing the completeness and accuracy of Full-Chip Level (full-chip level) regression verification, reducing the construction difficulty of test cases, realizing the automation process of instruction distribution, greatly improving the work efficiency, reducing the labor cost, and having certain guiding significance for the operation time of read and write instructions in different application scenarios in the chip specification book.

[0092] The chip instruction verification device provided in the embodiments of the present application, the chip instruction verification device and the chip under test are in communication connection, the chip under test includes a plurality of chip partitions, each chip partition includes a plurality of storage partitions, and the device is configured to perform the steps of the chip instruction verification method according to any one of the above embodiments.

[0093] The embodiments of the present application provide a storage medium having computer instructions stored thereon, and the instructions are executed by a processor to implement the steps of the chip instruction verification method according to any one of the above embodiments.

[0094] In the embodiments of the present application, the storage medium can be a magnetic disk, an optical disk, a read only memory (ROM), or a random access memory (RAM), etc.

[0095] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0096] The above describes in detail the chip instruction verification method, device and storage medium provided in the embodiments of the present application, and the specific examples are applied to explain the principles and implementation modes of the present application; the above embodiment descriptions are only used to help understand the method and its core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range can be changed, and the above description should not be understood as limiting the present application.

Claims

1. A method for verifying instructions of a chip, the method being applied to a chip under test, the chip under test comprising multiple chip partitions, each chip partition comprising multiple memory partitions, characterized in that, include: Obtain several test commands; A control model is used to control the delay of several test commands to form a test command sequence, which includes multiple test commands whose timing conforms to a preset sequence. The test instruction sequence is output to the chip under test.

2. The method according to claim 1, characterized in that, A control model is used to control the delay of several test commands, including: Select the current instruction from a list of test instructions; Perform the storage partition time conflict verification on the current instruction; Perform chip partition time conflict verification on the current instruction; Perform bus position conflict verification on the current instruction.

3. The method according to claim 2, characterized in that, Each storage partition includes multiple sub-partitions; The storage partition time conflict verification is performed on the current instruction among several test instructions, including: Obtain the first execution object of the current instruction, the second execution object of the current instruction, and the instruction timing list; the instruction timing list includes multiple first instructions, a first execution object for each first instruction, and a second execution object for each first instruction; the first instructions include instructions in execution and instructions that have been completed; the first execution object is a sub-partition used to execute the instruction; the second execution object is a storage partition used to execute the instruction; Based on the instruction timing table, detect whether there is a time conflict between the current instruction and the first instruction within the storage partition.

4. The method according to claim 3, characterized in that, The instruction timing list also includes: the remaining operation time for each of the first instructions; Based on the instruction timing table, detecting whether there is a time conflict between the current instruction and the first instruction within the storage partition includes: A second instruction is selected from the first instruction in the instruction sequence list; the first execution object of the second instruction is at least partially the same as the first execution object of the current instruction, and / or the second execution object of the second instruction is the same as the second execution object of the current instruction; Check if the remaining operation time of the second instruction is equal to 0; If the remaining operation time of all second instructions is equal to 0, it is determined that there is no time conflict between the current instruction and the first instruction within the storage partition.

5. The method according to claim 4, characterized in that, After detecting whether the remaining operation time of the second instruction is equal to 0, the method further includes: If the remaining operation time of at least some of the second instructions is not equal to 0, wait for a preset time interval and then update the remaining operation time of the first instruction. Check again whether the remaining operation time of the second instruction is equal to 0; If the remaining operation time of all second instructions is equal to 0, it is determined that there is no time conflict between the current instruction and the first instruction within the storage partition.

6. The method according to claim 2, characterized in that, Perform chip partition time conflict verification on the current instruction, including: The system obtains a second execution object of the current instruction, a third execution object of the current instruction, and an instruction timing table; the instruction timing table includes a plurality of first instructions, a second execution object for each first instruction, and a third execution object for each first instruction; the first instructions include instructions in execution and instructions that have been completed; the second execution object is a storage partition used to execute the instruction; the third execution object is a chip partition used to execute the instruction; Based on the instruction timing table, detect whether there is a time conflict between the current instruction and the first instruction within the chip partition; Based on the instruction timing table, detect whether there is a time conflict between the current instruction and the first instruction between the chip partitions.

7. The method according to claim 6, characterized in that, The instruction timing list also includes: the remaining operation time for each of the first instructions; Based on the instruction timing table, detecting whether there is a time conflict between the current instruction and the first instruction within the chip partition includes: A third instruction is selected from the first instruction in the instruction sequence list; the second execution object of the third instruction is at least partially the same as the second execution object of the current instruction, and / or the third execution object of the third instruction is the same as the third execution object of the current instruction; Check whether the remaining operation time of the third instruction is equal to 0; If the remaining operation time of all third instructions is equal to 0, it is determined that there is no time conflict between the current instruction and the first instruction within the chip partition.

8. The method according to claim 7, characterized in that, After detecting whether the remaining operation time of the third instruction is equal to 0, the method further includes: If the remaining operation time of at least some of the third instructions is not equal to 0, wait for a preset time interval and then update the remaining operation time of the first instruction. Check again whether the remaining operation time of the third instruction is equal to 0; If the remaining operation time of all third instructions is equal to 0, it is determined that there is no time conflict between the current instruction and the first instruction within the chip partition.

9. The method according to claim 6, characterized in that, The instruction timing list also includes: the remaining operation time for each of the first instructions; Based on the instruction timing table, detecting whether there is a time conflict between the current instruction and the first instruction between the chip partitions includes: A fourth instruction is selected from the first instruction in the instruction sequence list; the third execution target of the fourth instruction is at least partially the same as the third execution target of the current instruction. Check whether the remaining operation time of the fourth instruction is equal to 0; If the remaining operation time of all fourth instructions is equal to 0, it is determined that there is no time conflict between the current instruction and the first instruction between the chip partitions.

10. The method according to claim 9, characterized in that, After detecting whether the remaining operation time of the fourth instruction is equal to 0, the method further includes: If the remaining operation time of at least some of the fourth instructions is not equal to 0, wait for a preset time interval and then update the remaining operation time of the first instruction. Check again whether the remaining operation time of the fourth instruction is equal to 0; If the remaining operation time of all fourth instructions is equal to 0, it is determined that there is no time conflict between the current instruction and the first instruction between the chip partitions.

11. The method according to claim 2, characterized in that, The chip under test also includes a bus and a controller. The bus is coupled between multiple chip partitions and also coupled between the chip partitions and the controller. Perform bus position conflict verification on the current instruction, including: Obtain the preset position information and position information list of the current instruction; the position information list includes multiple first instructions and first position information of each first instruction; the first instructions include instructions in execution and instructions that have been completed; the first position information includes the position information of the test data generated by the first instruction on the bus; the preset position information includes the position information of the test data generated by the current instruction on the bus; Based on the location information list, it is detected whether there is a location conflict between the preset location information of the current instruction and the first location information of the first instruction.

12. The method according to claim 11, characterized in that, Based on the location information list, detecting whether there is a location conflict between the preset location information of the current instruction and the first location information of the first instruction includes: The method obtains a first execution object, a second execution object, a third execution object, and an instruction timing table for the current instruction; the instruction timing table includes multiple first instructions, a first execution object for each first instruction, a second execution object for each first instruction, and a third execution object for each first instruction; the first execution object is a sub-partition used to execute the instruction; the second execution object is a storage partition used to execute the instruction; and the third execution object is a chip partition used to execute the instruction. A second instruction is selected from the first instruction in the location information list; the first execution object of the second instruction is at least partially the same as the first execution object of the current instruction, and / or the second execution object of the second instruction is the same as the second execution object of the current instruction; A third instruction is selected from the first instruction in the location information list; the second execution object of the third instruction is at least partially the same as the second execution object of the current instruction, and / or the third execution object of the third instruction is the same as the third execution object of the current instruction; A fourth instruction is selected from the first instruction in the location information list; the third execution object of the fourth instruction is at least partially the same as the third execution object of the current instruction. Detect whether the preset position information of the current instruction and the first position information of the second instruction, the third instruction, or the fourth instruction have the same area; If not, it is determined that the preset position information of the current instruction and the first position information of the first instruction do not conflict in position.

13. The method according to claim 12, characterized in that, After detecting whether the preset position information of the current instruction and the first position information of the second instruction, the third instruction, or the fourth instruction have the same region, the method further includes: If present, after waiting for a preset time interval, update the preset position information of the current instruction and update the first position information of the first instruction; The preset position information of the current instruction and the first position information of the second instruction, the third instruction, or the fourth instruction are checked again to see if they have the same area; If not, it is determined that the preset position information of the current instruction and the first position information of the first instruction do not conflict in position.

14. A chip instruction verification apparatus, the apparatus being communicatively connected to a chip under test, the chip under test comprising multiple chip partitions, each chip partition comprising multiple memory partitions, characterized in that, The apparatus is configured to perform the steps of the method as described in any one of claims 1 to 13.

15. A storage medium, characterized in that, It stores computer instructions that, when executed by a processor, implement the steps of the method according to any one of claims 1 to 13.

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