Digital time converter circuit based on self-pinch-off switched capacitor unit

Abstract

The invention belongs to the field of digital-analog hybrid circuits, and particularly provides a digital to time converter (DTC) circuit with high linearity and low noise, which is used for overcoming the rigidity compromise between the linearity and the thermal noise of a traditional resistor-capacitor charging and discharging type DTC and realizing the combination of high linearity and low noise. The invention provides a capacitor unit based on a self-pinch-off switch. The capacitor unit can show capacitive performance at the initial stage of capacitor discharging so as to provide DTC delay. In the end stage of capacitor discharge, the output inverter is resistive, so that the linearity of the output inverter is improved, and the noise is reduced. Compared with a traditional structure, the linear degree can be improved by more than six times, and noise can be reduced by 1.4 dB.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of digital-analog hybrid circuits, and specifically provides a digital time converter (DTC) circuit with high linearity and low noise. BACKGROUND

[0002] In the 5.5G era, wireless and optical communication have unprecedentedly stringent requirements for the noise index of the clock, and a low-noise fractional phase-locked loop is a prerequisite for all applications. It has been recognized in the industry that an architecture with a digital time converter (DTC) as the core is a promising technical path to achieve an ultra-low noise and ultra-low spurious fractional loop. However, the thermal noise of the DTC determines the in-band noise floor, and its nonlinearity generates fractional spurs; the traditional resistance-capacitance charging and discharging type DTC is rigidly compromised between linearity and thermal noise - the higher the linearity, the greater the thermal noise. This trade-off makes the engineering design of a high-linearity and low-noise DTC a difficult problem. SUMMARY

[0003] In order to alleviate the problem that the traditional structure DTC is difficult to balance low noise and high linearity, the application proposes a digital time converter circuit using a self-clamping switch capacitor, which provides a larger and stable discharge slope at the input flip threshold point of the output inverter by introducing a self-clamping switch, thereby achieving the effect of improving linearity and reducing the noise of the output inverter. In order to achieve the above purpose, the technical scheme adopted by the application is as follows.

[0004] A DTC circuit with high linearity and low noise, characterized in that a self-clamping switch is added in the capacitor unit. The self-clamping switch can provide a smaller on-resistance in the initial stage of capacitor discharge, so that the DTC has the ability to provide a larger time delay. At the same time, the self-clamping switch can provide a larger off-state resistance at the end of capacitor discharge, isolating the capacitor and the input node of the output inverter, thereby providing a relatively constant and high real impedance at the input node of the output inverter when the number of capacitors connected to the DTC is different, thereby realizing the linearization of the output inverter and reducing its noise. Since the noise and nonlinearity of the output inverter play a dominant role in the DTC, reducing the noise and improving the linearity of the output inverter helps to achieve low noise and high linearity of the DTC as a whole. BRIEF DESCRIPTION OF DRAWINGS

[0005] In order to make the technical solutions of the present application clearer, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings.

[0006] Figure 1 The DTC principle diagram with the self-clamping switch capacitor unit in the present application.

[0007] Figure 2 The principle diagram of the self-clamping switch capacitor unit in the present application.

[0008] Figure 3 The linearity comparison between the DTC based on the self-clamping switch capacitor unit and the traditional DTC in the present application.

[0009] Figure 4 The phase noise comparison between the DTC based on the self-clamping switch capacitor unit and the traditional DTC in the present application. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical solutions and technical effects of the present application clearer and more complete, the following will further describe the present application in combination with the drawings and embodiments.

[0011] The present embodiment provides a digital time converter circuit based on the self-clamping switch capacitor unit, as shown in FIG. 1. It is composed of a charge-discharge circuit, a capacitor array composed of several self-clamping switch capacitor units and an output inverter. Figure 1 Each self-clamping switch capacitor unit has a control terminal, which controls whether the switch capacitor is connected to the DTC or not. When connected, the discharge capacitor becomes larger, and the delay of the DTC becomes higher. On the contrary, when not connected, the discharge capacitor becomes smaller, and the delay of the DTC becomes smaller.

[0012] Figure 2 The left half of FIG. 2 shows the principle diagram of the self-clamping switch capacitor unit, in which C1 is a capacitor, which can be composed of a linear capacitor or a nonlinear capacitor. M5 is a self-clamping switch based on a P-channel transistor, which controls whether C1 is connected to the discharge end of the capacitor unit or not. The equivalent resistance and equivalent capacitance of the self-clamping switch capacitor unit under different discharge end biases. When the bias is large, M5 is turned on, its resistance is low, and C1 is completely connected to the DTC. When the bias is small, the top plate voltage of C1 becomes low, M5 is turned off, and at this time M5 isolates C1 from the DTC, so that the capacitor unit behaves as a resistor at this time.

[0013] Figure 3The linearity comparison between the DTC based on the self-clamp switched-capacitor unit and the traditional DTC is shown.Under the same constraints of delay coverage and power consumption, the maximum nonlinearity of the traditional DTC is 2.8ps, while the average maximum nonlinearity of the DTC based on the self-clamp switched-capacitor unit is 754fs and the standard deviation is 94fs in the gate-level Monte Carlo simulation.The inventors also verify the application by tape-out, and the DTC proposed in the application achieves a maximum nonlinearity of 441fs, which is more than six times the improvement in linearity compared with the traditional DTC.

[0014] Figure 4 The noise comparison between the DTC based on the self-clamp switched-capacitor unit and the traditional DTC is shown.Under the same constraints of delay coverage and power consumption, the DTC proposed in the application achieves a noise reduction of 1.4dB compared with the traditional DTC.

Claims

1. A DTC circuit with high linearity and low noise, comprising a charging and discharging circuit, a capacitor array composed of several self-pinch-off switching capacitor units, and an output inverter.

2. The high linearity, low noise DTC circuit according to claim 1, characterized in that... A self-pinch-off switch is incorporated into the capacitor cell. This switch is a PMOS transistor connected to the capacitor's top plate and the DTC charging / discharging node. When the DTC discharges from a high voltage to a low voltage and the self-pinch-off switch opens, it initially exhibits low on-resistance, effectively connecting the capacitor in parallel to the discharge node for a delay effect. At the end of the discharge, the self-pinch-off switch exhibits high resistance, isolating the capacitor from the discharge node and making the capacitor cell resistive. This provides a higher real impedance to the output inverter at the moment of output inverter flip-up, improving its linearity and reducing noise.

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