Transistor and preparation method thereof

Abstract

The invention provides a transistor and a preparation method thereof. The transistor comprises a channel layer, a first barrier layer, a second barrier layer and an electrode structure, the first barrier layer is located on the channel layer, the first barrier layer is provided with a plurality of grooves, the bottoms of the grooves are located in the channel layer, and the side walls and the bottoms of the grooves are of magnesium ion injection structures; the second barrier layer is located at the bottoms of the grooves, the electrode structures are located in the grooves, and the electrode structures are connected with the second barrier layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a transistor and a method for fabricating the same. Background Technology

[0002] Gallium nitride on silicon is widely used in the semiconductor field, such as in transistors.

[0003] The related technology provides a transistor structure including a channel layer, a barrier layer, and an electrode structure. The channel layer is located on the barrier layer, and both the channel layer and the barrier layer have grooves. The electrode structure passes through the grooves and is connected to the channel layer.

[0004] In related technologies, the ohmic contact resistance between the electrode structure and the channel layer is relatively large. In high-frequency applications, the large ohmic contact resistance can lead to severe overheating of the transistor and low transistor reliability. Summary of the Invention

[0005] This disclosure provides a transistor and its fabrication method, which can significantly reduce the resistance between the electrode structure and the channel layer, thereby improving the reliability of the transistor. The technical solution is as follows:

[0006] On one hand, a transistor is provided, the transistor comprising: a channel layer, a first barrier layer, a second barrier layer, and an electrode structure;

[0007] The first barrier layer is located on the channel layer, and the first barrier layer has a plurality of grooves with the bottom located on the channel layer. The sidewalls and bottom of the grooves are magnesium ion implantation structures.

[0008] The second barrier layer is located at the bottom of the plurality of grooves, the electrode structure is located within the grooves, and the electrode structure is connected to the second barrier layer.

[0009] Optionally, the groove is a cylindrical groove with a diameter R of 50 nm and a depth H of 80 nm.

[0010] Optionally, the plurality of grooves are arranged in rows and columns, and the spacing L between the grooves in adjacent columns is 95 to 105 nm.

[0011] Optionally, along the direction from the first barrier layer to the channel layer, the energy gradient of magnesium ion implantation in the magnesium ion implantation structure increases, while the dose gradient of magnesium ion implantation decreases.

[0012] Optionally, the top surface of the second barrier layer is not higher than the top surface of the channel layer, and the second barrier layer is an N-type heavily doped In. 0.1 Ga 0.9 N layers.

[0013] Optionally, the electrode structure is Scx Ti y A stack consisting of an Al layer, a Ni layer, and an Au layer, wherein x and y are greater than 0;

[0014] The Sc x Ti y The thickness of the layer is 15-25 nm, the thickness of the Al layer is 145-155 nm, the thickness of the Ni layer is 35-45 nm, and the thickness of the Au layer is 55-65 nm.

[0015] On the other hand, a method for fabricating a transistor is provided, the method comprising:

[0016] Create the channel layer;

[0017] A first barrier layer is fabricated on the channel layer;

[0018] Magnesium ion implantation is performed on multiple magnesium ion implantation regions on the surface of the first barrier layer, wherein the depth of magnesium ion implantation is greater than the thickness of the first barrier layer.

[0019] The plurality of magnesium ion implantation regions are patterned, and a plurality of grooves with their bottoms located in the channel layer are formed, wherein the sidewalls of the grooves are magnesium ion implantation structures.

[0020] A second barrier layer is fabricated, the second barrier layer being located at the bottom of the plurality of grooves;

[0021] An electrode structure is fabricated, the electrode structure is located within the groove, and the electrode structure is connected to the second barrier layer.

[0022] Optionally, magnesium ion implantation is performed on multiple magnesium ion implantation regions on the surface of the first barrier layer, including:

[0023] Along the direction from the first barrier layer to the channel layer, the energy gradient of magnesium ion implantation is controlled to increase during the magnesium ion implantation process, and the dose gradient of magnesium ion implantation is controlled to decrease during the magnesium ion implantation process.

[0024] Optionally, along the direction from the first barrier layer to the channel layer, the magnesium ion implantation energy is controlled to increase in a gradient of 30 keV, 50 keV, and 80 keV during the magnesium ion implantation process, and the magnesium ion implantation dose is controlled to be 5 × 10⁻⁶. 13 cm -2 3×10 13 cm -2 1×10 13 cm -2 Gradient decrease.

[0025] Optionally, the fabrication of the electrode structure includes:

[0026] Under conditions of 445–455℃ and 3–7 MPa vacuum pressure, vacuum pulsed magnetic field technology was used to sc x Ti y The Al, Ni, and Au layers undergo transient liquid-phase bonding for 45–55 ms to form an electrode structure, where x and y are greater than 0.

[0027] The beneficial effects of the technical solutions provided in this disclosure are:

[0028] In this embodiment, the first barrier layer has multiple grooves with their bottoms located in the channel layer. The sidewalls and bottoms of the grooves are magnesium ion implantation structures, which can precisely control the Schottky barrier height between the channel layer and the first barrier layer, thereby reducing the contact resistance between the electrode structure and the channel layer. The second barrier layer is located at the bottom of the multiple grooves and is connected to the channel layer. This can reduce the energy difference between the second barrier layer and the conduction-band edge of the channel layer, reduce the barrier height of the channel layer, and further reduce the contact resistance between the electrode structure and the channel layer. In summary, the transistor provided in this embodiment can reduce the barrier height between the electrode structure and the channel layer, thereby reducing the resistance between the electrode structure and the channel layer, reducing transistor heat generation, and improving transistor yield. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the structure of a transistor provided in an embodiment of this disclosure;

[0031] Figure 2 This is a top view schematic diagram of a transistor structure provided in an embodiment of this disclosure;

[0032] Figure 3 This is a flowchart of a transistor fabrication method provided in an embodiment of this disclosure;

[0033] Figure 4 This is a flowchart of another transistor fabrication method provided in this disclosure embodiment;

[0034] Figure 5 This is a schematic diagram of a transistor fabrication process provided in an embodiment of the present disclosure;

[0035] Figure 6This is a schematic diagram of a transistor fabrication process provided in an embodiment of the present disclosure;

[0036] Figure 7 This is a schematic diagram of a transistor fabrication process provided in an embodiment of the present disclosure;

[0037] Figure 8 This is a schematic diagram of a transistor fabrication process provided in an embodiment of the present disclosure;

[0038] Figure 9 This is a schematic diagram of a transistor manufacturing process provided in an embodiment of this disclosure.

[0039] The attached figures are labeled as follows:

[0040] 100: Substrate; 101: Channel layer; 102: First barrier layer; 103: Second barrier layer; 104: Buffer layer; 105: Cap layer;

[0041] 20: Electrode structure;

[0042] 301: Photoresist mask layer; 302: Magnesium ion implantation structure;

[0043] 1001: Groove;

[0044] L: Spacing between the grooves of two adjacent columns; H: Depth of the groove; R: Diameter of the groove. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0046] Figure 1 This is a schematic diagram of a transistor structure provided in an embodiment of this disclosure. See also... Figure 1 The transistor includes a channel layer 101, a first barrier layer 102, a second barrier layer 103, and an electrode structure 20.

[0047] The first barrier layer 102 is located on the channel layer 101. The first barrier layer 102 has a plurality of grooves 1001 with the bottom located on the channel layer 101. The sidewalls and bottom of the grooves 1001 are magnesium ion implantation structures 302.

[0048] The second barrier layer 103 is located at the bottom of the plurality of grooves 1001, and the electrode structure 20 is located inside the grooves 1001 and is connected to the second barrier layer 103.

[0049] In this embodiment, the first barrier layer has multiple grooves with their bottoms located in the channel layer. The sidewalls and bottoms of the grooves are magnesium ion implantation structures, which can precisely control the Schottky barrier height between the channel layer and the first barrier layer, thereby reducing the contact resistance between the electrode structure and the channel layer. The second barrier layer is located at the bottom of the multiple grooves and is connected to the channel layer. This can reduce the energy difference between the second barrier layer and the conduction band edge of the channel layer, reduce the barrier height of the channel layer, and further reduce the contact resistance between the electrode structure and the channel layer. In summary, using the transistor provided in this embodiment can reduce the barrier height between the electrode structure and the channel layer, thereby reducing the resistance between the electrode structure and the channel layer, reducing transistor heat generation, and improving transistor yield.

[0050] In this embodiment of the disclosure, the groove 1001 can be a cylindrical groove.

[0051] In this embodiment of the disclosure, the ratio of the diameter R of the groove 1001 to the depth H of the groove 1001 is 0.6 to 0.8; the ratio of the spacing L of the grooves 1001 to the diameter R of the grooves 1001 is 1.5 to 2.0.

[0052] The diameter R of the groove 1001 can be 45-55 nm, and the depth H of the groove 1001 can be 75-85 nm.

[0053] In this implementation, the groove is a cylindrical groove, which can make the current diffusion more uniform; the diameter of the groove is 45-55nm and the depth of the groove is 75-85nm. The electrode structure is connected to the second barrier layer through the groove, which can reduce the energy difference between the second barrier layer and the edge of the channel layer conduction band, reduce the barrier height of the channel layer, and further reduce the contact resistance between the electrode structure and the channel layer. It also prevents the size from being too large, which would cause the magnesium ion gradient ion implantation part to be completely etched.

[0054] For example, the diameter R of the groove 1001 is 50 nm and the depth H of the groove 1001 is 80 nm.

[0055] In other embodiments, the groove 1001 may also be of other shapes, such as a prismatic groove.

[0056] Figure 2 This is a top view schematic diagram of a transistor according to an embodiment of this disclosure. See also... Figure 2 Multiple grooves 1001 are arranged in rows and columns, and the spacing L between two adjacent columns of grooves 1001 can be 95 to 105 nm.

[0057] In this implementation, multiple grooves are arranged in rows and columns, and the distance L between two adjacent grooves is 95 to 105 nm. This ensures that there is sufficient distance between the grooves to maintain the thermal stability of the transistor, and also makes the current distribution uniform, so as to achieve a low-resistance and high-reliability ohmic contact between the electrode structure and the barrier layer.

[0058] For example, the spacing L of the grooves 1001 between two adjacent columns is 95 to 105 nm.

[0059] In this embodiment of the disclosure, the light-emitting diode includes two rows of grooves 1001, each row of grooves 1001 including a plurality of grooves 1001; the electrode structure 20 includes two electrodes, each electrode being connected to one of the rows of grooves 1001 respectively.

[0060] In this embodiment of the present disclosure, along the direction from the first barrier layer 102 to the channel layer 101, the energy gradient of magnesium ion implantation in the magnesium ion implantation structure 302 increases and the dose gradient of magnesium ion implantation decreases.

[0061] In this implementation, the energy gradient of magnesium ion implantation in the magnesium ion implantation structure increases along the direction from the first barrier layer to the channel layer, which can ensure the highest hole concentration in the channel layer and reduce the ohmic contact resistance of the electrode structure and the channel layer; the dose gradient of magnesium ion implantation decreases, which can avoid the accumulation of lattice damage in the channel layer, reduce leakage current and improve the reliability of the transistor.

[0062] In this embodiment of the disclosure, the energy difference between two adjacent gradient magnesium ion implantations is greater than or equal to 20 keV, and the dose ratio of two adjacent gradient magnesium ion implantations is 2:1 to 5:1.

[0063] In this embodiment, the top surface of the second barrier layer 103 is not higher than the top surface of the channel layer 101, and the second barrier layer 103 is an N-type heavily doped In. 0.1 Ga 0.9 N layers.

[0064] In this implementation, the top surface of the second barrier layer is not higher than the top surface of the channel layer, which avoids contact between the second barrier layer and the first barrier layer, thus preventing an increase in the contact resistance between the electrode structure and the second barrier layer; the second barrier layer is N-type heavily doped In. 0.1 Ga 0.9 The N-layer structure can lower the potential barrier; experiments have shown that the contact resistivity is reduced to 4.8 × 10⁻⁶. -7 ~5×10 -7 Ω·cm 2 (The relevant technology is 1×10) -5 Ω·cm 2 ).

[0065] In this embodiment of the disclosure, the Si doping concentration in the second barrier layer 103 can be 1×10⁻⁶. 20 cm -3 .

[0066] In this embodiment of the disclosure, the electrode structure 20 can be Sc x Ti y A stack consisting of Al, Ni, and Au layers, where x and y are greater than 0.

[0067] In this implementation, Sc x Ti y A low-resistivity ScN interface phase is formed between the layer and the GaN surface (ρ≈10). -6 Ω·mm 2 The lattice fit is as low as 1.2%, the Al layer can remain stable in the solid state, and the Ni and Au layers can form a dense diffusion barrier, which reduces ohmic contact resistance and ensures interface flatness and bonding strength, significantly improving the thermal stability of the transistor (from 300°C in related technologies to 500°C).

[0068] For example, x = 0.2, y = 0.8.

[0069] In this embodiment of the disclosure, Sc x Ti y The thickness of the layer can be 15–25 nm, the thickness of the Al layer can be 145–155 nm, the thickness of the Ni layer can be 35–45 nm, and the thickness of the Au layer can be 55–65 nm.

[0070] In this implementation, Sc x Ti y The thickness of the layer is 15-25 nm, which can ensure that sufficient Sc reacts with GaN to form low-resistivity ScN, while avoiding excessive thickness that would lead to high-resistivity TiN residue; the thickness of the Al layer is 145-155 nm, which can provide a low-resistivity pathway, and the thickness is slightly below the melting limit to inhibit the agglomeration of spheres at 450 °C; the thickness of the Ni layer is 35-45 nm, which can form a dense diffusion barrier to prevent the interdiffusion of Al ions and Au ions; the thickness of the Au layer is 55-65 nm, which can improve the bonding strength.

[0071] For example, Sc x Ti y The thickness of the layer is 20nm, the thickness of the Al layer is 150nm, the thickness of the Ni layer is 40nm, and the thickness of the Au layer is 60nm.

[0072] In this embodiment of the disclosure, the channel layer 101 can be a GaN channel layer, and the thickness of the channel layer 101 can be 150-350 nm.

[0073] For example, the thickness of the channel layer 101 is 300 nm.

[0074] In this embodiment of the disclosure, the first barrier layer 102 may be an AlGaN barrier layer.

[0075] In this embodiment of the disclosure, the thickness of the first barrier layer 102 can be 20-30 nm.

[0076] For example, the thickness of the first barrier layer 102 is 25 nm.

[0077] In this embodiment of the disclosure, the molar amount of Al in the first barrier layer 102 is 0.2 to 0.3.

[0078] For example, the molar amount of Al in the first barrier layer 102 is 0.25.

[0079] In embodiments of this disclosure, the transistor may further include a substrate 100, a buffer layer 104, and a cap layer 105.

[0080] The buffer layer 104, the channel layer 101, the first barrier layer 102, and the cap layer 105 are sequentially stacked on the substrate 100.

[0081] The substrate provides a platform for transistor growth. The cap layer protects the transistor and improves its stability.

[0082] In this embodiment of the disclosure, the substrate 100 may be a SiC substrate with a size of 4 to 8 inches;

[0083] Alternatively, substrate 100 can be a diamond substrate, sapphire substrate, or Si substrate, with a size of 2 to 8 feet.

[0084] For example, substrate 100 is a sapphire substrate with a size of 5 feet.

[0085] In this embodiment of the disclosure, the thickness of the substrate 100 can be 500 to 1000 μm.

[0086] For example, the thickness of the substrate 100 is 800 μm.

[0087] Of course, in other embodiments, the transistor may not have a substrate, and this disclosure does not limit this.

[0088] In this embodiment of the disclosure, the buffer layer 104 can be a GaN buffer layer.

[0089] In this embodiment of the disclosure, the thickness of the buffer layer 104 can be 1.2 to 6 μm.

[0090] For example, the thickness of the buffer layer 104 is 3 μm.

[0091] In this embodiment of the disclosure, the cap layer 105 can be a GaN layer.

[0092] In this embodiment of the disclosure, the thickness of the cap layer 105 can be 3 to 6 nm.

[0093] For example, the thickness of the cap layer 105 is 5 nm.

[0094] In this embodiment of the disclosure, an insertion layer may also be included between the channel layer 101 and the first barrier layer 102.

[0095] In this embodiment of the disclosure, the insertion layer can be an AlN layer.

[0096] In this embodiment of the disclosure, a passivation layer may also be included on the cap layer.

[0097] In this embodiment of the disclosure, the passivation layer may be a SiN layer.

[0098] Figure 3 This is a flowchart of a transistor fabrication method provided in an embodiment of this disclosure. See also... Figure 3 The method includes the following steps:

[0099] S11, Create the channel layer.

[0100] S12. A first barrier layer is formed on the channel layer.

[0101] S13. Magnesium ion implantation is performed on multiple magnesium ion implantation regions on the surface of the first barrier layer, wherein the depth of magnesium ion implantation is greater than the thickness of the first barrier layer.

[0102] S14. The plurality of magnesium ion implantation regions are patterned to form a plurality of grooves with their bottoms located in the channel layer, and the sidewalls of the grooves are magnesium ion implantation structures.

[0103] S15. Fabricate a second barrier layer, which is located at the bottom of the plurality of grooves.

[0104] S16. Fabricate an electrode structure, wherein the electrode structure is located within the groove and is connected to the second barrier layer.

[0105] In this embodiment, the first barrier layer has multiple grooves with their bottoms located in the channel layer. The sidewalls and bottoms of the grooves are magnesium ion implantation structures, which can precisely control the Schottky barrier height between the channel layer and the first barrier layer, thereby reducing the contact resistance between the electrode structure and the channel layer. The second barrier layer is located at the bottom of the multiple grooves and is connected to the channel layer. This can reduce the energy difference between the second barrier layer and the conduction band edge of the channel layer, reduce the barrier height of the channel layer, and further reduce the contact resistance between the electrode structure and the channel layer. In summary, using the transistor provided in this embodiment can reduce the barrier height between the electrode structure and the channel layer, thereby reducing the resistance between the electrode structure and the channel layer, reducing transistor heat generation, and improving transistor yield.

[0106] Figure 4 This is a flowchart of another transistor fabrication method provided in this disclosure. See also... Figure 4 The method includes the following steps:

[0107] S21. Provide a substrate and process the substrate.

[0108] In this embodiment of the disclosure, the substrate may be a SiC substrate with a size of 4 to 8 inches;

[0109] Alternatively, the substrate can be a diamond substrate, a sapphire substrate, or a Si substrate, with a size of 2 to 8 feet.

[0110] For example, the substrate is a sapphire substrate with a size of 5 feet.

[0111] In the embodiments disclosed herein, the thickness of the substrate can be 500–1000 μm.

[0112] For example, the thickness of the substrate is 800 μm.

[0113] In this embodiment of the disclosure, the cleaning process is carried out for 3 to 8 minutes using a sulfuric acid-hydrogen peroxide mixture (SPM) at a temperature of 50 to 100°C.

[0114] For example, SPM cleaning was performed for 5 minutes at a temperature of 80°C.

[0115] The ratio of H2SO4:H2O2:H2O is 3:1:6.

[0116] S22. Fabricate a buffer layer on the substrate.

[0117] In this embodiment of the disclosure, step S22 may include:

[0118] The buffer layer can be fabricated using physical vapor deposition (PVD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), atomic layer deposition (ALD), or pulsed laser deposition (PLD).

[0119] For example, the buffer layer is created using MOCVD.

[0120] In this embodiment of the disclosure, the buffer layer can be a GaN buffer layer.

[0121] In this embodiment of the disclosure, the thickness of the buffer layer can be 1.2 to 6 μm.

[0122] For example, the thickness of the buffer layer is 3 μm.

[0123] S23. Create a channel layer on the buffer layer.

[0124] In this embodiment of the disclosure, the channel layer can be a GaN channel layer, and the thickness of the channel layer can be 150-350 nm.

[0125] For example, the thickness of the channel layer is 300 nm.

[0126] In this embodiment of the disclosure, step S23 may further include: fabricating an insertion layer on the channel layer.

[0127] In this embodiment of the disclosure, the insertion layer can be an AlN layer.

[0128] S24. Create the first barrier layer on the channel layer.

[0129] In this embodiment of the disclosure, the first barrier layer may be an AlGaN barrier layer.

[0130] In this embodiment of the disclosure, the thickness of the first barrier layer can be 20-30 nm.

[0131] For example, the thickness of the first barrier layer is 25 nm.

[0132] In this embodiment of the disclosure, the molar amount of Al in the first barrier layer is 0.2 to 0.3.

[0133] For example, the molar amount of Al in the first barrier layer is 0.25.

[0134] S25. Create a cap layer on the first barrier layer.

[0135] In this embodiment of the disclosure, the cap layer can be a GaN layer.

[0136] In this embodiment of the disclosure, the thickness of the cap layer can be 3 to 6 nm.

[0137] For example, the thickness of the cap layer is 5 nm.

[0138] In this embodiment of the disclosure, step S25 may further include: forming a passivation layer on the cap layer.

[0139] In this embodiment of the disclosure, the passivation layer can be a SiN layer fabricated by MOCVD.

[0140] Figure 5 This is a schematic diagram of a transistor fabrication process provided in an embodiment of this disclosure. See also... Figure 5 The buffer layer 104, the channel layer 101, the first barrier layer 102 and the cap layer 105 are sequentially stacked on the substrate 100.

[0141] S26. Magnesium ions are implanted into the cap layer, channel layer, and first barrier layer.

[0142] For example, step S26 may include:

[0143] The first step is to form a photoresist mask layer on the cap layer.

[0144] In this embodiment of the disclosure, forming a photoresist mask layer on the epitaxial structure may include:

[0145] The cap layer surface is ultrasonically cleaned and then dried.

[0146] Spin-coat photoresist onto the cap layer surface;

[0147] The photoresist is exposed and developed to form a photoresist mask layer.

[0148] Figure 6 This is a schematic diagram of a transistor fabrication process provided in an embodiment of this disclosure. See also... Figure 6 The photoresist mask layer 301 is located on the surface of the cap layer 105, as referenced. Figure 2 and Figure 5 The photoresist mask layer 301 has multiple vias, and the positions of the multiple vias correspond to the positions of the multiple magnesium ion implantation regions to be formed.

[0149] The second step involves implanting magnesium ions into multiple regions of the cap layer, channel layer, and first barrier layer under the cover of the photoresist mask layer.

[0150] The third step is to remove the photoresist mask layer.

[0151] Figure 7 This is a schematic diagram of a transistor manufacturing process provided in an embodiment of this disclosure. Figure 7 ,exist Figure 6 Based on this, ion implantation is performed to remove the photoresist mask layer 301 to form a magnesium ion implantation structure 302.

[0152] In this embodiment of the disclosure, the energy gradient energy difference of magnesium ion implantation is greater than or equal to 20 keV, and the gradient dose ratio of magnesium ion implantation is 2:1 to 5:1.

[0153] In this embodiment of the present disclosure, along the direction from the first barrier layer to the channel layer, the energy gradient of magnesium ion implantation in the magnesium ion implantation structure increases and the dose gradient of magnesium ion implantation decreases.

[0154] In this implementation, the energy gradient of magnesium ion implantation in the magnesium ion implantation structure increases along the direction from the first barrier layer to the channel layer, which can ensure the highest hole concentration in the channel layer and reduce the ohmic contact resistance of the electrode structure and the channel layer; the dose gradient of magnesium ion implantation decreases, which can avoid the accumulation of lattice damage in the channel layer, reduce leakage current and improve the reliability of the transistor.

[0155] In this embodiment of the disclosure, along the direction from the first barrier layer to the channel layer, the energy of magnesium ion implantation during the magnesium ion implantation process is controlled to increase in a gradient of 30keV, 50keV, and 80keV, and the dose of magnesium ion implantation during the magnesium ion implantation process is controlled to be 5×10 13 cm -2 3×10 13 cm -2 1×10 13 cm -2 Gradient decrease.

[0156] In this implementation, along the direction from the first barrier layer to the channel layer, the magnesium ion implantation energy is controlled to increase in gradients of 30keV, 50keV, and 80keV during the magnesium ion implantation process, and the magnesium ion implantation dose is controlled to be 5 × 10⁻⁶. 13 cm -2 3×10 13 cm -2 1×10 13 cm -2Gradient reduction allows for precise control of the Schottky barrier height, reducing the contact resistance between the electrode structure and the second barrier layer. Experiments show that reducing the Schottky barrier height from 1.0 eV to 0.3 eV lowers the contact resistance to 0.08 Ω·mm (compared to 0.3–0.5 Ω·mm in related technologies), suppressing carrier scattering and achieving an electron mobility greater than 1800 cm⁻¹. 2 / (V·s).

[0157] S27. The magnesium ion implantation region is patterned, and a groove with its bottom located in the channel layer is formed. The sidewall of the groove is a magnesium ion implantation structure.

[0158] In this embodiment of the disclosure, a patterned mask layer is formed on the surface of the cap layer; a groove is made under the cover of the mask layer, and the bottom of the groove is located in the channel layer.

[0159] Figure 8 This is a schematic diagram of a transistor fabrication process provided in an embodiment of this disclosure. See also... Figure 8 The magnesium ion implantation structure 302 of the channel layer 101 and the first barrier layer 102 has a groove 1001.

[0160] S28. A second barrier layer is formed within the groove.

[0161] For example, step S28 may include:

[0162] The first step is to deposit a second barrier layer, which covers the groove and the surface of the first barrier layer.

[0163] The second step is to etch the second barrier layer, removing the portion outside the groove and the excess portion inside the groove, so that the top surface of the second barrier layer is not higher than the top surface of the channel layer.

[0164] In this embodiment of the disclosure, the top surface of the second barrier layer is not higher than the top surface of the channel layer, and the second barrier layer is an N-type heavily doped In. 0.1 Ga 0.9 N layers.

[0165] In this implementation, the top surface of the second barrier layer is not higher than the top surface of the channel layer, which avoids contact between the second barrier layer and the first barrier layer, thus preventing an increase in the contact resistance between the electrode structure and the second barrier layer; the second barrier layer is N-type heavily doped In. 0.1 Ga 0.9 The N-layer structure can lower the potential barrier; experiments have shown that the contact resistivity is reduced to 4.8 × 10⁻⁶. -7 ~5×10 -7 Ω·cm 2 (The relevant technology is 1×10) -5 Ω·cm 2 ).

[0166] In this embodiment of the disclosure, the Si doping concentration in the second barrier layer can be 1×10⁻⁶. 20 cm -3 .

[0167] Figure 9 This is a schematic diagram of a transistor fabrication process provided in an embodiment of this disclosure. See also... Figure 9 The second barrier layer 103 is located within the groove 1001.

[0168] S29. Fabricate an electrode structure, which passes through the groove and connects to the second barrier layer.

[0169] In this embodiment of the disclosure, vacuum pulsed magnetic field technology is used to heat Sc at a temperature of 445–455°C and a vacuum pressure of 3–7 MPa. x Ti y The Al, Ni, and Au layers undergo transient liquid-phase bonding for 45–55 ms to form an electrode structure, where x and y are greater than 0.

[0170] In this implementation, vacuum pulsed magnetic field technology is used to heat Sc at a temperature of 445–455℃ and a vacuum pressure of 3–7 MPa. x Ti y The electrode structure is formed by transient liquid-phase bonding of Al, Ni, and Au layers over 45–55 ms, which allows for the simultaneous completion of Sc. x Ti y Transient liquid-phase reaction of four layers: Al, Ni, and Au: Sc layer reacts with GaN surface to form a low-resistivity ScN interface phase (ρ≈10). -6 Ω·mm 2 The Al layer can maintain solid-state suppression spheres, and the Ni and Au layers can form a dense diffusion barrier, which reduces ohmic contact resistance and ensures interface flatness and bonding strength, significantly improving the thermal stability of transistors (from 300°C in related technologies to 500°C).

[0171] Among them, Sc x Ti y The thickness of the layer can be 15–25 nm, the thickness of the Al layer can be 145–155 nm, the thickness of the Ni layer can be 35–45 nm, and the thickness of the Au layer can be 55–65 nm.

[0172] In this implementation, Sc x Ti yThe thickness of the layer is 15-25 nm, which can ensure that sufficient Sc reacts with GaN to form low-resistivity ScN, while avoiding excessive thickness that would lead to high-resistivity TiN residue; the thickness of the Al layer is 145-155 nm, which can provide a low-resistivity pathway, and the thickness is slightly below the melting limit to inhibit the agglomeration of spheres at 450 °C; the thickness of the Ni layer is 35-45 nm, which can form a dense diffusion barrier to prevent the interdiffusion of Al ions and Au ions; the thickness of the Au layer is 55-65 nm, which can improve the bonding strength.

[0173] For example, Sc x Ti y The thickness of the layer is 20nm, the thickness of the Al layer is 150nm, the thickness of the Ni layer is 40nm, and the thickness of the Au layer is 60nm.

[0174] In this embodiment of the disclosure, Sc x Ti y The Sc content in the layer is 10-30%.

[0175] S30. Test the transistor after annealing.

[0176] In this embodiment of the disclosure, the resistance, capacitance, current and voltage of the transistor are tested.

[0177] The transistors provided in this disclosure, through bandgap design, interface processing engineering, and ultrafast thermal control, resolve the reliability contradiction of the resistance of the transistor's ohmic contact. The transistors provided in this disclosure can provide core process support for 10MHz ultra-high frequency power systems.

[0178] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A transistor, characterized in that, The transistor includes: a channel layer (101), a first barrier layer (102), a second barrier layer (103), and an electrode structure (20); The first barrier layer (102) is located on the channel layer (101). The first barrier layer (102) has a plurality of grooves (1001) with the bottom located on the channel layer (101). The sidewalls and bottom of the grooves (1001) are magnesium ion implantation structures (302). The second barrier layer (103) is located at the bottom of the plurality of grooves (1001), the electrode structure (20) is located in the grooves (1001), and the electrode structure (20) is connected to the second barrier layer (103).

2. The transistor according to claim 1, characterized in that, The groove (1001) is a cylindrical groove with a diameter R of 50 nm and a depth H of 80 nm.

3. The transistor according to claim 1 or 2, characterized in that, The plurality of grooves (1001) are arranged in rows and columns, and the spacing L between two adjacent columns of the grooves (1001) is 95-105 nm.

4. The transistor according to claim 1 or 2, characterized in that, Along the direction from the first barrier layer (102) to the channel layer (101), the energy gradient of magnesium ion implantation in the magnesium ion implantation structure (302) increases and the dose gradient of magnesium ion implantation decreases.

5. The transistor according to claim 1 or 2, characterized in that, The top surface of the second barrier layer (103) is not higher than the top surface of the channel layer (101), and the second barrier layer (103) is an N-type heavily doped In. 0.1 Ga 0.9 N layers.

6. The transistor according to claim 1 or 2, characterized in that, The electrode structure (20) is Sc x Ti y A stack consisting of an Al layer, a Ni layer, and an Au layer, wherein x and y are greater than 0; The Sc x Ti y The thickness of the layer is 15-25 nm, the thickness of the Al layer is 145-155 nm, the thickness of the Ni layer is 35-45 nm, and the thickness of the Au layer is 55-65 nm.

7. A method for fabricating a transistor, characterized in that, The transistor fabrication method includes: Create the channel layer; A first barrier layer is fabricated on the channel layer; Magnesium ion implantation is performed on multiple magnesium ion implantation regions on the surface of the first barrier layer, wherein the depth of magnesium ion implantation is greater than the thickness of the first barrier layer. The plurality of magnesium ion implantation regions are patterned, and a plurality of grooves with their bottoms located in the channel layer are formed, wherein the sidewalls of the grooves are magnesium ion implantation structures. A second barrier layer is fabricated, the second barrier layer being located at the bottom of the plurality of grooves; An electrode structure is fabricated, the electrode structure is located within the groove, and the electrode structure is connected to the second barrier layer.

8. The transistor fabrication method according to claim 7, characterized in that, Magnesium ion implantation is performed on multiple magnesium ion implantation regions on the surface of the first barrier layer, including: Along the direction from the first barrier layer to the channel layer, the energy gradient of magnesium ion implantation is controlled to increase during the magnesium ion implantation process, and the dose gradient of magnesium ion implantation is controlled to decrease during the magnesium ion implantation process.

9. The transistor fabrication method according to claim 8, characterized in that, Along the direction from the first barrier layer to the channel layer, the magnesium ion implantation energy is controlled to increase in gradients of 30 keV, 50 keV, and 80 keV during the magnesium ion implantation process, and the magnesium ion implantation dose is controlled to be 5 × 10⁻⁶. 13 cm -2 3×10 13 cm -2 1×10 13 cm -2 Gradient decrease.

10. The transistor fabrication method according to any one of claims 7 to 9, characterized in that, The fabrication of the electrode structure includes: Under conditions of 445–455℃ and 3–7 MPa vacuum pressure, vacuum pulsed magnetic field technology was used to sc x Ti y The Al, Ni, and Au layers undergo transient liquid-phase bonding for 45–55 ms to form an electrode structure, where x and y are greater than 0.

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