Semiconductor device and preparation method thereof, and electronic equipment
By setting a gate cap layer and an insulating layer to cover the sidewalls of the gate cap layer and the portion not covered by the gate in GaN HEMT devices, and combining this with a passivation layer to cover the heterostructure, the gate leakage problem is solved, the power consumption of the device is reduced, and the reliability and electrical performance are improved.
Patent Information
- Application Number
- CN202511565216.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-29
- Publication Date
- 2026-02-06
AI Technical Summary
Existing GaN HEMT enhancement-mode devices suffer from gate leakage, resulting in high power consumption, which affects circuit safety and design complexity.
A gate cap layer is set under the gate, and an insulating layer is used to cover the sidewalls of the gate cap layer and the part not covered by the gate. Combined with a passivation layer to cover the heterostructure and the gate, an insulating structure is formed to block the leakage path.
It effectively reduces surface leakage current at the gate, reduces power consumption of semiconductor devices, and improves device reliability and electrical performance.
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Figure CN121487293A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology
[0002] Due to the superior switching characteristics, faster switching frequency, and lower losses of gallium nitride (GaN) material, GaN power devices offer better switching performance and smaller size, enabling the implementation of smaller, lighter, more efficient, and energy-saving power systems. Currently, GaN power devices are primarily used in fast chargers for smartphones and computers, and they show promising future applications in electric vehicles, photovoltaic power generation, uninterruptible power supplies (UPS), and data centers.
[0003] High Electron Mobility Transistor (HEMT) devices are semiconductor devices that are widely used as radio frequency devices or power devices due to their advantages such as high breakdown electric field, high channel electron concentration, high electron mobility and high temperature stability.
[0004] For GaN HEMT devices, due to the presence of a high concentration of 2-dimensional electron gas (2DEG), the gate cannot deplete the 2DEG in the channel under zero bias. This means that current still flows through the channel when the gate voltage is zero. Therefore, a negative bias needs to be applied to the gate to deplete the 2DEG and put the HEMT in the off state. However, this reduces circuit safety, increases circuit design complexity, and increases power consumption. Therefore, realizing an enhancement-mode HEMT that is in the off state under zero gate bias is crucial for advancing the application of GaN HEMT devices in the power domain.
[0005] Currently, GaN HEMT enhancement-mode devices mainly include PGaN gate technology. PGaN gate technology involves placing a PGaN layer under the gate to raise the energy band at the channel location and deplete the 2DEG in the channel, thereby realizing an enhancement-mode HEMT device. However, GaN HEMT devices using PGaN gate technology often suffer from gate leakage, resulting in high device power consumption. To further reduce the power consumption of GaNHEMT devices, reducing gate leakage has become an urgent problem to be solved. Summary of the Invention
[0006] This disclosure provides a semiconductor device and its fabrication method, as well as an electronic device, for reducing gate leakage current in enhancement-mode HEMTs, thereby reducing the power consumption of the HEMT device.
[0007] To achieve the above objectives, the present disclosure provides the following technical solutions: A first aspect of this disclosure provides a semiconductor device including a substrate, a heterostructure, a gate cap layer, a gate, an insulating layer, and a passivation layer. The heterostructure is disposed on one side of the substrate. The gate cap layer is disposed on the side of the heterostructure away from the substrate and partially covers the heterostructure. The gate is disposed on the side of the gate cap layer away from the substrate and covers at least a portion of the gate cap layer. The insulating layer covers the sidewalls of the gate cap layer and the portion of the gate cap layer away from the substrate that is not covered by the gate. The passivation layer covers the sidewalls of the heterostructure, the portion of the heterostructure away from the substrate that is not covered by the gate cap layer, the gate, and the insulating layer.
[0008] In the semiconductor device provided in the embodiments of this disclosure, the gate cap layer is located on the side of the heterostructure away from the substrate, and the gate is disposed on the side of the gate cap layer away from the substrate. Thus, when the voltage applied to the gate is zero, the two-dimensional electron gas in the channel layer below the gate can be depleted by the holes in the gate cap layer, while the remaining two-dimensional electron gas can be retained, thereby realizing enhancement-mode HEMT.
[0009] Furthermore, since the sidewalls of the gate cap layer and the portion of the gate cap layer away from the substrate that is not covered by the gate are covered by an insulating layer, some leakage paths on the surface of the gate cap layer are blocked, thus reducing the surface leakage of the gate and reducing the power consumption of the semiconductor device.
[0010] Passivation layers cover the surface of semiconductor devices, isolating them from the external environment and improving their reliability and core electrical performance.
[0011] In some embodiments, the boundary of the gate's orthogonal projection onto the substrate is located within the boundary of the gate cap layer's orthogonal projection onto the substrate, and the insulating layer covers the sidewalls of the gate cap layer and the portion of the gate cap layer away from the substrate that is not covered by the gate.
[0012] In some embodiments, the boundary of the gate's orthographic projection on the substrate coincides with the boundary of the gate cap layer's orthographic projection on the substrate, and an insulating layer covers the sidewalls of the gate cap layer.
[0013] In some embodiments, the insulating layer is configured to be formed by oxidation of the gate cap layer.
[0014] In some embodiments, the gate includes a gate oxide layer and a gate body, the gate oxide layer covering the sidewalls of the gate body and the surface of the gate body away from the substrate.
[0015] In some embodiments, the semiconductor device further includes a contact structure that extends through the passivation layer and the gate oxide layer and is connected to the gate body.
[0016] In some embodiments, the passivation layer includes a first passivation layer and a second passivation layer. The first passivation layer covers the sidewalls of a portion of the heterostructure and the portion of the heterostructure away from the substrate that is not covered by the gate cap layer. The second passivation layer covers the first passivation layer, the gate, and the insulating layer. In some feasible embodiments, the first passivation layer is formed before the insulating layer to prevent oxidation of the sidewalls of the heterostructure and the portion away from the substrate that is not covered by the gate cap layer during the formation of the insulating layer. The second passivation layer is formed after the insulating layer to isolate the semiconductor device from the external environment, thereby improving the reliability and core electrical performance of the semiconductor device.
[0017] In some embodiments, the end of the first passivation layer near the gate cap layer is in contact with the gate cap layer.
[0018] In some embodiments, the end of the first passivation layer near the gate cap layer contacts the insulating layer.
[0019] In some embodiments, the end of the first passivation layer near the gate cap layer is in contact with the second passivation layer.
[0020] In some embodiments, the material of the passivation layer includes a plasma-enhanced oxide film and / or low-temperature titanium nitride, and the materials of the first passivation layer and the second passivation layer may be the same or different.
[0021] A second aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: A heterostructure is formed on a substrate. An initial gate cap layer is formed on the heterostructure, the initial gate cap layer covering a portion of the heterostructure. An initial gate is formed on the initial gate cap layer, the initial gate covering at least a portion of the initial gate cap layer, to obtain an epitaxial structure. The epitaxial structure is then acid-washed. A first passivation layer is formed, covering the sidewalls of the heterostructure and the portion of the heterostructure away from the substrate not covered by the initial gate cap layer. The sidewalls of the initial gate cap layer, the portion of the initial gate cap layer not covered by the initial gate, and the initial gate are oxidized to form a gate cap layer, a gate, an insulating layer, and a gate oxide layer. A second passivation layer is formed, covering the first passivation layer, the gate, and the insulating layer.
[0022] A third aspect of this disclosure provides an electronic device including a printed circuit board and a semiconductor device as described in any of the above embodiments. The printed circuit board is electrically connected to the semiconductor device.
[0023] The technical effects of the second and third aspects can be found in the technical effects of the different design methods in the first aspect, and will not be repeated here. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.
[0025] Figure 1 This is a schematic diagram of the structure of an electronic device provided in some embodiments of this disclosure; Figure 2 This is a schematic diagram of the structure of a base station provided in some embodiments of this disclosure; Figure 3 This is a schematic diagram of the structure of an AAU provided in some embodiments of this disclosure; Figure 4 This is a schematic diagram of the structure of a charger provided in some embodiments of this disclosure; Figure 5 This is a schematic diagram of the structure of a HEMT device provided in some embodiments of this disclosure; Figure 6 This is a schematic diagram of the structure during the fabrication process of a HEMT device, provided in some embodiments of this disclosure; Figure 7 A flow chart of a surface passivation process for an HEMT device provided for some embodiments of this disclosure; Figure 8 This is a schematic diagram of the structure during the surface passivation process of a HEMT device provided in some embodiments of this disclosure; Figure 9 This is a schematic diagram illustrating the gate leakage current of a HEMT device provided in some embodiments of this disclosure; Figure 10 This is a schematic diagram of a semiconductor device structure provided in some embodiments of the present disclosure; Figure 11 This is a schematic diagram of another semiconductor device structure provided in some embodiments of this disclosure; Figure 12 This is a schematic diagram of another semiconductor device structure provided in some embodiments of the present disclosure; Figure 13 This is a schematic diagram of another semiconductor device structure provided in some embodiments of the present disclosure; Figure 14 This is a schematic diagram of another semiconductor device structure provided in some embodiments of the present disclosure; Figure 15 This is a schematic diagram of another semiconductor device structure provided in some embodiments of the present disclosure; Figure 16This is a schematic diagram of another semiconductor device structure provided in some embodiments of the present disclosure; Figure 17 This is a schematic diagram of another semiconductor device structure provided in some embodiments of the present disclosure; Figure 18 This is a flowchart illustrating a semiconductor device fabrication method provided in some embodiments of the present disclosure; Figure 19 This is a schematic diagram of the structure during the fabrication process of a semiconductor device, provided by some embodiments of this disclosure; Figure 20 A schematic diagram of a process for forming a heterostructure on a substrate, provided for some embodiments of this disclosure; Figure 21 This is a schematic diagram of a process for removing part of the passivation medium, provided in some embodiments of this disclosure; Figure 22 This is a schematic diagram illustrating gate leakage current in a semiconductor device, provided for some embodiments of this disclosure. Detailed Implementation
[0026] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.
[0027] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.
[0028] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.
[0029] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.
[0030] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.
[0031] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.
[0032] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).
[0033] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).
[0034] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
[0035] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.
[0036] As used in this paper, the term "two-dimensional electron gas (2DEG)" refers to a two-dimensional free electron in which the motion of electrons perpendicular to the interface is bound by a potential well and quantized, while their motion parallel to the surface remains free.
[0037] As used herein, the term "heterogeneous structure" refers to a stacked structure formed from two or more different semiconductor materials.
[0038] Figure 1 This is a schematic diagram of the structure of an electronic device provided in some embodiments of this disclosure.
[0039] This disclosure provides an electronic device 1000, such as... Figure 1 As shown, the electronic device 1000 includes a semiconductor device 100 and a printed circuit board 200. This electronic device 1000 can be, for example, a charger, a small household appliance for charging, a drone, aerospace equipment, a lidar driver, a laser, a detector, radar, 5G (the 5th Generation Mobile Network) communication equipment, or other different types of user equipment or terminal equipment. Alternatively, the electronic device can also be a network device such as a base station. This disclosure does not impose any special limitations on the specific form of the electronic device.
[0040] HEMT devices are semiconductor electronic devices that are widely used as radio frequency devices or power devices due to their advantages such as high breakdown electric field, high channel electron concentration, high electron mobility and high temperature stability.
[0041] Figure 2 This is a schematic diagram of the structure of a base station provided in some embodiments of this disclosure.
[0042] When HEMT devices are used as radio frequency devices, the structure of the electronic device is explained using an electronic base station as an example. Figure 2 As shown, base station 1 includes a baseband unit (BBU) 11 and an active antenna unit (AAU) 12. The BBU 11 is primarily responsible for baseband digital signal processing, such as Fast Fourier Transform (FFT) / Inverse Fast Fourier Transform (IFFT), modulation / demodulation, and channel coding / decoding.
[0043] Figure 3 This is a schematic diagram of the structure of an AAU provided in some embodiments of this disclosure.
[0044] like Figure 3 As shown, the AAU12 includes a computing unit 1210, a first transmission unit 1220, and an antenna unit 1230. The computing unit 1210 includes a second transmission unit 1211, a baseband unit 1212, a power supply unit 1213, and a control unit 1214. These units are electrically connected. The control unit 1214 is responsible for controlling the radio frequency (RF) signals, the second transmission unit 1211 is responsible for transmitting RF signals, and the baseband unit 1212 is responsible for converting digital signals to analog signals. The baseband unit 1212 can be, for example, a digital-to-analog converter (DAC), which converts the digital signals output by the BBU11 into analog signals. The power supply unit 1213 is electrically connected to a power supply 1240 and supplies power to the control unit 1210, the second transmission unit 1211, and the baseband unit 1212 within the computing unit 1210. The first transmission unit 1220 is responsible for transmitting and amplifying the RF signals. The first transmission unit 1220 includes a radio frequency (RF) unit 1221 and a power amplifier (PA) 1222. The RF unit 1221 converts analog signals into low-power RF signals, and the PA 1222 performs power reduction on the low-power RF signals before outputting them to the antenna unit 1230. The antenna unit 1230 is responsible for radiating the RF signals outwards. Figure 3As shown, AAU12 may include multiple RF units 1221, multiple PAs 1222, and multiple antenna units 1230. It should be noted that the PAs 1222 can be HEMT devices, and the BBU11 and AAU12 can be interconnected through printed circuit boards (PCBs), optical fibers, and cables.
[0045] It should be understood that when HEMT devices are used as power amplifiers (PAs), the electronic devices provided in the embodiments of this disclosure are not limited to... Figure 2 and Figure 3 The base station shown, and any electronic device that requires a power amplifier to amplify the signal, fall under the application scenarios of this disclosure.
[0046] Figure 4 This is a schematic diagram of the structure of a charger provided for some embodiments of this disclosure.
[0047] When HEMT devices are used as power devices, the structure of the electronic device is explained using a charger as an example. Figure 4 As shown, charger 2 may include power devices, resistors R, inductors L, capacitors C, etc., and the power devices may be, for example, HEMT devices. The HEMT devices, resistors R, inductors L, and capacitors C can be interconnected via a PCB.
[0048] It should be understood that when HEMT devices are used as power devices, the electronic devices provided in the embodiments of this disclosure are not limited to... Figure 4 The charger shown is applicable to any electronic device that requires the use of power devices, and is a scenario in which the embodiments of this application are described.
[0049] To alleviate the problems of depletion-mode HEMT devices, an enhanced (E-Mode) HEMT device is provided.
[0050] Enhancement-mode HEMT devices are highly compatible with other parts of the circuit and do not require a separate power supply system. Furthermore, when HEMT devices are used in electronics, depletion-mode HEMT devices not only require a separate negative bias system, but also, for system safety, the operation of this negative bias system must precede the power supply. Since enhancement-mode HEMT devices do not require a separate power supply system, conduction damage during system startup and mode transitions can be avoided. Moreover, enhancement-mode HEMTs are normally-off devices, saving energy.
[0051] Figure 5 This is a schematic diagram of the structure of a HEMT device provided in some embodiments of this disclosure.
[0052] In some alternative embodiments, such as Figure 5As shown, the HEMT device includes a substrate 10, a heterostructure 20, a gate cap layer 30, a source S, a drain D, and a gate G.
[0053] The heterostructure 20 includes a channel layer 21 and a barrier layer 22, with the channel layer 21 disposed on the side of the barrier layer 22 closer to the substrate 10. Alternatively, the barrier layer 22 can be understood as being disposed on the channel layer 21. The channel layer 21 is made of gallium nitride (GaN), and the barrier layer 22 is made of aluminum gallium nitride (AlGaN).
[0054] The gate cap layer 30 is made of P-type doped GaN.
[0055] The operating principle of a HEMT device is as follows: the source (S) and drain (D) form conductive ohmic contacts with the barrier layer 22, respectively, and the gate (G) forms a Schottky contact with the barrier layer 22. The dashed lines in the channel layer 21 represent the 2DEG generated through polarization in the heterostructure 20 formed by the channel layer 21 and the barrier layer 22 in the HEMT. The 2DEG is used to efficiently conduct electrons under the influence of an electric field. The source (S) and drain (D) are used to allow the 2DEG to flow within the channel layer 21 between the source (S) and drain (D) under the influence of an electric field; conduction between the source (S) and drain (D) occurs at the 2DEG in the channel layer 21. The gate (G) is disposed between the source (S) and drain (D) to allow or impede the passage of the 2DEG. The 2DEG exhibits high conductivity, partly because the 2DEG in the potential well is located on the intrinsic semiconductor side, where there is no scattering effect from ionized impurity centers. Therefore, the mobility of the 2DEG moving along the planar direction is relatively high (especially at lower temperatures and when lattice vibrations are weakened).
[0056] In this embodiment, the gate cap layer 30 can adjust the band structure of the heterostructure 20, causing the electrons directly below the gate cap layer 30 to be depleted. For example... Figure 5 As shown, 2DEG is in a pinch-off state without bias. That is to say, HEMT is a normally off device.
[0057] Figure 6 This is a structural schematic diagram of the fabrication process of a HEMT device provided in some embodiments of this disclosure.
[0058] like Figure 6 As shown, the fabrication method of HEMT devices includes: A heterostructure 20 is formed on a substrate 10, and a P-type GaN layer is formed on the surface of the heterostructure 20. A gate G is formed on the surface of the P-type GaN layer. The P-type GaN layer is etched to form a gate cap layer 30; a source S and a drain D are then formed. In HEMT devices fabricated by this method, due to the high requirements of the etching process for P-type GaN material, surface defects and residual impurities often exist in the gate cap layer 30 during the fabrication process. These surface defects and residual impurities form surface leakage paths, resulting in surface leakage at the gate G.
[0059] Figure 7 This is a flow chart of a surface passivation process for a HEMT device provided in some embodiments of this disclosure. Figure 8 This is a schematic diagram of the structure during the surface passivation process of a HEMT device provided in some embodiments of this disclosure. Figure 9 This is a schematic diagram illustrating the gate leakage current of a HEMT device provided in some embodiments of this disclosure.
[0060] Furthermore, to improve the performance and reliability of semiconductor devices, passivation treatment is typically performed on the surface of the semiconductor device to isolate it from the external environment. In one related technology, such as... Figure 7 As shown, the following process is used to perform surface passivation treatment on HEMT devices: S101: As Figure 8 As shown, acid baths are used to clean the surface of HEMT devices; S102: As Figure 8 As shown, an epitaxial passivation medium is used to form a passivation layer; S103: As Figure 8 As shown, a contact structure is provided that passes through the passivation layer to connect the gate, source, and drain.
[0061] Among them, the gate G connection structure 50G, the source connection structure 50S, and the drain connection structure 50D can be connected to external circuits to realize the control of HEMT devices.
[0062] In the above process, to ensure the strong adhesion of the passivation layer 40, an acid bath cleaning process is required to remove the oxide layer and some impurities from the HEMT device surface. During this process, the P-type GaN surface will be further damaged, increasing the surface leakage paths, such as... Figure 9 As shown, this increases the leakage current on the gate G surface, resulting in increased power consumption of the HEMT device.
[0063] To improve the performance and reliability of HEMT devices while reducing gate leakage current and thus power consumption, one aspect of this disclosure provides a semiconductor device 100.
[0064] For ease of description, the direction in which each film layer is stacked in the semiconductor device 100 is referred to as the first direction X, and the second direction Y intersects with the first direction X. For example, the second direction Y is perpendicular to the first direction X.
[0065] Figure 10 This is a schematic diagram of a semiconductor device structure provided in some embodiments of the present disclosure. Figure 11 This is a schematic diagram of another semiconductor device structure provided in an embodiment of this disclosure.
[0066] like Figure 10As shown, the semiconductor device 100 includes a substrate 110, a heterostructure 120, a gate cap layer 130, a gate G, and a passivation layer 140.
[0067] Continue reading Figure 10 In some feasible embodiments, the heterostructure 120 includes a channel layer 121 and a barrier layer 122, wherein the channel layer 121 is located on one side of the substrate 110, and the barrier layer 122 is located on the side of the channel layer 121 away from the substrate 110. The channel layer 121 contains 2DEG generated by polarization interaction with the barrier layer 122.
[0068] Continue reading Figure 10 In some feasible embodiments, the gate cap layer 130 is located on the side of the heterostructure 120 away from the substrate and partially covers the heterostructure 120. That is, along the second direction Y, the width of the gate cap layer 130 is smaller than the width of the heterostructure 120. In this way, the source S and drain D can be disposed on both sides of the heterostructure 120 away from the gate cap layer 130, and 2DEG connects the source S and drain D, and is turned on / off under the control of the gate G.
[0069] Continue reading Figure 10 In some feasible embodiments, the gate G is located on the side of the gate cap layer 130 away from the substrate 110. It should be noted that, along the second direction Y, the width H1 of the gate G is less than or equal to the width H2 of the gate cap layer 130.
[0070] In some feasible implementations, the gate cap layer 130 is made of a semiconductor material, the insulating layer 150 is made of a semiconductor oxide, and the insulating layer 150 is configured to be formed by oxidation of the gate cap layer 130.
[0071] As an example, the gate cap layer 130 can be made of P-type GaN, and the insulating layer 150 can be made of gallium trioxide (Ga2O3), a product of P-type GaN oxidation.
[0072] like Figure 11 As shown, the passivation layer 140 may include a first passivation layer 141 and a second passivation layer 142.
[0073] Continue reading Figure 11 In some feasible embodiments, the first passivation layer 141 covers the portion of the surface of the heterostructure 120 not covered by the gate cap layer 130 and the insulating layer 150. The insulating layer 150 covers the sidewalls of the gate cap layer 130 and the portion of the gate cap layer 130 away from the substrate not covered by the gate. The second passivation layer 142 covers the first passivation layer 141, the insulating layer 150, and the gate G.
[0074] It should be noted that in some embodiments, the insulating layer 150 is fabricated by rapidly oxidizing the surface of the gate cap layer 130 through rapid thermal oxidation (RTO), thereby disrupting part of the conductive channels and reducing gate G leakage current. During this process, it is understood that the surface of the heterostructure 120 is a barrier layer 122. If the barrier layer 122 is oxidized, it will disrupt the ohmic contact between the source (S), drain (D), and the barrier layer, increasing the contact resistance and conduction loss; it may also disrupt the 2DEG channel, reducing the conductivity of the semiconductor device 100; simultaneously, it will affect the adhesion of the passivation layer, impacting subsequent processes. Therefore, it is necessary to avoid oxidizing the surface of the heterostructure 120, i.e., the barrier layer 122, while oxidizing the surface of the gate cap layer 130. In this embodiment, a first passivation layer 141 is applied to the surface of the heterostructure 120 not covered by the gate cap layer 130. During the subsequent RTO process, this prevents the surface of the heterostructure 120 from being oxidized, thus avoiding the aforementioned potential adverse effects.
[0075] Continue reading Figure 11 In some feasible embodiments, along the second direction Y, the width H1 of the gate G is the same as the width H2 of the gate cap layer 130. At this time, the side of the gate cap layer 130 away from the substrate 110 is completely covered by the gate G. During the RTO process, at least a portion of the exposed sidewalls of the gate cap layer 130 are oxidized, that is, the insulating layer 150 covers at least a portion of the sidewalls of the gate cap layer 130.
[0076] Figure 12 This is a schematic diagram of another semiconductor device structure provided for some embodiments of this disclosure.
[0077] like Figure 12 As shown, in some feasible embodiments, along the second direction Y, the width H1 of the gate G is smaller than the width H2 of the gate cap layer 130. At this time, the side of the gate cap layer 130 away from the substrate 110 is partially covered by the gate G. During the RTO process, at least a portion of the exposed sidewalls of the gate cap layer 130 and the portion of the gate cap layer 130 away from the substrate 110 that is not covered by the gate G are oxidized, that is, the insulating layer 150 covers at least a portion of the sidewalls of the gate cap layer 130 and the portion of the gate cap layer 130 away from the substrate 110 that is not covered by the gate G.
[0078] Figure 13 This is a schematic diagram of another semiconductor device structure provided for some embodiments of this disclosure.
[0079] like Figure 13 As shown, in some feasible embodiments, during the RTO process, the surface of the gate G is also oxidized to form a gate oxide layer 160 covering the gate body. As an example, the material of the gate G includes TiN, and in this case, the material of the gate oxide layer 160 is TiO2.
[0080] In some feasible embodiments, the semiconductor device 100 further includes a contact structure 170G, which is connected to the gate G through the passivation layer 140. Further, the contact structure 170G is connected to the gate body through the second passivation layer 142 and the gate oxide layer 160. It is understood that external circuitry can transmit control signals to the gate G through the contact structure 170G to control the on / off state of the semiconductor device 100.
[0081] See Figure 11 In some feasible implementations, in order to improve the performance and reliability of the semiconductor device 100 and to prevent impurities adhering to the surface of the insulating layer 150 from forming conductive channels again and increasing the leakage current of the gate G, a second passivation layer 142 is provided to cover the first passivation layer 141, the insulating layer 150 and the gate G.
[0082] As an example, the first passivation layer 141 may be made of materials including plasma-enhanced oxide (PEOX), low-temperature silicon nitride (LPSiN), or any other feasible semiconductor thin film material, and this disclosure does not limit this.
[0083] As an example, the second passivation layer 142 may be made of materials including PEOX, LPSiN or other feasible semiconductor thin film materials, and this disclosure does not limit this.
[0084] Furthermore, the first passivation layer 141 and the second passivation layer 142 can be made of the same material or different materials, and this disclosure does not limit this.
[0085] Figure 14 This is a schematic diagram of yet another semiconductor device structure provided in some embodiments of this disclosure. Figure 15 This is a schematic diagram of yet another semiconductor device structure provided in some embodiments of this disclosure. Figure 16 This is a schematic diagram of another semiconductor device structure provided for some embodiments of this disclosure.
[0086] In some feasible implementations, the process of forming the first passivation layer 141 includes: depositing a first passivation film 143 on the stacked heterostructure 120, the gate cap layer 130, and the gate G, followed by reopening the gate cap layer 130 to expose at least a portion of its sidewalls, depending on the size of the opening: like Figure 14As shown, in some embodiments, along the second direction Y, the width H3 of the opening is equal to the width H2 of the gate cap layer 130. In this case, the surface of the heterostructure 120 includes a portion covered by the gate cap layer 130 and a portion not covered by the gate cap layer 130, wherein the portion not covered by the gate cap layer 130 is the exposed portion. The first passivation layer 141 completely covers the portion of the heterostructure 120 surface not covered by the gate cap layer 130. Since the first passivation layer 141 has a certain thickness H4, along the first direction X, the first passivation layer 141 covers part of the sidewall of the gate cap layer 130. During the RTO process, the portion of the sidewall of the gate cap layer 130 not covered by the first passivation layer 141 is oxidized to form an insulating layer 150. At this time, the side of the first passivation layer 141 closest to the gate cap layer 130 contacts the gate cap layer 130.
[0087] like Figure 15 As shown, in some other embodiments, along the second direction Y, the width H3 of the opening is greater than the width H2 of the gate cap layer 130. In this case, the surface of the heterostructure 120 includes a portion covered by the gate cap layer 130, a portion not covered by the gate cap layer 130, and a portion covered by the insulating layer 150. The portion not covered by the gate cap layer 130 and the insulating layer 150 is the exposed portion. The first passivation layer 141 partially covers the portion of the surface of the heterostructure 120 not covered by the gate cap layer 130, and the sidewall of the gate cap layer 130 is completely exposed. During the RTO process, the sidewall of the gate cap layer 130 is completely oxidized. At the same time, due to the expansion of the volume of the insulating layer 150 formed after the surface of the gate cap layer 130 is oxidized, the side of the first passivation layer 141 near the gate cap layer 130 contacts the insulating layer 150 after the RTO.
[0088] like Figure 16 As shown, in some embodiments, the width H3 of the opening is larger along the second direction Y. In this case, the surface of the heterostructure 120 includes a portion covered by the gate cap layer 130, a portion not covered by the gate cap layer 130, a portion covered by the insulating layer 150, and a portion covered by the second passivation layer 142. The portion not covered by the gate cap layer 130, the insulating layer 150, and the second passivation layer 142 is the exposed portion. The first passivation layer 141 partially covers the portion of the heterostructure 120 surface not covered by the gate cap layer 130. The sidewalls of the gate cap layer 130 are completely exposed. During the RTO process, the sidewalls of the gate cap layer 130 are completely oxidized. At the same time, the insulating layer 150 formed after the surface of the gate cap layer 130 is oxidized expands in volume. However, after the volume expansion, the insulating layer 150 is not enough to contact the first passivation layer 141. There is a gap between the insulating layer 150 and the first passivation layer 141. In the subsequent process of forming the second passivation layer 142, the gap is filled by the second passivation layer 142. That is, the side of the first passivation layer 141 near the gate cap layer 130 contacts the second passivation layer 142.
[0089] Figure 17This is a schematic diagram of another semiconductor device structure provided for some embodiments of this disclosure.
[0090] like Figure 17 As shown, in some feasible embodiments, the semiconductor device 100 further includes a source S and a drain D, which are disposed on the heterostructure 120. As an example, the source S and the drain D are disposed on opposite sides of the barrier layer 122 with respect to the gate G. It is understood that the contact structure 170S can contact the source S through the first passivation layer 141 and the second passivation layer 142, and the contact structure 170D can contact the drain D through the first passivation layer 141 and the second passivation layer 142.
[0091] Another aspect of this disclosure provides a method for fabricating a semiconductor device.
[0092] Figure 18 This is a flowchart illustrating a semiconductor device fabrication method according to some embodiments of the present disclosure. Figure 19 This is a schematic diagram of the structure during the fabrication process of a semiconductor device, provided for some embodiments of this disclosure.
[0093] like Figure 18 As shown, the method for fabricating a semiconductor device includes steps S10-S70: S10, such as Figure 19 As shown, a heterostructure 120 is formed on the substrate 110.
[0094] The heterostructure 120 includes a channel layer 121 and a barrier layer 122, with the channel layer 121 disposed on the side of the barrier layer 122 close to the substrate 110.
[0095] For example, S10 includes S11.
[0096] Figure 20 This is a schematic diagram of a process for forming a heterostructure on a substrate, provided for some embodiments of this disclosure.
[0097] S11, such as Figure 20 As shown, a channel layer 121 and a barrier layer 122 are sequentially formed on the substrate 110.
[0098] The methods for forming the channel layer 121 and the barrier layer 122 include metal-organic chemical vapor deposition (MOCVD) growth or molecular beam epitaxy (MBE) growth. For example, the channel layer 121 can be formed on one side of the substrate 110 using a reaction gas including ammonia (NH3), hydrogen (H2), and trimethyl gallium. Hydrogen can be used as a carrier gas to transport the reaction gas into the growth chamber. Ammonia can be used as a nitrogen source, and trimethyl gallium is used to provide a group III element. Exemplarily, nitrogen (N2) can also be used instead of hydrogen to transport the reaction gas into the growth chamber. As another example, the barrier layer 122 can be formed on the side of the channel layer 121 away from the substrate 110 using a reaction gas including ammonia, hydrogen (or nitrogen), trimethyl aluminum, and trimethyl gallium. Hydrogen or nitrogen can be used as a carrier gas to transport the reaction gases into the growth chamber, trimethylaluminum and trimethylgallium are used to provide group III elements, and nitrogen or ammonia can be used as a nitrogen source.
[0099] The material of the channel layer 121 may include one or more of GaN, AlGaN, indium aluminum nitride (InAlN), AlN, and scandium aluminum nitride (ScAlN). The material of the barrier layer 122 may include one or more of GaN, AlGaN, InAlN, AlN, and ScAlN. The materials of the channel layer 121 and the barrier layer 122 are different. For example, the channel layer 121 may be made of GaN, and the barrier layer 122 may be made of AlGaN.
[0100] S20, such as Figure 19 As shown, an initial gate cap layer 131 is formed on the side of the heterostructure 120 away from the substrate 110.
[0101] The initial gate cap layer 131 is disposed on the heterostructure 120, for example, the initial gate cap layer 131 is disposed on the surface of the heterostructure 120 away from the substrate 10. Exemplarily, S20 includes S21.
[0102] S21. A gate cap film 132 is formed on the heterostructure 120, and the gate cap film 132 is etched to form an initial gate cap layer 131.
[0103] The methods for forming the gate cap film 132 include MOCVD growth and MBE growth. For example, the material of the gate cap film 132 can be P-type AlGaN. Furthermore, magnesium (Mg) can be doped during the growth of AlGaN to form the P-type AlGaN gate cap film 132.
[0104] S30, such as Figure 19 As shown, an initial gate G1 is formed on the initial gate cap layer 131.
[0105] The initial gate G1 covers at least a portion of the initial gate cap layer 131.
[0106] For example, the material of the initial gate G1 may include metals such as nickel (Ni), gold (Au), etc., or semiconductor materials such as titanium nitride (TiN), etc.
[0107] Understandably, the initial gate G1 is disposed on the surface of the initial gate cap layer 131, and the pattern of the initial gate G1 is smaller than or equal to the pattern of the initial gate cap layer 131. That is, the boundary of the orthographic projection of the initial gate G1 onto the substrate 110 coincides with the boundary of the orthographic projection of the initial gate cap layer 131 onto the substrate 110, or the boundary of the orthographic projection of the initial gate G1 onto the substrate 110 is located within the boundary of the orthographic projection of the initial gate cap layer 131 onto the substrate 110.
[0108] S40, such as Figure 19 As shown, the epitaxial structure formed in the acid bath and cleaning step S30.
[0109] The surface oxides and some impurities of the epitaxial structure formed in step S30 are removed by acid bath and cleaning.
[0110] S50, such as Figure 19 As shown, a first passivation layer 141 is formed, which covers the sidewalls of the heterostructure 120 and the portion of the heterostructure 120 away from the substrate 110 that is not covered by the initial gate cap layer 131.
[0111] Figure 21 This is a schematic diagram of the structure during the formation of the first passivation layer 141, provided for some embodiments of this disclosure.
[0112] For example, such as Figure 21 As shown, the steps for forming the first passivation layer 141 are as follows: a first passivation film 143 is formed on the epitaxial structure after acid bath and cleaning in step S40; photoresist is coated on the surface of the first passivation film 143; exposure is performed to expose the overlapping portion of the orthogonal projection of the photoresist on the substrate 110 and the orthogonal projection of the initial gate cap layer 131 on the substrate 110; development is performed to dissolve the photosensitive portion of the photoresist, exposing the first passivation film 143 covering the initial gate G1 and the initial gate cap layer 131; etching is performed to remove the first passivation film 143 covering the initial gate G1 and the initial gate cap layer 131, for example, plasma etching can be used to remove this portion of the first passivation film 143; and residual photoresist is removed to form the first passivation layer 141.
[0113] Understandably, due to the influence of process precision, the size of the opening is difficult to control precisely. The opening only needs to expose at least part of the sidewall of the initial gate cap layer 131.
[0114] S60, such as Figure 19 As shown, the epitaxial structure formed in oxidation step S50.
[0115] The sidewalls of the initial gate cap layer 131, the portion of the initial gate cap layer 131 not covered by the initial gate G1, and the surface of the initial gate G1 are oxidized to form the gate cap layer 130, the gate body, the insulating layer 150, and the gate oxide layer 160.
[0116] For example, oxidation can be performed using a rapid oxygen annealing (RTO) process, which involves annealing the initial gate cap layer 131 surface with oxygen in a rapid thermal processing (RTP) machine.
[0117] For example, during the RTO process, the temperature can be set to 500℃~850℃, the time to 30S~60S, and the oxygen flow rate to 2L / min. It should be noted that if the set temperature is below 500℃ during the RTO process, it is difficult to effectively block leakage current paths, resulting in poor insulation. If the set temperature is above 850℃, the excessively high temperature places excessive demands on the RTP equipment, and the excessively high temperature will affect the thermal budget of the semiconductor device, affecting the activation of Mg% in the gate cap layer 130, and directly affecting the turn-on voltage of the semiconductor device.
[0118] S70, such as Figure 19 As shown, a second passivation film 144 is deposited to form a second passivation layer 142.
[0119] Figure 22 This is a schematic diagram illustrating gate leakage current in a semiconductor device, provided for some embodiments of this disclosure.
[0120] like Figure 22 As shown, the semiconductor device 100 prepared through the above process steps forms an insulating layer 150 by oxidizing the surface of the initial gate cap layer 131. This reduces surface defects in the gate cap layer 130, blocking some leakage channels and thus reducing leakage current at the gate G. Simultaneously, the presence of the first passivation layer 141 prevents the barrier layer 122 in the heterostructure 120 from being oxidized during the RTO process. The presence of the second passivation layer 142 further isolates the semiconductor device 100 from the external environment, ensuring the long-term reliability of the semiconductor device 100, reducing surface states, decreasing carrier recombination, and improving the core electrical performance of the semiconductor device 100.
[0121] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A semiconductor device, characterized in that, include: Substrate; A heterogeneous structure is disposed on one side of the substrate; A gate cap layer is disposed on the side of the heterostructure away from the substrate and partially covers the heterostructure; A gate is disposed on the side of the gate cap layer away from the substrate and covers at least a portion of the gate cap layer; An insulating layer covering the sidewalls of the gate cap layer and the portion of the gate cap layer not covered by the gate on the side away from the substrate; A passivation layer covers the sidewalls of the heterostructure, the portion of the heterostructure away from the substrate that is not covered by the gate cap layer, the gate, and the insulating layer.
2. The semiconductor device according to claim 1, characterized in that, The boundary of the gate's orthogonal projection onto the substrate lies within the boundary of the gate cap layer's orthogonal projection onto the substrate. The insulating layer covers the sidewalls of the gate cap layer and the portion of the gate cap layer away from the substrate that is not covered by the gate.
3. The semiconductor device according to claim 1, characterized in that, The boundary of the gate as projected onto the substrate coincides with the boundary of the gate cap layer as projected onto the substrate, and the insulating layer covers the sidewalls of the gate cap layer.
4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The insulating layer is configured to be formed by oxidation of the gate cap layer.
5. The semiconductor device according to claim 1, characterized in that, The gate includes a gate oxide layer and a gate body, the gate oxide layer covering the sidewalls of the gate body and the surface of the gate body away from the substrate.
6. The semiconductor device according to claim 5, characterized in that, It also includes a contact structure that penetrates the passivation layer and the gate oxide layer and is connected to the gate body.
7. The semiconductor device according to claim 1, characterized in that, The passivation layer includes: A first passivation layer covers the sidewalls of the heterostructure and the exposed surface area of the heterostructure away from the substrate; A second passivation layer covers the first passivation layer, the insulating layer, and the gate.
8. The semiconductor device according to claim 7, characterized in that, The first passivation layer is located near the end of the gate cap layer and is in contact with the gate cap layer.
9. The semiconductor device according to claim 7, characterized in that, The first passivation layer is located near the end of the gate cap layer and is in contact with the insulating layer.
10. The semiconductor device according to claim 7, characterized in that, The first passivation layer is located near the end of the gate cap layer and is in contact with the second passivation layer.
11. The semiconductor device according to any one of claims 7 to 10, characterized in that, The passivation layer is made of plasma-enhanced oxide and / or low-temperature silicon nitride.
12. A method for fabricating a semiconductor device, characterized in that, include: Forming heterostructures on a substrate; An initial gate cap layer is formed on the heterostructure, and the initial gate cap layer partially covers the heterostructure. An initial gate is formed on the initial gate cap layer, the initial gate covering at least a portion of the initial gate cap layer, to obtain an epitaxial structure; Acid bath and cleaning of the epitaxial structure; A first passivation layer is formed, which covers the sidewalls of the heterostructure and the portion of the heterostructure away from the substrate that is not covered by the initial gate cap layer; Oxidize the sidewalls of the initial gate cap layer, the portion of the initial gate cap layer not covered by the initial gate, and the initial gate to form a gate cap layer, a gate, an insulating layer, and a gate oxide layer; A second passivation layer is formed, which covers the first passivation layer, the gate, and the insulating layer.
13. An electronic device, characterized in that, include: The semiconductor device as described in any one of claims 1-11; A printed circuit board, which is electrically connected to the semiconductor device.